JP3967746B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device in which SRAM memory cells and bipolar transistors are mounted on the same semiconductor substrate.

The semiconductor integrated circuit device of the present invention's under development, memory cell, a bipolar transistor, is mounted on the n-channel MOSFET (M etal O xide S emiconductor F ield E ffect T ransistor) and the same semiconductor substrate a p-channel MOSFET Yes. Memory cell is an SRAM that stores information 1 [bit] (S tatic R andom A ccess M emory). Bipolar transistors, n-channel MOSFETs, and p-channel MOSFETs are used as components of peripheral circuits. That is, the semiconductor integrated circuit device of the present invention's under development is composed of a Bi-CMOS (Bi polar- C omplementary MOS) -SRAM.

  The bipolar transistor is configured, for example, of an npn type in which an n-type emitter region, a p-type base region, and an n-type collector region are sequentially arranged from the main surface of the epitaxial layer in the depth direction.

  The n-type collector region includes an intrinsic collector region, a high concentration collector region, and a collector contact region. The intrinsic collector region is composed of an n-type well region. The high concentration collector region is composed of a buried n + type semiconductor region formed between the semiconductor substrate and the n type well region. The collector contact region is composed of an n + type semiconductor region formed on the main surface of the n type well region.

  The p-type base region is composed of an intrinsic base region and a high concentration base region. The intrinsic base region is composed of a p-type semiconductor region formed on the main surface of the n-type well region, and the high-concentration base region is composed of a p + -type semiconductor region formed on the main surface of the n-type well region.

  The n-type emitter region is composed of an n + -type semiconductor region formed on the main surface of a p-type semiconductor region which is an intrinsic base region. An emitter electrode is electrically connected to the n + type semiconductor region. The emitter electrode (n-type) is formed of a second-layer polycrystalline silicon film.

  The n-channel MOSFET is formed on the main surface of the p-type well region. This n-channel MOSFET is mainly composed of a channel formation region (p-type well region), a gate insulating film, a gate electrode, a pair of n + -type semiconductor regions which are a source region and a drain region, and a pair of n-type semiconductor regions. ing.

  The p-channel MOSFET is formed on the main surface of the n-type well region. This p-channel MOSFET mainly includes a channel formation region (n-type well region), a gate insulating film, a gate electrode, a pair of p + -type semiconductor regions which are a source region and a drain region, and a pair of p-type semiconductor regions. ing.

  The gate electrodes of the n-channel MOSFET and p-channel MOSFET are formed of a second-layer polycrystalline silicon film and a refractory metal film formed on the main surface thereof. The refractory metal film is formed of, for example, a tungsten silicide (WSix) film. The upper surfaces of these gate electrodes are covered with a cap insulating film (silicon oxide film).

The memory cell includes a flip-flop circuit composed of two inverter circuits and two transfer MOSFETs. Each of the two inverter circuit, and a driving MOSFET and load TFT (T hin F ilm T ransistor ).

  The one transfer MOSFET is disposed between one storage node portion (input / output terminal) of the flip-flop circuit and one data line (bit line), and the operation is controlled by a word line. The other transfer MOSFET is disposed between the other storage node (input / output terminal) of the flip-flop circuit and the other data line (bit line), and the operation is controlled by the word line. The gate electrodes of both transfer MOSFETs are formed of a second-layer polycrystalline silicon film and a refractory metal film formed on the main surface thereof.

  Each of the two driving MOSFETs is formed on the main surface of the p-type well region. Each of these two driving MOSFETs is mainly composed of a pair of n-type semiconductor regions which are a channel formation region (p-type well region), a gate insulating film, a gate electrode, a source region and a drain region. The gate electrodes of the two driving MOSFETs are the first-layer polycrystalline silicon films prior to the gate electrodes of the n-channel MOSFET, p-channel MOSFET and memory cell transfer MOSFET constituting the peripheral circuit. It is formed with.

  Each gate electrode of the two load TFTs is formed of a third-layer polycrystalline silicon film. The channel forming region, the source region, and the drain region of the two load TFTs are formed in the fourth-layer polycrystalline silicon film. The gate insulating films of the two load TFTs are each formed of an interlayer insulating film formed between the third-layer polycrystalline silicon film and the fourth-layer polycrystalline silicon film. This interlayer insulating film is formed of, for example, a silicon oxide film.

  A reference power supply wiring (ground plate) fixed to a reference potential (for example, 0 [V]) Vss is electrically connected to each source region of the two driving MOSFETs. An operation power supply wiring fixed to an operation potential (for example, 3.3 [V]) Vcc is electrically connected to each source region of the two load TFTs. The reference power supply wiring is formed of a second-layer polycrystalline silicon film, and the operation power supply wiring is formed of a fourth-layer polycrystalline silicon film.

  In the flip-flop circuit of the memory cell, a capacitance element is added to each storage node portion of the two inverter circuits. The capacitive element has a laminated structure in which a lower electrode, a dielectric film, and an upper electrode are sequentially stacked. The lower electrode is formed of a second-layer polycrystalline silicon film and is also used as a reference power supply wiring. The upper electrode is formed of a third-layer polycrystalline silicon film and is also used as the gate electrode of the load TFT. The dielectric film is formed of an interlayer insulating film formed between the second-layer polycrystalline silicon film and the third-layer polycrystalline silicon film. This interlayer insulating film is formed of, for example, a silicon oxide film.

In the semiconductor integrated circuit device configured as described above, it is important to select the emitter electrode (n-type) connected to the emitter region (n-type) of the bipolar transistor and to set the film thickness thereof. The base current (I _B ) of the bipolar transistor is determined by the concentration gradient of holes in the emitter region injected from the base region (p-type). Since the diffusion length of holes in the emitter region is about 0.1 [μm], in order to stably obtain the base current, the depth of the emitter region (high concentration n + -type semiconductor region) and the emitter electrode The total emitter depth including the thick film must be about twice the diffusion length of holes (about 0.2 [μm]) or more. That is, by making the total emitter depth more than about twice the diffusion length of holes in the emitter region, the base current (I _B ) can be reduced and the emitter ground current gain (h _FE = I _C / I _B ) Can be increased.

  A semiconductor integrated circuit device having the SRAM memory cell, bipolar transistor, n-channel MOSFET and p-channel MOSFET is described in, for example, Japanese Patent Application Laid-Open No. 3-278454.

The present inventor conducted the following investigation on the above-described semiconductor integrated circuit device of 0.4 [μm] or later.
In the 0.4 [μm] generation device, since the depth of the emitter region is about 0.05 [μm], the thickness of the emitter electrode, that is, the thickness of the second-layer polycrystalline silicon film is 0. About 15 [μm] is required. The thickness of the emitter electrode varies due to variations in the thickness of the polycrystalline silicon film itself and over-etching when the connection hole is formed in the upper interlayer insulating film. If it is set to 15 [μm] or less, the concentration gradient of holes in the emitter region becomes large or the concentration gradient varies, and the characteristics of the bipolar transistor become unstable.

  The gate electrode of a bulk MOSFET such as the n-channel MOSFET, p-channel MOSFET, driving MOSFET, transfer MOSFET, etc. is a first-layer polycrystalline silicon film into which an n-type impurity is introduced for the purpose of adjusting the flat band voltage Vfb For the purpose of reducing the delay of the word line, it is composed of a laminated structure of a tungsten silicide film having a small specific resistance, and its upper surface is covered with a cap insulating film. The first-layer polycrystalline silicon film is set to a thickness of about 80 [nm], the tungsten silicide film is set to a thickness of about 80 [nm], and the cap insulating film is set to a thickness of about 80 [nm]. Set to The cap insulating film must be set to such a thickness that arsenic (As) ions do not leak into the tungsten silicide film of the gate electrode when forming the source region and drain region of the n-channel conductivity type bulk MOSFET. Since arsenic ions have a large molecular weight, when arsenic ions are implanted into the tungsten silicide film, the tungsten silicide crystal becomes amorphous and internal stress is generated in the tungsten silicide film in the subsequent heat treatment process, and the tungsten silicide film peels off and disappears. Such problems occur.

  The third-layer polycrystalline silicon film used as the gate electrode of the load TFT is set to a thickness of about 50 [nm], and is used as a channel formation region and an operation power supply wiring of the load TFT. The fourth polycrystalline silicon film is set to a thickness of about 40 [nm].

JP-A-3-278454

The present inventor has found the following problems with respect to such a semiconductor integrated circuit device.
The first problem is that it is extremely difficult to process the polycrystalline silicon film of the memory cell, and the yield during the manufacturing process is reduced.

The total thickness of the gate electrode of the bulk MOSFET and the cap insulating film covering the upper surface is set to 240 [nm], the thickness of the second polycrystalline silicon film is set to 150 [nm], and the second layer When patterning a polycrystalline silicon film by anisotropic dry etching, at least 160 [%] overetching is required. If the Si / SiO ₂ etching ratio at this time is 10, the underlying interlayer insulating film (silicon oxide film) of the polycrystalline silicon film of the second layer is etched by 24 [nm] by overetching. Therefore, on the base of the third layer polycrystalline silicon film, the total film thickness 240 [nm] of the gate electrode of the bulk MOSFET and the cap insulating film covering the upper surface thereof, the second layer polycrystalline silicon film There is a total of 414 [nm] steps including the thickness of 150 [nm] and the thickness of the interlayer insulating film 24 [nm]. Therefore, when the thickness of the third-layer polycrystalline silicon film is set to 50 [nm] and this third-layer polycrystalline silicon film is patterned by anisotropic dry etching, at least 830 [%] The above overetching is necessary. In addition, since there is a base step that is more than eight times the film thickness, the etching on the side of the base step proceeds even when the etching corresponding to the film thickness is completed (at the end of just etching). Since the change becomes unclear, the in-line monitoring of just etching during the processing of the third-layer polycrystalline silicon film becomes unstable.

  Such a situation becomes more prominent when the fourth-layer polycrystalline silicon film is processed. First, when 830 [%] overetching is performed on the third-layer polycrystalline silicon film, the underlying interlayer insulating film is cut by 41 [nm]. Therefore, when processing the fourth-layer polycrystalline silicon film, the thickness of the third-layer polycrystalline silicon film is 50 [nm], and the interlayer insulation is performed by over-etching the third-layer polycrystalline silicon film. There is a step of 505 [nm] including the film scraping amount of 41 [nm]. Since the thickness of the fourth-layer polycrystalline silicon film is 40 [nm], when processing the ground of 510 [nm], overetching of at least 1280 [%] is required. Furthermore, since there is a base step of about 12 times the film thickness, when etching the fourth layer polycrystalline silicon film, just etching is performed compared to processing the third layer polycrystalline silicon film. In-line monitors become even more unstable.

  As described above, when the polycrystalline silicon film on the memory cell is processed, overetching of the film to be etched needs to be 800% or more, and the in-line monitor of the just etching during the etching is unstable. Therefore, it is impossible to find stable mass production process conditions.

  In the case of a CMOS-SRAM, the second-layer polycrystalline silicon film is not used as an emitter electrode, but a tungsten silicide film having a thickness of about 50 [nm] is used instead to reduce the step of the memory cell. The burden is reduced.

The second problem is that high-performance load TFTs and capacitive elements cannot be obtained.
The performance of the load TFT can be enhanced by reducing the thickness of the interlayer insulating film which is a gate insulating film. In addition, the performance of the capacitive element can be enhanced by reducing the thickness of the interlayer insulating film that is a dielectric film. The lower limit of the film thickness is limited by the power supply voltage used and the film quality of the interlayer insulating film. For example, when the power supply voltage is 3.3 [V] and the interlayer insulating film is not damaged by dry etching or the like, The film thickness of the interlayer insulating film can be reduced to about 15 [nm].

  However, when actually setting the film thickness of the interlayer insulating film, it is necessary to set it by adding the amount of abrasion by dry etching. For example, an interlayer insulating film that is a dielectric film of a capacitor element must be set to a film thickness of 56 [nm] or more in consideration of the amount of scraping 41 [nm] due to overetching of the third-layer polycrystalline silicon film. Don't be. Similarly, the interlayer insulating film, which is the gate insulating film of the load TFT, has a thickness of 52 [nm] due to over-etching of the fourth polycrystalline silicon film (a fourth multi-layer with a thickness of 40 [nm]). In consideration of the case where overetching of 1300 [%] is performed on the crystalline silicon film at a selection ratio of 10, the film thickness must be set to 67 [nm] or more. Thus, the film thickness of the actual interlayer insulating film must be set to about three times the film thickness controlled by the intrinsic film quality of the interlayer insulating film, and a high-performance load TFT and capacitive element can be obtained. I can't.

  In the case of a CMOS-SRAM, the second-layer polycrystalline silicon film is replaced with a tungsten silicide film having a thickness of about 50 [nm] to reduce the level of the memory cell. The amount of overetching of the polycrystalline silicon film of the fourth layer is reduced, and accordingly, the film thickness of the interlayer insulating film that is the gate insulating film of the load TFT and the film thickness of the interlayer insulating film that is the dielectric film of the capacitive element Is set thin to improve the performance of load TFTs and capacitive elements.

  The third problem is that the method of taking the reference potential (ground potential) is insufficient and the writing operation and reading operation of the memory cell become unstable.

  For example, when the emitter electrode of the bipolar transistor and the reference power supply wiring of the memory cell are formed by the second polycrystalline silicon film having a thickness of 150 [nm], the processing of the memory cell is extremely difficult as described above. The reference power supply wiring cannot be thickened or cannot have a laminated structure with the tungsten silicide film. As a countermeasure, there is a method in which a metal wiring fixed at a reference potential is provided and the reference power supply wiring and the metal wiring are connected to each cell through a connection hole, but the third layer is bypassed to bypass this connection hole. A pattern formed of a polycrystalline silicon film and a pattern formed of a fourth-layer polycrystalline silicon film must be laid out, which increases the area occupied by the memory cell and cannot be put into practical use. Therefore, the parasitic resistance of the reference power supply wiring is larger than that of a CMOS-SRAM memory cell that can use a tungsten silicide film for the reference power supply wiring, and the low potential node rises during writing or reading of the memory cell. End up.

Generally, main memories such as computers and work stations are not accessed at high speed, and an error correction function is added, so a CMOS-SRAM with a soft error rate of about 1000 [fit] is low speed. It is possible. On the other hand, since cache memories such as computers and work stations are accessed at high speed and no error correction function is added, memory cells with a high soft error rate of about 100 [fit] are required. When the memory cell described above is used, the power supply voltage and the soft error rate with the storage capacity as a parameter have a correlation as shown in FIG. 55 (correlation diagram showing the relationship between the power supply voltage and the soft error rate). In a 3.3 [V] power supply voltage cache memory, a storage capacity of 10 [fF / node] is required to make the soft error rate 100 [fit]. For example, in a memory cell having a 0.4 [μm] processing rule and a cell size of 13 [μm ² ], the storage capacity excluding the capacitive element is about 4 [fF / node]. A capacitive element is required.

Under the constraint of 0.4 [μm] processing rule and a cell size of 13 [μm ² ], the area of the capacitive element can be secured only about 3 [μm ² / node], so that 6 [fF / node]. In order to obtain a capacitive element, the thickness of the dielectric film of the capacitive element, that is, the interlayer insulating film, must be set to 17 [nm] or less in terms of a silicon oxide film (SiO ₂ ). However, since the thickness of the dielectric film (interlayer insulating film) of the capacitive element cannot be set to 55 [μm] or less in terms of a silicon oxide film, Bi-CMOS SRAM cannot be used as a cache memory. .

  An object of the present invention is to provide a processing margin of the memory cell in a semiconductor integrated circuit device having a memory cell and a bipolar transistor in which a capacitor element is added to a storage node portion of an inverter circuit composed of a driving MISFET and a load TFT. It is to provide a technology capable of ensuring the above.

  Another object of the present invention is to provide a technique capable of improving the performance of load TFTs and capacitive elements mounted in the semiconductor integrated circuit device.

  Another object of the present invention is to provide a technique capable of stabilizing a write operation and a read operation of a memory cell mounted on the semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

(1) In a semiconductor integrated circuit device having a memory cell and a bipolar transistor in which a capacitor element is added to a storage node portion of an inverter circuit composed of a driving MISFET and a load TFT, connected to a source region of the driving MISFET The reference power supply wiring and the emitter electrode connected to the emitter region of the bipolar transistor are formed of the uppermost polycrystalline silicon film.

(2) The film thickness of the intermediate polycrystalline silicon film between the uppermost polycrystalline silicon film and the first polycrystalline silicon film is less than half the thickness of the uppermost polycrystalline silicon film. Set to.

(3) The intermediate polycrystalline silicon film is covered with the uppermost polycrystalline silicon film in the memory cell formation region.

(4) The reference power supply wiring is lined for each memory cell with a metal wiring formed in an upper layer.

(5) The capacitive element includes the uppermost polycrystalline silicon film as an upper electrode, the lowermost polycrystalline silicon film lower than the uppermost polycrystalline silicon film, and the uppermost polycrystalline silicon film. An interlayer insulating film between the lower polycrystalline silicon film is used as a dielectric film, and the upper electrode of the capacitive element is also used as the reference power supply wiring.

(6) The load TFT is formed with a polycrystalline silicon film one layer lower than the uppermost polycrystalline silicon film as a gate electrode, and a polycrystalline silicon film two layers lower than the uppermost polycrystalline silicon film with a channel. A region, a source region, a drain region, and an interlayer insulating film between these polycrystalline silicon films are used as a gate insulating film, and the gate electrode of the load TFT is also used as a lower electrode of the capacitor element.

(7) The total emitter depth obtained by combining the depth of the emitter region formed in the semiconductor substrate and the thickness of the emitter electrode formed of the uppermost polycrystalline silicon film is determined in the emitter region or emitter electrode. The hole diffusion length is about twice (about 0.2 [μm]) or more. That is, the total emitter depth is set to be about twice or more the diffusion length of the minority carriers in the emitter region or emitter electrode.

(8) The surface of the reference power supply wiring is selectively silicided, and the emitter electrode is not silicided.
According to the above-described means, it is not necessary to increase the thickness of the polycrystalline silicon film that is two layers below the uppermost layer used as the channel formation region of the load TET and the operation power supply wiring. The level difference of the underlying layer of the polycrystalline silicon film can be greatly reduced, and the amount of over-etching when processing this one lower polycrystalline silicon film can be reduced. Accordingly, the interlayer insulating film between the lower polycrystalline silicon film and the lower polycrystalline silicon film can be thinned, and the performance of the load TFT using the interlayer insulating film as a gate insulating film can be improved. Can be achieved.

  Further, since the polycrystalline silicon film in the intermediate layer is covered with the polycrystalline silicon film in the uppermost layer, the interlayer insulating film between the polycrystalline silicon film in the uppermost layer and the polycrystalline silicon film in the lower layer is the uppermost layer. It is not scraped off by overetching when processing the upper polycrystalline silicon film. Accordingly, the interlayer insulating film between the uppermost polycrystalline silicon film and the lower polycrystalline silicon film can be thinned, and the performance of the capacitive element using the interlayer insulating film as a dielectric film can be improved. be able to.

  In addition, since there is only a step due to the gate electrode of a bulk MOSFET such as a driving MOSFET or a step due to a field insulating film, the underlying step of the etched portion of the uppermost polycrystalline silicon film can be processed stably. A processing margin of the memory cell can be secured.

In addition, since the reference power supply wiring is formed of the uppermost polycrystalline silicon film, the reference power supply wiring and the upper layer thereof are not dependent on the arrangement of the polysilicon pattern or active region pattern made of the intermediate polycrystalline silicon film. A connection hole for connecting the formed metal wiring can be arranged at an arbitrary position. Accordingly, since the ground parasitic resistance of the memory cell can be reduced without increasing the area occupied by the memory cell, it is possible to stabilize the writing operation and the reading operation of the memory cell. In addition, the emitter ground current gain (h _FE ) of the bipolar transistor can be improved, and the performance of the bipolar transistor can be improved. In addition, the wiring resistance of the reference power supply wiring can be reduced, and the operation speed of the memory cell can be improved.

(9) In a method for manufacturing a semiconductor integrated circuit device having a MISFET and a capacitor,
Forming the upper electrode of the capacitive element with an uppermost polycrystalline silicon film;
Forming an insulating film covering the surface of the upper electrode of the capacitive element;
Forming a silicide layer in a self-aligned manner with respect to the insulating film.

(10) In the means (9), the surface of the upper electrode of the capacitive element is selectively silicided.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
In a semiconductor integrated circuit device having a memory cell and a bipolar transistor in which a capacitor element is added to a storage node portion of an inverter circuit composed of a driving MOSFET and a load TFT, a processing margin of the memory cell can be secured. .

In addition, it is possible to improve the performance of the load TFT and the capacitor mounted on the semiconductor integrated circuit device.
Further, it is possible to stabilize the writing operation and the reading operation of the memory cell mounted on the semiconductor integrated circuit device.

The configuration of the present invention will be described below together with embodiments in which the present invention is applied to a semiconductor integrated circuit device.
In all the drawings for explaining the embodiments, parts having the same function are given the same reference numerals, and repeated explanation thereof is omitted.

(Embodiment 1)
A schematic configuration of a semiconductor integrated circuit device according to the first embodiment of the present invention is shown in FIG. 1 (main part sectional view) and FIG. 2 (main part sectional view).

  As shown in FIGS. 1 and 2, the semiconductor integrated circuit device is mainly composed of, for example, a p − type semiconductor substrate 1A and an epitaxial layer 1B formed on the main surface thereof. In the memory cell formation region of p − type semiconductor substrate 1A, p type well region 6A is formed on the main surface of epitaxial layer 1B. In the bipolar formation region of the p − type semiconductor substrate 1A, an n-type well region 5A is formed on the main surface of the epitaxial layer 1B. In the nMOS formation region of the p − type semiconductor substrate 1A, a p type well region 6B is formed on the main surface of the epitaxial layer 1B. In the pMOS formation region of the p − type semiconductor substrate 1A, an n-type well region 5B is formed on the main surface of the epitaxial layer 1B. A p-type semiconductor region (Burred-p) 9 is formed in the p-type well region 6A.

  A shallow buried p-type semiconductor region 4A is formed between the p-type well region 6A and the p − type semiconductor substrate 1A, and the p − type semiconductor substrate under the shallow buried p type semiconductor region 4A. A deep buried n-type semiconductor region 2 is formed on the main surface of 1A. A shallow buried n + type semiconductor region 3A is formed between the n type well region 5A and the p − type semiconductor substrate 1A. A shallow buried p-type semiconductor region 4B is formed between the p-type well region 6B and the p − type semiconductor substrate 1A. Between the n-type well region 5B and the p − -type semiconductor substrate 1, a shallow buried n + -type semiconductor region 3B is formed.

In the p − type semiconductor substrate 1A, the memory cell M is mounted on the memory cell formation region, the bipolar transistor Tr is mounted on the bipolar formation region, the n-channel MOSFET Qn is mounted on the nMOS formation region, and the pMOS A p-channel MOSFET Qp is mounted on the formation region. The memory cell M is composed of an SRAM that stores 1 [bit] information. Each of the bipolar transistor Tr, the n-channel MOSFET Qn, and the p-channel MOSFET Qp is used as a component of the peripheral circuit. That is, the semiconductor integrated circuit device of the present embodiment is composed of Bi-CMOS-SRAM. Hereinafter, will be explained with reference to MOSFET, not limited to this, it is the course of may be MISFET (M etal I nsulator S emiconductor FET).

As shown in FIG. 2, the n-channel MOSFET Qn is formed on the main surface of a p-type well region 6B whose periphery is defined by a field insulating film 7. The n-channel MOSFET Qn mainly includes a channel formation region (p-type well region 6B), a gate insulating film 10, a gate electrode 13, a pair of n-type semiconductor regions 18 serving as a source region and a drain region, and a pair of n + -type semiconductors. The area 20 is configured. That, n-channel MOSFETQn is composed of LDD (L ightiy D oped D rain ) structure.

  A first-layer metal wiring 35 is electrically connected to each of the pair of n + -type semiconductor regions 20 which are the source region and the drain region of the n-channel MOSFET Qn through a connection hole 34 formed in the interlayer insulating film 33. Has been. The interlayer insulating film 33 is formed of, for example, a silicon oxide film. The first-layer metal wiring 35 is formed of, for example, an aluminum film or an aluminum alloy film.

  As shown in FIG. 2, the p-channel MOSFET Qp is formed on the main surface of an n-type well region 5B whose periphery is defined by a field insulating film 7. This p-channel MOSFET Qp mainly includes a channel formation region (n-type well region 5B), a gate insulating film 10, a gate electrode 13, a pair of p-type semiconductor regions 16 as a source region and a drain region, and a pair of p + -type semiconductors. The area 21 is configured. That is, the p-channel MOSFET Qp has an LDD structure. A pair of n-type semiconductor regions (n pocket regions) 15 are formed under each of the pair of p-type semiconductor regions 16 which are the source region and the drain region of the p-channel MOSFET Qp.

  A first-layer metal wiring 35 is electrically connected to each of the pair of p + -type semiconductor regions 21 which are the source region and the drain region of the p-channel MOSFET Qp through a connection hole 34 formed in the interlayer insulating film 33. Has been. A polysilicon pattern 25 made of polycrystalline silicon of the second layer is electrically connected to the p + type semiconductor region 21 on the source side of the p-channel MOSFET Qp adjacent to the memory cell array through the connection hole 24, and the memory Vcc power is supplied to the cell.

  Each gate electrode 13 of the n-channel MOSFET Qn and the p-channel MOSFET Qp is formed of a first-layer polycrystalline silicon film 11 and a refractory metal film 12 formed on the main surface thereof. The refractory metal film 12 is formed of, for example, a tungsten silicide (WSix) film. The upper surfaces of these gate electrodes 13 are covered with a cap insulating film. The cap insulating film is made of, for example, a silicon oxide film.

  As shown in FIG. 1, the bipolar transistor Tr is formed on the main surface of an n-type well region 5A whose periphery is defined by a field insulating film 7. The bipolar transistor Tr is an npn type in which an n-type emitter region, a p-type base region, and an n-type collector region are sequentially arranged from the main surface of the n-type well region 5A (epitaxial layer 1B) in the depth direction. It is configured.

  The n-type collector region includes an intrinsic collector region, a high concentration collector region, and a collector contact region. The intrinsic collector region is composed of an n-type well region 5A, the high concentration collector region is composed of a buried n + -type semiconductor region 3A, and the collector contact region is composed of an n + -type semiconductor region 8. A first-layer metal wiring 35 is electrically connected to the n + -type semiconductor region 8 as a collector contact region through a connection hole 34 formed in the interlayer insulating film 33.

  The p-type base region is composed of an intrinsic base region and a high concentration base region. The intrinsic base region is composed of the p-type semiconductor region 22, and the high concentration base region is composed of the p + -type semiconductor region 21. A first-layer metal wiring 35 is electrically connected to the p + type semiconductor region 21, which is the high concentration base region, through a connection hole 34 formed in the interlayer insulating film 33.

  The n-type emitter region is composed of an n + -type semiconductor region 32. An emitter electrode (31B) is electrically connected to the n + -type semiconductor region 32 as the emitter region through an emitter opening 30B. The emitter electrode (31B) is formed of a polycrystalline silicon film 31 of the fourth layer. For the purpose of reducing the resistance value and forming the n + -type semiconductor region 32, the polycrystalline silicon film 31 of the fourth layer has an n-type impurity (for example, phosphorus (P)) during the deposition or after the deposition. An n-type impurity (for example, As) is introduced. That is, the n + -type semiconductor region 32 that is the emitter region is formed by diffusing the n-type impurity introduced into the emitter electrode 31 B into the main surface of the p-type semiconductor region 22. A first-layer metal wiring 35 is electrically connected to the emitter electrode 31 </ b> B through a connection hole 34 formed in the interlayer insulating film 33. Further, an emitter electrode 31B composed of a depth of an n + type semiconductor region 32 which is an emitter region formed in the semiconductor substrate 1 and a fourth-layer polycrystalline silicon film 31 which is the uppermost polycrystalline silicon film. The total emitter depth in combination with the film thickness is configured to be 0.2 [μm] or more as will be described later.

  As shown in FIG. 3 (equivalent circuit diagram), the memory cell M includes a flip-flop circuit composed of two inverter circuits and two transfer MOSFETs Qt1 and Qt2. One inverter circuit includes a driving MOSFET Qd1 and a load TFT Qf1. The other inverter circuit is composed of a driving MOSFET Qd2 and a load TFT Qf2. The drain regions of the driving MOSFET Qd1 and the load TFT Qf1 constitute an accumulation node portion (storage node portion) A of the flip-flop circuit. The drain regions of the driving MOSFET Qd2 and the load TFT Qf2 constitute an accumulation node portion (storage node portion) B of the flip-flop circuit.

  The transfer MOSFET Qt1 is disposed between the storage node (storage node) part A of the flip-flop circuit and the data line DL1, and its operation is controlled by the word line WL. The transfer MOSFET Qt2 is arranged between the storage node (storage node) part B of the flip-flop circuit and the data line DL2, and its operation is controlled by the word line WL. One semiconductor region of the transfer MOSFET Qt1 is connected to the storage node portion A, the other semiconductor region is connected to the data line DL1, and its gate electrode is connected to the word line WL. One semiconductor region of the transfer MOSFET Qt2 is connected to the storage node portion B, the other semiconductor region is connected to the data line DL2, and its gate electrode is connected to the word line WL.

  The gate electrodes of the driving MOSFET Qd1 and the load TFT Qf1 are connected to the storage node portion B of the flip-flop circuit, and the gate electrodes of the driving MOSFET Qd2 and the load TFT Qf2 are connected to the storage node portion A of the flip-flop circuit. ing.

  An operating power supply wiring 25A fixed at an operating potential (for example, 3.3 [V]) Vcc is electrically connected to the source region of the load TFT Qf1. Further, an operation power supply wiring 25B fixed to the operation potential Vcc is electrically connected to the source region of the load TFT Qf2.

A reference power supply line 31A fixed to a reference potential (for example, 0 [V]) Vss is electrically connected to the source regions of the driving MOSFETs Qd1 and Qd2.
A capacitor element C1 is added to the storage node portion A of the flip-flop circuit. A capacitor element C2 is added to the storage node portion B of the flip-flop circuit.

  As shown in FIG. 1, the transfer MOSFET Qt1 is formed on the main surface of a p-type well region 6A whose periphery is defined by a field insulating film 7. The transfer MOSFET Qt1 mainly includes a channel formation region (p-type well region 6A), a gate insulating film 10, a gate electrode 13, a pair of n-type semiconductor regions 18 serving as a source region and a drain region, and a pair of n + -type semiconductors. The area 20 is configured. That is, the transfer MOSFET Qt1 has an n-channel conductivity type and an LDD structure. The gate electrode 13 of the transfer MOSFET Qt1 is formed in the same process as the gate electrode 13 of the n-channel MOSFET Qn described above. A first-layer metal wiring 35 is electrically connected to the other n + -type semiconductor region 20 of the transfer MOSFET Qt 1 through a connection hole 34 formed in the interlayer insulating film 33.

  Although not shown in the figure, the transfer MOSFET Qt2 is configured in the same manner as the transfer MOSFET Qt1.

  Although not shown in detail in the drawing, the driving MOSFET Qd2 is formed on the main surface of the p-type well region 6A whose periphery is defined by the field insulating film 7. This driving MOSFET Qd2 is mainly composed of a channel formation region (p-type well region 6A), a gate insulating film 10, a gate electrode 13, a pair of n-type semiconductor regions 17 which are a source region and a drain region. In other words, the driving MOSFET Qd2 is composed of an n-channel conductivity type and has a single drain structure. The gate electrode 13 of the drive MOSFET Qt2 is formed in the same process as the gate electrode 13 of the transfer MOSFET Qt1 described above.

  Although not shown in the drawing, the driving MOSFET Qd1 is configured in the same manner as the driving MOSFET Qd2.

  The load TFT Qf1 includes a channel formation region, a gate insulating film, a gate electrode, a source region, and a drain region. The gate electrode is composed of a polysilicon pattern 28 made of a third-layer polycrystalline silicon film. The channel formation region, the source region, and the drain region are formed in a polysilicon pattern 25 made of a second-layer polycrystalline silicon film. The gate insulating film is composed of an interlayer insulating film 26 formed between the second-layer polysilicon pattern 25 and the third-layer polysilicon pattern 28. Note that the second layer polysilicon pattern 25 is electrically isolated from the gate electrode 13 by the interlayer insulating film 23.

  Although not shown in the figure, the load TFT Qf2 is configured in the same manner as the load TFT Qf1.

  The operation power supply wiring 25A is composed of a second-layer polysilicon pattern 25. The operation power supply wiring 25A is electrically connected to the source region of the load TFT Qf1 formed in the second-layer polysilicon pattern 25. The operation power supply wiring 25B is composed of a second-layer polysilicon pattern 25. The operation power supply wiring 25B is electrically connected to the source region of the load TFT Qf2 formed in the second-layer polysilicon pattern 25.

The capacitive element C1, a laminated structure (STC Structure: St acked C apacitor) stacked lower electrode, a dielectric film, the respective upper electrode sequentially is composed of. The lower electrode is composed of a polysilicon pattern 28 made of a third-layer polycrystalline silicon film, and is also used as the gate electrode of the load TFT Qf2. The upper electrode is composed of a polysilicon pattern 31 made of a fourth-layer polycrystalline silicon film, and also serves as a reference power supply wiring (31A). The dielectric film is composed of an interlayer insulating film 29 formed between the third-layer polysilicon pattern 28 and the fourth-layer polysilicon pattern 31. The interlayer insulating film 29 is made of, for example, a silicon oxide film.

The capacitive element C2, the laminated structure (STC Structure: St acked C apacitor) stacked lower electrode, a dielectric film, the respective upper electrode sequentially is composed of. The lower electrode is composed of the third-layer polysilicon pattern 28, and is also used as the gate electrode of the load TFT Qf1. The upper electrode is composed of the fourth-layer polysilicon pattern 31 and is also used as the reference power supply wiring (31A). The dielectric film is composed of an interlayer insulating film 29 formed between the third-layer polysilicon pattern 28 and the fourth-layer polysilicon pattern 31.

The second-layer polycrystalline silicon film (polysilicon pattern 25) is set to a thickness of about 40 [nm], for example. The third-layer polycrystalline silicon film (polysilicon pattern 28) is set to a thickness of about 50 [nm], for example. The fourth-layer polycrystalline silicon film (polysilicon pattern 31) is set to a thickness of about 150 [nm] (that is, 0.15 [μm]), for example. That is, the semiconductor integrated circuit device of the present embodiment has a four-layer polysilicon structure, and is intermediate between the fourth-layer polycrystalline silicon film 31 and the first-layer polycrystalline silicon film 11 which are the uppermost layers. The thickness of each of the second-layer polycrystalline silicon film 25 and the third-layer polycrystalline silicon film 28 is half the thickness of the fourth-layer polycrystalline silicon film 31 that is the uppermost layer. It is set as follows. The depth of the n + -type semiconductor region 32 which is an emitter region is configured to be about 0.05 [μm], and the total emitter depth is obtained by combining the depth of the emitter region 32 and the thickness of the emitter electrode 31B. Is composed of 0.2 [μm] or more. As a result, the base current (I _B ) of the bipolar transistor Tr can be reduced, and the emitter ground current gain (h _FE = I _C / I _B ) of the bipolar transistor Tr can be improved. That is, the performance of the bipolar transistor Tr can be improved.

  The transfer MOSFETs Qt1 and Qt2 and the drive MOSFETs Qd1 and Qd2 configured as described above are arranged as shown in FIG. 4 (planar layout diagram), and the load TFTs Qf1 and Qf2 and the operation power supply wirings 25A and 25B are shown in FIG. 5 (planar layout diagram), and capacitive elements C1, C2 and reference power supply wiring 31A are arranged as shown in FIG. 6 (planar layout diagram). 4 to 6, the II-II line corresponds to the cross-sectional view in the memory cell formation region of FIG.

  One polysilicon pattern 28 of the third layer passes through the connection hole 27 shown in FIGS. 1, 5, and 7 (planar layout diagrams), and the polysilicon layer 28 of the second layer, which is the drain region of the load TFT Qf1. The silicon pattern 25, the gate electrode 13 of the driving MOSFET Qd2, the n + type semiconductor region 17 which is the drain region of the driving MOSFET Qd1, and one n + type semiconductor region 20 of the transfer MOSFET Qt1 are electrically connected. That is, the lower electrode (polysilicon pattern 28) of the capacitive element C1, the gate electrode (polysilicon pattern 28) of the load TFT Qf2, the gate electrode 13 of the drive MOSFET Qd2, the drain region (polysilicon pattern 25) of the load TFT Qf1, the drive The drain region of the MOSFET Qd1 and the one n + type semiconductor region 20 of the transfer MOSFET Qt1 are electrically connected through one connection hole 27.

  The other polysilicon pattern 28 of the third layer passes through the connection hole 27 shown in FIGS. 5 and 7, and the other polysilicon pattern 25 of the second layer, which is the drain region of the load TFT Qf2, and the driving MOSFET Qd1. The gate electrode 13, the n + type semiconductor region 17 which is the drain region of the driving MOSFET Qd2, and one n + type semiconductor region 20 of the transfer MOSFET Qt2 are electrically connected. That is, the lower electrode of the capacitive element C2 (polysilicon pattern 28), the gate electrode of the load TFT Qf1 (polysilicon pattern 28), the gate electrode 13 of the drive MOSFET Qd1, the drain region of the load TFT Qf2 (polysilicon pattern 25), the drive The drain region of the MOSFET Qd2 and the one n + -type semiconductor region 20 of the transfer MOSFET Qt2 are electrically connected through one connection hole 27. In FIG. 7, the II-II line corresponds to the cross-sectional view in the memory cell formation region of FIG.

  As shown in FIG. 6, the fourth-layer polysilicon pattern 31 covers the second-layer polysilicon pattern 25 and the third-layer polysilicon pattern 28. That is, each of the second-layer polycrystalline silicon film 25 and the third-layer polycrystalline silicon film 28 is covered with the fourth-layer polycrystalline silicon film 31 in the memory cell formation region.

  As shown in FIGS. 1 and 6, a first-layer metal wiring 35 is electrically connected to the fourth-layer polysilicon pattern 31 through a connection hole 34 formed in the interlayer insulating film 33. Yes. That is, the reference power supply wiring (polysilicon pattern 31) 31A is lined for each memory cell by the metal wiring 35 formed in the upper layer.

As shown in FIGS. 1 and 2, an interlayer insulating film 36 is formed on the first-layer metal wiring 35. Interlayer insulating film 36 is formed of a silicon oxide film deposited by CVD, for example (C hemical V apor D eposition) .

On the interlayer insulating film 36, as shown in FIGS. 1 and 8 (planar layout diagrams), data lines DL1 and DL2 which are second-layer metal wirings are formed. Each of the data lines DL1 and DL2 is formed of, for example, an aluminum film or an aluminum alloy film. In FIG. 8, the II-II line corresponds to the cross-sectional view in the memory cell formation region of FIG.
Each of the data lines DL1 and DL2 is covered with a final protective film 37. This final protective film 37 is formed of, for example, a silicon nitride film.

  As shown in FIG. 6, the polysilicon pattern 31 of the fourth layer has a through hole for allowing hydrogen released from the silicon nitride film (final protective film 37) formed thereon to permeate the lower layer. 31C is provided. The through hole 31C is formed on the load TFTs Qf1 and Qf2.

  As shown in FIGS. 1 and 7, the polysilicon pattern 31 is electrically connected to the n + type semiconductor region 17 which is the source region of the driving MOSFET Qd1 through the connection hole 30A, and is used for driving through the connection hole 30A. It is electrically connected to the n + type semiconductor region 17 which is the source region of the MOSFET Qd2.

Next, a method for manufacturing the semiconductor integrated circuit device will be described with reference to the drawings.
First, a p − type semiconductor substrate 1A is prepared.

  Next, a deep n − type semiconductor region 2 and a shallow p type semiconductor region 4A are formed on the main surface of the memory cell formation region of the p − type semiconductor substrate 1A, and a shallow n + type semiconductor region 3A and nMOS are formed on the main surface of the bipolar formation region. A shallow p-type semiconductor region 4B is selectively formed on the main surface of the formation region, and a shallow n + -type semiconductor region 3B is selectively formed on the main surface of the pMOS formation region.

  Next, an epitaxial layer 1B is grown on the main surface of the p − type semiconductor substrate 1A by an epitaxial growth method. In this step, deep buried n − type semiconductor region 2, shallow buried p type semiconductor regions 4A and 4B, and shallow buried n + type semiconductor regions 3A and 3B are formed.

  Next, an n-type well region 5A is formed on the main surface of the buried n + -type semiconductor region 3A, a p-type well region 6A is formed on the main surface of the buried p-type semiconductor region 4A, and the buried type An n type well region 5B is selectively formed on the main surface of the n + type semiconductor region 3B, and a p type well region 6B is selectively formed on the main surface of the buried p type semiconductor region 4B.

Next, a field insulating film 7 is formed on the main surface of the epitaxial layer 1B by using a thermal oxidation method.
Next, an n + type semiconductor region 8 as a collector contact region is formed on the main surface of the n type well region 5A. Thereafter, a p-type semiconductor region (Burred-p) 9 is formed in the p-type well region 6A.
The manufacturing process so far is shown in FIG. 9 (main part sectional view) and FIG. 10 (main part sectional view).

  Next, a gate insulating film 10 is formed on the main surfaces of the p-type well region 6A, the n-type well region 5A, the p-type well region 6B, and the n-type well region 5B.

Next, a gate electrode 13 is formed on each main surface of the gate insulating film 10, and a cap insulating film 14 is formed on the upper surface of the gate electrode 13. The gate electrode 13 is formed of a first-layer polycrystalline silicon film 11 and a refractory metal film 12 stacked on the main surface thereof. The refractory metal film 12 is formed of, for example, a tungsten silicide (WSi ₂ ) film. The cap insulating film 14 is formed of, for example, a silicon oxide film deposited by the CVD method. The polycrystalline silicon film 11 of the first layer is set to a thickness of about 80 [nm], for example, the refractory metal film 12 is set to a thickness of about 80 [nm], and the cap insulating film 14 is set to, for example, 100 The film thickness is set to about [nm]. Note that each of the cap insulating film 14, the refractory metal film 12, and the polycrystalline silicon film 11 is processed using the same photoresist mask.

  Next, a pair of n-type semiconductor regions (n pocket regions) 15 are formed on the main surface of the n-type well region 5B, and a pair of p-type semiconductor regions 16 which are a source region and a drain region are formed. Each of the pair of n-type semiconductor regions 15 and the pair of p-type semiconductor regions 16 is formed in self-alignment with the gate electrode 13.

Next, a pair of deep n-type semiconductor regions 17 that are a source region and a drain region are formed on the main surface of the driving MOS formation region of the p-type well region 6A. Each of the pair of deep n-type semiconductor regions 17 is formed by introducing an n-type impurity (for example, phosphorus (P)) in a self-aligned manner with respect to the gate electrode 13. The deep n-type semiconductor region 17 can increase the mutual conductance gm of the driving MOSFET and can increase the overlap length of the drain region with respect to the gate electrode 13, so that the α-ray resistance can be increased. In this process, the driving MOSFETs Qd1 and Qd2 are almost completed.
The manufacturing process up to this point is shown in FIG. 11 (main part sectional view) and FIG. 12 (main part sectional view).

Next, a pair of n-type semiconductor regions 18 as a source region and a drain region are formed on the main surface of the transfer MOS formation region of the p-type well region 6A, and the source region and the p-type well region 6B are formed on the main surface. A pair of n-type semiconductor regions 18 which are drain regions are formed. Each of the pair of n-type semiconductor regions 18 is formed by introducing an n-type impurity (for example, P) in a self-aligned manner with respect to the gate electrode 13.
The manufacturing process up to this point is shown in FIG. 13 (main part sectional view) and FIG. 14 (main part sectional view).

  Next, a side wall spacer 19 is formed on the side wall surface of the gate electrode 13. The side wall spacer 19 is formed by forming an insulating film made of, for example, a silicon oxide film on the entire surface of the epitaxial layer 1B including the gate electrode 13 and then anisotropically etching the insulating film.

  Next, a pair of n + -type semiconductor regions 20 as a source region and a drain region are formed on the main surface of the transfer MOS formation region of the p-type well region 6A, and a source region and a drain region are formed on the main surface of the p-type well region 6B. Each of the pair of n + -type semiconductor regions 20 is formed. Each of the pair of n + -type semiconductor regions 20 is formed by introducing an n-type impurity (for example, As) in a self-aligned manner with respect to the sidewall spacer 19. In this step, the n-channel MOSFET Qn and the transfer MOSFETs Qt1 and Qt2 are almost completed.

  Next, a pair of p + -type semiconductor regions 21 which are source and drain regions are formed on the main surface of the n-type well region 5B, and p-type which is a high-concentration base region is formed on the main surface of the n-type well region 5A. Each of the + type semiconductor regions 21 is formed. Each of the pair of p + -type semiconductor regions 21 is formed by introducing a p-type impurity (for example, B) in a self-aligned manner with respect to the sidewall spacer 19. The p + type semiconductor region 21 which is a high concentration base region is formed by selectively introducing p-type impurities. In this step, the p-channel MOSFET Qp is almost completed.

Next, a p-type semiconductor region 22 which is an intrinsic base region is formed on the main surface of the n-type well region 5A. The p-type semiconductor region 22 is formed by selectively introducing a p-type impurity (for example, BF ₂ ).
The manufacturing process so far is shown in FIG. 15 (main part sectional view) and FIG. 16 (main part sectional view).

  Next, an interlayer insulating film 23 is formed on the entire surface of the epitaxial layer 1B. The interlayer insulating film 23 is formed of a silicon oxide film set to a thickness of about 100 [nm], for example.

  Next, a connection hole 24 is formed in the interlayer insulating film 23 to expose a part of the surface of the n + type semiconductor region 21 which is the source region of the p-channel MOSFET Qp.

  Next, a second-layer polycrystalline silicon film 25 is formed on the entire surface of the interlayer insulating film 23 including the connection hole 24. The polycrystalline silicon film 25 of the second layer is set to a thickness of about 40 [nm], for example.

Next, a p-type impurity (for example, BF ₂ ) is selectively introduced into an area around the polycrystalline silicon film 25 excluding the TFT formation area by an ion implantation method.
The manufacturing process so far is shown in FIG. 17 (main part sectional view) and FIG. 18 (main part sectional view).

  Next, the polycrystalline silicon film 25 is patterned to form two polysilicon patterns 25. One polysilicon pattern 25 is used as the operation power supply wiring 25A, and is also used as a channel formation region, a source region, and a drain region of the load MOSFET Qf1. The other polysilicon pattern 25 is used as the operation power supply wiring 25B and is used as a channel formation region, a source region, and a drain region of the load MOSFET Qf2. The planar layout of the two polysilicon patterns 25 is as shown in FIG.

Next, the source region and drain region of the TFT Qf 1 are formed in the one polysilicon pattern 25, and the source region and drain of the TFT Qf 2 are formed in the other polysilicon pattern 25. These source and drain regions are formed by selectively introducing a p-type impurity (for example, BF ₂ ) by an ion implantation method.
The manufacturing process so far is shown in FIG. 19 (main part sectional view) and FIG. 20 (main part sectional view).

  Next, an interlayer insulating film 26, which is the gate insulating film of each of the TFTs Qf1 and Qf2, is formed on the entire surface of the epitaxial layer 1B including the polysilicon pattern 25. The interlayer insulating film 26 is formed of a silicon oxide film set to a thickness of about 40 [nm], for example.

  Next, the drain region of the one polysilicon pattern 25, the gate electrode 13 of the driving MOSFET Qt2, the n + type semiconductor region 17 which is the drain region of the driving MOSFET Qd1, and the n + type semiconductor region 20 of one of the transfer MOSFET Qt1 A connection hole 27 exposing a part of each surface is formed, and the drain region of the other polysilicon pattern 25, the gate electrode 13 of the driving MOSFET Qt1, and the n + type semiconductor region 17 which is the drain region of the driving MOSFET Qd2. Then, a connection hole 27 for exposing a part of the surface of each of the n + type semiconductor regions 20 of the transfer MOSFET Qt2 is formed.

  Next, a third-layer polycrystalline silicon film 28 is formed on the entire surface of the interlayer insulating film 26 including the connection holes 27. The polycrystalline silicon film 28 is set to a thickness of about 50 [nm], for example.

Next, the polycrystalline silicon film 28 is patterned to form a polysilicon pattern 28 which is the gate electrode of the transfer TFT Qf1 and the lower electrode of the capacitive element C1, and is also the gate electrode of the transfer TFT Qf2. Then, a polysilicon pattern 28 which is a lower electrode of the capacitive element C2 is formed. In this step, each of the transfer TFTs Qf1 and Qf2 is almost completed. The planar layout of the two polysilicon patterns 28 is as shown in FIG.
The manufacturing process so far is shown in FIG. 21 (main part sectional view) and FIG. 22 (main part sectional view).

  Next, an interlayer insulating film 29 that is a dielectric film of each of the capacitive elements C1 and C2 is formed on the entire surface of the interlayer insulating film 26 including the polysilicon pattern 28. The interlayer insulating film 29 is formed of a silicon oxide film set to a thickness of about 20 [nm], for example.

  Next, a connection hole 30A for exposing a part of the surface of the n + type semiconductor region 17 which is the source region of the driving MOSFET Qd1, and a part of the surface of the n + type semiconductor region 17 which is the source region of the driving MOSFET Qd2. Each of the connection holes 30A for exposing the p-type semiconductor region 22 is formed, and an emitter opening 30B for exposing a part of the surface of the p-type semiconductor region 22 as the intrinsic base region is formed.

  Next, a fourth-layer polycrystalline silicon film 31 is formed on the entire surface of the interlayer insulating film 29 including the connection hole 30A and the emitter opening 30B. The polycrystalline silicon film 31 is set to a thickness of about 150 [nm], for example. The polycrystalline silicon film 31 has n-type impurities (for example, P) or its deposition during the deposition for the purpose of reducing the resistance value and forming the emitter region (n + -type semiconductor region 32) of the bipolar transistor Tr. Later, an n-type impurity (for example, As) is introduced.

  Next, the polycrystalline silicon film 31 is patterned to form a polysilicon pattern 31 which is an upper electrode of each of the capacitive element C1 and the capacitive element C2 and is a reference power supply wiring (31A), and an emitter electrode. 31B is formed. The polysilicon pattern 31 covers the second-layer polysilicon pattern 25 and the third-layer polysilicon pattern 28 in the memory cell formation region. Further, the polysilicon pattern 31 is formed with a through hole 31C for allowing hydrogen released from the silicon nitride film formed in the upper layer to pass through the lower layer. The planar layout of the polysilicon pattern 31 is as shown in FIG. As will be described in the third embodiment, if the polysilicon pattern 31, the upper electrodes of the capacitors C1 and C2, and the reference power supply wiring (31A) are salicided except for the emitter electrode 31B, an Al shunt is necessary. The density can be increased and the density can be increased. Here, the reason for avoiding salicide formation of the emitter electrode 31B is to prevent an increase in base current.

Next, thermal diffusion treatment is performed to diffuse the n-type impurity introduced into the emitter electrode 31B into the main surface of the p-type semiconductor region 22 which is an intrinsic base region, and the depth of the emitter region is 0.05 [μm]. The n + -type semiconductor region 32 which is an emitter region is formed so as to reach a certain degree. By this step, the bipolar transistor Tr is almost completed.
The manufacturing process up to this point is shown in FIG. 23 (main part cross-sectional view) and FIG. 24 (main part cross-sectional view).

  Next, an interlayer insulating film 33 is formed on the entire surface of the epitaxial layer 1B including the polysilicon pattern 31 and the emitter electrode 31B. This interlayer insulating film 33 is formed of, for example, a silicon oxide film deposited by the CVD method.

Next, a connection hole 34 exposing a part of the surface of the polysilicon pattern 31, a connection hole 34 exposing a part of the surface of the other n + type semiconductor region 20 of the transfer MOSFET Qt1, and the high-concentration base region A connection hole 34 that exposes a part of the surface of the p + -type semiconductor region 21, a connection hole 34 that exposes a part of the surface of the emitter electrode 31 B, and a part of the n + -type semiconductor region 8 that is a collector contact region A connection hole 34 that exposes the surface of the n + type semiconductor region 20, a connection hole 34 that exposes a part of the surface of one n + type semiconductor region 20 of the n-channel MOSFET Qn, and a part of the surface of the other n + type semiconductor region 20. The connection hole 34, the connection hole 34 exposing a part of the surface of one p + type semiconductor region 21 of the p-channel MOSFET Qp, and the part of the surface of the other p + type semiconductor region 21 A connection hole 34 or the like that exposes is formed.
The manufacturing process up to this point is shown in FIG. 25 (main part sectional view) and FIG. 26 (main part sectional view).

Next, a first-layer metal wiring 35 is formed on the interlayer insulating film 33. In this step, the reference power supply wiring (polysilicon pattern 31) 31A is backed for each memory cell M by the metal wiring 35 formed in the upper layer.
Next, an interlayer insulating film 36 is formed on the entire surface of the interlayer insulating film 33 including the metal wiring 35.

  Next, the data lines DL1 and DL2 which are second-layer metal wirings are formed on the interlayer insulating film 36, respectively.

  Next, a final protective film 37 is formed on the entire surface of the interlayer insulating film 36 including the data lines DL1 and DL2, so that the semiconductor integrated circuit device shown in FIGS. 1 and 2 is almost completed. The final protective film is formed of a silicon nitride film.

  When arsenic (As) is used as the n-type impurity in the formation process of the fourth-layer polycrystalline silicon film 31, the n + -type semiconductor region 32 having a steep concentration profile is formed by shallowing by subsequent heat treatment. Thus, the high performance of the bipolar transistor Tr can be achieved. In addition, when phosphorus (P) is used as the n-type impurity, the n-type impurity is uniformly distributed in the polycrystalline silicon film 31, and the connection resistance (contact resistance) in the connection between the base and the polycrystalline silicon film 31 is reduced. Therefore, the area occupied by the connection hole can be reduced, and the area occupied by the memory cell can be reduced by an amount corresponding thereto.

  Thus, according to the present embodiment, the following operational effects can be obtained.

  Since the polycrystalline silicon film 25 that is two layers below the uppermost layer used as the channel formation region of the load TETQf1 (or Qf2) and the operation power supply wiring 25A (or 25B) does not need to be thicker, it is 1 The underlying step of the lower polycrystalline silicon film 28 can be greatly reduced, and the amount of overetching when processing the lower polycrystalline silicon film 28 can be reduced. Accordingly, the interlayer insulating film 26 between the one lower polycrystalline silicon film 28 and the two lower polycrystalline silicon films 25 can be thinned, and the load TFT Qf1 using the interlayer insulating film 26 as a gate insulating film. (Or Qf2) can be improved in performance.

  Further, since the intermediate polycrystalline silicon films 25 and 28 are covered with the uppermost polycrystalline silicon film 31, the intermediate polycrystalline silicon film 31 and the lower polycrystalline silicon film 28 are disposed between the uppermost polycrystalline silicon film 31 and the polycrystalline silicon film 28. The interlayer insulating film 29 is not cut by overetching when the uppermost polycrystalline silicon film 31 is processed. Therefore, the interlayer insulating film 29 between the uppermost polycrystalline silicon film 31 and the lower polycrystalline silicon film 28 can be thinned, and the capacitive element C1 ( Alternatively, high performance of C2) can be achieved.

  Further, the underlying step of the etched portion of the uppermost polycrystalline silicon film 31 includes only the step due to the gate electrode 13 of the bulk MOSFET such as the driving MOSFETs Qd1 and Qd2, the transfer MOSFETs Qt1 and Qt2, and the step due to the field insulating film 7. Therefore, stable processing can be performed, and a processing margin of the memory cell can be ensured.

  Further, since the reference power supply wiring (31A) is formed by the uppermost polycrystalline silicon film 31, it depends on the arrangement of the polysilicon pattern 25, the polysilicon pattern 28 and the active region pattern made of the intermediate polycrystalline silicon film. Without this, the connection hole 34 for connecting the reference power supply wiring (31A) and the metal wiring 35 formed in the upper layer thereof can be arranged at an arbitrary position. Accordingly, since the ground parasitic resistance of the memory cell M can be reduced without increasing the area occupied by the memory cell M, the writing operation and the reading operation of the memory cell M can be stabilized.

  Further, hydrogen released from the final protective film 37 formed in the upper layer through the through hole 31C provided in the uppermost polycrystalline silicon film 31 can be transmitted to each of the load TFTs Qf1 and Qf2. The on / off characteristics of the TFTs Qf1 and Qf2 can be improved.

  Further, the lower electrode (polysilicon pattern 28) of the capacitive element C1, the gate electrode (polysilicon pattern 28) of the load TFT Qf2, the gate electrode 13 of the drive MOSFET Qd2, the drain region (polysilicon pattern 25) of the load TFT Qf1, the drive The drain region of the MOSFET Qd1 and the one n + type semiconductor region 20 of the transfer MOSFET Qt1 are electrically connected through one connection hole 27, the lower electrode (polysilicon pattern 28) of the capacitive element C2, and the load TFT Qf1. The gate electrode (polysilicon pattern 28), the gate electrode 13 of the driving MOSFET Qd1, the drain region of the load TFT Qf2 (polysilicon pattern 25), the drain region of the driving MOSFET Qd2, and one of the n + -type semiconductor regions 20 of the transfer MOSFET Qt2. 1 each Since the two connection holes 27 are electrically connected, the number of connection holes connecting the upper layer and the lower layer can be reduced, and the occupied area (cell size) of the memory cell M can be reduced correspondingly. Can do. In addition, since the routing wiring (in-cell wiring) for electrically connecting the elements can be simplified, the writing operation and the reading operation of the memory cell can be speeded up.

(Embodiment 2)
A schematic configuration of a semiconductor integrated circuit device according to the second embodiment of the present invention is shown in FIG. 27 (main part cross-sectional view) and FIG. In FIG. 27 and FIG. 28, the hatching (parallel oblique lines) of the cross section is omitted for easy understanding of the drawing.

  As shown in FIGS. 27 and 28, the semiconductor integrated circuit device mainly includes, for example, a semiconductor substrate in which an epitaxial layer 1B is formed on the main surface of a p − type semiconductor substrate 1A. A memory cell M is mounted in the memory cell formation region of the semiconductor substrate, a bipolar transistor Tr is mounted in the bipolar formation region, an n-channel MOSFET Qn is mounted in the nMOS formation region, and a p-channel MOSFET Qp is mounted in the pMOS formation region. It is installed.

  As shown in FIG. 27, the n-channel MOSFET Qn is formed on the main surface of a p-type well region 6B whose periphery is defined by a field insulating film 7. An electrode 31N is electrically connected to each of the pair of n + -type semiconductor regions 20 which are the source region and the drain region of the n-channel MOSFET Qn, and the electrode 31N is wired through a connection hole 34 formed in the interlayer insulating film 33. 35 is electrically connected. The electrode 31N is formed of a fourth-layer polycrystalline silicon film. The wiring 35 is formed of a first layer metal film. Although the first-layer metal film is not shown, for example, a lower titanium tungsten (TiW) film (or titanium nitride (TiN) film), an intermediate aluminum alloy film, an upper TiW film (or (TiN film) is formed in a three-layer structure in which the respective layers are sequentially stacked. The lower TiW film is formed mainly for the purpose of improving electromigration resistance and stress migration resistance. The aluminum alloy film of the intermediate layer is formed of, for example, an aluminum alloy film to which Cu is added for the purpose of improving electromigration resistance and Si is added for the purpose of reducing mutual diffusion between aluminum particles and silicon particles. Is done. The upper TiW film is formed mainly for the purpose of preventing aluminum hill rocks generated on the surface of the intermediate aluminum alloy film and reducing the reflectivity of the surface of the intermediate aluminum alloy film.

  As shown in FIG. 27, the p-channel MOSFET Qp is formed on the main surface of an n-type well region 5B whose periphery is defined by a field insulating film 7. In each of the pair of p + -type semiconductor regions 21 which are the source region and the drain region of the p-channel MOSFET Qp, a wiring 35 made of a first-layer metal film is electrically connected through a connection hole 34 formed in the interlayer insulating film 33. It is connected to the. Further, in the p + type semiconductor region 21 on the source side of the p channel MOSFET Qp adjacent to the memory cell array, a polysilicon pattern 25 made of a second layer of polycrystalline silicon is electrically connected through a connection hole (not shown). Connected and Vcc power is supplied to the memory cell.

  Each gate electrode 13 of the n-channel MOSFET Qn and the p-channel MOSFET Qp is formed of a first-layer polycrystalline silicon film 11 and a refractory metal film 12 formed on the main surface thereof. The refractory metal film 12 is formed of, for example, a tungsten silicide (WSix) film. The upper surfaces of these gate electrodes 13 are covered with a cap insulating film.

  As shown in FIG. 28, the bipolar transistor Tr is formed on the main surface of an n-type well region 5A whose periphery is defined by a field insulating film 7. The bipolar transistor Tr is an npn type in which an n-type emitter region, a p-type base region, and an n-type collector region are sequentially arranged from the main surface of the n-type well region 5A (epitaxial layer 1B) in the depth direction. It is configured.

  A wiring 35 made of a first-layer metal film is electrically connected to the n + -type semiconductor region 8 which is a collector contact region of the n-type collector region through a connection hole 34 formed in the interlayer insulating film 33. Yes.

  A wiring 35 made of a first-layer metal film is electrically connected to the p + -type semiconductor region 21, which is a high-concentration base region of the p-type base region, through a connection hole 34 formed in the interlayer insulating film 33. ing.

  An emitter electrode (31B) is electrically connected to the n + -type semiconductor region 32, which is the n-type emitter region, through an emitter opening 30B. The emitter electrode (31B) is formed of a polycrystalline silicon film 31 of the fourth layer. The fourth-layer polycrystalline silicon film 31 has an n-type impurity (for example, P) during the deposition or an n-type impurity after the deposition for the purpose of reducing the resistance value and forming the n + -type semiconductor region 32. (For example, As) is introduced. That is, the n + -type semiconductor region 32 that is the emitter region is formed by diffusing the n-type impurity introduced into the emitter electrode 31 B into the main surface of the p-type semiconductor region 22. A wiring 35 made of a first-layer metal film is electrically connected to the emitter electrode 31B through a connection hole 34 formed in the interlayer insulating film 33.

  As shown in FIG. 3 (equivalent circuit diagram), the memory cell M includes a flip-flop circuit composed of two inverter circuits and two transfer MOSFETs Qt1 and Qt2. One inverter circuit includes a driving MOSFET Qd1 and a load TFT Qf1. The other inverter circuit is composed of a driving MOSFET Qd2 and a load TFT Qf2.

  The transfer MOSFET Qt1 is disposed between the storage node (storage node) part A of the flip-flop circuit and the data line DL1, and its operation is controlled by the word line WL. The transfer MOSFET Qt2 is arranged between the storage node (storage node) part B of the flip-flop circuit and the data line DL2, and its operation is controlled by the word line WL. One semiconductor region of the transfer MOSFET Qt1 is connected to the storage node portion A, the other semiconductor region is connected to the data line DL1, and its gate electrode is connected to the word line WL. One semiconductor region of the transfer MOSFET Qt2 is connected to the storage node portion B, the other semiconductor region is connected to the data line DL2, and its gate electrode is connected to the word line WL.

  The gate electrodes of the driving MOSFET Qd1 and the load TFT Qf1 are connected to the storage node portion B of the flip-flop circuit, and the gate electrodes of the driving MOSFET Qd2 and the load TFT Qf2 are connected to the storage node portion A of the flip-flop circuit. ing.

  An operating power supply wiring 25A fixed at an operating potential (for example, 3.3 [V]) Vcc is electrically connected to the source region of the load TFT Qf1. Further, an operation power supply wiring 25B fixed to the operation potential Vcc is electrically connected to the source region of the load TFT Qf2.

  A reference power supply line 31A fixed to a reference potential (for example, 0 [V]) Vss is electrically connected to the source regions of the driving MOSFETs Qd1 and Qd2.

  A capacitor element C1 is added to the storage node portion A of the flip-flop circuit. A capacitor element C2 is added to the storage node portion B of the flip-flop circuit.

  As shown in FIG. 27, the transfer MOSFET Qt1 is formed on the main surface of a p-type well region 6A whose periphery is defined by a field insulating film 7. The gate electrode 13 of the transfer MOSFET Qt1 is formed in the same process as the gate electrode 13 of the aforementioned n-channel MOSFET Qn. A wiring 35M made of a first-layer metal film is electrically connected to the other n + -type semiconductor region 20 of the transfer MOSFET Qt1 through a connection hole 34 formed in the interlayer insulating film 33.

  Although not shown in the figure, the transfer MOSFET Qt2 is configured in the same manner as the transfer MOSFET Qt1.

  Although not shown in detail in the drawing, the driving MOSFET Qd2 is formed on the main surface of the p-type well region 6A whose periphery is defined by the field insulating film 7. The gate electrode 13 of the driving MOSFET Qd2 is formed in the same process as the gate electrode 13 of the transfer MOSFET Qt1 described above.

  Although not shown in the drawing, the driving MOSFET Qd1 is configured in the same manner as the driving MOSFET Qd2.

  The load TFT Qf1 includes a channel formation region, a gate insulating film, a gate electrode, a source region, and a drain region. The gate electrode is composed of a polysilicon pattern 28 made of a third-layer polycrystalline silicon film. The channel formation region, the source region, and the drain region are formed in a polysilicon pattern 25 made of a second-layer polycrystalline silicon film. The gate insulating film is composed of an interlayer insulating film 26 formed between the second-layer polysilicon pattern 25 and the third-layer polysilicon pattern 28. Note that the second layer polysilicon pattern 25 is electrically isolated from the gate electrode 13 by the interlayer insulating film 23.

  Although not shown in the figure, the load TFT Qf2 is configured in the same manner as the load TFT Qf1.

  The operation power supply wiring 25A is composed of a second-layer polysilicon pattern 25. The operation power supply wiring 25A is electrically connected to the source region of the load TFT Qf1 formed in the second-layer polysilicon pattern 25. The operation power supply wiring 25B is composed of a second-layer polysilicon pattern 25. The operation power supply wiring 25B is electrically connected to the source region of the load TFT Qf2 formed in the second-layer polysilicon pattern 25.

The capacitive element C1, a laminated structure (STC Structure: St acked C apacitor) stacked lower electrode, a dielectric film, the respective upper electrode sequentially is composed of. The lower electrode is composed of a polysilicon pattern 28 made of a third-layer polycrystalline silicon film, and is also used as the gate electrode of the load TFT Qf2. The upper electrode is composed of a polysilicon pattern 31 made of a fourth-layer polycrystalline silicon film, and also serves as a reference power supply wiring (31A). The dielectric film is composed of an interlayer insulating film 29 formed between the third-layer polysilicon pattern 28 and the fourth-layer polysilicon pattern 31. The interlayer insulating film 29 is made of, for example, a silicon oxide film.

The capacitive element C2, the laminated structure (STC Structure: St acked C apacitor) stacked lower electrode, a dielectric film, the respective upper electrode sequentially is composed of. The lower electrode is composed of the third-layer polysilicon pattern 28, and is also used as the gate electrode of the load TFT Qf1. The upper electrode is composed of the fourth-layer polysilicon pattern 31 and is also used as the reference power supply wiring (31A). The dielectric film is composed of an interlayer insulating film 29 formed between the third-layer polysilicon pattern 28 and the fourth-layer polysilicon pattern 31.

  The second-layer polycrystalline silicon film (polysilicon pattern 25) is set to a thickness of about 40 [nm], for example. The third-layer polycrystalline silicon film (polysilicon pattern 28) is set to a thickness of about 50 [nm], for example. The fourth-layer polycrystalline silicon film (polysilicon pattern 31) is set to a thickness of about 150 [nm] (that is, 0.15 [μm]), for example. That is, the semiconductor integrated circuit device of the present embodiment has a four-layer polysilicon structure, and is intermediate between the fourth-layer polycrystalline silicon film 31 and the first-layer polycrystalline silicon film 11 which are the uppermost layers. The thickness of each of the second-layer polycrystalline silicon film 25 and the third-layer polycrystalline silicon film 28 is half the thickness of the fourth-layer polycrystalline silicon film 31 that is the uppermost layer. It is set as follows.

  The transfer MOSFETs Qt1 and Qt2 and the drive MOSFETs Qd1 and Qd2 are arranged as shown in FIG. 29 (planar layout diagram), and load TFTs Qf1 and Qf2, operating power supply wirings 25A and 25B, capacitive elements C1 and C2, reference power supplies Each of the wirings 31A is arranged as shown in FIGS. 30 and 31 (planar layout diagrams). 29 to 31, the line III-III corresponds to the cross-sectional view in the memory cell formation region of FIG.

  One polysilicon pattern 28 of the third layer passes through the connection hole 27 shown in FIGS. 27, 29 and 30 (planar layout diagrams), and one polysilicon pattern of the second layer which is the drain region of the load TFT Qf1. The silicon pattern 25, the gate electrode 13 of the driving MOSFET Qd2, the n + type semiconductor region 17 which is the drain region of the driving MOSFET Qd1, and one n + type semiconductor region 20 of the transfer MOSFET Qt1 are electrically connected. That is, the lower electrode (polysilicon pattern 28) of the capacitive element C1, the gate electrode (polysilicon pattern 28) of the load TFT Qf2, the gate electrode 13 of the drive MOSFET Qd2, the drain region (polysilicon pattern 25) of the load TFT Qf1, the drive The drain region of the MOSFET Qd1 and the one n + type semiconductor region 20 of the transfer MOSFET Qt1 are electrically connected through one connection hole 27.

  The other polysilicon pattern 28 of the third layer passes through the connection hole 27 shown in FIGS. 29 and 30, and the second polysilicon pattern 25 of the second layer, which is the drain region of the load TFT Qf2, and the driving MOSFET Qd1. The gate electrode 13, the n + type semiconductor region 17 which is the drain region of the driving MOSFET Qd2, and one n + type semiconductor region 20 of the transfer MOSFET Qt2 are electrically connected. That is, the lower electrode of the capacitive element C2 (polysilicon pattern 28), the gate electrode of the load TFT Qf1 (polysilicon pattern 28), the gate electrode 13 of the drive MOSFET Qd1, the drain region of the load TFT Qf2 (polysilicon pattern 25), the drive The drain region of the MOSFET Qd2 and the one n + -type semiconductor region 20 of the transfer MOSFET Qt2 are electrically connected through one connection hole 27.

  As shown in FIGS. 27 and 30, the fourth layer polysilicon pattern 31 covers the second layer polysilicon pattern 25 and the third layer polysilicon pattern 28. That is, each of the second-layer polycrystalline silicon film 25 and the third-layer polycrystalline silicon film 28 is covered with the fourth-layer polycrystalline silicon film 31 in the memory cell formation region.

  As shown in FIG. 27, the fourth-layer polysilicon pattern 31 is electrically connected to a wiring 35L made of a first-layer metal film through a connection hole 34 formed in the interlayer insulating film 33. Yes. That is, the reference power supply wiring (polysilicon pattern 31) 31A is lined for each memory cell by the wiring 35L formed in the upper layer.

  As shown in FIG. 27, an interlayer insulating film 36 is formed on the first layer wiring 35L. On the interlayer insulating film 36, as shown in FIGS. 27 and 32 (planar layout diagrams), data lines DL1 and DL2 made of a second-layer metal film are formed. Similarly to the first-layer metal film, the second-layer metal film is a lower-layer TiW film (or TiN film), an intermediate-layer aluminum alloy film, or an upper-layer TiW film (or TiN film). It is comprised by the 3 layer structure which laminated | stacked one by one. In FIG. 32, line III-III corresponds to a cross-sectional view in the memory cell formation region of FIG.

As shown in FIG. 27, an interlayer insulating film 38 is formed on each of the second-layer data lines DL1 and DL2. On the interlayer insulating film 38, as shown in FIGS. 27 and 32, divided word line and a third layer metal film (D evided W ord L ine) DWL, the main word line (G lobal W ord L ine) GWL is formed. Although not shown, the divided word line DWL is electrically connected to the word line WL integrated with the respective gate electrodes 13 of the transfer MOSFETs Qt1 and Qt2, and used as a backing wiring for the word line WL. ing. Similarly to the first-layer metal film, the third-layer metal film is a lower-layer TiW film (or TiN film), an intermediate-layer aluminum alloy film, or an upper-layer TiW film (or TiN film). It is comprised by the 3 layer structure which laminated | stacked sequentially.

  Each of the third layer divided word line DWL and the main word line GWL is covered with a final protective film 37 made of, for example, a silicon nitride film. That is, the semiconductor integrated circuit device of this embodiment is configured with a three-layer metal wiring structure.

  As shown in FIG. 32, one wiring 35M is electrically connected to the second layer data line DL2 through a connection hole 41 formed in the interlayer insulating film. The one wiring 35M is electrically connected to one n + type semiconductor region 20 of the transfer MOSFET Qt1. Further, as shown in FIG. 32, the other wiring 35M is electrically connected to the second-layer data line DL1 through the connection hole 41 formed in the interlayer insulating film 36. The other wiring 35M is electrically connected to one n + type semiconductor region 20 of the transfer MOSFET Qt2.

Although not shown, each of the interlayer insulating films 36 and 38 has, for example, a three-layer structure in which a lower silicon oxide film, an intermediate silicon oxide film, and an upper silicon oxide film are sequentially stacked. Yes. The lower silicon oxide film is formed by, for example, a plasma CVD method using tetraethoxysilane (TEOS) gas (organosilane) as a main source gas. The plasma CVD method using the TEOS gas can form a dense and high-quality silicon oxide film. A silicon oxide film of the intermediate layer, for example, planarization of the surface of the interlayer insulating film as a main purpose, SOG (S pin O n G lass) method, that is, coated with spin-coating method, then baked, the entire surface is etched back Processing is performed. Similar to the lower silicon oxide film, the upper silicon oxide film is formed by plasma CVD using TEOS gas. The interlayer insulating film 33 is, for example, a CVD silicon oxide film is formed by sequentially depositing a BPSG film (B oron P hospho S ilicate G lass).

  In the semiconductor integrated circuit device, as shown in FIG. 33 (equivalent circuit diagram), an electrostatic breakdown preventing circuit Cp is arranged in a connection path between the input external terminal BP1 and the internal circuit. Further, in the semiconductor integrated circuit device, as shown in FIG. 34 (equivalent circuit diagram), an electrostatic breakdown preventing circuit Cp is arranged in a connection path between the internal circuit and the output external terminal BP2. In the electrostatic breakdown prevention circuit Cp, excessive static electricity charged on a human body, a package or a device during an artificial handling or assembly process flows into the internal circuit as a surge current through each of the input external terminal BP1 and the output external terminal BP2. It is arranged for the purpose of preventing so-called electrostatic breakdown. The electrostatic breakdown preventing circuit Cp is generally composed of a protective resistance element R for smoothing a surge current and a MOSFET Qk for drawing the surge current to the substrate side.

  As shown in FIG. 28, the MOSFET Qk is formed on the main surface of a p-type well region 6B whose periphery is defined by a field insulating film 7. The MOSFET Qk is mainly composed of a channel formation region (p-type well region 6B), a gate insulating film 10, a gate electrode 13, a pair of n-type semiconductor regions 17 which are a source region and a drain region. That is, the MOSFET Qk has an n-channel conductivity type single drain structure, like the driving MOSFET Qd2. This single-drain MOSFET Qk can set the punch through breakdown voltage between the source region and the drain region to be lower than that of the LDD structure MOSFET, and can easily extract the surge current to the substrate side.

As shown in FIG. 35 (block diagram), the semiconductor integrated circuit device includes a control buffer circuit unit COB, an X address buffer circuit unit XAB, an input / output buffer circuit unit IOB, a Y address buffer circuit unit YAB, and a Y switch circuit unit YSW. , A predecoder circuit unit PDEC, a sense amplifier circuit unit SA, and two memory mats MAT. Between each of the two memory mats MAT main word driver circuit portion (G lobal W ord D river) GWD is disposed.

  A write enable signal, an output enable signal, a chip select signal, and the like are input to the control buffer circuit unit COB through an external terminal. An X address signal is input to the X address buffer circuit unit XAB through an external terminal. Input / output signals are input to the input / output buffer circuit IOB through an external terminal. A Y address signal is input to the Y address buffer circuit YAB through an external terminal.

Each of the two memory mats MAT is composed of four memory blocks MB as shown in FIG. 35 and FIG. 36 (enlarged block diagram of the main part of FIG. 35). Of the four memory blocks MB, between the memory blocks MB1 and Memoribumekku MB2 disposed divided word driver circuit portion (D evided W ord D river) DWD is, between the memory block MB3 and memory block MB4 The divided word driver circuit unit DWD is arranged.

  In each of the plurality of memory blocks MB, a plurality of the memory cells M are arranged. Each of the plurality of memory blocks MB is provided with a plurality of the aforementioned divided word lines DWL. Each of the plurality of divided word lines DWL extends in the X direction. A plurality of the aforementioned main word lines GWL are arranged in each of the plurality of memory blocks MB. Each of the plurality of main word lines GWL extends in the X direction across the memory blocks MB. In addition, although not shown, each of the plurality of memory blocks MB is provided with a plurality of the data lines DL1 and DL2 described above. Each of the plurality of data lines DL1 and DL2 extends in the Y direction.

  Next, the operation of the semiconductor integrated circuit device will be described with reference to FIGS. 35, 36 and 37 (enlarged block diagram of the principal part of FIG. 36).

When reading data (information) stored in the memory cell M, the main word driver circuit unit GWD selects the main word line GWL based on the logic of the output signal of the X address buffer circuit unit XAB. Each divided word line DWL is selected by taking the logic of the selected main word line GWL and the selection signal of the X address buffer circuit XAB through the predecoder circuit part PDEC by the divided word driver circuit part DWD. . On the other hand, the read address column is selected by the Y address buffer circuit unit YAB, the read state is set, and the memory cell M is selected. The read data of the memory cell M is amplified by the sense amplifier section AS through the data line and becomes an output signal through the input / output buffer circuit section IOB. Note that description of data writing is omitted.
Thus, according to the second embodiment, the same effects as those of the first embodiment can be obtained.

(Embodiment 3)
A schematic configuration of a semiconductor integrated circuit device according to the third embodiment of the present invention is shown in FIG. 38 (main part sectional view) and FIG. 39 (main part sectional view). 38 and 39, the cross-sectional hatching (parallel oblique lines) is omitted for easy understanding of the drawing.

  As shown in FIGS. 38 and 39, the semiconductor integrated circuit device according to the present embodiment has a two-layer metal wiring structure. The wiring 35 is formed of a first layer metal film. Each of the data lines DL1 and DL2 shown in FIGS. 38 and 40 (planar layout diagrams) is formed of a first-layer metal film. Each of the divided word line DWL and the main word line GWL is formed of a second-layer metal film.

  In the memory cell formation region of the semiconductor integrated circuit device, as shown in FIGS. 38 and 41 (planar layout diagrams), a silicide layer 31S is formed on the surface of the reference power supply line 31A. That is, the reference power supply line 31A is formed of the fourth-layer polycrystalline silicon film 31 and the silicide layer 31S formed on the surface thereof. Each upper electrode of the capacitive elements C1 and C2 is formed of a fourth-layer polycrystalline silicon film 31 and a silicide layer 31S formed on the surface thereof. Note that the silicide layer 31S is not formed on the surface of the emitter electrode 31B of the bipolar transistor Tr.

  As shown in FIG. 42 (planar pattern diagram), the reference power supply line 31A is formed over the entire area of the memory block MB, and the reference power supply line 31A is electrically connected to the other semiconductor region of the transfer MOSFET and the data line. A slit 50 is provided for connection.

  As shown in FIG. 42, the silicide layer 31S is formed in the entire region except for the edge of the reference power supply wiring 31A (region in the vicinity of the slit 50).

  Next, a method for manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. 43 to 48, the hatching of the cross section (parallel oblique lines) is omitted for easy understanding of the drawing.

  First, in the same manufacturing process as that of the first embodiment, the n-channel MOSFET Qn, the p-channel MOSFET Qp, the transfer MOSFETs Qt1 and Qt2, the drive MOSFETs Qd1 and Qd2, and the reference power line 31A are formed on the main surface of the p − type semiconductor substrate 1A. , Load TFTs Qf1 and Qf2, capacitive elements C1 and C2, bipolar transistor Tr, and MOSFET Qk of an electrostatic breakdown preventing circuit are formed. The manufacturing process so far is shown in FIGS.

  Next, a thin insulating film (dielectric film of the capacitive element C) 39 is formed on the entire surface of the substrate including the surface of the reference power supply wiring 31A and the surface of the emitter electrode 31B of the bipolar transistor Tr. The insulating film 39 is formed of, for example, a silicon oxide film.

  Next, a mask 40 having an opening in the region of the reference power supply wiring 31A is formed. The mask 40 is formed of, for example, a photoresist film. This mask 40 covers the edge (near the slit) of the reference power supply wiring 31A.

  Next, using the mask 40 as an etching mask, the insulating film 39 is patterned to remove the insulating film 39 on the reference power supply wiring 31A. In this step, the edge of the reference power line 31A is covered with an insulating film 39. The surface of the emitter electrode 31B of the bipolar transistor Tr is covered with an insulating film 39. The surfaces of the electrodes 31N of the n-channel MOSFET Qn and MOSFET Qk are covered with an insulating film 39. The steps up to here are shown in FIGS.

Next, the mask 40 is removed.
Next, a refractory metal film such as a titanium (Ti) film, a tungsten (W) film, or a molybdenum (Mo) film is formed on the entire surface of the substrate including the surface of the reference power supply wiring 31A. In the present embodiment, as the refractory metal film, for example, a Ti film is used and deposited by a sputtering method.

  Next, a low-temperature heat treatment of about 500 to 600 [° C.] is performed in a nitrogen atmosphere to react Si of the reference power supply wiring 31A and Ti of the refractory metal film, thereby forming a silicide layer on the surface of the reference power supply wiring 31A. 31S is formed. In this step, since the edge of the reference power line 31A is covered with the insulating film 39, the silicide layer 31S is not formed on the edge of the reference power line 31A. Further, since the surface of the emitter electrode 31B of the bipolar transistor Tr is covered with the insulating film 39, the silicide layer 31S is not formed on the surface of the emitter electrode 31B. That is, the silicide layer 31S is formed in a self-aligned manner with respect to the insulating film 39. At this time, the Ti film on the insulating film 39 becomes a TiNx film by the low-temperature heat treatment in the nitrogen atmosphere.

Next, the TiNx film on the insulating film 39 is selectively removed by, for example, a wet etching method.
Next, a high-temperature heat treatment of about 900 to 1000 [° C.] is performed to promote the reaction of the silicide layer 31S and to reduce the resistance of the silicide layer 31S. The sheet resistance of the silicide layer 31S is about 5Ω / □, and the sheet resistance of the polycrystalline silicon film 31 into which impurities are introduced is about 200Ω / □. In this silicidation, the entire thickness of the fourth-layer polycrystalline silicon film 31 is not silicided, but is silicided so that the polycrystalline silicon film 31 remains under the silicide layer 31S. That is, the silicide layer 31S is formed on the surface of the fourth-layer polycrystalline silicon film 31. When the entire thickness of the fourth-layer polycrystalline silicon film 31 is silicided, the film quality of the dielectric film 29 of the lower capacitive element may be deteriorated due to contamination or the like. By forming the silicide layer 31S on the fourth polycrystalline silicon film 31, deterioration of the dielectric film 29 due to silicidation can be prevented. The steps up to here are shown in FIGS.

Next, the interlayer insulating film 33, the connection hole 34, the wiring 35 made of the first-layer metal film, the data lines DL1 and DL2 made of the first-layer metal film, the interlayer insulating film 36, the divided word line DWL, the main By forming the word line GWL and the final protective film 37, the semiconductor integrated circuit device of this embodiment shown in FIGS. 38 and 39 is almost completed.
Thus, according to the third embodiment, the same effect as in the first embodiment can be obtained.

  Further, by forming the silicide layer 31S on the surface of the reference power supply line 31A, the resistance of the reference power supply line 31A can be reduced, so that the second layer metal film as in the second embodiment described above. It is not necessary to back the reference power supply wiring 31A with the wiring 35 made of the above, and the wiring 35 for backing can be eliminated. Therefore, the word lines DL1 and DL2 can be formed of the first layer metal film, and the divided word lines DWL and the main word line GWL can be formed of the second layer metal film. A layer metal wiring structure can be used. As a result, compared to the three-layer metal wiring structure, the number of manufacturing steps can be reduced by the amount corresponding to the one-layer interlayer insulating film (three-layer structure) and the one-layer metal film (three-layer structure). The yield of the semiconductor integrated circuit device can be increased.

  In the method of manufacturing a semiconductor integrated circuit device having a memory cell M and a bipolar transistor Tr in which a capacitive element C is added to a storage node portion of an inverter circuit composed of a driving MOSFET Qd and a load TFT Qf, the driving MOSFET Qd Connected to the source region (n + -type semiconductor region 17) of the capacitor transistor C and to the reference power supply wiring 31A that also serves as the upper electrode of the capacitive element C and to the emitter region (n + -type semiconductor region 32) of the bipolar transistor Tr. Forming an emitter electrode 31B with the uppermost polycrystalline silicon film 31, forming an insulating film 39 covering the edge of the reference power supply wiring 31A and the surface of the emitter electrode 31B, and the reference power supply wiring Forming a silicide layer 31S on the surface of 31A in a self-aligned manner with respect to the insulating film 39; Provided. Thereby, since the surface of the emitter electrode 31B is covered with the insulating film 39, the silicide layer 31S is not formed on the surface of the emitter electrode 31B. Since the silicide layer 31S is formed by the reaction between Si of the polycrystalline silicon film and metal atoms of the refractory metal film, when the silicide layer 31S is formed on the surface of the emitter electrode 31B, the substantial emitter electrode 31B is formed. The total emitter depth, which combines the depth of the emitter region and the thickness of the emitter electrode 31B, becomes shorter than the hole diffusion length. However, as described above, since the silicide layer 31S is not formed on the surface of the emitter electrode 31B, the total emitter depth can be made about twice or more the hole diffusion length, and the current amplification of the bipolar transistor Tr. The rate can be secured.

  Further, since the edge of the reference power supply wiring 31A is covered with the insulating film 39, the silicide layer 31S is not formed on the edge of the reference power supply wiring 31A. Therefore, the dielectric film between the upper electrode and the lower electrode of the capacitive element C can be prevented from being contaminated by the silicide layer 31S, so that the reliability of the capacitive element C can be improved.

(Embodiment 4)
A schematic configuration of a semiconductor integrated circuit device according to the fourth embodiment of the present invention is shown in FIG. 49 (main part sectional view) and FIG. 50 (main part sectional view). 49 and 50, illustration of cross-sectional hatching (parallel oblique lines) is omitted for easy understanding of the drawing.

  As shown in FIGS. 49 and 50, the semiconductor integrated circuit device according to the present embodiment has a two-layer metal wiring structure. The wiring 35 and the data line DL are formed of a first layer metal film. Further, each of the divided word line DWL and the main word line GWL is formed of a second-layer metal film.

  A silicide layer 31S is formed on the surface of the reference power supply wiring 31A. A silicide layer 31S is formed on the surface of the pair of n + type semiconductor regions 20 that are the source region and the drain region of the n-channel MOSFET Qn. A silicide layer 31S is formed on the surface of the pair of p + -type semiconductor regions 21 that are the source region and the drain region of the p-channel MOSFET Qp. A silicide layer 31S is formed on the surface of the other n + type semiconductor region 20 of the transfer MOSFET Qt. A silicide layer 31S is formed on the surface of the p + type semiconductor region 21 which is a high concentration base region of the bipolar transistor Tr and on the surface of the n + type semiconductor region 8 which is a collector contact region. Note that the silicide layer 31S is not formed on the surface of the emitter electrode 31B of the bipolar transistor Tr. Further, the silicide layer 31S is not formed on the surface of the pair of n-type semiconductor regions 17 which are the source region and the drain region of the MOSFET Qk of the electrostatic breakdown prevention circuit.

  Next, a method for manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. 51 to 54, illustration of cross-sectional hatching (parallel oblique lines) is omitted for easy understanding of the drawings.

  First, in the same manufacturing process as in the first embodiment, an n-channel MOSFET Qn, a p-channel MOSFET Qp, a transfer MOSFET Qt, a drive MOSFET Qd, a reference power supply wiring 31A, and a load TFT Qf are formed on the main surface of the p − type semiconductor substrate 1A. The capacitive element C, the bipolar transistor Tr, and the MOSFET Qk of the electrostatic breakdown prevention circuit are formed.

  Next, a thin insulating film 39 is formed on the entire surface of the substrate including the surface of the reference power line 31A and the surface of the emitter electrode 31B of the bipolar transistor Tr. The insulating film 39 is formed of, for example, a silicon oxide film.

  Next, a mask 40 is formed on the emitter electrode 31B of the bipolar transistor Tr, on the MOSFET Qk, and on the edge of the reference power line 31A.

  Next, patterning is performed using the mask 40 as an etching mask, and the surface of the n + type semiconductor region 20, the surface of the p + type semiconductor region 21, the surface of the n + type semiconductor region 20, and the n + type semiconductor. The surface of region 8 and the surface of reference power supply line 31A are exposed. In this step, the surface of the emitter electrode 31B of the bipolar transistor Tr and the surface of the pair of n-type semiconductor regions 17 that are the source region and drain region of the MOSFET Qk of the electrostatic breakdown prevention circuit are not exposed. The steps so far are shown in FIGS.

Next, the mask 40 is removed.
Next, on the surface of the n + type semiconductor region 20, on the surface of the p + type semiconductor region 21, on the surface of the n + type semiconductor region 20, on the surface of the n + type semiconductor region 8, and the surface of the reference power supply wiring 31A A refractory metal film is formed on the entire surface of the substrate including the top.

  Next, a low temperature heat treatment of about 500 to 600 [° C.] is performed in a nitrogen atmosphere to form a silicide layer 31S on the surface of each semiconductor region and the surface of the reference power supply wiring 31A. In this step, since the edge of the reference power line 31A is covered with the insulating film 39, the silicide layer 31S is not formed on the edge of the reference power line 31A. Further, since the surface of the emitter electrode 31B of the bipolar transistor Tr is covered with the insulating film 39, the silicide layer 31S is not formed on the upper surface of the emitter electrode 31B. Further, since the surface of the n-type semiconductor region 17 of the MOSFET Qk is covered with the insulating film 39, the silicide layer 31S is not formed on the surface of the n-type semiconductor region 17 of the MOSFET Qk. That is, the silicide layer 31S is formed in a self-aligned manner with respect to the insulating film 39. Further, the refractory metal film on the insulating film 39 becomes a metal nitride film by the low temperature heat treatment in the nitrogen atmosphere.

Next, the metal nitride film on the insulating film 39 is selectively removed by, for example, a wet etching method.
Next, a high-temperature heat treatment of about 900 to 1000 [° C.] is performed to promote the reaction of the silicide layer 31S and to reduce the resistance of the silicide layer 31S. The steps up to here are shown in FIGS.

Next, the interlayer insulating film 33, the connection hole 34, the wiring 35 made of the first layer metal film, the data line DL made of the first layer metal film, the interlayer insulating film 36, the divided word line DWL, the main word line By forming the GWL and the final protective film 37, the semiconductor integrated circuit device of this embodiment shown in FIGS. 49 and 50 is almost completed.
Thus, according to the fourth embodiment, the same effect as in the third embodiment described above can be obtained.

  Further, on the surface of the pair of n + type semiconductor regions 20 that are the source region and the drain region of the n channel MOSFET Qn, on the surface of the pair of p + type semiconductor regions 21 that are the source region and the drain region of the p channel MOSFET Qp, Silicide is formed on the surface of the other n + type semiconductor region 20 of the MOSFET Qt, on the surface of the p + type semiconductor region 21 which is the high concentration base region of the bipolar transistor Tr and on the surface of the n + type semiconductor region 8 which is the collector contact region. By forming the layer 31S, the sheet resistance and contact resistance of various diffusion layers can be reduced, so that the operation speed of the semiconductor integrated circuit device can be increased.

  Further, since the surface of the n-type semiconductor region 17 of the MOSFET Qk is covered with the insulating film 39, the silicide layer 31S is not formed on the surface of the n-type semiconductor region 17 of the MOSFET Qk. Therefore, since the resistance of the source region and the drain region of the MOSFET Qk can be prevented from being reduced, damage to the MOSFET Qk due to surge current concentration can be prevented.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

1 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention. It is principal part sectional drawing of the said semiconductor integrated circuit device. 2 is an equivalent circuit diagram of a memory cell mounted on the semiconductor integrated circuit device. FIG. FIG. 3 is a plan layout view of the memory cell. FIG. 3 is a plan layout view of the memory cell. FIG. 3 is a plan layout view of the memory cell. FIG. 3 is a plan layout view of the memory cell. FIG. 3 is a plan layout view of the memory cell. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the said semiconductor integrated circuit device. FIG. 3 is a plan layout view of a memory cell mounted on the semiconductor integrated circuit device. FIG. 3 is a plan layout view of the memory cell. FIG. 3 is a plan layout view of the memory cell. FIG. 3 is a plan layout view of the memory cell. FIG. 3 is an equivalent circuit diagram of an electrostatic breakdown preventing circuit mounted on the semiconductor integrated circuit device. FIG. 3 is an equivalent circuit diagram of an electrostatic breakdown preventing circuit mounted on the semiconductor integrated circuit device. It is a block diagram of the semiconductor integrated circuit device. It is a principal part enlarged block diagram of FIG. It is a principal part enlarged block diagram of FIG. It is principal part sectional drawing of the semiconductor integrated circuit device which is Embodiment 3 of this invention. It is principal part sectional drawing of the said semiconductor integrated circuit device. FIG. 3 is a plan layout view of a memory cell mounted on the semiconductor integrated circuit device. FIG. 3 is a plan layout view of the memory cell. FIG. 4 is a plan pattern diagram of a reference power supply wiring mounted on the semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is a top view of the reference power supply wiring mounted in the semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing of the semiconductor integrated circuit device which is Embodiment 4 of this invention. It is principal part sectional drawing of the said semiconductor integrated circuit device. It is a top view of the reference power supply wiring mounted in the semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. FIG. 6 is a correlation diagram showing a relationship between a power supply voltage and a soft error rate using a storage capacity of a memory cell mounted on a semiconductor integrated circuit device as a parameter.

Explanation of symbols

  1A ... p-type semiconductor substrate, 1B ... epitaxial layer, 2 ... buried n + type semiconductor region, 3A, 3B ... buried n + type semiconductor region, 4A, 4B ... buried p type semiconductor 5A, 5B ... n-type well region, 6A, 6B ... p-type well region, 7 ... field insulating film, 8 ... n + type semiconductor region, 9 ... p-type semiconductor region, 10 ... gate insulating film, 11 ... first First polycrystalline silicon film, 12 ... refractory metal film, 13 ... gate electrode, 14 ... cap insulating film, 15 ... n-type semiconductor region, 16 ... p-type semiconductor region, 17 ... n + type semiconductor region, 18 ... n-type semiconductor region, 19 ... sidewall spacer, 20 ... n + type semiconductor region, 21 ... p + type semiconductor region, 22 ... p-type semiconductor region, 23 ... interlayer insulating film, 24 ... connection hole, 25 ... second Polycrystalline silicon film, 25A, 25B ... operating power supply wiring, 26 ... interlayer break Edge film 27... Connection hole 28. Second layer polycrystalline silicon film 29. Interlayer insulating film 30 A. Connection hole 30 B Emitter opening 31. Fourth layer polycrystalline silicon film 31 A. Reference power supply wiring, 31B ... emitter electrode, 32 ... n + type semiconductor region, 33 ... interlayer insulating film, 34 ... connection hole, 35 ... first layer metal wiring, 36 ... interlayer insulating film, 37 ... final protective film, WL ... word line, DL1, DL2 ... data line, M ... memory cell, Qd1, Qd2 ... driving MOSFET, Qt1, Qt2 ... transfer MOSFET, Qf1, Qf2 ... load TFT, Tr ... bipolar transistor, Qn ... n channel MOSFET, Qp ... p-channel MOSFET

Claims (10)

A method of manufacturing a semiconductor integrated circuit device having a capacitive element and a MISFET,
Forming a lower electrode of the capacitive element on a semiconductor substrate;
Forming an upper electrode made of a silicon film on the lower electrode through a dielectric film of the capacitive element;
Forming an insulating film on the entire surface of the upper electrode and the substrate;
Patterning the insulating film to remove the insulating film on the upper electrode;
Forming a silicide on the upper electrode,
The MISFET includes a first MISFET and a second MISFET,
In the patterning of the insulating film, the surface of the semiconductor region that is the source region or drain region of the first MISFET is exposed, and the surface of the semiconductor region that is the source region or drain region of the second MISFET is the insulating layer. Done to cover the membrane,
A method of manufacturing a semiconductor integrated circuit device, wherein, in the silicide formation step, silicide is formed on a surface of the upper electrode and a surface of a semiconductor region of the first MISFET. In the manufacturing method of the semiconductor integrated circuit device according to claim 1,
The second MISFET constitutes a MISFET for preventing electrostatic breakdown,
The method of manufacturing a semiconductor integrated circuit device, wherein the first MISFET constitutes a memory cell. In the manufacturing method of the semiconductor integrated circuit device according to claim 1,
By patterning the insulating film, the insulating film remains on the edge of the upper electrode,
A method of manufacturing a semiconductor integrated circuit device, wherein the silicide is not formed on an edge of the upper electrode. A semiconductor integrated circuit device having a capacitive element and a MISFET,
The MISFET includes a first MISFET and a second MISFET,
A lower electrode of the capacitive element is formed on a semiconductor substrate;
An upper electrode made of a silicon film is formed on the lower electrode via a dielectric film of the capacitive element,
An insulating film is formed on the entire surface of the upper electrode and the substrate;
The insulating film is removed on the upper electrode, the surface of the semiconductor region which is the source region or drain region of the first MISFET is exposed, and the semiconductor region which is the source region or drain region of the second MISFET is exposed. Formed so that the surface is covered with the insulating film,
A semiconductor integrated circuit device, wherein silicide is formed on the upper electrode in a self-aligned manner with respect to the insulating film, and silicide is formed on a surface of a semiconductor region of the first MISFET. The semiconductor integrated circuit device according to claim 4,
The second MISFET constitutes a MISFET for preventing electrostatic breakdown,
The semiconductor integrated circuit device, wherein the first MISFET constitutes a memory cell. The semiconductor integrated circuit device according to claim 4,
A semiconductor integrated circuit device, wherein the insulating film is formed on the edge of the upper electrode, and the silicide is not formed. The semiconductor integrated circuit device according to claim 4,
A semiconductor integrated circuit device, wherein no silicide is formed on a surface of a semiconductor region of the second MISFET. In the manufacturing method of the semiconductor integrated circuit device according to claim 1,
A method of manufacturing a semiconductor integrated circuit device, wherein no silicide is formed on a surface of a semiconductor region of the second MISFET in the silicide formation step. The semiconductor integrated circuit device according to claim 4,
The MISFET includes a third MISFET,
The semiconductor integrated circuit device, wherein the capacitive element is formed on the third MISFET and connected to the third MISFET. In the manufacturing method of the semiconductor integrated circuit device according to claim 1,
The MISFET includes a third MISFET,
The method of manufacturing a semiconductor integrated circuit device, wherein the capacitive element is formed on the third MISFET and connected to the third MISFET.

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