JP3951648B2 - Multilayer electronic component and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer electronic component in which internal electrodes such as a multilayer capacitor and a multilayer inductor are connected by via holes, and a method for manufacturing the multilayer electronic component, and a wiring board on which the multilayer electronic component is mounted, and a multilayer electronic component. The present invention relates to a decoupling device and a high-frequency circuit provided.
[0002]
[Prior art]
For a capacitor used as a decoupling capacitor such as an MPU, an equivalent series inductance (ESL) is a problem.
[0003]
In order to solve such problems, a multilayer capacitor with reduced ESL is disclosed in Japanese Patent Laid-Open No. 11-204372.
[0004]
FIG. 7A is a perspective view showing the internal structure of a conventional multilayer capacitor, and FIG. 7B is a cross-sectional view showing the internal structure.
FIG. 8 is a plan view of the first internal electrode formation layer showing the internal structure of the multilayer capacitor.
FIG. 9 is a plan view of a second internal electrode formation layer showing the internal structure of the multilayer capacitor.
7 to 9, 51 is a dielectric, 52 is a first internal electrode, 53 is a second internal electrode, 54 is a first via hole, 55 is a second via hole, 56 is a first external electrode, 57 is a second external electrode, 61 is an island-like internal electrode non-forming portion provided in the first internal electrode 52 layer, and 62 is an island-like internal electrode provided in the second internal electrode 53 layer. It is a non-forming part.
[0005]
As shown in FIG. 7, the multilayer capacitor is composed of a plurality of pairs of dielectrics 51 formed of a plurality of dielectric layers and facing each other through a predetermined dielectric layer in the dielectrics 51 and alternately formed in the stacking direction. The first internal electrode 52 and the second internal electrode 53 are configured.
[0006]
The plurality of first via holes 54 respectively conducting between the plurality of first inner electrodes 52 and between the plurality of first inner electrodes 52 and the plurality of first outer electrodes 56 formed on the outer surface of the capacitor are dielectrics. 51 is formed inside. Similarly, a plurality of second via holes respectively conducting between the plurality of second inner electrodes 53 and between the plurality of second inner electrodes 53 and the plurality of second outer electrodes 57 formed on the outer surface of the capacitor. 55 is formed inside the dielectric 51.
[0007]
As shown in FIG. 8, the first internal electrode 52 is provided with an island-shaped internal electrode non-forming portion 61 having a diameter larger than the diameter of the via hole 55 at a position where the second via hole 55 penetrates. . Thus, the second via hole 55 penetrates the layer of the first internal electrode 52 but is electrically insulated from the first internal electrode 52.
[0008]
On the other hand, as shown in FIG. 9, the second internal electrode 53 is provided with an island-shaped internal electrode non-forming portion 62 having a diameter larger than the diameter of the via hole 54 at a position where the first via hole 54 penetrates. ing. Thereby, the first via hole 54 penetrates the layer of the second internal electrode 53, but is electrically insulated from the second internal electrode 53.
[0009]
The multilayer capacitor having such a structure is manufactured by the following process. That is, for example, a plurality of ceramic green sheets are prepared as a dielectric layer constituting the dielectric 51, internal electrodes 52 and 53 are formed on a predetermined ceramic green sheet, these ceramic green sheets are stacked and pressed in the stacking direction. Cut into necessary units (usually, a ceramic green sheet is a large-sized sheet from which a plurality of raw chips can be taken and forms a plurality of raw chips at the same time). Thereafter, the raw chip obtained by cutting is baked, and an external electrode is formed by a method such as applying and printing a conductive paste.
[0010]
Here, in forming the internal electrodes 52 and 53, screen printing using a conductive paste is usually applied.
[0011]
A screen plate is placed on a ceramic green sheet on which an internal electrode pattern is to be printed, and a conductive paste is placed on the screen plate. Next, by moving the squeegee on the screen plate, a pattern made of a conductive paste is formed on the surface of the ceramic green sheet in accordance with the pattern previously formed on the screen plate. Here, the pattern of the screen printing plate is formed so that the conductive paste passes through the portion corresponding to the internal electrode and does not pass through the portion corresponding to the island-like internal electrode non-forming portion. Thus, the paste-like internal electrode screen-printed in a predetermined pattern is formed as a solid internal electrode by firing thereafter.
[0012]
[Problems to be solved by the invention]
Such conventional multilayer capacitors and methods for manufacturing the same have the following problems to be solved.
[0013]
Since the island-shaped internal electrode non-forming portion formed on the internal electrode has a minute diameter of, for example, 500 μm or less, it is easily affected by bleeding due to printing as shown in FIG.
[0014]
FIG. 10 is a plan view showing a pattern of the printed internal electrode. In FIG. 10, 151 is a ceramic green sheet, 152 is an internal electrode formed of a conductive paste, 161 is an island-shaped conductive paste non-printing portion, and 165 is a blur.
[0015]
Such bleeding due to printing occurs because the non-printing pattern of the screen plate slightly shifts due to the shape of the squeegee during screen printing and the printing pressure during printing of the squeegee. That is, when the squeegee moves on the screen printing plate, the screen printing plate receives a pressure from the squeegee and thus shifts in the moving direction. For this reason, as shown in FIG. 10, the blur 165 which spreads in the advancing direction of a squeegee is produced in the edge part of the island-like non-printing part 161. In particular, the portion through which the conductive paste passes (for example, the mesh portion) is very thin due to its properties, so the strength is weak, deformation such as elongation occurs, and a slight deviation or blurring occurs due to printing pressure of the squeegee. It is easy to produce.
[0016]
In order to solve this problem, multilayer capacitors as shown in FIGS. 11 and 12 have been devised.
FIG. 11 is a perspective view showing the internal structure of the multilayer capacitor.
FIG. 12 is a plan view of a cross section through which the first internal electrode shows the internal structure of the multilayer capacitor.
[0017]
11 and 12, 51 is a dielectric, 52 is a first internal electrode, 53 is a second internal electrode, 54 is a first via hole, 55 is a second via hole, and 61 is a first internal electrode 2. Reference numeral 71 denotes an island-shaped internal electrode non-forming portion provided in the connecting portion for connecting the island-shaped internal electrode non-forming portions.
[0018]
As shown in FIGS. 11 and 12, the first and second internal electrodes 52 and 53 constituting the multilayer capacitor have a connection portion 71 of an electrode non-forming portion connecting the island-shaped internal electrode non-forming portion 61. It is provided in the shape. Other configurations are the same as those of the multilayer capacitor shown in FIG. As shown in FIG. 11, the second internal electrode is electrically connected to the second via hole and insulated from the first via hole, as opposed to the structure of the first internal electrode. The same as the first internal electrode. The grid-like connecting portion 71 corresponds to a portion under the portion of the screen printing plate through which the conductive paste is not allowed to pass during screen printing. Since the portions of the screen printing plate that do not allow the conductive paste to pass through are connected to each other, the non-printing pattern is unlikely to shift due to the progress of the squeegee. With such a structure, pattern defects due to bleeding during printing can be suppressed, and internal electrodes can be formed stably.
[0019]
However, such a multilayer capacitor has the following new problem.
That is, as shown in FIG. 12, by providing the connecting portion 71 that connects the island-like internal electrode non-forming portion 61, the first and second internal electrodes 52, 53 of one layer are divided into a plurality of portions. . As a result, the electric resistance in each layer increases, so that the equivalent series resistance (ESR) of the multilayer capacitor as a whole increases and the characteristics deteriorate.
[0020]
Further, when barrel plating is performed on the external electrode, for example, the steel plate (electric medium) is mixed with the electrolytic solution to perform the electrolytic plating.
[0021]
Here, the electrolytic plating is performed only when the steel ball contacts the external electrode. However, since the internal electrode is not electrically connected, the steel ball must be in contact with each of the external electrodes that conduct to this. If you can not plate. For this reason, the efficiency of plating deteriorates. On the other hand, in order to improve the quality of plating, the plating time becomes long, but the capacitor is put in the barrel containing the steel ball for a long time, and the frequency of generating secondary defects due to collision etc. Will increase.
[0022]
Similarly, since the internal electrodes are electrically separated from each other, the external electrodes connected to the internal electrodes are also electrically separated from each other. Therefore, when performing characteristic measurement, measurement is performed for each external electrode. The measurement is complicated.
[0023]
An object of the present invention is to provide a multilayer electronic component such as a multilayer capacitor with improved ESL and ESR, and a method for manufacturing the same.
[0024]
Another object of the present invention is to provide a wiring board, a decoupling circuit, and a high-frequency circuit that are configured using the multilayer capacitor as described above.
[0025]
[Means for Solving the Problems]
The present invention separates the first internal electrode by a plurality of island-shaped electrode non-forming portions through which the second via hole passes and a connecting portion of the electrode non-forming portions that connect the island-shaped electrode non-forming portions, A plurality of island-like electrode non-formation parts through which the first via hole passes and a second internal electrode is separated by a connection part of the electrode non-formation part that connects the island-like electrode non-formation parts to each other. Through the position where the first internal electrodes are electrically connected to each other at the connecting portion of the electrode non-forming portion in the first internal electrode forming layer, and the second via hole is not formed in the electrode in the second internal electrode forming layer The multilayer capacitor is formed by passing through the position where the second internal electrodes are electrically connected to each other at the connecting portion.
[0026]
In the present invention, the multilayer electronic component is mounted to constitute a wiring board.
[0027]
According to the present invention, a decoupling circuit is configured by including the laminated electronic component.
[0028]
In addition, the present invention constitutes a high-frequency circuit including the multilayer electronic component, the wiring board, and the decoupling circuit.
[0029]
In the present invention, the conductive paste on the screen plate is printed on the dielectric surface under the screen plate by moving the squeegee to form the first and second internal electrodes. The multilayer capacitor is manufactured by proceeding in the same direction as the connecting direction of the connecting portion.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
The configuration of the multilayer capacitor in accordance with the first embodiment will be described with reference to FIGS.
FIG. 1A is a perspective view partially showing the internal structure of the multilayer capacitor, and FIG. 1B is a cross-sectional view showing the internal structure.
FIG. 2 is a plan view of a first internal electrode formation layer showing the internal structure of the multilayer capacitor.
FIG. 3 is a plan view of a second internal electrode formation layer showing the internal structure of the multilayer capacitor.
1 to 3, 1 is a dielectric, 2 is a first internal electrode, 3 is a second internal electrode, 4 is a first via hole, 5 is a second via hole, 6 is a first external electrode, 7 is a second external electrode, 11 is an island-shaped internal electrode non-formation portion provided in the layer of the first internal electrode 2, 12 is a connection portion connecting the island-shaped internal electrode non-formation portion 11, and 13 is a first Reference numeral 14 denotes an island-shaped internal electrode non-formation portion provided in the layer of the internal electrode 3, and reference numeral 14 denotes a connection portion connecting the island-shaped internal electrode non-formation portions 13.
[0031]
As shown in FIG. 1, a multilayer capacitor is composed of a plurality of pairs of dielectrics 1 formed of a plurality of dielectric layers and opposed to each other via a predetermined dielectric layer in the dielectrics 1 and alternately formed in the stacking direction. The first internal electrode 2 and the second internal electrode 3 are configured.
[0032]
A plurality of first via holes 4 are electrically connected between the plurality of first inner electrodes 2 and between the plurality of first inner electrodes 2 and the plurality of first outer electrodes 6 formed on the outer surface of the capacitor. It is formed inside the body layer 1. Similarly, the plurality of second inner electrodes 3 are electrically connected to each other and between the plurality of second inner electrodes 3 and the plurality of second outer electrodes 7 formed on the outer surface of the capacitor. A via hole 5 is formed inside the dielectric layer 1.
[0033]
As shown in FIG. 2, the first internal electrode 2 is provided with an island-shaped first internal electrode non-forming portion 11 having a diameter larger than the diameter of the via hole 5 at a position where the second via hole 5 penetrates. It has been. Thereby, the second via hole 5 penetrates the layer of the first internal electrode 2 but is electrically insulated from the first internal electrode 2. Further, the first internal electrode non-forming portion 11 is connected to form a linear connecting portion 12 parallel to a certain side of the internal electrode 2.
[0034]
The first via hole 4 is formed in a region where the linear connecting portion 12 is provided, and is separated from the island-shaped first electrode non-forming portion 11 and the connecting portion 12 into a plurality of first interiors. The electrodes 2 are electrically connected. In this way, all the internal electrodes 2 provided in the layer are made conductive.
[0035]
As shown in FIG. 3, the second internal electrode 3 is provided with an island-like second internal electrode non-forming portion 13 having a diameter larger than the diameter of the via hole 4 at a position where the first via hole 4 penetrates. It has been. Thereby, the first via hole 4 penetrates the layer of the second internal electrode 3 but is electrically insulated from the second internal electrode 3. In addition, the second internal electrode non-forming portion 13 is connected to form a linear connecting portion 14 parallel to a side where the internal electrode 3 is provided.
[0036]
The second via hole 5 is formed in a region where the linear connecting portion 14 is provided, and the second interior is separated into a plurality of island-shaped second electrode non-forming portions 13 and the connecting portion 14. The electrodes 3 are electrically connected. In this way, all the internal electrodes 3 provided in the layer are made conductive.
[0037]
With such a structure, the resistance of each internal electrode can be kept low, so that an increase in ESR can be suppressed while reducing ESL as a multilayer capacitor.
[0038]
In addition, since all the electrodes in the layer are conductive, the measurement may be performed using one external electrode when measuring characteristics. For this reason, characteristic measurement can be simplified.
[0039]
When the first and second external electrodes 6 and 7 are plated, the first and second external electrodes 6 and 7 are respectively connected to the first and second internal electrodes 2 and 3 and the first and second external electrodes 6 and 7, respectively. 2 through the via holes 4 and 5, so that if one of the first and second external electrodes 6 and 7 is in contact with one of the steel balls, electrolytic plating can be performed and plating can be performed efficiently. It can be performed.
[0040]
Next, the configuration of the multilayer capacitor in accordance with the second embodiment will be described with reference to FIGS.
FIG. 4 is a perspective view partially showing the internal structure of the multilayer capacitor.
FIG. 5A is a plan view of the first internal electrode formation layer showing the internal structure of the multilayer capacitor, and FIG. 5B is a plan view of the second internal electrode formation layer.
4 and 5, 1 is a dielectric, 2 is a first internal electrode, 3 is a second internal electrode, 4 is a first via hole, 5 is a second via hole, 6 is a first external electrode, 7 is a second external electrode, 11 is an island-like internal electrode non-formation portion provided on the first internal electrode 2, 13 is an island-like internal electrode non-formation portion provided on the second internal electrode 3, Reference numeral 15 denotes a connecting portion that connects the island-shaped internal electrode non-forming portions 11, and 16 denotes a connecting portion that connects the island-shaped internal electrode non-forming portions 13.
[0041]
In the multilayer capacitor shown in FIGS. 4 and 5, the connecting portions 15 and 16 are each formed in a straight line perpendicular to two opposing sides of each internal electrode. This is the same as the multilayer capacitor shown in FIG.
[0042]
By adopting such a structure, the same effect as that of the first embodiment can be obtained, and the portion where the conductive paste is not printed, that is, the portion where the plate thickness is thick is increased and is in a lattice shape. Strength is increased, durability is improved, and printing accuracy is improved.
[0043]
In the above-described embodiment, the multilayer capacitor has been described. However, the present invention is not limited to this, and any multilayer electronic component having a structure in which internal electrodes are connected by via holes, such as a multilayer inductor, can be applied to the present invention. .
[0044]
Next, the configuration of the MPU using the multilayer capacitor as a decoupling capacitor will be described with reference to FIG.
[0045]
FIG. 6 is a cross-sectional view schematically showing a structural example of an MPU using the multilayer capacitor according to the first and second embodiments as a decoupling capacitor.
[0046]
As shown in FIG. 6, the MPU 21 includes a wiring board 23 having a multilayer structure in which a cavity 22 is provided on the lower surface side. An MPU chip 24 is surface-mounted on the upper surface of the wiring board 23. In addition, the multilayer capacitor 100 functioning as a decoupling capacitor, for example, the multilayer capacitor according to the first embodiment is accommodated in the cavity 22 of the wiring board 23. Further, the wiring board 23 is surface-mounted on the mother board 25.
[0047]
Wiring conductors necessary for the MPU 21 are formed on the surface and inside of the wiring board 23 as schematically illustrated. For example, a typical one will be described. Inside the wiring board 23, a hot-side electrode 26 for power supply and a ground electrode 27 are formed.
[0048]
The power hot electrode 26 is electrically connected to the first external electrode 6 of the multilayer capacitor 100 via the power hot via hole 30, and the MPU chip 24 is specified via the power hot via hole 31. Are electrically connected to the hot-side conductive land 34 on the mother board 25 via the hot-side via-hole conductor 33 for power supply.
[0049]
The ground electrode 27 is electrically connected to the second external electrode 7 of the multilayer capacitor 100 via the ground via-hole conductor 35, and the specific terminal 37 of the MPU chip 24 is connected via the ground via-hole conductor 36. And is further electrically connected to the ground conductive land 39 of the mother board 25 through the ground via hole 38.
[0050]
For connection between the first and second external electrodes 6 and 7 and the via-hole conductors 30 and 35 of the multilayer capacitor 100 described above, connection by bumps is applied although not shown in detail in FIG.
[0051]
Thus, by providing the multilayer capacitor shown in the above-described embodiment as a decoupling capacitor, a high-frequency circuit such as a high-performance MPU that can sufficiently cope with high-speed operation can be configured.
[0052]
【The invention's effect】
According to this invention, the first internal electrodes are separated by the connecting portions of the plurality of island-shaped electrode non-forming portions through which the second via holes pass and the island-shaped electrode non-forming portions connecting the island-shaped electrode non-forming portions. The second internal electrode is separated by a plurality of island-shaped electrode non-forming portions through which the first via hole passes and a connecting portion of the electrode non-forming portions connecting the island-shaped electrode non-forming portions, The via hole is passed through a position where the first internal electrodes are electrically connected to each other at the connecting portion of the electrode non-forming portion in the first internal electrode forming layer, and the second via hole is passed through the electrode in the second internal electrode forming layer. A multilayer capacitor is configured by passing through the position where the second internal electrodes are electrically connected to each other at the connecting portion of the non-formed portion. As a result, the internal electrodes of each layer are not electrically separated and are electrically conducted within the layer, so that the resistance value can be kept low, and a multilayer capacitor with a low ESR can be configured. .
[0053]
Moreover, according to this invention, the wiring board which has the outstanding transmission characteristic can be comprised by mounting the said multilayer electronic component.
[0054]
Moreover, according to this invention, the decoupling circuit which has the outstanding performance can be comprised by providing the said multilayer electronic component.
[0055]
In addition, according to the present invention, a high-frequency circuit having excellent transmission characteristics can be configured by including the multilayer electronic component, the wiring board, and the decoupling circuit.
[0056]
According to the present invention, when the first and second internal electrodes are formed by printing the conductive paste on the screen plate on the dielectric surface under the screen plate by moving the squeegee, the squeegee is not formed. By manufacturing the multilayer capacitor by proceeding in the same direction as the connecting direction of the connecting portion of the part, it is possible to prevent bleeding and blurring during internal electrode printing, and to manufacture a highly reliable multilayer capacitor with high accuracy. be able to.
[Brief description of the drawings]
FIGS. 1A and 1B are a perspective view and a cross-sectional view showing the internal structure of the multilayer capacitor according to the first embodiment. FIG. 2 is a plan view of a first internal electrode forming layer showing the internal structure of the multilayer capacitor according to the first embodiment. FIG. 3 is a plan view of a second internal electrode forming layer showing the internal structure of the multilayer capacitor according to the first embodiment. FIG. 4 is a perspective view showing the internal structure of the multilayer capacitor according to the second embodiment. FIG. 5 is a plan view of a formation layer through which the first and second internal electrodes pass showing the internal structure of the multilayer capacitor. FIG. 6 shows an MPU using the multilayer capacitor according to the first and second embodiments as a decoupling capacitor. FIG. 7 is a perspective view and a cross-sectional view showing an internal structure of a conventional multilayer capacitor. FIG. 8 is a cross-section through which a first internal electrode showing the internal structure of a conventional multilayer capacitor is passed. Plan view at [Fig.9] FIG. 10 is a plan view showing a pattern of a printed internal electrode showing the internal structure of the multilayer capacitor in FIG. 10. FIG. 11 is a plan view showing the internal structure of the multilayer capacitor as the premise of the present application. FIG. 12 is a plan view of the first internal electrode forming layer showing the internal structure of the multilayer capacitor as the premise of the present application.
1, 51-dielectric 2,52-first internal electrode 3,53-second internal electrode 4,54-first via hole 5,55-second via hole 6,56-first external electrode 7 57-second external electrode 11-island-like internal electrode non-forming portion 12 provided on the first internal electrode 2-connecting portion 13 connecting the island-like internal electrode non-forming portion 11-second internal electrode 3 is an island-like internal electrode non-forming part 14 -an island-like internal electrode non-forming part 13 is connected 15 -an island-like internal electrode non-forming part 11 is connected 16 -island-like internal electrode Connecting part 21-MPU connecting non-forming part 13
22-Cavity 23-Wiring board 24-MPU chip 25-Motherboard 26-Power supply hot side electrode 27-Ground electrode 30, 31-Power supply hot side via hole 32, 37-Specific terminal 33 of MPU chip 24-Power supply hot Side via hole conductor 34-Hot side conductive land 35, 36, 38 of motherboard 25-Ground via hole conductor 39-Ground conductive land 61 of motherboard 25-Island-like internal electrode provided on first internal electrode 52 not formed Part 62-island-like internal electrode non-formation part 71 provided on the second internal electrode 53-connecting part 151 connecting the island-like internal electrode non-formation part-ceramic green sheet 152-internal electrode formed of conductive paste 161-Island-shaped internal electrode non-forming portion 165-Bleeding of conductive paste by printing

Claims (6)

A plurality of first via holes, each of which is composed of a plurality of layers, alternately stacked via a dielectric layer, connecting the first internal electrodes to each other and conducting to the first external electrode; A plurality of second via holes that connect the second inner electrodes to each other and are electrically connected to the second outer electrodes, and a plurality of island-shaped first holes through which the second via holes pass through the first inner electrode formation layer. In a multilayer electronic component in which one internal electrode non-forming portion is provided, and a plurality of island-shaped second internal electrode non-forming portions through which the first via hole passes are provided in the second internal electrode forming layer.
The first internal electrode is separated by a connection portion of the electrode non-forming portion that connects the first internal electrode non-forming portions,
The second internal electrode is separated by a connecting portion of the electrode non-forming portion that connects the second internal electrode non-forming portions,
Passing the first via hole through a position where the first internal electrodes separated by the connecting portion of the first internal electrode non-forming portion in the first internal electrode forming layer are electrically connected to each other;
Passing the second via hole through a position where the second internal electrodes separated by the connecting portion of the second internal electrode non-forming portion in the second internal electrode forming layer are electrically connected to each other ;
The first and second internal electrodes separated by the connecting portions of the first and second electrode non-forming portions are respectively separated by the first and second electrode non-forming portions. Form a rectangular shape that is cut out,
In the sides of the rectangular first and second internal electrodes, the length of the portion cut out by the first and second electrode non-forming portions is determined by the first and second electrode non-forming portions. A multilayer electronic component characterized in that it is shorter than the length of the part that is not cut out . 2. The multilayer electronic component according to claim 1, wherein the first and second electrode non-forming portions are partitioned by a circular arc having a larger diameter than the first and second via holes. . Multilayer wiring board having electronic components according to claim 1 or 2. Decoupling circuit comprising a multilayer electronic component according to claim 1 or 2. The multilayer electronic component according to claim 1 or 2, the wiring board according to claim 3, the high-frequency circuit comprising one of the decoupling circuit according to claim 4. A method of manufacturing a multilayer electronic component according to claim 1 or 2 ,
When the first and second internal electrodes are formed by printing the conductive paste on the screen plate on the dielectric surface under the screen plate by moving the squeegee, the squeegee is used to remove the first and second electrodes. A method for manufacturing a multilayer electronic component, wherein the process advances in the same direction as the connecting direction of the connecting portion of the forming portion.

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