JP3943749B2 - Schottky barrier diode - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a Schottky barrier diode, and more particularly to a structure of a Schottky barrier diode suitable for high breakdown voltage and large current.
[0002]
[Prior art]
With the increase in voltage and operating frequency of power conversion equipment such as inverters, higher withstand voltage and higher speed of semiconductor switching elements constituting power conversion equipment and freewheeling diodes or freewheeling diodes connected in reverse parallel to the switching elements Is strongly demanded. Since these diodes are required to have a function of rectifying high voltage and large current with low loss, pn junction diodes are generally employed.
[0003]
In the pn junction diode, minority carriers are accumulated in the semiconductor when energized, and a large reverse recovery current flows transiently when turned off. In addition, this reverse current generates a loss in the semiconductor and generates noise.
[0004]
Various pn junction diodes having improved reverse recovery current characteristics have been developed. However, in this type of diode using minority carriers, there is an inherent limitation in reducing the reverse recovery current.
[0005]
On the other hand, in the Schottky barrier diode, the reverse current at turn-off can be made extremely small because the carrier for carrying charge inside the semiconductor is only the majority carrier and there is no injection and accumulation of minority carriers. However, a conventional Schottky barrier diode based on silicon has a high on-resistance when energized and a large generation loss, so that it is difficult to apply to a high-voltage and large-current power conversion device.
[0006]
If the base material is SiC, the above problem can be solved. However, the leakage current increases when a reverse voltage is applied. In particular, when a reverse voltage close to the withstand voltage is applied in a high temperature state, the leakage current increases and the loss in the reverse voltage blocking state increases. If this loss occurs locally in the device, the device may be thermally destroyed by partial thermal runaway.
[0007]
FIG. 6 is a diagram showing a conventional configuration for reducing leakage current when a reverse voltage is applied to a Si-based Schottky barrier diode. The figure shows J. et al. By Baliga, Solid-state Electronics, Vo. l28, no. 11, pp. 1089-1093 (1985) was announced as a technology called Junction-Barrier-Controlled Schottky (JBS) Rectifier.
[0008]
In the figure, 11 is a semiconductor substrate based on Si, 12 is an n + type layer having a high impurity concentration, 13 is an n− type layer having a low impurity concentration, and the semiconductor substrate 11 is an n + type layer 12 and an n− type layer. 13. 14 is a plurality of p + type layers formed on the Schottky barrier portion on the surface of the n− type layer 13, 15 is a Schottky metal forming a Schottky barrier on the surface of the n− type layer 13, and 16 is the n− type layer 13. The cathode electrode is in ohmic contact with the surface with low resistance. 131 is a main surface of the n − -type layer 13, and 151 is a Schottky barrier formed on the main surface 131.
[0009]
The plurality of p + type layers 14 are dispersedly arranged at intervals. This interval is such that depletion layers extending from the pn junctions of the p + type layer 14 and the n − type layer 13 toward the n − type layer overlap each other when a reverse voltage is applied, and the depletion layers overlap each other. The electric field strength due to the reverse voltage applied to the barrier is reduced, and the leakage current in the Schottky barrier portion is reduced.
[0010]
[Problems to be solved by the invention]
It can be expected that the reverse voltage characteristics can be improved by applying the conventional technique related to a Schottky barrier diode based on Si to a Schottky barrier diode based on SiC.
[0011]
However, it is very difficult to apply the technology for a semiconductor substrate based on Si to a Schottky diode using a semiconductor substrate based on SiC as it is.
[0012]
That is, in FIG. 6, the distance between the p + -type layers 14 is such that depletion layers extending from the respective p + -type layers overlap each other when the reverse voltage is applied in order to reduce the electric field strength of the reverse voltage applied to the intervening Schottky barrier. It is necessary to reduce the interval to an extent. In order to maintain the reverse voltage blocking capability against a high reverse voltage of several hundreds to several thousand volts, the p + type layer 14 must be formed as a relatively deep high concentration layer.
[0013]
In the case of a SiC substrate, the junction breakdown electric field has a junction design that takes advantage of the physical property of about 10 times that of Si, so the impurity concentration of the n − -type layer 13 is 70 to 100 times higher than that of Si. Can be set to concentration. When such a high concentration is set, the spread of the depletion layer is remarkably reduced. In order to exhibit the pinch-off effect of the depletion layer, the interval between the p + -type layers 14 needs to be an extremely narrow value of about 1 μm or less. .
[0014]
The deep p + type layer can be formed by diffusing acceptor impurities such as boron and aluminum by a thermal diffusion method on a Si substrate. However, in a SiC substrate, the thermal diffusion coefficient of these impurities is very small, so this diffusion method cannot be applied in practice, and must be formed directly by an ion implantation method.
[0015]
However, it is extremely difficult to selectively form a deep implantation layer of about 1 μm by ion implantation. That is, it is very difficult to form an implantation mask having a large thickness and a narrow interval.
[0016]
For example, when a photoresist is used as an implantation mask, a film thickness of about 4 μm is required for implantation of boron having a depth of 1 μm. It is difficult to accurately process this thick resist with a width and interval of 1 μm or less. As described above, it is difficult to directly apply the structure of the conventional example with the Si substrate capable of reducing the leakage current to the high breakdown voltage SiC Schottky barrier diode using the SiC substrate.
[0017]
The present invention has been made in view of the above-mentioned various problems, and provides a high-breakdown-voltage, high-current Schottky barrier diode with reduced leakage current and improved reverse voltage blocking capability.
[0018]
[Means for Solving the Problems]
The present invention employs the following means in order to solve the above problems.
[0019]
A SiC semiconductor substrate comprising a first semiconductor layer of a first conductivity type having a low impurity concentration and a second semiconductor layer of a first conductivity type having a high impurity concentration;
The main surface of the first semiconductor layer was formed by ion implantation with a first ion implantation energy.
A plurality of first surface layers of a second conductivity type having a relatively large depth and spacing between each other;
A second conductivity type formed by ion implantation between the first surface layers with a second ion implantation energy smaller than the first ion implantation energy and having a depth and an interval between the first surface layers smaller than those of the first surface layer. A second surface layer of
A Schottky metal bonded to the main surface of the first semiconductor layer and in ohmic contact with the first surface layer and the second surface layer with low resistance;
The cathode electrode is in ohmic contact with the second semiconductor layer.
[0020]
In the Schottky barrier diode,
An interval between the second surface layers is lower than a breakdown voltage of a Schottky barrier diode element constituted by the Schottky metal and the cathode electrode when a reverse bias voltage is applied between the Schottky metal and the cathode electrode . At one voltage, depletion layers extending in adjacent second surface layers overlap each other,
The space between the first surface layers is a depletion that spreads to adjacent first surface layers at a second voltage higher than the first voltage when a reverse bias voltage is applied between the Schottky metal and the cathode electrode. It is characterized in that the distance is set so that the layers overlap each other.
[0021]
In the Schottky barrier diode,
The distance between the second surface layers is 0.10 to 1.0 μm, and the distance between the first surface layers is 3 to 25 μm.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
[0023]
FIG. 1 is a perspective view showing a unit cell of a Schottky barrier diode according to the present embodiment, and FIG. 2 is a perspective view showing an arrangement example of unit cells of the Schottky barrier diode according to the present embodiment.
[0024]
In these figures, 1 is a semiconductor substrate based on SiC, 2 is an impurity concentration of about 3 × 10 ¹⁹ , a low resistance n + type layer having a thickness of about 300 μm, and 3 is an impurity concentration of about 1 × 10 ¹⁶ and a thickness. N-type layer 4 having a high resistance of about 12 μm, 4 is a p + type layer forming a relatively high concentration first surface layer having a depth of about 1 μm, a width of about 1 μm, and a boron implantation amount of about 1 × 10 ¹⁵ / cm ^2. The first surface layer 4 is provided along the periphery of the unit cell. 41 is a second surface layer in the form of a stripe having a relatively high concentration and having a depth and width of about 0.15 μm and a boron implantation amount of about 1 × 10 ¹⁴ / cm ² provided on the surface surrounded by the first surface layer 4. The second surface layer 41 is in contact with the first surface layer 4 at the periphery of the unit cell.
[0025]
Reference numeral 31 denotes a surface exposed portion of the n − -type layer 3 having a width of about 0.2 μm exposed between two adjacent second surface layers 41 on the main surface.
[0026]
5 is a Schottky metal such as Ti / Al or Pt which serves as an anode electrode on the main surface, and makes a low resistance contact with the first surface layer 4 and the second surface layer 41 on the main surface.
[0027]
A Schottky barrier 51 is formed at a portion where the Schottky metal 5 and the surface exposed portion 31 of the n − -type layer 3 are in contact with each other.
[0028]
Reference numeral 6 denotes a cathode electrode made of Ni or the like which is in ohmic contact with the other main surface where the n + type layer 2 is exposed with low resistance.
[0029]
Next, the operation of each part will be described.
[0030]
The rectifying action as a diode is performed in a Schottky barrier 51 portion formed between the Schottky metal 5 and the n − -type layer 3. That is, when a voltage is applied so that the Schottky metal 5 has a positive potential with respect to the cathode electrode 6, the electrons have a Schottky barrier 51 (a relatively low barrier voltage of about 0.1 to 0.5 V). It flows from the Schottky metal 5 side to the n − type layer 3 side.
[0031]
Further, when a voltage is applied in the opposite direction, the electrons are blocked by the Schottky barrier 51 and current flow is blocked.
[0032]
The operation of the layer 4 and the layer 41 which are two kinds of p + type layers having different depths, widths, and mutual distances is as follows.
[0033]
That is, when a reverse voltage is applied, the depletion layer extends into the n − -type layer 3 from each surface of the Schottky barrier 51, the first surface layer 4, and the second surface layer 41, and is adjacent to each other at a reverse voltage of about 100V. Depletion layers extending from the surface layer 41 overlap each other.
[0034]
When a higher reverse voltage is applied, the depletion layer further expands, and depletion layers extending from the adjacent first surface layers 4 overlap each other at a reverse voltage of about 800V. When a higher reverse voltage is applied, the depletion layer spreads uniformly in the n − type layer 3 toward the n + type layer 2, and at about 1200 V, the tip reaches the n + type layer 2. Surrender.
[0035]
The reverse electric field applied to the Schottky barrier becomes stronger as the reverse voltage is increased by applying the reverse voltage. When the reverse voltage becomes equal to or higher than the voltage at which the depletion layers extending from the second surface layer 41 overlap, the application of an electric field having a higher intensity is suppressed by the pinch-off effect of this portion.
[0036]
When a higher reverse voltage is applied, a depletion layer extending from the first surface layer 4 is overlapped this time, and an increase in electric field strength applied to the pn junction of the Schottky barrier 51 and the second surface layer 41 is suppressed.
[0037]
By such an action, an increase in leakage current at the Schottky barrier when a reverse high voltage is applied can be suppressed, and a Schottky barrier diode having a high breakdown voltage and a low leakage current can be obtained.
[0038]
FIG. 2 is a perspective view showing an arrangement example of the unit cells of the Schottky barrier diode according to this embodiment described above. In the figure, the Schottky barrier diode is configured by juxtaposing six unit cells. In the figure, the same parts as those shown in FIG. The number of cells juxtaposed in the semiconductor chip is determined by the current capacity of the semiconductor chip, and usually several million cells are juxtaposed.
[0039]
In the figure, the first surface layer 4 formed on the main surface with a relatively deep and wide width is arranged in a lattice pattern at intervals of 3 to 5 μm, for example.
[0040]
Further, in the region surrounded by the first surface layer 4 on the main surface, stripe-shaped second surface layers 41 that are relatively shallow and narrow are arranged at intervals of 0.2 to 0.35 μm, for example.
[0041]
The interval is designed to an appropriate value depending on the withstand voltage of the Schottky barrier diode. That is, since the value of the impurity concentration of the n − -type layer 3 is changed by the design withstand voltage, the interval between the first surface layer 4 and the interval between the second surface layers 41 must be optimized according to the impurity concentration. . In a 600 V to 5,000 V Schottky barrier diode, which is called a normal high voltage device, the distance between the first surface layers 4 is 3 to 25 μm, and the distance between the second surface layers 41 is 0.1 to 1.0 μm.
[0042]
FIG. 3 is a diagram showing an example in which termination is applied to the peripheral portion of the chip. Although not shown in FIG. 2, a special device as shown in FIG. 3 is required in order to reduce the electric field at the peripheral edge of the chip.
[0043]
In the figure, reference numeral 40 denotes a p + type layer formed at the peripheral edge of the chip where the Schottky metal 5 terminates. The p + type layer 40 is an implanted layer having a width of about 30 μm and a depth of 2 to 3 μm formed by implanting boron at a high concentration of about 1 × 10 ¹⁵ / cm ² . In addition, this layer is formed to be significantly deeper than the first surface layer 4 that is the first surface layer 4, and the pn junction formed with the n − -type layer 3 is formed from the surface to a significantly deeper position. The p + type layer 40 functions as a so-called guard ring, as disclosed in, for example, Japanese Patent Application Laid-Open No. 60-74481, and is applied to a high breakdown voltage diode that needs to alleviate electric field concentration at the periphery of the junction. Means. In addition to the above, a technique such as a field limiting ring (FLR), a field freight (FP), or a junction termination extension (JTE) can be applied to the termination.
[0044]
FIG. 4A and FIG. 4B are diagrams showing another example of the two-dimensional structure of the unit cell. In FIG. 4A, the first surface layer 4 formed on the main surface with a relatively deep and wide width is formed at the peripheral edge of the unit cell. Further, a relatively shallow and narrow second surface layer 41 is arranged in a lattice pattern in a region surrounded by the first surface layer 4 on the main surface.
[0045]
In FIG. 4B, the first surface layer 4 formed on the main surface with a relatively deep and wide width is formed at the peripheral edge of the unit cell. Further, in the region surrounded by the first surface layer 4 on the main surface, the second surface layer 41 having a relatively shallow surface area and a small surface area is arranged in an island shape.
In the figure, the same parts as those shown in FIGS. 1 to 3 are denoted by the same reference numerals, and the description thereof is omitted.
[0046]
In the unit cells having the two-dimensional structure shown in FIGS. 4A and 4B as well as the unit cell having the two-dimensional structure shown in FIG. An increase in current can be suppressed, and a Schottky barrier diode with high breakdown voltage and low leakage current can be obtained.
[0047]
FIG. 5 is a diagram showing a method for manufacturing the Schottky barrier diode according to the present embodiment. In the figure, the same parts as those shown in FIGS. 1 to 4 are denoted by the same reference numerals, and the description thereof is omitted.
[0048]
FIG. 5A is a diagram showing the main surface of the n − type layer 3, and the lower n + type layer 2 is omitted. Next, in FIG. 5B, ions are selectively implanted into the surface of the n − -type layer 3 to form the first surface layer 4. In the ion implantation, the first surface layer 4 is formed by implanting an ion implantation amount of about 1 × 10 ¹⁵ / cm ² and implanting energy in three stages of 500 KeV, 300 KeV, and 50 KeV. At this time, a photoresist film having a thickness of 4.0 μm is used as an implantation mask. Next, in FIG. 5C, a photoresist film having a thickness of 0.3 μm is used as an implantation mask, the implantation amount is about 1 × 10 ¹⁴ / cm ² , boron is implanted with an implantation energy of 50 KeV, and the second surface is implanted. Layer 41 is formed. Next, in FIG. 5D, annealing is performed at about 1500 ° C. for activation treatment. Thereafter, a Schottky metal 5 such as Ti / Al is deposited on the surface. The functional region of the device is formed by the above process.
[0049]
【The invention's effect】
As described above, according to the present invention, on the main surface of the first conductivity type SiC semiconductor substrate that forms the Schottky junction, the second conductivity type first surface layer having a large depth and a large distance between each other, Since the second surface layer of the second conductivity type having a small depth and a small interval between them is formed, a high breakdown voltage, large current Schottky barrier diode with reduced reverse leakage current can be obtained.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a unit cell of a Schottky barrier diode according to an embodiment of the present invention.
FIG. 2 is a perspective view showing an arrangement example of unit cells of the Schottky barrier diode according to the embodiment of the present invention.
FIG. 3 is a diagram illustrating an example in which termination is applied to the periphery of a chip.
FIG. 4 is a diagram showing another example of the two-dimensional structure of the unit cell.
FIG. 5 is a diagram showing a manufacturing method of the Schottky barrier diode according to the embodiment.
FIG. 6 is a diagram showing a configuration for reducing leakage current of a conventional Schottky barrier diode.
[Explanation of symbols]
1 semiconductor substrate 2 n + type layer 3 n− type layer 4 p + type layer (first surface layer)
5 Schottky metal 6 Cathode electrode 31 Surface exposed portion 41 of n− type layer p + type layer (second surface layer)
51 Schottky barrier

Claims (3)

A SiC semiconductor substrate comprising a first semiconductor layer of a first conductivity type having a low impurity concentration and a second semiconductor layer of a first conductivity type having a high impurity concentration;
A plurality of first surface layers of a second conductivity type formed by ion implantation at a main surface of the first semiconductor layer with a first ion implantation energy and having a relatively large depth and distance between each other;
A second conductivity type formed by ion implantation between the first surface layers with a second ion implantation energy smaller than the first ion implantation energy and having a depth and an interval between the first surface layers smaller than those of the first surface layer. A second surface layer of
A Schottky metal bonded to the main surface of the first semiconductor layer and in ohmic contact with the first surface layer and the second surface layer with low resistance;
A Schottky barrier diode comprising a cathode electrode in ohmic contact with the second semiconductor layer. In the description of claim 1,
An interval between the second surface layers is lower than a breakdown voltage of a Schottky barrier diode element constituted by the Schottky metal and the cathode electrode when a reverse bias voltage is applied between the Schottky metal and the cathode electrode . At one voltage, depletion layers extending in adjacent second surface layers overlap each other,
The space between the first surface layers is a depletion spreading to adjacent first surface layers at a second voltage higher than the first voltage when a reverse bias voltage is applied between the Schottky metal and the cathode electrode. A Schottky barrier diode, characterized in that the layers are set at a distance overlapping each other. In any one of Claims 1 to 2,
The distance between the second surface layers is 0.10 to 1.0 μm, and the distance between the first surface layers is 3 to 25 μm.

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