JP3937677B2 - Nonvolatile semiconductor memory device and write control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and a writing control method thereof, and more particularly to a nonvolatile semiconductor memory device that can be electrically rewritten without erasing data and a writing control method thereof.
[0002]
[Background Art and Problems to be Solved by the Invention]
In a conventional flash EEPROM or the like, data is written by injecting hot electrons generated when a current is passed from the drain to the source of the memory transistor into the floating gate. Data is erased by extracting electrons stored in the floating gate from the drain of the memory transistor using the tunnel phenomenon.
[0003]
Therefore, when data is changed, it is necessary to erase the data once and then write it, so that it takes time to write the data and the procedure is complicated.
[0004]
Further, since it was necessary to apply a high voltage to the drain during erasing and writing, it was difficult to make the memory cells finer or finer.
[0005]
The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide a nonvolatile semiconductor memory device such as a RAM that can be written with ease of use without requiring an erasing operation, and the same. It is to provide a writing control method.
[0006]
[Means for Solving the Problems]
The nonvolatile semiconductor memory device of the present invention includes a control gate and a gate region including a charge storage layer sandwiched between a first insulating film and a second insulating film having different conditions for generating a tunnel current, a first diffusion region, A second diffusion region, the control gate is on the m-th (1 ≦ m ≦ M) word line, the first diffusion region and the second diffusion region are n−1 and n (1 ≦ n), respectively. ≦ N) When a memory cell array having a plurality of memory cells connected to a bit line and writing a first value into the memory cell, a tunnel current flows out from the charge storage layer through the first insulating film. When the voltage VB1 having the same value is applied to the (n-1) th and nth bit lines, the voltage VW1 is applied to the mth word line, and the second value is written to the memory cell, To the charge storage layer through the first insulating film A write control circuit that controls to apply the same voltage VB2 to the (n-1) th and nth bit lines and the voltage VW2 to the mth word line so that a channel current flows. It is characterized by that.
[0007]
Here, the first insulating film and the second insulating film may have different conditions relating to a potential difference in which a tunnel current is generated due to, for example, the same composition and different film thicknesses. It may be the case where the conditions for generating are different.
[0008]
The first insulating film may be an insulating film between the control gate and the charge storage layer, or may be a film between the base and the charge storage layer.
[0009]
The charge storage layer may be formed as a floating gate, for example, or may be formed as a charge storage layer using an electron trap order.
[0010]
When the first value is written into the memory cell, the electric field and potential difference are such that electrons are injected into the control gate through the first insulating film by VB1 and VW1 (current flows out from the control gate). A voltage is applied so as to generate
[0011]
When the second value is written in the memory cell, the electric field and the potential difference are set in such a direction that electrons are extracted from the control gate by VB2 and VW2 through the first insulating film (current flows into the control gate). Apply voltage to generate.
[0012]
As described above, according to the present invention, a tunnel current is generated only in the first insulating film, the direction of movement of electrons is changed by changing the direction of the electric field, and electrons are injected into the charge storage layer, or charged and accumulated. The charge can be extracted from the layer.
[0013]
Therefore, direct writing can be performed without erasing, and a nonvolatile memory can be used as a RAM.
[0014]
In the present invention, the bit line having at least one more than the number N of memory cells that can be controlled by one word line is obtained by connecting the first diffusion region and the second diffusion region of each memory cell to adjacent bit lines. A simple configuration of providing As described above, according to the present invention, it is possible to realize use as a RAM of a nonvolatile memory with a small number of wirings.
[0015]
Further, by applying a voltage to the word line and the bit line by the control method of the present invention, the charge storage layer sandwiched between the first insulating film and the second insulating film having different conditions for generating the tunnel current is used. Use as a RAM of a nonvolatile memory can be realized with a simple configuration.
[0016]
In the nonvolatile semiconductor memory device of the present invention, when the potential difference generated in the gate region is V1, tunnel current does not flow through either the first insulating film or the second insulating film, and the potential difference generated in the gate region is V2 (V1 < V2), the tunnel current flows only through the first insulating film and the tunnel current does not flow through the second insulating film, and the write control circuit writes data to the memory cell. When performing, the potential difference generated in the gate region becomes V2, and the direction of the electric field generated in the first insulating film is reversed between the case where the first value is written and the case where the second value is written. When the voltages applied to the (n-1) th and nth bit lines and the mth word line are controlled and the memory cell is not written, the potential difference generated in the gate region becomes V1. N-1 and nth bi Trine, and controlling the voltage applied to the word line of the m.
[0017]
According to the present invention, the voltage corresponding to the condition generated in the tunnel current of the first insulating film and the second insulating film in the control circuit is set to the n−1th, nth bit line, and mth word line. Therefore, even if the conditions generated in the tunnel currents of the first insulating film and the second insulating film are different, it is possible to cope with this by simply changing the control contents.
[0018]
In the nonvolatile semiconductor memory device of the present invention, the write control circuit applies a voltage to the n−1th, nth bit line, and mth word line within a range in which no tunnel current is generated in the second insulating film. It controls to apply.
[0019]
According to the present invention, the control circuit applies a voltage according to the content of the condition generated in the tunnel current of the second insulating film to the n−1th, nth bit line, and mth word line. Since the control is performed, even if the conditions generated in the tunnel current of the second insulating film are different, it is possible to cope with it by changing the control contents.
[0020]
In the nonvolatile semiconductor memory device of the present invention, when the potential difference generated in the gate region is V, tunnel current does not flow in either the first insulating film or the second insulating film, and the potential difference generated in the gate region is 2V. In this case, the tunnel current flows only in the first insulating film and the tunnel current does not flow in the second insulating film, and the write control circuit writes the first value in the memory cell. In this case, when 0 is applied to the (n−1) -th and n-th bit lines and 2V is applied to the m-th word line, the second value is written into the memory cell. It is configured to apply V to the (n−1) th and nth bit lines and to apply −V to the mth word line.
[0021]
−V and 2V mean voltages when V is one unit, and the standard of one unit can be arbitrarily determined. For example, the power supply voltage may be one unit.
[0022]
According to the present invention, the voltage applied to the first diffusion region and the second diffusion region may be one half or zero of the voltage applied to the control gate. As described above, since it is not necessary to apply a high voltage to the first diffusion region and the second diffusion region, the memory cell can be miniaturized.
[0023]
The write control circuit of the nonvolatile semiconductor memory device of the present invention applies at least two voltages of −V and 2V to the mth word line in one cycle at the time of writing. .
[0024]
As a result, even when two or more different types of values are written simultaneously, it can be written in one cycle.
[0025]
According to the present invention, a gate region including a charge storage layer sandwiched between a control gate and a first insulating film and a second insulating film having different conditions for generating a tunnel current, a first diffusion region, and a second diffusion region are provided. And the control gate is the mth (1 ≦ m ≦ M) word line, the first diffusion region and the second diffusion region are the (n−1) th and nth (1 ≦ n ≦ N) bit lines, respectively. A write control method for a non-volatile semiconductor memory device including a memory cell array having a plurality of memory cells connected to the memory cell, wherein a first value is written from the charge storage layer when the first value is written to the memory cell. A voltage VB1 having the same value is applied to the (n-1) th and nth bit lines and a voltage VW1 is applied to the mth word line so that a tunnel current flows out through the film, and a second voltage is applied to the memory cell. When writing a value, the first Control is performed so that a voltage VB2 of the same value is applied to the (n−1) th and nth bit lines and a voltage VW2 is applied to the mth word line so that a tunnel current flows into the charge storage layer through the edge film. It is characterized by doing.
[0026]
According to the write control method of the nonvolatile semiconductor memory device of the present invention, when the potential difference generated in the gate region is V1, no tunnel current flows in either the first insulating film or the second insulating film, and the potential difference generated in the gate region. Is V2 (V1 <V2), the tunnel current flows only in the first insulating film and the tunnel current does not flow in the second insulating film. When performing, the potential difference generated in the gate region becomes V2, and the direction of the electric field generated in the first insulating film is reversed between the case where the first value is written and the case where the second value is written. When the voltages applied to the (n-1) th and nth bit lines and the mth word line are controlled and the memory cell is not written, the potential difference generated in the gate region becomes V1. N-1 and nth bi Trine, and controlling the voltage applied to the word line of the m.
[0027]
According to the write control method of the nonvolatile semiconductor memory device of the present invention, a voltage is applied to the n−1th, nth bit lines, and the mth word line within a range in which no tunnel current is generated in the second insulating film. It controls to do.
[0028]
According to the write control method of the nonvolatile semiconductor memory device of the present invention, when the potential difference generated in the gate region is V, a tunnel current does not flow in either the first insulating film or the second insulating film, and the gate region is generated in the gate region. When the potential difference is 2 V, a tunnel current flows only in the first insulating film and a tunnel current does not flow in the second insulating film, and the first value is written in the memory cell. In this case, when 0 is applied to the (n−1) -th and n-th bit lines and 2V is applied to the m-th word line, the second value is written into the memory cell. It is configured to apply V to the (n−1) th and nth bit lines and to apply −V to the mth word line.
[0029]
The write control method for a nonvolatile semiconductor memory device according to the present invention is characterized in that at the time of writing, at least two voltages of −V and 2V are applied to the mth word line in one cycle.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0031]
FIG. 1 is a diagram for explaining an example of the configuration of the nonvolatile semiconductor memory device of this embodiment.
[0032]
The semiconductor memory device 10 includes a memory cell array (nonvolatile memory) 20 in which a plurality of nonvolatile memory cells are arranged in a matrix and a control circuit 120. The control circuit 120 includes a sense amplifier 30, a column decoder 40, an address buffer 50, a word line control 60, a word decoder 70, a read amplifier / write buffer 80, a data input / output buffer 90, and a command control 100, and a write control circuit. Function as.
[0033]
Command control 100 Receives a memory control command from the outside (CPU or the like) and outputs a control signal to the read amplifier / write buffer 80 and the word line control 60.
[0034]
The address buffer 50 stores an access address received from the outside (CPU or the like).
[0035]
The column decoder 40 identifies a bit line to which an access target memory cell is connected based on the access address.
[0036]
The word decoder 70 identifies a word line to which an access target memory cell is connected based on the access address.
[0037]
The data input / output buffer 90 receives and holds write data from the outside (CPU or the like) when a write request is made, and holds and outputs data read from the memory cell array 20 when a read request is made.
[0038]
The read amplifier / write buffer 80 receives an input command from the command control 100, and at the time of the write request, the read amplifier / write buffer 80 is based on whether the write data received from the data input / output buffer 90 is the first value or the second value. Then, a process for instructing the sense amplifier 30 to apply a voltage to the bit line to which the write target memory cell is connected is performed. At the time of reading, the read value is specified as either the first value or the second value based on the signal received from the sense amplifier 30 and output to the data input / output buffer 90.
[0039]
The sense amplifier 30 is an amplifier circuit, and performs a process of precharging a bit line connected to a read target memory cell and amplifying a current detected from the memory cell when a read request is made. At the time of a write request, a process in which a voltage instructed by the read amplifier / write buffer 80 is applied to two adjacent bit lines connected to the write target memory cell is performed.
[0040]
When a write request is made, the word line control 60 applies 0v → to the word line to which the write target memory cell is connected. 2 V _cc → − V _cc The process which applies the voltage which changes with 1 cycle is performed. Where V _cc Means power supply voltage. When a read request is made, a process for activating the word line connected to the read target memory cell is performed.
[0041]
2A and 2B are cross-sectional structure diagrams for describing the structure of the memory cell of this embodiment.
[0042]
FIG. 2A shows a memory cell in the case where the charge storage layer is formed using a floating gate.
[0043]
As shown in the figure, in the memory cell of this embodiment, an n-channel MOSFET is formed on a P-type silicon substrate 250, and an n-type first diffusion region 230 and an n-type second diffusion region 240 are formed. Are formed as a source and a drain, respectively.
[0044]
A floating gate 226, a first insulating film 224, and a control gate 222 are provided on the second insulating film 228. Note that portions of the second insulating film 228, the floating gate 226, the first insulating film 224, and the control gate 222 are referred to as a gate region 220.
[0045]
The floating gate 226 is made of polysilicon or the like which is in an electrically floating state, and is formed of a silicon oxide film (SiO ₂ ) Are surrounded by a first insulating film 224 and a second insulating film 228.
[0046]
Here, the conditions for generating a tunnel current are different between the first insulating film and the second insulating film. That is, in the potential difference V of the gate region 220, a tunnel current does not flow in either the first insulating film 224 or the second insulating film 228. A current flows and the second insulating film 228 has a configuration in which a tunnel current does not flow.
[0047]
For example, the first insulating film 224 can be configured to satisfy the above condition by making the thickness of the first insulating film 224 thinner than that of the second insulating film 228.
[0048]
Here, V and 2V mean voltages when V is one unit, and the standard of one unit can be arbitrarily determined. For example, the power supply voltage (V _cc ) May be V.
[0049]
In FIG. 2B, the charge storage layer is formed of a silicon nitride film (Si _Three N _Four A memory cell when formed as a charge storage layer using a trap order such as) is shown. The structure of the first diffusion region 230, the second diffusion region 240, and the gate region 220 is shown in FIG. A ).
[0050]
The charge storage layer of the memory cell of this embodiment mode is as shown in FIG. Ni A roving gate 226 may be used, or a charge storage layer 276 using a trap order may be used as shown in FIG.
[0051]
FIG. 3 is a diagram for explaining a connection relationship between a memory cell, a bit line, and a word line.
[0052]
As shown in the figure, memory cells Tr connected to one word line _mn Is N. Here the bit line is BL ₁ ~ BL _N N dummy bit lines BL ₀ have.
[0053]
As described above, the nonvolatile semiconductor memory device according to the present embodiment is characterized by having at least one more bit line than the number N of memory elements that can be controlled by one word line.
[0054]
For example, the memory cell Tr _mn The control gate is connected to the mth (1 ≦ m ≦ M) word line, the first diffusion region (source) and the second diffusion region (drain) are n−1th and nth (1 ≦ n ≦ M), respectively. N) bit line.
[0055]
FIG. 4 is a flowchart for explaining the data write control method of the nonvolatile semiconductor memory device of the present embodiment.
[0056]
The nonvolatile semiconductor memory device of the present embodiment receives an access address in the address buffer (see 50 in FIG. 1) and an access request command in the command control unit 100 (see 100 in FIG. 1), and is a write request. The write data is received by the data input / output buffer (see 90 in FIG. 1).
[0057]
When the nonvolatile semiconductor memory device of this embodiment receives an access request signal (access address, access command, data) or the like, it determines whether or not it is a write request (steps S10 and S20).
[0058]
If it is a write request, the access address is decoded by a column decoder or word recorder, and the word line WL to be controlled is decoded. _m , Bit line BL _n Is specified (steps S20 and S30).
[0059]
If the write value is the first value, the bit line BL _n , BL _n-1 Same voltage V for both _cc Is applied (steps S40 and S50).
[0060]
If the write value is the second value, the bit line BL _n , BL _n-1 The same voltage 0 is applied to both of them (steps S40 and S60).
[0061]
And 0v → 2 V _cc → − V _cc A voltage that changes is applied in one cycle (step S70).
[0062]
FIG. 5 is a diagram showing a voltage applied to a word line to which a write target memory cell is connected during writing in the present embodiment. As shown in the figure, 0v → 2 V _cc → − V _cc The reason why the changing voltage is applied in one cycle 310 is to enable simultaneous writing of both the first value and the second value in one cycle.
[0063]
Next, how the charge is extracted from the charge storage layer or injected into the charge storage layer in steps S50, S60, and S70 will be described.
[0064]
6A, 6B, and 6C are diagrams for explaining the case where electrons are injected into the charge storage layer. That is, the first value (0) is written in the memory cell.
[0065]
The memory cell 210 in FIGS. 6A, 6B, and 6C has the same structure as the memory cell 210 in FIG. It is assumed that a tunnel current flows in the first insulating film 224 when a potential difference of 6 volts occurs in the gate region 220.
[0066]
The control gate 222 of the memory cell 210 is connected to the word line WL. _m The first diffusion region 230 (n +) as a source is connected to the bit line BL. _n-1 The second diffusion region 240 (n +), which is a drain, is connected to the bit line BL. _n It is connected to the.
[0067]
In this embodiment, when electrons are injected into the charge storage layer, 3 V is applied to the source and drain, and a voltage that changes from 6 v to −3 v in one cycle is applied to the gate.
[0068]
In FIG. 6A, the memory cell Tr _mn Bit line BL to which the source (S) and drain (D) are connected _n-1 , BL _n 3v is applied to the memory cell Tr _mn This represents a state before a voltage is applied to the word line to which the gate (G) is connected (0 v in the normal state).
[0069]
As shown in the figure, 3v is applied to the source (S) and the drain (D), the gate (G) is 0v, and the bulk (B) is also 0v. For this reason, there is no potential difference between the bulk and the gate region 220. In addition, since the potential difference between the source (S) and drain (D) and the gate region 220 is 3 v, no tunnel current flows through the first insulating film 224.
[0070]
In FIG. 6B, the memory cell Tr _mn Bit line BL to which the source (S) and drain (D) are connected _n-1 , BL _n 3v is applied to the memory cell Tr _mn 6v is applied to the word line to which the gate (G) is connected.
[0071]
As shown in the figure, 3v is applied to the source (S) and drain (D), and the gate (G) is 6v. Since the source (S) and the drain (D) are 3v, the channel 410 is also 3v, and the potential difference among the gate region 220, the source (S), the drain (D), and the channel 410 is 3v.
[0072]
Therefore, the potential difference generated in the gate region is 3 v, and no tunnel current flows through the first insulating film 224.
[0073]
In FIG. 6C, the memory cell Tr _mn Bit line BL to which the source (S) and drain (D) are connected _n-1 , BL _n 3v is applied to the memory cell Tr _mn -3v is applied to the word line to which the gate (G) is connected.
[0074]
As shown in the figure, 3v is applied to the source (S) and drain (D), and the gate (G) is -3v, so it is not conductive. However, in 420, the potential difference between the gate region 220 and the source (S) becomes 6v, and in 430, the potential difference between the gate region 220 and the drain (D) becomes 6v.
[0075]
Therefore, the potential difference between the portions 420 and 430 of the gate region 220 becomes 6 v, and a tunnel current flows from the floating gate 226 to the control gate 222 in the first insulating film 224. As a result, electrons are injected into the floating gate 226. For this reason, the floating gate becomes-, and this state is assumed to be a state in which the first value (0) is written.
[0076]
After that, the gate is set to 0v to return to the normal state. With this series of operations, the first value (0) can be written into the memory cell by injecting electrons into the floating gate.
[0077]
7A, 7B, and 7C are diagrams for explaining the case where electrons are extracted from the charge storage layer. That is, the second value (1) is written in the memory cell.
[0078]
The memory cell 210 in FIGS. 7A, 7B, and 7C has the same structure as the memory cell 210 in FIG. It is assumed that a tunnel current flows in the first insulating film 224 when a potential difference of 6 volts occurs in the gate region 220.
[0079]
The control gate 222 of the memory cell 210 is connected to the word line WL. _m The first diffusion region 230 (n +) as a source is connected to the bit line BL. _n-1 The second diffusion region 240 (n +), which is a drain, is connected to the bit line BL. _n It is connected to the.
[0080]
In this embodiment, when electrons are extracted from the charge storage layer, 0 V is applied to the source and drain, and a voltage that changes from 6 v to −3 v in one cycle is applied to the gate.
[0081]
Figure 7 In (A), the memory cell Tr _mn Bit line BL to which the source (S) and drain (D) are connected _n-1 , BL _n 0v is applied to the memory cell Tr _mn This represents a state before a voltage is applied to the word line to which the gate (G) is connected (0 v in the normal state).
[0082]
As shown in the figure, 0 v is applied to the source (S) and drain (D), the gate (G) is 0 v, and the bulk (B) is also 0 v. Therefore, there is no potential difference between the bulk, source (S), drain (D), and gate region 220, so that no tunnel current flows through the first insulating film 224.
[0083]
In FIG. 7B, the memory cell Tr _mn Bit line BL to which the source (S) and drain (D) are connected _n-1 , BL _n 0v is applied to the memory cell Tr _mn 6v is applied to the word line to which the gate (G) is connected.
[0084]
As shown in the figure, 0 v is applied to the source (S) and the drain (D), and the gate (G) is 6 v, so that the channel 410 is formed by conduction. Since the source (S) and the drain (D) are 0v, the channel 410 is also 0v, and the potential difference among the gate region 220, the source (S), the drain (D), and the channel 410 is 6v.
[0085]
Therefore, the potential difference generated in the gate region is 6 v, and a tunnel current flows from the control gate 222 to the floating gate 226 in the first insulating film 224. As a result, electrons are extracted from the floating gate 226. For this reason, the floating gate becomes +, and this state is assumed to be a state in which the second value (1) is written.
[0086]
In FIG. 7C, the memory cell Tr _mn Bit line BL to which the source (S) and drain (D) are connected _n-1 , BL _n 0v is applied to the memory cell Tr _mn -3v is applied to the word line to which the gate (G) is connected.
[0087]
As shown in the figure, since the source (S), drain (D), and bulk (B) are 0 v, the potential difference generated in the gate region 220 is 3 v, and no tunnel current flows through the first insulating film 224.
[0088]
After that, the gate is set to 0v to return to the normal state. With this series of operations, electrons can be extracted from the floating gate and the second value (1) can be written into the memory cell.
[0089]
Next, a case where data is read from the memory cell will be described.
[0090]
Bit line BL connected to the second diffusion region (D) of the memory cell to be read _n Is precharged, the word line connected to the memory cell to be read is selected, and a positive voltage is applied.
[0091]
At this time, if the data stored in the memory cell is the first value (0), electrons are accumulated in the floating gate and are in a negative state, so the threshold voltage rises and the positive voltage applied to the control gate is Canceled and not turned ON. For this reason, since no current flows through the bit line, if the current cannot be detected by the sense amplifier, it is determined that the first value (0) is stored.
[0092]
Further, when the data stored in the memory cell is the second value (1), since the electrons are not accumulated in the floating gate, it is neutral and the threshold voltage does not change. Therefore, it is turned on by a positive voltage applied to the control gate and current flows through the bit line. Therefore, when the current is detected by the sense amplifier, it is determined that the second value (1) is stored.
[0093]
In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.
[0094]
In this embodiment, the case where a tunnel current flows through the first insulating film sandwiched between the control gate and the floating gate has been described as an example, but the present invention is not limited to this. For example, the second insulating film may have a configuration in which a tunnel current flows.
[0095]
In this embodiment, the case where two types of voltages are applied in one cycle has been described as an example, but the present invention is not limited to this. For example, when a value is written in one memory cell, one type of voltage corresponding to the written value may be applied.
[0096]
In this embodiment, the nonvolatile semiconductor memory device having the configuration shown in FIG. 1 is described as an example, but the present invention is not limited to this. For example, a configuration having a plurality of nonvolatile semiconductor memory devices configured as shown in FIG. In this way, different values can be written in a plurality of nonvolatile semiconductor memory devices in one cycle.
[0097]
In this embodiment, the case where a memory cell is configured using an n-channel MOS transistor has been described as an example. However, the present invention is not limited to this.
[0098]
In this embodiment mode, no tunnel current flows through either the first insulating film 224 or the second insulating film 228 when the potential difference V of the gate region 220 is reached. Although the case where the tunnel current flows only through the film 224 and the tunnel current does not flow through the second insulating film 228 has been described as an example, the present invention is not limited thereto. In the potential difference V1 of the gate region 220, no tunnel current flows through either the first insulating film 224 or the second insulating film 228. When the potential difference of the gate region 220 becomes V2 (V1 <V2), the first insulating film The present invention can be applied to any case where a tunnel current flows only through 224 and no tunnel current flows through the second insulating film 228.
[0099]
In the present embodiment, the power supply voltage V _cc 0 or Vcc is applied to the bit line, and 0v → V is applied to the word line. _cc → 2V _cc However, the present invention is not limited to this example.
[0100]
The reference voltage and the voltage applied to the bit line and the word can take a given value determined by the conditions under which a tunnel current is generated in the first insulating film and the second insulating film.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an example of a configuration of a nonvolatile semiconductor memory device according to an embodiment.
FIGS. 2A and 2B are cross-sectional structure diagrams for explaining a structure of a memory cell of this embodiment mode;
FIG. 3 is a diagram for explaining a connection relationship between a memory cell and a bit line and a word line;
FIG. 4 is a flowchart for explaining a data write control method of the nonvolatile semiconductor memory device according to the embodiment;
FIG. 5 is a diagram showing a voltage applied to a word line to which a write target memory cell is connected at the time of writing in the present embodiment.
6A, 6B, and 6C are diagrams for explaining a case where electrons are injected into a charge storage layer.
FIGS. 7A, 7B, and 7C are diagrams for explaining a case where electrons are extracted from a charge storage layer. FIGS.
[Explanation of symbols]
10 Semiconductor memory device
20 Memory cell array
30 sense amplifiers
40 column decoder
50 address buffer
60 Word line control
70 word decoder
80 Read amplifier / write buffer
90 Data input / output buffer
120 control circuit
210 memory cells
220 Gate area
222 Control gate
224 First insulating film
226 floating gate
228 Second insulating film
230 First diffusion region
240 Second diffusion region
250 p-type silicon substrate
260 memory cells
270 gate region
272 Control gate
274 First insulating film
276 floating gate
278 Second insulating film
280 First diffusion region
290 Second diffusion region
300 p-type silicon substrate
410 channels
440 Tunnel current

Claims (10)

A control gate and a gate region including a charge storage layer sandwiched between a first insulating film and a second insulating film having different conditions for generating a tunnel current, a first diffusion region, and a second diffusion region; When the gate, the first diffusion region, and the second diffusion region have a predetermined potential difference, the first insulating film has a plurality of memory cells through which a tunnel current flows, and the control gate has an mth (m is 1 ≦ m The first diffusion region and the second diffusion region of the memory cell connected to the word line of ≦ M odd number are the n−1th and nth (n is an odd number of 1 ≦ n ≦ N) bit line, respectively. And the control gate is connected to the mth (m is an even number of 1 ≦ m ≦ M) word line, the first diffusion region and the second diffusion region of the memory cell are respectively the (n-1) th and (n-1) th. n (where n is an even number of 1 ≦ n ≦ N) To the first diffusion region and the second diffusion region of each memory cell, the first diffusion region or the second diffusion region of all other memory cells whose control gates are connected to the same word line. A memory cell array configured to be connected to a bit line different from any of the bit lines connected to the diffusion region of
In the case where a first value that is a logical value of 0 or 1 is written in the memory cell, the control gate, the first diffusion region, and the second diffusion region are separated from the charge storage layer by the first insulation. A voltage is applied to the n−1th and nth bit lines and the mth word line so as to have the predetermined potential difference in the direction of flowing a tunnel current through the film;
When writing a second value that is a logical value of 0 or 1 different from the first value to the memory cell, the control gate, the first diffusion region, and the second diffusion region are the first one. A voltage is applied to the (n−1) th and nth bit lines and the mth word line so as to have the predetermined potential difference in a direction in which a tunnel current flows into the charge storage layer through one insulating film. A writing control circuit for controlling
A non-volatile semiconductor memory device comprising: In claim 1,
The memory cell is
When the potential difference between the control gate and the first diffusion region and the second diffusion region is V1, tunnel current does not flow through either the first insulating film or the second insulating film, and the control gate, the first diffusion region, When the potential difference of the second diffusion region is V2 (V1 <V2), the tunnel current flows only in the first insulating film, and the tunnel current does not flow in the second insulating film,
The write control circuit is
When writing to the memory cell, the potential difference between the control gate, the first diffusion region, and the second diffusion region is V2, and when writing the first value and writing the second value. Controlling the voltage applied to the n−1th and nth bit lines and the mth word line so that the direction of the electric field generated in the first insulating film is reversed in
When writing to the memory cell is not performed, the n−1th and nth bit lines and the mth bit line are set so that the potential difference between the control gate and the first and second diffusion regions is V1. A nonvolatile semiconductor memory device, wherein a voltage applied to a word line is controlled. In any one of Claims 1 thru | or 2.
The memory cell is
When the potential difference between the control gate and the first diffusion region and the second diffusion region is V1, tunnel current does not flow through either the first insulating film or the second insulating film, and the control gate, the first diffusion region, When the potential difference of the second diffusion region is V2 (V1 <V2), the tunnel current flows only in the first insulating film, and the tunnel current does not flow in the second insulating film,
The write control circuit is
In order that the potential difference between the control gate and the first diffusion region and the second diffusion region is V2 or less, the n−1th, nth bit lines, A non-volatile semiconductor memory device that controls to apply a voltage to an m-th word line. In any one of Claims 1 thru | or 3,
The memory cell is
When the potential difference between the control gate and the first diffusion region and the second diffusion region is V, tunnel current does not flow in either the first insulating film or the second insulating film, and the control gate and the first diffusion region When the potential difference between the second diffusion region and the second diffusion region is 2 V, the tunnel current flows only in the first insulating film, and the tunnel current does not flow in the second insulating film.
The write control circuit is
When writing the first value to the memory cell, 0 is applied to the n−1th and nth bit lines and 2V is applied to the mth word line,
When the second value is written in the memory cell, V is applied to the n−1th and nth bit lines and −V is applied to the mth word line. A non-volatile semiconductor memory device. In claim 4,
The write control circuit is
At least two voltages of -V and 2V are applied to the m-th word line at the time of writing in one cycle in which 0 or V is applied to the n-1 and n-th bit lines. A non-volatile semiconductor memory device. A control gate and a gate region including a charge storage layer sandwiched between a first insulating film and a second insulating film having different conditions for generating a tunnel current, a first diffusion region, and a second diffusion region; When the gate, the first diffusion region, and the second diffusion region have a predetermined potential difference, the first insulating film has a plurality of memory cells through which a tunnel current flows, and the control gate has an mth (m is 1 ≦ m The first diffusion region and the second diffusion region of the memory cell connected to the word line of ≦ M odd number are the n−1th and nth (n is an odd number of 1 ≦ n ≦ N) bit line, respectively. And the control gate is connected to the mth (m is an even number of 1 ≦ m ≦ M) word line, the first diffusion region and the second diffusion region of the memory cell are respectively the (n-1) th and (n-1) th. n (where n is an even number of 1 ≦ n ≦ N) To the first diffusion region and the second diffusion region of each memory cell, the first diffusion region or the second diffusion region of all other memory cells whose control gates are connected to the same word line. A write control method for a nonvolatile semiconductor memory device including a memory cell array configured to be connected to a bit line different from any of the bit lines connected to the diffusion region of
In the case where a first value that is a logical value of 0 or 1 is written in the memory cell, the control gate, the first diffusion region, and the second diffusion region are separated from the charge storage layer by the first insulation. A voltage is applied to the n−1th and nth bit lines and the mth word line so as to have the predetermined potential difference in the direction of flowing a tunnel current through the film;
When writing a second value that is a logical value of 0 or 1 different from the first value to the memory cell, the control gate, the first diffusion region, and the second diffusion region are the first one. A voltage is applied to the (n−1) th and nth bit lines and the mth word line so as to have the predetermined potential difference in a direction in which a tunnel current flows into the charge storage layer through one insulating film. A write control method for a nonvolatile semiconductor memory device, characterized by: In claim 6,
In the memory cell, when the potential difference between the control gate and the first diffusion region and the second diffusion region is V1, no tunnel current flows through either the first insulating film or the second insulating film, When the potential difference between the first diffusion region and the second diffusion region is V2 (V1 <V2), the tunnel current flows only in the first insulating film, and the tunnel current does not flow in the second insulating film. If you are
When writing to the memory cell, the potential difference between the control gate, the first diffusion region, and the second diffusion region is V2, and when writing the first value and writing the second value. Controlling the voltage applied to the n−1th and nth bit lines and the mth word line so that the direction of the electric field generated in the first insulating film is reversed in
When writing to the memory cell is not performed, the n−1th and nth bit lines and the mth bit line are set so that the potential difference between the control gate and the first and second diffusion regions is V1. A write control method for a nonvolatile semiconductor memory device, wherein a voltage applied to a word line is controlled. In any of claims 6 to 7,
In the memory cell, when the potential difference between the control gate and the first diffusion region and the second diffusion region is V1, no tunnel current flows through either the first insulating film or the second insulating film, When the potential difference between the first diffusion region and the second diffusion region is V2 (V1 <V2), the tunnel current flows only in the first insulating film, and the tunnel current does not flow in the second insulating film. If you are
In order that the potential difference between the control gate and the first diffusion region and the second diffusion region is V2 or less, the n−1th, nth bit lines, A write control method for a nonvolatile semiconductor memory device, wherein control is performed so that a voltage is applied to an m-th word line. In any of claims 6 to 8,
In the memory cell, when the potential difference between the control gate and the first diffusion region and the second diffusion region is V, no tunnel current flows in either the first insulating film or the second insulating film, and the control gate When the potential difference between the first diffusion region and the second diffusion region is 2V, the tunnel current flows only in the first insulating film, and the tunnel current does not flow in the second insulating film. When the first value is written in the memory cell, 0 is applied to the n−1th and nth bit lines and 2V is applied to the mth word line,
When the second value is written in the memory cell, V is applied to the n−1th and nth bit lines and −V is applied to the mth word line. A write control method for a nonvolatile semiconductor memory device. In claim 9,
At least two voltages of -V and 2V are applied to the m-th word line at the time of writing in one cycle in which 0 or V is applied to the n-1 and n-th bit lines. A writing control method for a nonvolatile semiconductor memory device.

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