JP3934173B2 - Display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The invention disclosed in this specification relates to a structure of an active matrix display device. Typically, the present invention relates to a structure of an active matrix liquid crystal display device.
[0002]
[Prior art]
In recent years, a display device called a flat panel display has attracted attention. The flat panel display is a general term for thin display devices having a thickness of several centimeters or less using a liquid crystal, a light emitting material, and further a fluorescent material.
[0003]
For example, a liquid crystal display device has a structure in which a liquid crystal is held between a pair of glass substrates. And it has the function to modulate the light which permeate | transmits a liquid-crystal layer by applying an electric field to a liquid crystal and changing the optical characteristic.
[0004]
What is called an active matrix type is known as a further advanced structure of a flat panel display. This has a configuration in which switching elements are arranged on the respective pixel electrodes arranged in a matrix. As the switching element, a thin film transistor using a silicon thin film is generally used.
[0005]
The silicon thin film constituting the thin film transistor is roughly classified into an amorphous silicon film and a crystalline silicon film. At present, an amorphous silicon film is used in practice.
[0006]
However, a thin film transistor using an amorphous silicon film has a problem that its operation speed is slow and a P-channel type is not practical, so that a peripheral drive circuit cannot be integrated.
[0007]
On the other hand, when a crystalline silicon film is used, a film capable of high-speed operation is obtained, and a P-channel type is also obtained. Therefore, the peripheral driver circuit can be formed using thin film transistors. The peripheral driver circuit can be integrated on the same substrate as the active matrix circuit.
[0008]
[Problems to be solved by the invention]
In the liquid crystal display device, the voltage applied to the liquid crystal is determined by the liquid crystal material. Accordingly, the drive voltage required for the active matrix circuit and the peripheral drive circuit for driving the active matrix circuit is determined accordingly.
[0009]
When an active matrix type liquid crystal display device is operated with a necessary driving voltage, a thin film transistor generally has insufficient withstand voltage. This shortage of breakdown voltage causes problems such as deterioration of characteristics of the thin film transistor, defective circuit operation, and an increase in leakage current. Generally, these problems are perceived as a reduction in device reliability.
[0010]
An object of the invention disclosed in this specification is to provide an active matrix display device integrated with a peripheral driving circuit, which solves the above-described problem of withstand voltage. That is, it is an object of the present invention to provide an active matrix display device integrated with a peripheral drive circuit having high reliability.
[0011]
[Means for Solving the Problems]
In the invention disclosed in this specification, an active matrix circuit formed on the same substrate and a peripheral driving circuit are integrated, and the driving voltage that requires a thin film transistor included in each circuit is tolerated. At the same time, a thin film transistor having characteristics required for each circuit is selectively arranged. That is, thin film transistors that operate with different structures and different operating principles are arranged in the active matrix circuit and the peripheral drive circuit. Such a configuration is obtained as a result of requiring the required characteristics.
[0012]
The following structure is employed as a thin film transistor that can withstand the above-described required driving voltage, in other words, a thin film transistor with an increased breakdown voltage.
[0013]
In the invention disclosed in this specification, an element having the following structural features is arranged in a buffer circuit of a peripheral drive circuit that requires high withstand voltage, high speed operation, and high ON current characteristics. Features.
[0014]
This element basically has a configuration of an insulated gate field effect transistor. The current path during the ON operation is different from the leak current path during the OFF operation.
[0015]
In other words, the moving path of carriers (electrons if N-channel type) during the ON operation and the moving path of carriers (holes if N-channel type) during the OFF operation are different.
[0016]
With such a configuration, a configuration with low OFF current characteristics, high breakdown voltage, and high reliability can be obtained. And it can be operated at high speed, and a larger ON current value can flow.
[0017]
In order to realize the above-described configuration, in the case of an N-channel thin film transistor, an N-type region is disposed in a channel formation region having a conductivity type that is substantially or substantially intrinsic. (Hereinafter, an explanation will be given by taking the N channel type as an example)
[0018]
In general, an N-type layer is formed in the channel formation region during the ON operation. Therefore, during the ON operation, the N-type region does not become a major obstacle to carriers moving in the channel formation region.
[0019]
On the other hand, in the OFF operation (in the case of the N channel type) in which a negative voltage is applied to the gate electrode, a P type inversion layer is formed in the channel formation region.
[0020]
However, the path width of the P-type semiconductor layer becomes narrow due to the presence of the N-type region described above, and the path becomes long and winding. Of course, in order to do this, the above-described N-type region is arranged so that the width of the path (path connecting the source and drain) made of the P-type inversion layer during the OFF operation becomes narrower and longer. There is a need.
[0021]
In this way, the carrier path that moves between the source and drain during the OFF operation can be made longer than the carrier movement path during the ON operation (the shortest distance connecting the source and drain).
[0022]
And the movement of the carrier at the time of OFF operation | movement can be suppressed and a proof pressure can be raised. At the same time, the OFF current value can be lowered. Further, high reliability can be obtained.
[0023]
A specific configuration example of this element is shown in FIG. The configuration shown in FIG. 1 has a configuration in which an ON current path 111 and an OFF current path 109 are different between the source region 101 and the drain region 103.
[0024]
That is, by disposing the regions 104, 106, and 107 having the same conductivity type as the source region and the drain region in the channel region, the P-type inversion path 109 is twisted by these regions during the OFF operation. . This path 109 is longer than the distance (channel length during the ON operation) connecting the source region and the drain region.
[0025]
In addition, it is important to improve the breakdown voltage and the reliability that the path of carriers conducted through the side surface of the active layer 100 can be eliminated during the OFF operation.
[0026]
On the side surface of the active layer, there are high-density traps formed at the time of patterning, and a carrier movement path through the trap is easily formed. In particular, the cause of the OFF current during the OFF operation is largely due to the movement of carriers via the side surface of the active layer. Further, the carrier movement path on the side surface of the active layer is unstable and causes a decrease in the reliability of the device.
[0027]
Therefore, setting the carrier movement path in the OFF operation as indicated by 109 in FIG. 1 is useful for increasing the withstand voltage during the OFF operation and providing high reliability.
[0028]
In addition, the thin film transistor shown in FIG. 1 has a short carrier movement path during the ON operation (compared to the OFF operation) and a wide width, so that high speed operation is possible and a large current flows. It has the characteristics that can be done.
[0029]
FIG. 2 shows a configuration example in which the active matrix circuit and the peripheral drive circuit are integrated on the same glass substrate. In the configuration shown in FIG. 2, a gate driver circuit is shown as a peripheral drive circuit. FIG. 3 shows details of the circuit shown in FIG.
[0030]
Note that a source driver circuit (not shown) has a configuration in which a sampling circuit is arranged after the buffer circuit of the gate driver circuit shown in FIG.
[0031]
In the gate driver circuit shown in FIG. 2, a buffer circuit is particularly required to have a high breakdown voltage. For example, in a liquid crystal electro-optical device, a predetermined voltage is required to make the liquid crystal respond. For example, at present, the buffer circuit is required to have a breakdown voltage of about 16 V at the minimum. In this case, it is known that the shift register circuit only needs to have a breakdown voltage of about 12V.
[0032]
In this case, the same breakdown voltage as that of the buffer circuit is required for the thin film transistor disposed in the pixel matrix circuit. However, the breakdown voltage of the thin film transistor disposed in the pixel can be increased by disposing the LDD region and the offset gate region. Further, by adopting a configuration in which a plurality of thin film transistors equivalently described later are connected in series, the breakdown voltage can be increased.
[0033]
On the other hand, since the buffer circuit is required to operate at high speed, there is a limit to improving the breakdown voltage by arranging the LDD region and the offset gate region. This is because if the LDD region and the offset gate region are arranged, the resistance between the source and the drain becomes high, which is a disadvantageous structure for high-speed operation.
[0034]
In addition, the thin film transistor constituting the buffer circuit needs to pass a large ON current, and from this point of view, it is disadvantageous to dispose an LDD region and an offset gate region that increase the resistance between the source and the drain.
[0035]
In addition, a configuration in which a plurality of thin film transistors described below are equivalently connected in series is disadvantageous in obtaining high-speed operation and large ON current characteristics in the sense that the distance between the source and the drain becomes long.
[0036]
Therefore, a thin film transistor as shown in FIG. 1 is arranged in the buffer circuit. By doing so, it is possible to obtain a high-speed operation and a high ON current characteristic required for the buffer circuit, and a high breakdown voltage characteristic. In particular, the reliability in the case of performing an operation or an operation in which a large ON current flows can be improved.
[0037]
The invention disclosed in this specification can be used not only for an active matrix liquid crystal display device but also for a flat panel display having an active matrix type. For example, the present invention can be used for an active matrix liquid crystal display device using an EL element.
[0038]
Further, the present invention can be used not for a direct-view flat panel display but for a projection-type display device that projects an optically modulated image on a screen onto a screen.
[0039]
One of the inventions disclosed in this specification is:
The active matrix circuit and the peripheral drive circuit are integrated on the same substrate,
The thin film transistors disposed in the active matrix circuit and the thin film transistors disposed in the peripheral driver circuit have essentially different operating principles.
[0040]
A specific example of the above configuration will be described with reference to FIGS. FIG. 2 shows a schematic configuration of one substrate of an active matrix display device integrated with a peripheral drive circuit.
[0041]
Here, a thin film transistor having a structure as shown in FIG. In the shift register circuit 201 of the peripheral driver circuit, thin film transistors as illustrated on the left side of FIG. 9B are arranged. In the active matrix circuit 205, a thin film transistor as shown on the right side of FIG.
[0042]
Here, the thin film transistors shown in FIG. 9 have essentially the same structure and operate based on the same principle. However, the thin film transistor shown in FIG. 1 has a different structure and operates based on different operating principles.
[0043]
The reason for this configuration is to satisfy various characteristics and features required for each circuit.
[0044]
Other inventions are:
The active matrix circuit and the peripheral drive circuit are integrated on the same substrate,
The thin film transistor disposed in the active matrix circuit and the thin film transistor disposed in the peripheral driving circuit have essentially different structures.
[0045]
Examples of the essentially different structures mentioned here include, for example, a planar type and a stagger type, a planar type and an inverted stagger type, the structure shown in FIG. 1, and the structure shown in FIG. It should be noted that the presence / absence of the LDD region and its size, the size of the active layer, the size of the electrode, the resistance and impurity concentration of the source / drain region, and the characteristics (for example, the size of the active layer) Differences such as differing properties) are not considered to be essentially different structures. That is, even if there is such a difference, it is regarded as the same structure.
[0046]
In general, when following essentially different operating principles, the structure is naturally different.
[0047]
Other inventions are:
The active matrix circuit and the peripheral drive circuit are integrated on the same substrate,
The peripheral driving circuit includes at least two kinds of thin film transistors having essentially different structures,
One of the two types of thin film transistors has essentially the same structure as the thin film transistors disposed in the active matrix circuit,
The other of the two types of thin film transistors has a structure that is essentially different from that of the thin film transistors arranged in the active matrix circuit.
[0048]
Other inventions are:
The active matrix circuit and the peripheral drive circuit are integrated on the same substrate,
In the peripheral driving circuit, at least two kinds of thin film transistors operating on essentially different operating principles are arranged,
One of the two types of thin film transistors operates on essentially the same operating principle as the thin film transistors arranged in the active matrix circuit,
The other of the two types of thin film transistors operates on an operating principle that is essentially different from that of the thin film transistors arranged in the active matrix circuit.
[0049]
Other aspects of the invention are:
The active matrix circuit and the peripheral drive circuit are integrated on the same substrate,
The thin film transistor disposed in the active matrix circuit and the thin film transistor disposed in the peripheral driver circuit have essentially different cross-sectional structures.
[0050]
Other aspects of the invention are:
The active matrix circuit and the peripheral drive circuit are integrated on the same substrate,
The thin film transistor disposed in the active matrix circuit and the thin film transistor disposed in the peripheral driving circuit have different structures,
The thin film transistor disposed in the peripheral driver circuit has a structure in which an ON current path and an OFF current path are different.
[0051]
Other aspects of the invention are:
The active matrix circuit and the peripheral drive circuit are integrated on the same substrate,
The thin film transistor disposed in the active matrix circuit and the thin film transistor disposed in the peripheral driving circuit have different structures,
The thin film transistor disposed in the peripheral driver circuit is characterized in that a plurality of regions having the same conductivity type as the source and drain regions are disposed in a channel formation region.
[0052]
DETAILED DESCRIPTION OF THE INVENTION
In an active matrix type liquid crystal display device integrated with a peripheral driving circuit as shown in FIG. 2, a thin film transistor having a structure as shown in FIG. In the active matrix region 205, a thin film transistor in which an LDD region is arranged and a thin film transistor in which a plurality of equivalent thin film transistors shown in FIG. 13 are connected in series are arranged.
[0053]
In this way, thin film transistors having different structures and different operating principles are selectively arranged in the peripheral drive circuit and the active matrix circuit. By doing in this way, it can be set as the circuit structure corresponding to the proof pressure and characteristic which are required for each circuit. An active matrix display device having high performance and high reliability can be obtained.
[0054]
【Example】
[Example 1]
This embodiment shows an example in which the invention disclosed in this specification is applied to a liquid crystal display device having an active matrix type. FIG. 2 shows an outline of an active matrix circuit (pixel matrix circuit) and a peripheral drive circuit for driving the active matrix circuit.
[0055]
In the configuration shown in FIG. 2, a gate driver circuit that is a peripheral drive circuit is configured by the shift register circuit 201, the NAND circuit 202, and the level shifter 204. However, the peripheral drive circuit is not necessarily configured only with this configuration. For example, a circuit having a predetermined arithmetic function and an integrated circuit having a predetermined function are arranged as necessary. Note that the peripheral driver circuit in this specification includes a configuration in which an external integrated circuit (IC chip) is arranged in addition to a thin film integrated circuit.
[0056]
Although not shown in FIG. 2, the source driver circuit has a structure in which a sampling circuit is arranged after the buffer circuit of the gate driver circuit.
[0057]
The invention disclosed in this specification is particularly characterized in that a thin film transistor having the structure shown in FIG. 1 is arranged in a buffer circuit.
[0058]
The thin film transistor as shown in FIG. 1 has a drawback that the occupied area becomes large. This is because it is necessary to form a complicated pattern such as the impurity regions 104 to 107, and it is difficult to reduce the size of the entire device in consideration of a margin for mask alignment.
[0059]
In a liquid crystal display device, it is required to maximize the aperture ratio of an active matrix region that needs to transmit light.
[0060]
Therefore, disposing a thin film transistor having a large occupation area as shown in FIG. 1 in the active matrix region is disadvantageous from the viewpoint of securing the aperture ratio.
[0061]
Therefore, in the configuration shown in this embodiment, the buffer circuit (204 in FIG. 2) of the peripheral driver circuit where the withstand voltage is most required is configured by a thin film transistor having the configuration shown in FIG. The buffer circuit is basically composed of a complementary circuit composed of a P-channel type thin film transistor having the same configuration as the N-channel type thin film transistor having the configuration shown in FIG.
[0062]
The thin film transistor shown in FIG. 1 will be described below. Here, a structure of an N-channel thin film transistor is described.
[0063]
FIG. 1A shows an outline of a thin film transistor viewed from above. In the structure illustrated in FIG. 1A, reference numeral 101 denotes a source region, 102 denotes a channel formation region, and 103 denotes a drain region. The active layer 100 of the thin film transistor is configured with these three regions as main components.
[0064]
Note that the channel formation region 102 is defined as a region where a channel serving as a channel (a channel connecting the source region and the drain region) is formed in at least a part of the channel forming region 102.
[0065]
The source region 101 and the drain region 103 are N-type. In the channel formation region 102, a region 105 having a substantially intrinsic conductivity type (I type) is formed. The area indicated by 105 is a path along which the carrier moves during the OFF operation.
[0066]
In order to control the threshold characteristics of the TFT, the region indicated by 105 is a weak P-type (generally P-type). ^- Type or P ^- It is also effective to be expressed as a type).
[0067]
Reference numerals 104, 106, and 107 denote N-type regions formed in the channel formation region 102. Reference numeral 108 denotes a gate electrode. In the configuration shown in FIG. 1, a gate insulating film (not shown) is formed so as to cover the active layer 100, and a gate electrode 108 is disposed thereon.
[0068]
During the ON operation, the positive voltage applied to the gate electrode 108 makes the region 105 serving as a channel N-type according to the electrostatic induction effect. In this state, the N-type regions indicated by 104, 106, and 107 are integrated with the channel in the channel formation region.
[0069]
Therefore, a state in which the entire channel formation region 102 becomes a carrier movement path is realized. That is, the carrier that becomes the carrier of the ON current is moved in the entire channel formation region indicated by 102.
[0070]
Thus, electrons that are carriers of the ON current move from the source region 101 to the drain region 103 through the channel formation region 102 with the shortest distance and using the entire channel formation region.
[0071]
In the OFF operation in which a negative voltage is applied to the gate electrode 108, the conductivity type of the intrinsic region indicated by 105 is inverted to the P type. However, the conductivity types of the N-type regions 104, 106, and 107 are not inverted and remain N-type.
[0072]
The OFF current (leakage current) is generated when carriers (in this case, holes) move from the drain region 103 to the channel formation region 102 over the barrier of the PN junction via the trap level and the impurity level.
[0073]
However, in the configuration shown in FIG. 1, the P-type inversion layer, which is a movement path of carriers (holes) moving from the drain region 103 to the source region 101, is thin and winding as indicated by 105. Yes.
[0074]
As a result, during the OFF operation, the movement of carriers from the drain region 103 to the source region 101 is greatly suppressed. As a result, the OFF current value is greatly suppressed. Further, the reverse breakdown voltage can be increased. Further, high reliability can be obtained.
[0075]
As described above, in the configuration shown in FIG. 1A, the N-type regions 104, 106, and 107 that serve as barriers are disposed in the channel formation region 102 during the OFF operation, and as a result, the carriers in the OFF operation operate. The travel route is restricted. As a result, the OFF current can be reduced and the breakdown voltage can be increased.
[0076]
Further, the N-type regions 104, 106, and 107 do not become a large barrier in the N-type channel formation region 105 during the ON operation. Therefore, the movement of carriers during the ON operation is not hindered, and a large current can flow. Moreover, high-speed operation can be performed.
[0077]
The state of operation of such a TFT will be described with reference to FIG. In FIG. 4, Vg represents a gate voltage (Vg> 0), Ec represents a conduction band, Ev represents a valence band, and Ef represents a Fermi level.
[0078]
First, consider a case where the N-channel TFT is in an on state (a state where a positive voltage is applied to the gate).
[0079]
In this case, the region indicated by 105 is in a band state as shown in FIG. That is, electrons are accumulated on the semiconductor surface, and the electrons are easily moved.
[0080]
At this time, the regions 104, 106, and 107 are in a band state as shown in FIG. In the state of FIG. 4D, since the Fermi level Ef is originally pushed up near the conduction band Ec, many electrons are always present in the conductor.
[0081]
Therefore, when a positive voltage is applied to the gate, similarly to the region 105, the regions 104, 106, and 107 are in a band state in which electrons easily move. And the potential barrier between these regions does not become large. Accordingly, electrons which are majority carriers move from the source region 101 to the drain region 103. That is, electrons move along the path indicated by 111.
[0082]
Next, consider a case where the N-channel TFT is in an OFF state (a state where a negative voltage is applied to the gate). At this time, the region 105 serving as a channel during the ON operation is in a band state as shown in FIG. That is, the holes are gathered on the semiconductor surface (interface with the gate insulating film) and electrons are removed. For this reason, the movement of electrons between the source / drain is extremely small.
[0083]
On the other hand, in the N-type regions indicated by 104, 106 and 107, the Fermi level Ef is pushed up near the conduction band Ec. In this state, holes are minority carriers and do not collect on the surface of the semiconductor surface. Therefore, at the time of the OFF operation, the N-type region is in a state where the energy band is bent only slightly as shown in FIG. That is, the N-type regions indicated by 104, 106, and 107 maintain the N-type as they are during the OFF operation.
[0084]
During the OFF operation, the values of Ev and Ec are different as can be seen by comparing FIG. 4 (A) and FIG. 4 (B). This difference becomes a potential barrier. Due to the presence of this potential barrier, movement between the source and drain in the shortest distance, whether holes or electrons, is hindered.
[0085]
As shown in FIG. 4A, majority carriers become holes in the region 105 where the P-type inversion layer is formed during the OFF operation. However, since the above-described potential barrier exists, the majority carrier moves along a winding path indicated by 109.
[0086]
As described above, in the ON state, the path indicated by 111 is the carrier movement path, and in the OFF state, the path indicated by 109 is the carrier movement path.
[0087]
Here, an example of an N-channel thin film transistor is shown. In the case of a P-channel thin film transistor, a region that is basically N-type may be changed to P-type.
[0088]
5 and the following shows a process of forming a thin film transistor circuit having a CMOS structure that constitutes the shift register circuit of FIG. 2 and an N channel thin film transistor disposed in each pixel of the active matrix circuit on the same glass substrate. Note that the thin film transistors shown in FIGS. 5A and 5B have different arrangement positions, and the shapes and operating principles are essentially the same.
[0089]
In the figure, the manufacturing process of the CMOS circuit is shown on the left side. In addition, a manufacturing process of an N-channel thin film transistor arranged in the active matrix circuit is shown on the right side.
[0090]
Note that the numerical values and conditions in the manufacturing steps shown below are examples. That is, it can be changed or optimized as necessary, and is not limited to the described values.
[0091]
First, a silicon oxide film having a thickness of 3000 mm is formed as a base film 502 on a glass substrate (or quartz substrate) 501. A sputtering method is used as the film forming method.
[0092]
Next, an amorphous silicon film 503 is formed on the base film 502 to a thickness of 1000 mm by plasma CVD. The film forming method may be a low pressure thermal CVD method. In this way, the state shown in FIG.
[0093]
Next, the amorphous silicon film 103 is crystallized by heat treatment. As the crystallization method, laser light irradiation, lamp annealing, or a method using these methods in combination with heat treatment may be used.
[0094]
After the amorphous silicon film 503 is crystallized, patterning is performed to form island regions indicated by 504, 505, and 506. (Fig. 5 (B))
[0095]
In FIG. 5B, reference numeral 504 denotes an active layer of a P-channel thin film transistor which will later constitute a CMOS circuit. Reference numeral 505 denotes an active layer of an N-channel type thin film transistor that will later constitute a CMOS circuit. Reference numeral 506 is an active layer of an N-channel type thin film transistor which is disposed later in the pixel matrix circuit.
[0096]
In this way, the state shown in FIG. Next, an aluminum film 507 for forming a gate electrode is formed by sputtering to a thickness of 5000 mm. This aluminum film 507 contains scandium (or yttrium) in an amount of 0.1 to 0.2% by weight in order to suppress generation of hillocks and whiskers due to abnormal growth of aluminum later. (Fig. 5 (C))
[0097]
Hillocks and whiskers are needle-like or sting-like projections due to abnormal growth of aluminum following heating.
[0098]
When the aluminum film 507 is formed, an anodic oxide film 508 having a dense film quality is formed. The anodic oxide film 508 having a dense film quality is formed using an ethylene glycol solution containing 3% tartaric acid as an electrolytic solution.
[0099]
That is, in this electrolytic solution, the aluminum film 507 is used as an anode and platinum is used as a cathode, and an anodic oxidation current is passed. Here, the applied voltage is controlled so that the thickness of the anodic oxide film 508 is about 100 mm.
[0100]
This anodic oxide film functions to improve the adhesion of a resist mask to be arranged in a later step.
[0101]
In this way, the state shown in FIG. Next, as shown in FIG. 6A, resist masks 515, 516, and 517 are arranged, and the aluminum film 507 (see FIG. 5C) is patterned. At this time, care must be taken because the patterning of the aluminum film 507 becomes difficult if the thickness of the anodic oxide film 508 (see FIG. 5C) is large.
[0102]
In FIG. 6A, reference numerals 509, 511, and 513 denote aluminum patterns that serve as prototypes (bases) of the gate electrodes. Reference numerals 510, 512, and 514 denote anodic oxide films having a dense film quality remaining on the aluminum pattern.
[0103]
When the state shown in FIG. 6A is obtained, anodic oxidation is performed again. Here, an anodized film having a porous shape indicated by 518, 519, and 520 is formed. (Fig. 6 (B))
[0104]
In this step, an aqueous solution containing 3% oxalic acid is used as the electrolytic solution. In this electrolytic solution, anodization is performed using the arunnium pattern indicated by 509, 511, and 513 as an anode and platinum as a cathode.
[0105]
In this step, since resist masks 515, 516, and 517 and dense anodic oxide films 510, 512, and 514 exist, anodization proceeds on the side surfaces of aluminum patterns 509, 511, and 513.
[0106]
Accordingly, portions indicated by 518, 519, and 520 in FIG. 2B are formed as porous anodic oxide films. This porous anodic oxide film can be controlled by the anodic oxidation time.
[0107]
Here, the porous anodic oxide films 518, 519, and 520 are formed to a thickness of 5000 mm. This porous anodic oxide film is used later when a low concentration impurity region (LDD region) is formed.
[0108]
When the state shown in FIG. 6B is obtained, the resist masks 515, 516, and 517 are removed with a dedicated stripping solution. Then, anodic oxidation is again performed under conditions for forming an anodic oxide film having a dense film quality.
[0109]
As a result, an anodic oxide film having a dense film quality indicated by 51, 52 and 53 is formed. Here, anodic oxide films 51, 52, and 53 are formed in an integrated state with previously formed anodic oxide films 510, 512, and 514. (Fig. 6 (C))
[0110]
In this process, since the electrolytic solution penetrates into the porous anodic oxide films 518 to 520, the anodic oxidation having a dense film quality in the state shown by 51, 52 and 53 in FIG. 6C. A film is formed.
[0111]
The film thickness of the anodic oxide films 51, 52 and 53 having a dense film quality is 1000 mm. This anodic oxide film has a function of electrically and mechanically protecting the surface of the gate electrode (and the gate wiring extending therefrom). Specifically, it has a function of improving electrical insulation and suppressing generation of hillocks and whiskers.
[0112]
In the step shown in FIG. 6C, gate electrodes 521 of P-channel thin film transistors and gate electrodes 522 and 523 of N-channel thin film transistors are defined.
[0113]
After obtaining the state shown in FIG. 6C, P (phosphorus) ions are implanted. In this step, P ions are implanted with a dose for forming the source and drain regions. P ion implantation is performed by a known plasma doping method. (Fig. 7 (A))
[0114]
In this step, P ions are implanted at a relatively high concentration in each of the regions 524, 526, 527, 529, 530, and 532. The dose in this step is 1 × 10 ¹⁵ / Cm ² And The acceleration voltage of ions is 80 kV.
[0115]
In the P ion implantation step shown in FIG. 7A, P ions are not implanted into the respective regions 525, 528, and 531. Therefore, the intrinsic or substantially intrinsic state is maintained as it is.
[0116]
When the implantation of P ions shown in FIG. 7A is completed, the porous anodic oxide films 518, 519, and 520 are removed using a mixed acid obtained by mixing phosphoric acid, acetic acid, and nitric acid.
[0117]
Then, P ions are implanted again as shown in FIG. In this step, P ions are implanted with a dose amount lower than that in the step of FIG. Here, the dosage is 0.5 to 1 × 10 ¹⁴ / Cm ² And The acceleration voltage of ions is set to 70 kV.
[0118]
As a result of this step, each region indicated by 533, 535, 536, 538, 559, 541 is N ^- This is a type (weak N-type) region. That is, it becomes a low concentration impurity region to which P ions are added at a lower concentration than each region of 524, 526, 527, 529, 530, and 532. (Fig. 7 (B))
[0119]
The regions 534, 537, and 540 immediately below the gate electrode are defined as channel forming regions.
[0120]
Strictly speaking, the facet gate regions are formed on both sides of the channel formation region with the film thickness of the dense anodic oxide films 51, 52, 53 formed in the step of FIG. 6C. The However, in this embodiment, the thickness of the anodic oxide films 51, 52, and 53 is about 1000 mm, so that the description of the offset gate region is omitted in the drawing.
[0121]
When the impurity ion implantation shown in FIG. 7B is completed, a resist mask 542 is arranged as shown in FIG. 8A, and B (boron) ions are implanted this time.
[0122]
By the implantation of B ions, the conductivity types of the regions 543, 544, 545, and 546 are inverted from N-type to P-type. Here, the dose amount of B ions is 2 × 10. ¹⁵ / Cm ² And The acceleration voltage is 60 kV.
[0123]
After the implantation of B ions shown in FIG. 4A, the resist mask 542 is removed. Then, the entire region is irradiated with a KrF excimer laser to anneal the region into which the impurity ions have been implanted and activate the implanted impurity ions.
[0124]
In this way, the P and N channel type thin film transistors constituting the CMOS circuit and the N channel type thin film transistors arranged in the active matrix region are simultaneously formed.
[0125]
Then, an interlayer insulating film 551 is formed as shown in FIG. The interlayer insulating film 551 is composed of a silicon oxide film. In addition to the silicon oxide film, a laminated film of a silicon nitride film and a silicon oxide film, or a laminated film of a silicon oxide film or a silicon nitride film and a resin film can be used.
[0126]
After the interlayer insulating film 551 is formed, contact holes are formed. Then, a source electrode 552 and a drain electrode 553 of a P-channel thin film transistor, and a drain electrode 553 and a source electrode 554 of an N-channel thin film transistor are formed.
[0127]
Thus, a CMOS circuit in which a P-channel thin film transistor and an N-channel thin film transistor are configured to be complementary is completed. At the same time, a source electrode 555 (generally provided extending from an image signal line (source wiring) arranged in a matrix) and a drain electrode 556 are formed to complete an N-channel thin film transistor in a pixel matrix portion.
[0128]
When the state is obtained in FIG. 9A, a second interlayer insulating film 557 is formed. Then, contact holes are formed, and pixel electrodes 558 made of ITO are formed.
[0129]
Then, heat treatment is performed for 1 hour in a hydrogen atmosphere at 350 ° C. to repair defects in the active layer. In this way, a configuration is obtained in which the active matrix circuit (pixel matrix circuit) and a part of the peripheral drive circuit are arranged simultaneously.
[0130]
[Example 2]
This embodiment relates to a thin film transistor different from the structure shown in FIG. FIG. 10A shows an outline of the thin film transistor of this example as viewed from above. In this embodiment, an example of an N-channel thin film transistor is described.
[0131]
Note that FIG. 10B is a schematic diagram illustrating an operation state of the thin film transistor whose top schematic view is illustrated in FIG.
[0132]
In FIG. 10A, reference numeral 1001 denotes a semiconductor layer made of an island-shaped silicon thin film that constitutes an active layer of a thin film transistor. Reference numeral 1002 denotes an N-type region that functions as a source region.
[0133]
Reference numeral 1003 denotes an active layer region existing below the gate electrode 1006 and serving as a channel formation region. An N-type region 1005 is formed in the channel formation region 1003. The region other than the region indicated by 1005 in the channel formation region has an intrinsic or substantially intrinsic conductivity type.
[0134]
A region indicated by 1005 is integrated with an N-type channel during the ON operation. This region also serves as a barrier that hinders the movement of carriers that cause an OFF current in the channel formation region 1003 serving as an inverted P-type layer during the OFF operation.
[0135]
Reference numeral 1004 denotes a drain region having an N type. Reference numeral 1007 denotes an LDD (lightly doped drain) region disposed between the channel formation region 1003 and the drain region 1004. The LDD region 1007 contains an impurity imparting N-type at a lower concentration than the drain region 1004.
[0136]
The LDD region 1007 has a function of relaxing a strong electric field formed between the channel formation region 1003 and the drain region 1004 and suppressing carrier movement from the drain region to the channel formation region during the OFF operation. ing.
[0137]
An operation state of the configuration illustrated in FIG. FIG. 10B is a schematic diagram showing a carrier movement state (path) during the ON operation and the OFF operation of the thin film transistor shown in this embodiment.
[0138]
Reference numeral 1008 in FIG. 10 indicates a path along which carriers move when the thin film transistor is turned on. During the ON operation, a positive voltage is applied to the gate electrode 1006, and the channel formation region 1003 becomes N-type. At this time, since the N-type region 1005 is substantially integrated with the channel formation region 1003, carriers (electrons) move from the source region 1002 to the drain region 1004 through a path indicated by 1008. That is, during the ON operation, the carrier moves between the source / drain with the shortest distance and in the entire channel formation region 103.
[0139]
On the other hand, a negative voltage is applied to the gate electrode 1006 during the OFF operation. Then, the surface of the region other than the region indicated by 1005 in the channel formation region 1003 is inverted to P-type. At this time, the region indicated by 1005 remains N-type.
[0140]
During the OFF operation, since the N-type region 1005 serves as a barrier, the movement of carriers (holes) moving from the drain region 1004 to the source region 1002 is mostly performed by paths indicated by 1009 and 1010.
[0141]
However, the routes indicated by 1009 and 1010 are longer and narrower than the carrier moving route 1008 during the ON operation.
[0142]
That is, the ON current path is short and wide, and the OFF current path is long and narrow.
[0143]
By doing so, a configuration having a relatively large ON current value and a small OFF current value can be realized. And it can have a high pressure | voltage resistance. Further, it can operate at high speed and has high reliability.
[0144]
Example 3
This embodiment shows a manufacturing process of the thin film transistor shown in FIG. FIG. 11 illustrates a manufacturing process of the thin film transistor illustrated in FIG. 11, the same reference numerals as those in FIG. 1 denote the same portions as those in FIG. FIG. 11 shows a manufacturing process of a cross-sectional portion cut along AA ′ in FIG.
[0145]
First, a silicon oxide film is formed as a base film on a glass substrate 1101 to a thickness of 3000 mm using a sputtering method. Then, an active layer 100 made of a crystalline silicon film is formed. Here, the thickness of the active layer is 1000 mm. In this way, the state shown in FIG.
[0146]
Next, a silicon oxide film 1104 functioning as a gate insulating film is formed by a plasma CVD method. The thickness of the silicon oxide film 1104 is 1000 mm.
[0147]
Next, a resist mask 1103 is provided. The resist mask 1103 has a hatched pattern indicated by 105 in FIG. In this way, the state shown in FIG.
[0148]
Next, P ions are implanted. In this step, the regions indicated by 101, 104, 106, 107, and 103 become N-type. Here, 101 is a source region, 103 is a drain region, and 104, 106, and 107 are N-type regions. In this way, the state shown in FIG.
[0149]
Next, the gate electrode 108 is formed. The gate electrode is made of aluminum. Although not shown, an anodized film is formed on the surface of the gate electrode 108 made of aluminum. Thus, the state shown in FIG.
[0150]
The gate electrode can also be configured using various metal materials and silicide materials in addition to aluminum.
[0151]
Next, a silicon oxide film 1105 is formed as an interlayer insulating film to a thickness of 5000 mm by plasma CVD.
[0152]
Then, contact holes are formed, and a source electrode 1106 and a drain electrode 1107 are formed. Further, heat treatment is performed in a hydrogen atmosphere at 350 ° C. for 1 hour, whereby the thin film transistor illustrated in FIG. 11E is completed.
[0153]
Example 4
This embodiment will be described with reference to FIG. The thin film transistor shown in this embodiment is a bottom gate type in which the position of the gate electrode is on the substrate side. The main manufacturing steps of the semiconductor device of this example are as follows.
[0154]
(1) Formation of gate electrode / wiring, gate insulating film, semiconductor active layer (thin film semiconductor)
(2) Doping mask formation
(3) Doping and activation of doped impurities
(4) Interlayer insulation film formation
(5) Formation of contact holes to source and drain regions
(6) Formation of wiring using upper conductive material (metal, etc.)
[0155]
In this embodiment, as described in JP-A-5-275451 or 7-99317, in order to obtain a bottom gate type thin film transistor, a self-aligned doping mask is formed, and ion doping is performed on a thin film semiconductor. And activate. The detailed conditions of this embodiment, the thickness of the coating, etc. may be referred to the above publication.
[0156]
First, step (1) will be described with reference to FIG. First, the gate electrode 409 is formed on the glass substrate 400. Since a glass substrate uses a backside exposure technique, it is required to transmit light used for exposure.
[0157]
The gate electrode is formed using various metal materials or silicide materials. A silicon oxide film 419 functioning as a gate insulating film is formed over the gate electrode 409 by a plasma CVD method.
[0158]
Further, an amorphous silicon film (not shown) is formed on the gate insulating film 419 by a low pressure thermal CVD method. This amorphous silicon film is crystallized by laser annealing to form a crystalline silicon film. Further, by patterning this, an active layer 408 made of a crystalline silicon film is formed.
[0159]
Next, step (2) will be described. This process uses a backside exposure technique. That is, a silicon nitride film is deposited, a photoresist is applied thereon, and then light is irradiated from the back surface to expose the photoresist. Then, the silicon nitride film is etched thereby to obtain a doping mask 465. Although the doping masks 465 seem to be separated in the figure, they are all connected in the same manner as the gate electrode 409 because the back exposure technique is adopted. (Fig. 12 (B))
[0160]
Next, step (3) will be described. This step is performed using a known impurity doping method. Here, P (phosphorus) ions are implanted.
[0161]
As a result, the source region 401, the drain region 402, and the N-type regions 403 to 405 are formed in a self-aligned manner. (Fig. 12 (B))
[0162]
Furthermore, impurities introduced into the thin film semiconductor by doping are activated by lamp annealing.
[0163]
Next, step (4) will be described with reference to FIG. In this step, a silicon oxide film 456 that functions as an interlayer insulator is formed by a known insulating film forming technique. (Figure 12 (C))
[0164]
Next, step (5) will be described with reference to FIG. This step is performed using a known contact hole forming technique. The interlayer insulator 456 is etched to form contact holes 457 and 458 to the source region 401 and the drain region 402. (Fig. 12D)
[0165]
Next, step (6) will be described with reference to FIG. This step is performed using a known metal film forming technique and etching technique. As a result of this step, a source electrode / wiring 410 and a drain electrode / wiring 412 are formed. Further, heat treatment is performed in a hydrogen atmosphere at 350 ° C., whereby the thin film transistor illustrated in FIG. 12E is completed.
[0166]
Example 5
This embodiment relates to a configuration in which a thin film transistor with a reduced OFF current value is arranged in an active matrix region. This thin film transistor has a configuration in which a plurality of thin film transistors are equivalently connected in series.
[0167]
The thin film transistor shown here has the following structure.
That is, image signal lines (source lines) and gate signal lines arranged in a matrix,
A pixel electrode disposed in a region surrounded by the image signal line and the gate signal line;
Have
N thin film transistors of the same conductivity type are arranged adjacent to the pixel electrode and connected in series;
The source or drain region of the n = 1st thin film transistor of the plurality of thin film transistors is connected to the image signal line,
The drain or source region of the nth thin film transistor of the plurality of thin film transistors is connected to the pixel electrode,
The gate electrodes of nm (n> m) thin film transistors are connected to the gate signal line in common,
The m thin film transistors are characterized in that the gate potential is fixed to a potential at which the channel formation region has the same conductivity type as the source and drain regions.
[0168]
FIG. 13 shows an outline of the present embodiment. Here, a schematic configuration of a part of the active matrix region is shown as a representative example.
[0169]
The configuration shown in FIG. 13 has a configuration in which a capacitor line is shared in a thin film transistor group arranged in two pixels adjacent to each other in the gate signal line direction. Such a configuration is useful for increasing the aperture ratio.
[0170]
In FIG. 13, reference numeral 901 denotes an image signal line, and reference numerals 902 and 904 denote gate signal lines. Reference numerals 905 and 906 denote pixel electrodes, which are driven by signals from gate signal lines 902 and 904, respectively.
[0171]
Reference numerals 907 and 908 denote island-shaped semiconductor regions (active layers) formed of a crystalline silicon film. Each of these island-shaped semiconductor regions constitutes an active layer of the thin film transistor.
[0172]
FIG. 14 shows an equivalent circuit corresponding to the configuration of FIG. In the structure shown in this embodiment, the number of capacitor lines can be halved, so that the aperture ratio of the pixel can be increased.
[0173]
The thin film transistor shown in this embodiment has a configuration in which a plurality of thin film transistors are connected in series and a capacitor is disposed between the thin film transistors, as can be seen from the equivalent circuit of FIG.
[0174]
With such a configuration, the amount of charge leaking from the pixel electrode 905 to the image signal line 901 or the ratio thereof can be reduced. This is important in an active matrix circuit in which a configuration that reduces the charge leaking from the pixel electrode is required with the highest priority.
[0175]
However, on the other hand, since a structure in which a plurality of thin film transistors are connected in series is equivalent, the distance that the carrier moves is long, and the moving carrier must move through many junctions (not a few barriers exist). It becomes a structure. This is disadvantageous for increasing the operating speed and the ON current value.
[0176]
Therefore, the thin film transistors shown in FIGS. 13 and 14 are optimal for placement in an active matrix circuit, but are not suitable for placement in a peripheral driver circuit.
[0177]
When the active matrix circuit is constituted by the thin film transistors shown in this embodiment and the peripheral drive circuit is constituted by the CMOS circuit shown on the left side of FIG. 9 or the thin film transistor shown in FIG. 1, the thin film transistors arranged in the respective circuits are essential. Have different structures.
[0178]
In particular, the thin film transistor shown in FIG. 1 is substantially different in operating principle from the thin film transistor constituting the CMOS circuit on the left side of FIG. 9 and the thin film transistor shown in FIG.
[0179]
Such an arrangement results from the difference in the characteristics of the thin film transistors required for each part in the peripheral circuit integrated active matrix configuration. That is, there is a reason for disposing a thin film transistor having optimum characteristics in each part (for example, an active matrix circuit or a buffer circuit).
[0180]
Example 6
This embodiment relates to a process of forming a planar type thin film transistor and an inverted staggered type thin film transistor on a single glass substrate. When the configuration shown in this embodiment is adopted, the operation principle is the same, but the configuration is such that thin film transistors having substantially different structures are integrated. (Of course, the cross-sectional structure is also different)
[0181]
FIG. 15 shows a manufacturing process of this example. First, a silicon oxide film is formed on the glass substrate 601 as a base film as shown. Next, an amorphous silicon film is formed and crystallized by heating to obtain a crystalline silicon film (not shown).
[0182]
This crystalline silicon film (not shown) is patterned to form an active layer of a planar type thin film transistor denoted by reference numerals 602, 603, and 604.
[0183]
Next, a silicon oxide film 600 functioning as a gate insulating film of the right planar type thin film transistor is formed.
[0184]
Further, an aluminum film for forming the gate electrode is formed by sputtering. Then, porous anodic oxide films 606 and 609 are formed, and anodic oxide films 607 and 610 having a dense film quality are formed.
[0185]
In this step, gate electrodes 605 and 608 are defined. Then, impurity ions are implanted for the first time to form a source region 602 and a drain region 604. In this step, impurity ions are not implanted into the region 603. (Fig. 15 (A))
[0186]
Next, the porous anodic oxide film 609 is removed, and a second impurity ion implantation is performed. This step is performed with a dose amount lower than the first impurity ion implantation. Thus, low concentration impurity regions 61 and 62 are formed. (Fig. 15 (A))
[0187]
Next, a silicon oxide film 611 that forms a gate insulating film of the left inverted staggered thin film transistor is formed. In this way, the state shown in FIG.
[0188]
Next, an amorphous silicon film (not shown) for forming the active layer of the left inverted stagger type thin film transistor is formed. The amorphous silicon film is transformed into a crystalline silicon film by irradiating laser light. Further, the active layer 612 is formed by patterning. In this way, the state shown in FIG.
[0189]
Next, resist masks 613 and 614 are arranged, and impurity ions are implanted. Then, a source region 615 and a drain region 617 are formed. At this time, impurity ions are not implanted into the region 616. (Fig. 15D)
[0190]
Next, isotropic etching is performed, the resist mask 613 is moved back, and impurity ions are implanted again with a dose lower than that shown in FIG. Thus, low concentration impurity regions 618 and 619 are formed.
[0191]
Next, an interlayer insulating film 620 is formed. Furthermore, contact holes are formed. A source electrode 621 and a drain electrode 622 of a thin film transistor having an inverted stagger type, and a source electrode 623 and a drain electrode 624 of a planar type thin film transistor are formed.
[0192]
In this way, two thin film transistors having essentially different structures (the same principle of operation is the same) are formed on the same substrate.
[0193]
In the above description, the case of a liquid crystal display device has been focused as an application example of the invention. However, the invention disclosed in this specification can be used for other display devices having an active matrix type. For example, it can be used for an EL display device having an active matrix type.
[0194]
【The invention's effect】
By employing the invention disclosed in this specification, problems due to insufficient breakdown voltage of a thin film transistor can be solved. In addition, an active matrix display device having a peripheral drive circuit integrated configuration having stable and excellent performance can be obtained.
[Brief description of the drawings]
FIG. 1 illustrates a structure of a thin film transistor.
FIG. 2 is a diagram showing a configuration in which a peripheral drive circuit and an active matrix circuit are integrated.
FIG. 3 is a diagram showing a configuration of a circuit.
FIG. 4 is an energy band diagram showing an operation state of a thin film transistor.
FIGS. 5A and 5B illustrate a manufacturing process of a thin film transistor. FIGS.
6A and 6B illustrate a manufacturing process of a thin film transistor.
FIGS. 7A to 7C illustrate a manufacturing process of a thin film transistor. FIGS.
FIG. 8 illustrates a manufacturing process of a thin film transistor.
FIG. 9 illustrates a manufacturing process of a thin film transistor.
FIG. 10 illustrates a structure of a thin film transistor.
FIG. 11 illustrates a manufacturing process of a thin film transistor.
12A to 12C illustrate a manufacturing process of a thin film transistor.
FIG. 13 shows part of an active matrix circuit.
14 is a diagram showing an equivalent circuit of FIG. 13;
FIG. 15 illustrates a manufacturing process of a thin film transistor.
[Explanation of symbols]
100 active layer
101 Source area
102 Channel formation region
103 Drain region
104 N-type region
105 channels
106 N-type region
107 N-type region
108 Gate electrode
109 Carrier movement path during OFF operation
110 LDD (lightly doped drain) region
111 Carrier movement path during ON operation

Claims (4)

A display device in which an active matrix circuit and a peripheral drive circuit are formed on the same substrate,
Only in the thin film transistor disposed in the buffer circuit of the peripheral driver circuit, the source and drain regions in the channel formation region are short so that the carrier movement path during the ON operation is shorter than the carrier movement path during the OFF operation. A display device comprising a region having the same conductivity type. A display device in which an active matrix circuit and a peripheral drive circuit are formed on the same substrate ,
Only in the thin film transistor disposed in the buffer circuit of the peripheral drive circuit, the carrier movement path during the ON operation is shorter than the carrier movement path during the OFF operation, and the width of the carrier movement path during the ON operation A display device is characterized in that a region having the same conductivity type as the source and drain regions is arranged in the channel formation region so as to be wider than the width of the carrier movement path during the OFF operation. 3. The display device according to claim 1, wherein the thin film transistor disposed in the active matrix circuit has an LDD region or an offset gate region. 3. The display device according to claim 1, wherein the thin film transistor disposed in the active matrix circuit has a structure in which a plurality of thin film transistors are equivalently connected in series.

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