JP3931615B2 - Boosted voltage generating circuit, boosted voltage generating method of semiconductor memory device, and semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a boosted voltage generating circuit, a boosted voltage generating method of a semiconductor memory device, and a boosted voltage generating method for generating a boosted voltage having a predetermined time width when data is written in a memory cell or when data written in a memory cell is erased. The present invention relates to a semiconductor memory device using a circuit.
[0002]
[Problems to be solved by the invention]
For example, when writing or erasing data in the EEPROM, in order to extract electrons or inject electrons from the floating gate of the selected memory transistor, the memory transistor is not subjected to a certain time (writing time). It is necessary to apply a high voltage. This high voltage is applied not only to the transistors constituting the memory cell but also to the transistors constituting the peripheral circuits such as the level shift circuit and the switch circuit, etc., and damages to these transistors (for example, reduction of the dielectric strength of the oxide film) give. For this reason, it is preferable to minimize the application time of the high voltage to these circuits. Therefore, a booster circuit, for example, a charge pump circuit, built in the EEPROM generates and outputs a boosted voltage corresponding to a high voltage for the write time during data writing and erasing.
[0003]
The EEPROM includes an oscillation circuit that outputs a clock signal, for example, a CR oscillation circuit suitable for integration into an IC. The charge pump circuit starts a boost operation using the clock signal in response to a data write command or a data erase command, and ends the boost operation when the counter counts the clock signal by a fixed number of boost clocks. ing. That is, the output time during which the charge pump circuit generates and outputs the boosted voltage is determined by the frequency of the CR oscillation circuit (clock frequency) and the number of boosted clocks.
[0004]
However, the CR oscillation circuit has a large variation in clock frequency due to variations in temperature and power supply voltage. In particular, when the CR oscillation circuit is used in a vehicle having a wide temperature variation range such as an in-vehicle electronic device, the clock frequency may vary by ± 30%. As a result, the output time of the boosted voltage also varies at the same rate as the clock frequency. FIG. 7 shows the voltage waveform of the boosted voltage output from the charge pump circuit. The output time of the boosted voltage becomes shorter when the clock frequency is high, and becomes longer when the clock frequency is low.
[0005]
Therefore, in the conventional boosted voltage generation circuit, the necessary write time is secured for the highest clock frequency that is expected to fluctuate so that the output time of the boosted voltage is not short even if the temperature and the power supply voltage change. The number of boosting clocks was determined. As a result, as the clock frequency is lowered, the output time of the boosted voltage is longer than necessary, and the damage to the transistor is increased. Therefore, it is difficult to increase the number of times of data rewriting of the EEPROM.
[0006]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a boosted voltage generating circuit and a boosted voltage generating circuit of a semiconductor memory device capable of reducing damage to the element against the boosted voltage, and a semiconductor using the boosted voltage generating circuit. To provide a storage device.
[0007]
[Means for Solving the Problems]
According to the means described in claims 1 and 6, when writing data into the memory cell or erasing data written into the memory cell, the booster circuit performs a boosting operation using the clock signal output from the oscillation circuit. Start. In this case, the oscillation frequency of the oscillation circuit, that is, the clock frequency may vary depending on temperature, power supply voltage, and the like. In general, the rising characteristic of the boosted voltage when the booster circuit starts boosting varies depending on the clock frequency. When the clock frequency is different, the number of clock signals required for boosting by a predetermined voltage is different. This is because the boosting efficiency of the booster circuit changes depending on the clock frequency.
[0008]
Therefore, the boost control circuit measures the number of clock signals required for the boost voltage output from the boost circuit to reach the second reference voltage from the first reference voltage. In addition, when the booster circuit performs a boosting operation using a reference clock signal having a reference frequency, the number of standard clocks required for the boosted voltage to reach the second reference voltage from the first reference voltage is clarified in advance. ing.
[0009]
  The boost control circuit can grasp the deviation of the clock frequency from the reference frequency based on the measured clock number and standard clock number.The If the measured clock count is equal to the standard clock countCorresponds to the predetermined time required to write or erase dataWhen the number of clocks of the reference clock signal is the number of boosted clocks of the clock signal and the measured number of clocks is less than the standard number of clocks, the number of clocks according to the difference between the number of measurement clocks and the number of standard clocks If the number of boost clocks is equal to the number of boost clocks when the number of clocks is equal to the number of boost clocks, and the number of measurement clocks is greater than the number of standard clocks, the clock according to the difference between the number of measurement clocks and the standard clock number The value obtained by subtracting the number from the boost clock number when the measurement clock number is equal to the standard clock number is defined as the boost clock number.Then, the switching circuit provided between the oscillation circuit and the booster circuit is controlled to be opened and closed so that the clock signal is supplied from the oscillation circuit to the booster circuit by the number of boosted clocks.
[0010]
As a result, the booster circuit can output the boosted voltage only for a predetermined time required for writing or erasing data regardless of the variation of the clock frequency. As a result, at the time of writing or erasing data, damage due to application of the boost voltage to each element constituting the semiconductor memory device can be minimized, and the number of times data can be rewritten can be increased.
[0011]
According to the means described in claim 2, when the boosted voltage reaches the first and second reference voltages, the voltage level detection circuit outputs first and second arrival signals, respectively. The counting circuit starts counting the number of clocks of the clock signal by the first arrival signal and ends the counting by the second arrival signal. The clock number determination circuit determines the boost clock number according to the difference between the counted clock number and the standard clock number, and the gate control circuit counts the clock signal by the boost clock number when writing or erasing data. The open / close circuit is controlled to be in the open state only during the counting period.
[0012]
According to the means described in claim 3, substantially the same operation and effect as the means described in claim 2 can be obtained. However, since the first reference voltage is set to a steady output voltage when the booster circuit stops the boost operation, that is, a voltage at the start of boosting (for example, 0 V), the first reference voltage is reached by the voltage level detection circuit. The signal output becomes unnecessary, and the counting circuit counts the number of clock signals from the start of the boosting operation until the arrival signal is output. Thereby, the configuration of the voltage level detection circuit can be simplified as compared with the means described in claim 2.
[0013]
According to the means described in claim 4, since the booster circuit is a charge pump circuit, it is easy to make an IC. In addition, a desired high voltage can be generated with a relatively simple circuit configuration simply by increasing the number of constituent stages.
[0014]
According to the means described in claim 5, since the oscillating circuit is a CR oscillating circuit, it is possible to reduce the circuit area when the IC is formed. Although the oscillation frequency of the CR oscillation circuit is likely to fluctuate due to changes in temperature and power supply voltage, according to the present invention, it is possible to output a boosted voltage for a predetermined time required for data writing or erasing.
[0015]
According to the means described in claim 7, the boosted voltage generated by the boosted voltage generating circuit is applied to the word line driving circuit, the bit line driving circuit and the selected memory cell only when data is written or erased. The The application time of the boosted voltage is controlled to be equal to a predetermined time required for writing or erasing regardless of changes in temperature and power supply voltage, so that the word line driving circuit, bit line driving circuit and memory cell are applied. Damage can be minimized and the number of times data can be rewritten can be increased.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment in which a boosted voltage generation circuit of the present invention is applied to an EEPROM which is an electrically rewritable nonvolatile semiconductor memory device will be described with reference to FIGS.
First, a schematic electrical configuration of the EEPROM will be described with reference to FIGS. In FIG. 4 showing the entire configuration of the EEPROM 1, the memory cell array 2 has a configuration in which a plurality of memory cells 3 are arranged in a matrix. Each memory cell 3 includes a memory transistor Q1 having a floating gate and a selection transistor Q2. The gates of the select transistors Q2 arranged in the row direction are connected to the common word line WL0 (or WL1,...), And the drains of the select transistors Q2 arranged in the column direction are connected to the common bit line BL0 (or BL1,. …)It is connected to the.
[0017]
The gates (control gates) of the memory transistors Q1 arranged in the row direction are connected to the sources of the transistors Q3 provided in common for each row, and the gates of the transistors Q3 are connected to the word lines WL0 (or WL1,...). It is connected to the. The sources of the memory transistors Q1 are connected in common, and the common source is connected to the ground line 4 via the transistor Q5.
[0018]
The sense amplifier 5 includes current sense amplifiers (not shown) equal in number to the number of bit lines, and outputs data corresponding to the number of bits when reading data. Transistors Q4, Q4,... Constituting the column selector 6 are connected to bit lines BL0, BL1,... Between the sense amplifier 5 and the memory cell array 2, respectively.
[0019]
At the time of data writing, erasing, and reading, the row decoder 7 (corresponding to a row decoder) and the column decoder 8 (corresponding to a column decoder) are respectively given a row address and a column address from an address buffer (not shown). It has become. The row decoder 7 outputs row decode signals RD0, RD1,..., And the word line drive circuit 9 applies a voltage corresponding to the row decode signal RD0 (or RD1,...) To the word line WL0 (or WL1,...). It is designed to output.
[0020]
The column decoder 8 outputs column decode signals CD0, CD1,..., And the bit line drive circuit 10 supplies the column decode signal CD0 (or CD1,...) To the bit line BL0 (or BL1,...) And the gate of the transistor Q4. The voltage according to is output. The column decoder 8 outputs a control gate drive signal CG, and the control gate drive circuit 11 outputs a voltage corresponding to the control gate drive signal CG to the drain of the transistor Q3. Yes.
[0021]
The EEPROM 1 requires a high voltage (write voltage) when writing data to the memory cell 3 and erasing the written data. FIG. 5 shows an electrical configuration of the level shift circuit 12 for outputting this high voltage in the word line driving circuit 9.
[0022]
  In FIG. 5, a boosted voltage Vpp, which is a write voltage, is supplied to the power supply line 13 from a boosted voltage generation circuit 14 (see FIG. 1) described later at the time of data writing and data erasing. Transistors Q6 and Q7 and transistors Q8 and Q9 are connected in series between power supply line 13 and ground line 4, respectively, and the gates of transistors Q6 and Q8 are connected to the drains of transistors Q9 and Q7, respectively. Yes. A row decode signal RD0 (or RD1,...) Is applied to the gate of the transistor Q7, and an inverter is applied to the gate of the transistor Q9.15Thus, a signal obtained by inverting the row decode signal RD0 (or RD1,...) Is supplied.
[0023]
This level shift circuit 12 outputs the boosted voltage Vpp when the row decode signal RD0 (RD1,...) Is at the H level while the boosted voltage Vpp is supplied to the power supply line 13, and the row decode signal RD0 (RD1,. ) Outputs 0V when L level. The bit line driving circuit 10 and the control gate driving circuit 11 have the same configuration.
[0024]
Next, a boosted voltage generation circuit that generates the boosted voltage Vpp will be described with reference to FIGS.
FIG. 1 is a block diagram showing the overall electrical configuration of the boost voltage generation circuit. The boost voltage generation circuit 14 includes a CR oscillation circuit 16 (corresponding to an oscillation circuit), a charge pump circuit 17 (corresponding to a boost circuit) that generates a boost voltage Vpp using a clock signal SCK output from the CR oscillation circuit 16, and a CR A gate circuit 18 (corresponding to an open / close circuit) provided between the oscillation circuit 16 and the charge pump circuit 17 and a boost control circuit 19 for controlling the output time of the boost voltage Vpp by controlling the gate circuit 18 to open / close. ing.
[0025]
The CR oscillation circuit 16 has the electrical configuration shown in FIG. 2, and can be made relatively small in circuit area when integrated into an IC. Resistors R1, R2, and R3 for generating a reference voltage are connected in series between a power supply line 20 that supplies a voltage Vdd (for example, 5 V) and a ground line 4, and voltage dividing points 21 and 22 are respectively It is connected to the non-inverting input terminal of the comparator 25 via the analog switches 23 and 24. The output terminal of the comparator 25 is connected to the output terminal 29 of the CR oscillation circuit via a Schmitt trigger inverter 26 and inverters 27 and 28. The output terminal of the inverter 27 is an inverting input of the comparator 25 via a resistor R4. Connected to the terminal. A capacitor C 1 is connected between the inverting input terminal and the ground line 4. The analog switches 23 and 24 are controlled to be turned on and off, respectively, while the clock signal SCK output from the output terminal 29 is at L level, and are controlled to be turned off and on, respectively, while the clock signal SCK is at H level. ing.
[0026]
The clock signal SCK is supplied to the charge pump circuit 17 through a gate circuit 18 composed of a 3-input AND gate. The charge pump circuit 17 has the electrical configuration shown in FIG. That is, a large number of transistors Q101, Q102,..., Q10m necessary for generating the boosted voltage Vpp are connected in cascade between the power supply line 20 and the output terminal 30. Each transistor Q101, Q102,..., Q10m has a drain and a gate connected to each other, and operates as a one-way energization element like a diode. The signal line 32 is supplied with the clock signal SCK from the input terminal 31, and the signal line 33 is supplied with a signal obtained by inverting the clock signal SCK by the inverter 34.
[0027]
Are connected between the sources of the transistors Q101, Q103,... And the signal line 32, and capacitors C102, C104 are connected between the sources of the transistors Q102, Q104,. , ... are connected. The capacitor C10m connected between the output terminal 30 and the ground line 4 is for smoothing.
[0028]
1 includes a voltage detection circuit 35 (corresponding to a voltage level detection circuit), a counter 36 (corresponding to a counting circuit), a counter 37 (corresponding to an open / close control circuit), a register 38, and the number of clocks. The circuit 39 is configured. Of these, the voltage detection circuit 35 compares the divided voltage Vq and the reference voltage Vr with the resistors R5 and R6 for voltage division connected in series between the output terminal 40 of the boosted voltage generation circuit 14 and the ground line 4. Comparator 41 is included. A detection signal Sa (corresponding to an arrival signal) output from the comparator 41 is given to the gate circuit 18 and the counter 36. The voltage detection circuit 35 performs constant voltage control of the boost voltage Vpp to the target voltage Va, and detects that the boost voltage Vpp has reached the reference voltage (equal to the target voltage Va in this embodiment) at the start of the boost operation. It is provided for.
[0029]
The counter 36 starts counting the clock signal SCK in synchronization with the address decode signal Sb at the time of data writing or data erasing (the row decode signals RD0, RD1,... And the column decode signals CD0, CD1,. The count is stopped when the detection signal Sa changes from the H level to the L level. The register 38 stores a standard value of the number of clocks counted by the counter 36 when the frequency of the clock signal SCK is equal to the reference frequency, that is, the standard clock number Nb.
[0030]
The clock number determination circuit 39 includes a subtraction circuit 42 and a clock number setting circuit 43. The subtracting circuit 42 subtracts the standard clock number Nb stored in the register 38 from the clock number Na counted by the counter 36 to obtain the differential clock number Nc. The clock number setting circuit 43 determines the clock number Nd of the clock signal SCK corresponding to the data writing time or data erasing time (hereinafter referred to as writing time Tw) based on the differential clock number Nc, and the clock number Nd is addressed. The counter 37 is set in synchronization with the decode signal Sb.
[0031]
The counter 37 outputs a boost permission signal Sc to the gate circuit 18. When the clock number Nd is set, the counter 37 sets the boost permission signal Sc to the H level, starts counting the clock signal SCK, and returns the boost permission signal Sc to the L level when the clock number Nd has been counted. It has become.
[0032]
Next, the operation of this embodiment will be described with reference to FIG.
In the EEPROM 1, electrons are extracted from the floating gate of the memory transistor Q1 when writing data, and electrons are injected into the floating gate when erasing data, so that a boosted voltage Vpp (for example, 15 V) is required.
[0033]
For example, when data is written to the memory cell 3 selected by the word line WL0 and the bit line BL0, the word line driving circuit 9 and the bit line driving circuit 10 boost the voltage to the word line WL0 and the bit line BL0, respectively, during the writing time Tw. The voltage Vpp is output. At this time, the control gate drive circuit 11 outputs 0 V to the transistor Q3, and the transistors Q4 and Q5 are turned off.
[0034]
When erasing the written data, the word line driving circuit 9 outputs the boosted voltage Vpp to the word line WL0 and the bit line driving circuit 10 outputs 0 V to the bit line BL0 during the writing time Tw. At this time, the control gate drive circuit 11 outputs the boosted voltage Vpp to the transistor Q3, the transistor Q4 is turned off, and the transistor Q5 is turned on.
[0035]
Thus, since the boosted voltage Vpp is applied to the memory cell 3, the word line driving circuit 9, the bit line driving circuit 10, the control gate driving circuit 11, etc., the transistors Q1 to Q9 constituting them have a high breakdown voltage. Is used. In order to reduce damage to the transistors Q1 to Q9 (decrease in dielectric strength of the oxide film, etc.), the boosted voltage generation circuit 14 of this embodiment outputs the boosted voltage Vpp only during the writing time Tw. Hereinafter, the operation of the boost voltage generation circuit 14 will be described.
[0036]
The CR oscillation circuit 16 continues to oscillate while the power supply voltage Vdd is applied, and outputs a clock signal SCK. In the oscillation operation, the analog switches 23 and 24 select a reference voltage according to the level (H or L) of the clock signal SCK, and the comparator 25 compares the voltage of the capacitor C1 charged and discharged by the resistor R4 with the reference voltage. This is done by inverting the level of the clock signal SCK. The oscillation frequency (clock frequency) is determined by the resistance value of the resistor R4, the capacitance value of the capacitor C1, and the reference voltage value generated by the resistors R1 to R3. However, the oscillation frequency (clock frequency) has a characteristic that easily varies depending on the temperature and the power supply voltage Vdd.
[0037]
When the EEPROM 1 is not writing or erasing data, the counter 37 outputs the L level boost permission signal Sc, and the charge pump circuit 17 stops the boost operation. On the other hand, when a write command or an erase command is input to the EEPROM 1 and an address decode signal Sb is output from the row decoder 7 and the column decoder 8, the clock number setting circuit 43 is set at the time of previous writing (or erasing). The number of clocks Nd thus set is set in the counter 37. Thereby, the counter 37 sets the boost permission signal Sc to the H level and starts counting the clock signal SCK, and the charge pump circuit 17 starts the boost operation.
[0038]
In this boosting operation, when the boosted voltage Vpp becomes higher than the target voltage Va (= Vr × (R5 + R6) / R6), the detection signal Sa becomes L level, and the clock signal SCK is supplied from the CR oscillation circuit 16 to the charge pump circuit 17. Temporarily stops. As a result, the boosted voltage Vpp is controlled to be equal to the predetermined target voltage Va. Eventually, when the counter 37 finishes counting the number of clocks Nd, the boost permission signal Sc is returned to the L level, and the charge pump circuit 17 stops the boost operation. The boost control circuit 19 always controls the boost operation time to be equal to the write time Tw by determining the clock number Nd according to the clock frequency.
[0039]
FIG. 6A is a waveform diagram of the boosted voltage Vpp output from the charge pump circuit 17, and FIG. 6B is an enlarged view of the rising portion of the boosted voltage Vpp with respect to the time axis. As shown in FIG. 6B, the rising waveform of the boosted voltage Vpp varies depending on the clock frequency. That is, when the clock frequency is high, the rise time is short, and the number of clocks required for the boosted voltage Vpp to reach the target voltage Va from 0V is reduced. Conversely, when the clock frequency is low, the rise time is long, and the number of clocks required for the boosted voltage Vpp to reach the target voltage Va from 0V increases.
[0040]
As described above, the difference in the rise time and the number of clocks depending on the clock frequency is due to the leakage current of the transistors Q101, Q102,..., Q10m and the capacitors C101, C102,. This is because the boosting efficiency of the charge pump circuit 17 increases as the clock frequency increases due to the output current from 30 and the like.
[0041]
  The counter 36 starts counting the clock signal SCK when the charge pump circuit 17 starts the boosting operation, and stops counting when the boosted voltage Vpp reaches the target voltage Va and the detection signal Sa changes from H level to L level. To do. In the present embodiment, the first and second reference voltages are 0 V and the target voltage Va, respectively. The register 38 stores the standard clock number Nb in the case of the reference frequency shown in FIG. 6B, and the difference clock number Nc between the clock number Na counted by the counter 36 and the standard clock number Nb is a clock. It becomes a value corresponding to the difference frequency between the frequency and the reference frequency. Therefore, the clock number setting circuit 43 has the following:(1) , (2) , (3)The number of clocks Nd set in the counter 37 is determined according to the above.
[0042]
  (1)Number of clocks Na = standard number of clocks Nb
  Since the clock frequency is equal to the reference frequency,Clock signal S corresponding to write time Tw CK Number of clocks (reference frequency) NdAnd
  (2)When the number of clocks Na <standard number of clocks Nb
  Because the clock frequency is higher than the reference frequency,Number of clocks Nd at the reference frequencyA value obtained by adding the clock number corresponding to the difference clock number Nc to the clock number Nd.
  (3)When the number of clocks Na> the number of standard clocks Nb
  Because the clock frequency is lower than the reference frequency,Number of clocks Nd at the reference frequencyA value obtained by subtracting the number of clocks corresponding to the difference clock number Nc from is set as the clock number Nd.
[0043]
As a result, the clock number Nd increases when the clock frequency is high, the clock number Nd decreases when the clock frequency is low, and the time for the counter 37 to count the clock signal SCK by the clock number Nd is equal to the clock frequency. Regardless, it is always equal to the write time Tw. The number of clocks Nd set here is used for the boosting operation at the next writing (or erasing), but may be used for the current boosting operation.
[0044]
As described above, the boosted voltage generation circuit 14 provided in the EEPROM 1 of the present embodiment has the address decode signal Sb at the time of writing and erasing data regardless of the fluctuation of the oscillation frequency (clock frequency) of the CR oscillation circuit 16. The boosted voltage Vpp having a time width equal to the write time Tw can be output in synchronization with. That is, the memory cell 3, the word line driving circuit 9, the bit line driving circuit 10, and the control gate driving circuit 11 only have a certain writing time Tw required for the writing operation or the erasing operation only at the time of data writing or erasing. Boosted voltage Vpp is applied. Thereby, damage due to the application of the boosted voltage Vpp to the transistors Q1 to Q9 constituting the EEPROM 1 can be minimized, and the number of times data can be rewritten for the EEPROM 1 can be increased.
[0045]
This boost control uses the boost characteristic of the charge pump circuit 17 that the number of clocks required for the rise of the boost voltage Vpp differs depending on the clock frequency, so that it is not necessary to have a separate high-accuracy oscillation circuit. It is easy to apply.
[0046]
The boost control circuit 19 determines the number of clocks Nd to be set in the counter 37 that controls opening / closing of the gate circuit 18 based on the number of clocks required for rising of the boost voltage Vpp. In detecting the number of clocks required for the rise, the first reference voltage in the present invention is set to 0 V, which is a steady voltage when the charge pump circuit 17 stops boosting. Therefore, a circuit configuration for detecting the 0 V is used. Is no longer necessary. In addition, since the second reference voltage in the present invention is the target voltage Va, the detection signal Sa from the voltage detection circuit 35 provided for constant voltage control of the boosted voltage Vpp can be used as it is. There is no need to provide a circuit.
[0047]
The present invention is not limited to the embodiment described above and shown in the drawings. For example, the present invention can be modified or expanded as follows.
The boosted voltage generation circuit 14 can be similarly applied to a semiconductor memory device such as a flash memory or an EPROM.
The first and second reference voltages referred to in the present invention are not limited to 0 V and the target voltage Va, but may be two reference voltages having different voltage values. In this case, it is desirable to increase the voltage difference between the first reference voltage and the second reference voltage in order to accurately detect the difference in the boosting characteristics of the charge pump circuit 17 depending on the clock frequency.
The counter 37 counts the period from the start of the boost operation of the charge pump circuit 17 to the stop of the boost operation, but counts the period until the charge pump circuit 17 stops the boost operation after the boost voltage Vpp reaches the target voltage Va. You may do it. The oscillation circuit for the clock signal SCK is not limited to the CR oscillation circuit 16. The booster circuit is not limited to the charge pump circuit 17 and may be another switching power supply circuit.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall electrical configuration of a boost voltage generation circuit according to an embodiment of the present invention.
FIG. 2 is an electrical configuration diagram of a CR oscillation circuit.
FIG. 3 is an electrical configuration diagram of a charge pump circuit.
FIG. 4 is an overall electrical configuration diagram of an EEPROM;
FIG. 5 is an electrical configuration diagram of a level shift circuit.
FIG. 6 is a waveform diagram of a boosted voltage output from a charge pump circuit.
7 is a view corresponding to FIG. 6 showing the prior art.
[Explanation of symbols]
1 is an EEPROM (semiconductor memory device), 2 is a memory cell array, 3 is a memory cell, 7 is a row decoder (row decoder), 8 is a column decoder (column decoder), 14 is a boosted voltage generation circuit, and 16 is a CR oscillation circuit ( (Oscillation circuit), 17 is a charge pump circuit (boost circuit), 18 is a gate circuit (opening / closing circuit), 19 is a boost control circuit, 35 is a voltage detection circuit (voltage level detection circuit), 36 is a counter (counting circuit), 37 Is a counter (opening / closing control circuit), and 39 is a clock number determining circuit.

Claims (7)

In a boosted voltage generation circuit of a semiconductor memory device that generates a boosted voltage having a predetermined time width necessary for writing or erasing when data is written in a memory cell or when data written in a memory cell is erased,
An oscillation circuit that outputs a clock signal;
A booster circuit that generates a boosted voltage using a clock signal output from the oscillation circuit;
A switching circuit provided in a transmission path of a clock signal from the oscillation circuit to the booster circuit;
After the booster circuit starts the boosting operation, the number of clocks of the clock signal required for the boosted voltage to reach the second reference voltage from the first reference voltage is measured, and the measured clock number is the reference frequency. If the boost voltage when the boosting using the reference clock signal is equal to the standard number of clocks required from the first reference voltage reach the second reference voltage with the said reference corresponding to the predetermined time When the number of clocks of the clock signal is the number of boosted clocks of the clock signal and the measured number of clocks is smaller than the standard number of clocks, the number of clocks according to the difference between the number of measured clocks and the standard number of clocks is set. The value added to the boost clock number when the measurement clock number is equal to the standard clock number is defined as the boost clock number, and the measurement clock number is the standard clock number. If the number of locks is greater than the number of locks, a value obtained by subtracting the number of clocks corresponding to the difference between the number of measurement clocks and the number of standard clocks from the number of boosting clocks when the number of measurement clocks and the number of standard clocks is equal is obtained. And a step-up control circuit that controls opening / closing of the open / close circuit so that the clock signal passes through the open / close circuit by the number of step-up clocks when writing or erasing data. Boost voltage generation circuit. The boost control circuit includes:
A voltage level detection circuit that outputs a first arrival signal and a second arrival signal when the boosted voltage reaches the first reference voltage and the second reference voltage, respectively, and the voltage level detection circuit A counting circuit that counts the number of clocks of the clock signal between when the first arrival signal is output and when the second arrival signal is output;
A clock number determination circuit for determining the boost clock number according to the difference between the clock number counted by the counting circuit and the standard clock number;
2. The open / close control circuit that counts the clock signal by the number of boosted clocks at the time of writing or erasing the data and controls the open / close circuit to an open state during the counting period. Boosted voltage generation circuit of the semiconductor memory device. The first reference voltage is set to a steady output voltage when the booster circuit stops the boosting operation,
The boost control circuit includes:
A voltage level detection circuit that outputs a reaching signal when the boosted voltage reaches the second reference voltage;
A counting circuit that counts the number of clocks of the clock signal from when the booster circuit starts boosting operation until the arrival signal is output;
A clock number determination circuit for determining the boost clock number according to the difference between the clock number counted by the counting circuit and the standard clock number;
2. The open / close control circuit that counts the clock signal by the number of boosted clocks at the time of writing or erasing the data and controls the open / close circuit to an open state during the counting period. Boosted voltage generation circuit of the semiconductor memory device. 4. The boost voltage generation circuit for a semiconductor memory device according to claim 1, wherein the boost circuit is a charge pump circuit. 5. The boosted voltage generation circuit for a semiconductor memory device according to claim 1, wherein the oscillation circuit is a CR oscillation circuit. When data is written to the memory cell or when data written to the memory cell is erased, the boosted voltage starts to generate the boosted voltage using the clock signal output from the oscillation circuit, and the boosted voltage is set to the first reference. Measuring the number of clocks of the clock signal required to reach the second reference voltage from the voltage;
Clock count The measured is, when the boost voltage when the boosting using the reference clock signal having a reference frequency is equal to the number of standard clocks required to reach the second reference voltage from the first reference voltage When the number of clocks of the reference clock signal corresponding to the generation time of the boosted voltage necessary for writing or erasing the data is the boosted clock number of the clock signal, and the measured clock number is less than the standard clock number Is obtained by adding a clock number corresponding to a difference between the measurement clock number and the standard clock number to a boost clock number when the measurement clock number and the standard clock number are equal to each other. Is greater than the standard clock number, the clock according to the difference between the measurement clock number and the standard clock number Wherein a value obtained by subtracting from the step-up clock speed of when the measured number of clocks and the standard number of clocks equal to the number of boosting clock,
A method of generating a boosted voltage of a semiconductor memory device, wherein the clock signal is controlled to be supplied from the oscillation circuit to the booster circuit by the number of boosted clocks when the data is written or erased. A boosted voltage generation circuit according to any one of claims 1 to 5,
A memory cell array in which a plurality of memory cells are arranged in a matrix;
A row decoder that outputs a row decode signal in response to a row address signal;
A column decoder that outputs a column decode signal in response to a column address signal;
A word line driving circuit for outputting a boosted voltage generated by the boosted voltage generating circuit at the time of writing or erasing data to a word line corresponding to the row decode signal;
A semiconductor memory device comprising: a bit line driving circuit that outputs a boosted voltage generated by the boosted voltage generating circuit to a bit line corresponding to the column decode signal when data is written or erased.

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