JP3931569B2 - Modulator / demodulator and demodulation method thereof - Google Patents

Description

【００１６】
次に、得られた複素ベクトルを低域通過フィルタ（ＬＰＦ）２２で帯域制限することで、上式の第２項を消去し、次式（２）のような差分周波数のみの複素ベクトルＡを抽出することができる。
￣Ａ＝（ｘ，ｙ）＝Ｇ／２×ｃｏｓ(２πａｔ)，Ｇ／２×ｓｉｎ(２πａｔ)・・・・・・・・・・・・・（２）
Ａ／Ｄ変換器１２でサンプリングされたデータが入力される度に、この複素ベクトルＡが抽出され、”角度成分の算出処理部２３”に入力される。
【００１７】
次に”角度成分の算出処理部２３”で、１サンプル前の差分周波数複素ベクトルＡとの角度成分が算出される。
ここで、２つの複素ベクトルのなす角度はsinθで近似でき、以下のような算出式（３）で求められる。式（３）において、分母は絶対値、分子は外積をそれぞれ示している。
【数１】

【００１８】
次に、同期化処理部２４で符号抽出タイミングを生成し、符号抽出タイミングと角度成分の符号ビットからビット判定部２５で１，０のビットを決定し、ビットストリームとして出力する。
以上のような方法で、ＦＳＫ信号の復調処理が行われるが、上式（３）に示したように内部演算処理にルート演算と除算が必要となり、簡素なハードウェア構成では実現できない。
【００１９】
すなわち、上式（３）の分母項は受信信号の振幅値（受信レベル）を示しており、回線の周波数特性が図７に示すような理想的な（平坦な）特性の場合には、上式（３）の分母項はほぼ一定と見なせるので無視することができ、ハードウェア構成を簡略化できるが、図８に示すような周波数特性を有している回線の場合には分母項は決して無視することができず、振幅値（ベクトルの長さ）の正規化は重要な要素となる。
以上の公知の技術に対して、本発明の構成は、上記のルート演算と除算処理を行わないようにするもので、処理量の軽減が期待できるものである。以下に本発明に関する動作について説明を行う。
【００２０】
（全体構成）
図１は、本発明の一実施例を示す復調部の機能ブロック図である。
図１において、ＤＡＡ回路部３１、Ａ／Ｄ変換器３２、帯域分離フィルタ（ＢＰＦ）３３については、図１３に示した構成と同じである。本発明においては、周波数偏移復調部３４の内部に新たにレベル補正量算出部３５を設けるとともに、レベル補正量算出部３５からのｆ１，ｆ２周波数間のレベル補正量出力をもとに動作する帯域制限フィルタ係数選択部３６および帯域制限フィルタ係数テーブル３７を設け、帯域制限フィルタ係数選択部３６によりテーブル３７から入力したレベル補正量に最も近い帯域分離フィルタ３３のフィルタ係数を選択して、その係数をロードして、帯域分離フィルタ３３の係数を選択した係数に置き換える。
【００２１】
（レベル補正量算出部）
図２は、図１におけるレベル補正量算出部の詳細ブロック図である。
図２における上方のブロックはいずれもプログラムを示す機能部であり、下方の演算器５０、レジスタ５１、メモリ５２はそれぞれハードウェアを示している。各ブロックのプログラムをハードウェアを用いて実行することにより、レベル補正量算出機能が実現される。
最初の補正量でＢＰＦ３３の係数が変更されると、最初の補正が前段（ＢＰＦ）にかかってしまうため、２回目以降の補正は前回の補正量が含まれていることを考える必要がある。前回の補正量（ｆ１とｆ２の受信レベル比）をαとすると、２回目以降の補正量はｆ１との受信レベル比をα′とすると、補正量はα＋α′となる。前回の補正値で十分周波数特性が補正されている場合には、｜α＋α′｜≦｜α｜となるはずである。従って、２回目以降は、 ｜α＋α′｜＞｜α｜となったときにα＋α′を新しい補正値として更新する処理を行う必要がある。
レベル補正量算出部３５は、ＢＰＦ３３からの２つの周波数（二値信号）を入力して、２つの周波数に対する中心周波数を生成し、入力信号に中心周波数の同相成分と直交成分を乗算して複素ベクトルを生成する処理部４１と、その複素ベクトルを入力して、帯域制限フィルタにより中心周波数との差分周波数に関する複素ベクトルを抽出する処理部４２と、ビット判定タイミングで差分周波数の複素ベクトル長（振幅値）を算出する処理部４３と、２つのビット（周波数）の振幅値から振幅（受信）レベル比を算出する処理部４４と、算出された受信レベル比（補正量）をレジスタ等の記憶装置に記憶する処理部４５と、上記ビット判定タイミング毎に毎回算出された受信レベル比の絶対値と記憶装置に記憶された受信レベル比の絶対値とを比較する処理部４６と、比較結果から大きい方の受信レベル比で記憶装置の記憶内容を更新する処理部４７と、補正量によってＢＰＦ係数が変更された後に補正する場合には、｜α＋α′｜＞｜α｜であるか否かを判定する手段４８と、記憶装置の受信レベル比が更新されるタイミングで、補正量（α＋α′）の値をＢＰＦ係数選択部３６に送出する処理部４９とを備えている。
【００２２】
（レベル補正量算出処理）
図５は、レベル補正量算出部の処理フローチャートである。
ここで、図１および図２に記述されている特性周波数ｆ１,ｆ２間の受信レベル比（補正量）の算出方法について、図５のフローにより説明する。
一般的にＦＳＫモデムでは、最初のｆ１信号（マーク）を検出した後にデータハンドリングを開始する（ステップ１０１）。このとき、ｆ１信号受信時のビット判定タイミングにおける振幅値（複素ベクトルＡ長）を算出しておき、レジスタ等のメモリに記憶しておく（ステップ１０３）。次に、データハンドリングが開始され（ステップ１０４）、ｆ２信号（スペース）を受信すると（ステップ１０５）、その振幅値（複素ベクトルＡ長）を上記と同じようにビット判定タイミングで算出し（ステップ１０６）、次に、先に記憶されているｆ１信号の振幅値との比を算出し、その比を補正量としてレジスタ等のメモリに記憶する（ステップ１０７）。以後、ｆ２信号”０”がビット判定されるタイミングで、同様にｆ１信号の振幅値との比が算出される（ステップ１０５〜１０７）。そして、先に記憶されている補正量との比較を行うが、２回目以降の補正であるかを判断し（ステップ１０９）、２回目以降であれば、２回目以降の補正量をα′、前回の補正量をαとすると、｜α＋α′｜＞｜α｜であるか否かを判定する（ステップ１１０）。そして、２回目以降の場合に上記条件が満たされる場合は、（α＋α′）を新しい補正量としてレジスタ等のメモリに記憶されている補正量を更新し、その補正量をＢＰＦ係数選択部３６に送出する（ステップ１１１）。
【００２３】
ここで、ｆ１信号とｆ２信号の符号付きの振幅比（周波数間のレベル補正量）を算出する簡単な方法の具体例をあげておく。
最初に記憶したｆ１信号の振幅値を元に、たとえば±10dBの範囲で１dB刻みの値（Thresh）を算出し、レジスタ等のメモリに記憶しておく（ステップ１０３）。次に、ｆ２信号を受信し”０”がビット判定されるタイミングでｆ２信号の振幅値を算出し、その振幅値と各Threshと比較し、ｆ１信号に対する受信レベル比を±１.０dBの誤差範囲で特定し、補正量としてメモリ等の記憶装置に記憶する（ステップ１０７）。
以後同様に”０”がビット判定されるタイミングで算出されるｆ２信号の振幅値と各Threshと比較し、ｆ１信号に対する受信レベル比（補正量）を特定する。なお、前述のように、１回目の補正ではαを補正量として係数選択部に送出するが、２回目以降の場合には、｜α＋α′｜＞｜α｜であるか否かを判定して、式が成立した場合に（α＋α′）の補正量を係数選択部に送出する。
以上のような処理を行うことで、実際に比を求めるより処理を軽減することができる。
【００２４】
（ＢＰＦ係数選択部）
次にＢＰＦ係数選択部について説明を行う。
図３は、ＢＰＦ係数テーブルのデータ構成図、図４は、ＦＩＲ（有限インパルス応答）フィルタで構成されたディジタルフィルタのブロック図、図６は、ＢＰＦ係数選択部の動作フローチャート、図７は、理想的な周波数特性曲線図、図８は、実回線での周波数特性曲線図、図９は、ＢＰＦの周波数特性曲線図（１）、図１０は、ＢＰＦの周波数特性曲線図（２）、図１１は、ＢＰＦの周波数特性曲線図（３）である。
帯域制限フィルタ係数選択部３６は、周波数偏移復調部３４のレベル補正量算出部３５から２つの特性周波数ｆ１、ｆ２間の受信レベル比（レベル補正量）が出力されると、そのデータを元にＢＰＦ係数選択テーブル部３７からより適切なＢＰＦ係数を選択して、帯域制限フィルタ部３３の係数を置き換える構成になっている。
【００２５】
ＦＳＫ変復調装置の復調部は、通常はＢＰＦの特性として図９の実線で示すような周波数特性を持たせて帯域外の不要な信号を除去するが、図８に示すように回線の周波数特性により、ｆ２周波数の受信レベルがｆ１周波数の受信レベルより減衰する。このｆ１とｆ２の受信レベル比は回線によってある程度想定可能なため、図１０、図１１のように周波数特性に応じたＢＰＦの係数（１）（２）を用意し、ｆ１・ｆ２信号の補正量と対応させておく。図１０では、高周波の減衰量が大きいため（点線の特性曲線参照）、ｆ１の信号レベルよりｆ２の信号レベルを持ち上げている（実線の特性曲線参照）。図１１では、さらに高周波の減衰量が大きいため、ｆ１の信号レベルよりｆ２の信号レベルを図１０の場合よりもさらに持ち上げている（実線の特性曲線参照）。
すなわち、復調部の帯域制限フィルタ（ＢＰＦ）３３であるディジタルフィルタの機能ブロックは、図４に示すように、複数個のタップＴを接続して、それぞれフィルタ係数ｈ₀〜ｈ_Mの係数を組として設定している。一方、ＢＰＦ係数テーブル３７には、図３に示すようなＣ１〜Ｃｎの係数種別毎にｈ₀〜ｈ_Mの各フィルタ係数を用意しており、それぞれ図１０、図１１の周波数特性に対応させている。
【００２６】
このように、ＢＰＦ係数テーブル３７には、いくつかのＢＰＦ係数を用意して、テーブル参照データとしてメモリに格納しておく。
ＢＰＦ係数選択部３６には、入力として前述のｆ１・ｆ２間のレベル補正値が入力されるので、この入力値をもとに係数テーブル３７から最も近いものを選択し、ＢＰＦ３３に１組の係数群をロードして前段のＢＰＦ係数データをテーブルから選択されたＢＰＦ係数データ群で置き換える。
このときＢＰＦ３３は、図４に示すようなＦＩＲフィルタで構成されているので、任意のタイミングでフィルタ係数を変更しても安定しているので問題はない。
【００２７】
このように前段のＢＰＦ部３３で回線の周波数特性を補正することによって、上述の角度成分算出時のベクトルの正規化が行われることになり、内部処理で行われる正規化のための演算処理を省略することが可能であるため、簡素な構成で性能向上を実現できる。
ところで、本発明の実施例（図１，図２）の各部はブロツクで示してあり、それらは全てハード的に構成されているようにみえるが、この実施例では、Ａ／Ｄ変換器以降の処理ブロックを全てＤＳＰ（Digital Signal Processor）のソフトウエアで処理されるようなつている。しかし、これら全てをハードウェアで構成しても良いし、一部をハード的な回路で構成しても良い。
【００２８】
ＢＰＦ係数選択部３６は、図６に示すように、レベル補正量算出部３５からｆ１，ｆ２間のレベル補正値が送られてきたか否かを常時検出し（ステップ１１１）、送られてきたならば、ＢＰＦ係数テーブル３７を参照して、送られてきたレベル補正値を元に最も近い係数組を選択する（ステップ１１２）。次に、選択したＢＰＦ係数組（Ｃｎ）を帯域制限フィルタ（ＢＰＦ）３３にロードすることにより、ＢＰＦ係数組と置き換える（ステップ１１３）。
【００２９】
図５および図６に示すレベル補正量算出部およびＢＰＦ係数選択部の処理フローチャートをそれぞれプログラムに変換して、ＣＤ−ＲＯＭ等の記録媒体に格納しておけば、パソコン等のコンピュータに記録媒体を装着し、プログラムをローディングして実施させることで、本発明を容易に実現することができる。 なお、任意のコンピュータからネットワークを介して他のコンピュータに本発明のプログラムをダウンロードすることによっても容易に実現可能である。
【００３０】
【発明の効果】
以上説明したように、本発明によれば、周波数特性を持つ回線を介して入力されたＦＳＫ信号を復調する場合に、２つの周波数ｆ１・ｆ２間の受信レベルを正規化するための大規模なハードウェアや処理量の多いソフトウェアを不要にして、２つの周波数の受信レベルの比をもとに復調部前段の帯域制限フィルタ（ＢＰＦ）を選択的に変更し、それにより回線の周波数特性を補正するので、少ない処理量で正規化処理と同様の効果を得ることができる。
また、処理の前段で利得を補正するため、後段の演算精度に有利に働くという効果が得られる。
【図面の簡単な説明】
【図１】本発明の一実施例を示す周波数偏移変復調装置の復調部のブロック図である。
【図２】図１におけるレベル補正量算出部の詳細ブロック図である。
【図３】本発明の一実施例を示す帯域制限フィルタ係数テーブルのデータ構成図である。
【図４】図１における帯域制限フィルタ（ＢＰＦ）を構成するＦＩＲフィルタの機能ブロック図である。
【図５】本発明の一実施例を示すレベル補正量算出部の動作フローチャートである。
【図６】本発明の一実施例を示すＢＰＦ係数選択部の動作フローチャートである。
【図７】ＦＳＫ変復調器の理想的な周波数特性曲線図である。
【図８】同じく実回線での周波数特性曲線図である。
【図９】本発明におけるＢＰＦの周波数特性曲線図（１）である。
【図１０】同じくＢＰＦの周波数特性曲線図（２）である。
【図１１】同じくＢＰＦの周波数特性曲線図（３）である。
【図１２】本発明が適用される変復調装置の概略ブロック図である。
【図１３】本発明が適用されるＦＳＫ変復調装置の復調部のブロック図である。
【図１４】図１３におけるＦＳＫ復調部の機能ブロック図である。
【符号の説明】
３１…ＤＡＡ回路部、３２…Ａ／Ｄ変換器、
３３…帯域制限フィルタ(ＢＰＦ)、３４…周波数偏移復調部、
３５…レベル補正量算出部、３６…ＢＰＦ係数選択部、
３７…ＢＰＦ係数テーブル、４１…複素ベクトル生成処理部、
４２…差分周波数ベクトル抽出処理部、
４３…差分周波数複素ベクトル長算出処理部、
４４…振幅レベル比算出処理部、４５…受信レベル比の記憶処理部、
４６…タイミング毎受信レベル比の比較処理部、４８…補正条件確認部、
４７…記憶内容の更新処理部、４９…更新された受信レベル比送出処理部、
５１…レジスタ、５２…演算器、５２…メモリ、１…変復調装置、
２…コントローラ、３…変調復調部、４…変調部、５…復調部。[0001]
The present invention relates to a modulation / demodulation device that modulates / demodulates a signal transmitted / received between a communication line and a terminal device at the end of the communication line such as an analog telephone line, in particular, a frequency shift keying (FSK) method. It relates demodulator of adopted modem (modem), and more particularly relates to a method of demodulating normalization processing modem capable of obtaining the same effect as and frequency shift keying in a simple process.
[0002]
[Prior art]
Conventionally, the FSK (Frequency Shift Keying) communication system has been widely used in telephone line modems, etc., and the V series recommendation of the International Telegraph and Telephone Consultative Committee (CCITT), which has become the standard, is V. 21, V.R. There are FSK telephone line modem standards such as 23.
Of these, V. No. 21 is recommended that two frequencies, 1080 Hz and 1750 Hz, be center frequencies, and a frequency of ± 100 Hz is a characteristic frequency.
V. 23 has been recommended that the center frequency is 1500 Hz or 1700 Hz and the characteristic frequency is ± 200 Hz or ± 400 Hz (V.23 includes a backward frequency having a center frequency of 420 Hz and a characteristic frequency of ± 30 Hz. Channel exists).
[0003]
The following three are typical examples of FSK conventional techniques.
1) A method of reproducing data by directly counting the zero-crossing interval between two carrier frequencies (F1, F2). That is, this counts the number of times that the waveform of the carrier frequency (F1, F2) crosses the zero line, discriminates “F1” or “F2” by the number, and reproduces the data.
2) A method of providing two narrow bandpass filters for extracting two carrier frequency components and comparing the output signal levels of both when an FSK signal is input.
That is, this allows the carrier frequency components to pass through a narrow band pass filter of only F1 and a narrow band pass filter of only F2, and discriminates F1 and F2 by their output levels.
3) A method of generating a center frequency for two carrier frequencies and extracting a shift frequency component between the input frequency and the center frequency. That is, a center frequency F0 of F1 and F2 is generated, and it is determined whether the input frequency is + α or −α from F0, and F1 and F2 are extracted.
[0004]
In the methods 1) and 2), the demodulation process is simple, but there is a problem in that it is easily affected by noise on the line and the possibility of erroneous signal discrimination increases.
On the other hand, although the method 3) is a relatively complicated process, a stable and highly accurate demodulator can be realized.
[0005]
[Problems to be solved by the invention]
In general, the frequency characteristics on the line do not show ideal characteristics (flat frequency characteristics), and the amount of attenuation varies depending on the frequency.
Therefore, in the method 3), it is necessary to normalize the reception level (amplitude value) when calculating the frequency shift component.
In the case of a line having an ideal frequency characteristic, this normalization process can be omitted, and if the standard is specified so that the two frequencies are relatively close to each other, the frequency characteristic Can be considered flat.
[0006]
However, since the attenuation amounts of the two frequencies corresponding to the binary values are actually different as described above, the normalization process cannot be omitted. V. When the two frequencies are separated by as much as 800 Hz as in the case of 23 data channels, the attenuation amount on the high frequency side generally increases. In a poor quality line, an attenuation difference of 10 dB may occur.
When communication is performed on such a line, unless the reception level normalization process is performed, performance under high noise (S / N 10 dB or less) is affected, and sufficient communication performance cannot be obtained.
However, since this normalization processing requires a large amount of processing, it is desirable to omit it if possible. For example, when the processing is realized by an arithmetic processing device such as a DSP (Digital Signal Processor), if the normalization process is omitted, the amount of processing can be reduced and the current consumption can be kept low.
[0007]
As automatic control of the reception level, there is an automatic gain control (AGC) function. In general, the AGC function functions to converge at a very slow speed so as to perform a steady and stable operation of the reception level.
When the bit rate is increased in the FSK communication system, it is necessary to switch the bit (frequency) for 1 to 2 wavelengths of the sine wave of the carrier frequency, and it is necessary to determine this, but in adaptive processing such as AGC, 1 to Since the convergence speed cannot be increased as gain control is performed in units of two wavelengths, it does not function to correct the frequency characteristics of the line. A function for adjusting the gain more instantaneously is required. However, if such an adaptive process is performed, the amount of processing increases as in the normalization process.
[0008]
Therefore, the object of the present invention is to solve the conventional problem in this way, and to obtain the same effect as the normalization processing with a small amount of processing, to correct the frequency characteristic of the line, and to provide a highly accurate modulation / demodulation device and frequency and to provide a demodulating how the shift modulation.
The modem according to the present invention employs a method of reducing the amount of processing when the method 3), which is considered to be resistant to noise from the above three methods, is employed.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the modem device of the present invention selectively changes the band-limiting filter (BPF) in the previous stage of the demodulator based on the ratio of the reception levels of the two frequencies, thereby changing the two frequencies f1, The same effect as that of the normalization process can be obtained while omitting the process of normalizing the reception level between f2.
[0010]
The modulation / demodulation apparatus of the present invention is a modulation / demodulation apparatus (modem) in frequency shift keying (FSK) communication in which two frequencies having different frequencies are associated with each value of a binary signal for communication. I / F unit (DAA (Direct Access Arrangement) circuit unit), an A / D conversion unit that converts an analog signal from a line or the like through the DAA circuit unit into a digital signal, and a filter coefficient in a memory such as a register In an FSK demodulator having a band-limiting filter (BPF) configured by a digital filter that can be arbitrarily stored and stored in the filter coefficient,
A means for calculating a reception level ratio of two frequencies corresponding to a binary signal and a plurality of BPF coefficient tables, and a plurality of BPF coefficients based on the reception level ratio (correction amount) from the reception level ratio calculation means A BPF coefficient selection unit that selects an appropriate coefficient for correcting the reception level ratio from the table, and replaces the BPF coefficient selected by the coefficient selection unit with the coefficient of the band-limiting filter in the previous stage.
[0011]
The reception level ratio calculating means generates a center frequency for two frequencies (binary signal), and generates a complex vector by multiplying the input signal by an in-phase component and a quadrature component of the center frequency. A means for extracting a complex vector related to a difference frequency from the center frequency by a band limiting filter from a complex vector, a means for calculating a complex vector length (amplitude value) of a difference frequency at a bit determination timing, and receiving each time at each bit determination timing. Means for calculating the level ratio, means for storing the calculated reception level ratio (correction amount) in a storage device such as a register, and reception level calculated every time data is output from the A / D converter Means for comparing the absolute value of the ratio with the absolute value of the reception level ratio stored in the storage device, and a higher reception level from the comparison result Means for updating the storage contents of the storage device, the updated correction amount of the storage device in the case of the first correction, and the first correction amount and the current correction in the case of the second and subsequent corrections. On the condition that the added value of the amount is larger than the first correction amount, a value obtained by adding the first correction amount and the current correction amount is sent to the BPF coefficient selection unit.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the drawings.
FIG. 12 is a schematic block diagram of a modem device (modem) to which the present invention is applied.
The modem 1 includes a controller 2 connected to the CPU side, and a modem 3 composed of a modulator 4 and a demodulator 5. The controller 2 is a means for controlling the sequence as a modem, and the modulation unit 4 of the modulation / demodulation unit 3 performs frequency shift modulation on the bit string input from the controller, performs D / A conversion, and performs an analog signal (FSK modulation). ) Is sent to the transmission line, and the demodulator 5 performs A / D conversion on the analog signal (FSK modulation) input from the transmission line, passes through the band limiting filter, and performs frequency shift demodulation. The bit output is output to the controller unit.
[0013]
FIG. 13 and FIG. 14 are functional block diagrams showing an example of a demodulator of a known FSK modem.
13 and 14 do not illustrate the controller 2 in FIG. 12, it goes without saying that a standard modulation unit is required as the modem. Furthermore, a controller 2 for controlling the sequence as a modem is also necessary, but since these are all known, illustration and description are omitted.
[0014]
In FIG. 13, a signal input from a line is input to an A / D converter 12 via a DAA (Direct Access Arrangement) circuit unit 11, and converted into digital data. The digital data of the FSK signal waveform output from the A / D converter 12 passes through a band separation filter (BPF) 13 constituted by a digital filter, and unnecessary out-of-band components are removed. Then, the output signal is input to the FSK demodulator 14. The BPF 13 is a digital filter composed of an FIR (finite impulse response) filter, and can realize an arbitrary frequency characteristic by changing a filter coefficient stored in a memory such as a register.
[0015]
FIG. 14 shows an embodiment of a detailed configuration of the frequency shift demodulator in FIG.
The input FSK signal is first input to the complex processing unit 21. The complex processing unit 21 performs complex processing on the input signal by multiplying the input signal by the in-phase component and the quadrature component of the center frequency to generate a complex vector.
If the center frequency is f, the input frequency is f + a, and the input signal is cos (2π (f + a) t), the complex vector (x is an integer part and y is an imaginary part) as shown in the following equation (1). can get.

[0016]
Next, the obtained complex vector is band-limited by the low-pass filter (LPF) 22 to eliminate the second term of the above equation, and the complex vector A having only the difference frequency as represented by the following equation (2). Can be extracted.
￣A = (x, y) = G / 2 × cos (2πat), G / 2 × sin (2πat) (2)
Each time the data sampled by the A / D converter 12 is input, the complex vector A is extracted and input to the “angle component calculation processing unit 23”.
[0017]
Next, the “angle component calculation processing unit 23” calculates an angle component with the differential frequency complex vector A one sample before.
Here, the angle formed by the two complex vectors can be approximated by sin θ, and is obtained by the following calculation formula (3). In Equation (3), the denominator indicates an absolute value, and the numerator indicates an outer product.
[Expression 1]

[0018]
Next, the code extraction timing is generated by the synchronization processing unit 24, and the bit determining unit 25 determines 1 and 0 bits from the code extraction timing and the sign bit of the angle component, and outputs the bit stream.
Although the FSK signal is demodulated by the method as described above, as shown in the above equation (3), root calculation and division are required for internal calculation processing, which cannot be realized with a simple hardware configuration.
[0019]
That is, the denominator term of the above equation (3) indicates the amplitude value (reception level) of the received signal, and when the frequency characteristic of the line is an ideal (flat) characteristic as shown in FIG. The denominator term in Equation (3) can be ignored because it can be regarded as almost constant, and the hardware configuration can be simplified. However, in the case of a line having frequency characteristics as shown in FIG. Normalization of the amplitude value (vector length) is an important factor that cannot be ignored.
In contrast to the above known technique, the configuration of the present invention is such that the above route calculation and division processing are not performed, and a reduction in processing amount can be expected. The operation relating to the present invention will be described below.
[0020]
(overall structure)
FIG. 1 is a functional block diagram of a demodulator showing an embodiment of the present invention.
In FIG. 1, a DAA circuit unit 31, an A / D converter 32, and a band separation filter (BPF) 33 are the same as those shown in FIG. In the present invention, a level correction amount calculation unit 35 is newly provided in the frequency shift demodulation unit 34 and operates based on the level correction amount output between the f1 and f2 frequencies from the level correction amount calculation unit 35. A band limiting filter coefficient selecting unit 36 and a band limiting filter coefficient table 37 are provided, and the band limiting filter coefficient selecting unit 36 selects the filter coefficient of the band separation filter 33 that is closest to the level correction amount input from the table 37, and the coefficient And the coefficient of the band separation filter 33 is replaced with the selected coefficient.
[0021]
(Level correction amount calculation unit)
FIG. 2 is a detailed block diagram of the level correction amount calculation unit in FIG.
The upper blocks in FIG. 2 are all functional units indicating programs, and the lower arithmetic unit 50, register 51, and memory 52 indicate hardware. A level correction amount calculation function is realized by executing the program of each block using hardware.
When the coefficient of the BPF 33 is changed with the first correction amount, the first correction is applied to the preceding stage (BPF), so it is necessary to consider that the second and subsequent corrections include the previous correction amount. If the previous correction amount (reception level ratio between f1 and f2) is α, the correction amount after the second time is α + α ′ when the reception level ratio with f1 is α ′. When the frequency characteristic is sufficiently corrected with the previous correction value, | α + α ′ | ≦ | α | should be satisfied. Therefore, after the second time, it is necessary to perform a process of updating α + α ′ as a new correction value when | α + α ′ |> | α |.
The level correction amount calculation unit 35 receives the two frequencies (binary signal) from the BPF 33, generates a center frequency for the two frequencies, and multiplies the input signal by the in-phase component and the quadrature component of the center frequency to form a complex. A processing unit 41 that generates a vector, a processing unit 42 that inputs the complex vector and extracts a complex vector related to a difference frequency from the center frequency by a band limiting filter, and a complex vector length (amplitude) of the difference frequency at the bit determination timing Value), a processing unit 44 that calculates an amplitude (reception) level ratio from the amplitude values of two bits (frequency), and a storage device such as a register that stores the calculated reception level ratio (correction amount). And the absolute value of the reception level ratio calculated at each bit determination timing and the absolute value of the reception level ratio stored in the storage device. When the processing unit 46 to be compared, the processing unit 47 to update the storage contents of the storage device with the larger reception level ratio from the comparison result, and when the BPF coefficient is changed by the correction amount, | α + α ′ | Means 48 for determining whether or not> | α |, and a processing unit 49 for sending the value of the correction amount (α + α ′) to the BPF coefficient selection unit 36 at the timing when the reception level ratio of the storage device is updated. It has.
[0022]
(Level correction amount calculation processing)
FIG. 5 is a process flowchart of the level correction amount calculation unit.
Here, a method of calculating the reception level ratio (correction amount) between the characteristic frequencies f1 and f2 described in FIGS. 1 and 2 will be described with reference to the flow of FIG.
In general, the FSK modem starts data handling after detecting the first f1 signal (mark) (step 101). At this time, the amplitude value (complex vector A length) at the bit determination timing at the time of receiving the f1 signal is calculated and stored in a memory such as a register (step 103). Next, data handling is started (step 104), and when the f2 signal (space) is received (step 105), the amplitude value (complex vector A length) is calculated at the bit determination timing in the same manner as described above (step 106). Then, a ratio with the amplitude value of the previously stored f1 signal is calculated, and the ratio is stored in a memory such as a register as a correction amount (step 107). Thereafter, at the timing when the bit determination of the f2 signal “0” is performed, the ratio with the amplitude value of the f1 signal is similarly calculated (steps 105 to 107). Then, a comparison is made with the previously stored correction amount, but it is determined whether the correction is for the second time or later (step 109). If it is the second time or later, the correction amount for the second time or later is α ′, If the previous correction amount is α, it is determined whether or not | α + α ′ |> | α | (step 110). If the above condition is satisfied in the second and subsequent times, the correction amount stored in the memory such as a register is updated with (α + α ′) as a new correction amount, and the correction amount is stored in the BPF coefficient selection unit 36. Send out (step 111).
[0023]
Here, a specific example of a simple method for calculating a signed amplitude ratio (level correction amount between frequencies) of the f1 signal and the f2 signal will be given.
Based on the amplitude value of the f1 signal stored first, for example, a value (Thresh) in 1 dB increments within a range of ± 10 dB is calculated and stored in a memory such as a register (step 103). Next, when the f2 signal is received, the amplitude value of the f2 signal is calculated at the timing when “0” is bit-determined, the amplitude value is compared with each Thresh, and the received level ratio with respect to the f1 signal is an error of ± 1.0 dB. The range is specified and stored as a correction amount in a storage device such as a memory (step 107).
Thereafter, similarly, the amplitude value of the f2 signal calculated at the timing when “0” is bit-determined is compared with each Thresh, and the reception level ratio (correction amount) for the f1 signal is specified. As described above, in the first correction, α is sent as a correction amount to the coefficient selection unit. In the second and subsequent corrections, it is determined whether or not | α + α ′ |> | α |. When the equation holds, the correction amount of (α + α ′) is sent to the coefficient selection unit.
By performing the processing as described above, it is possible to reduce the processing compared to actually obtaining the ratio.
[0024]
(BPF coefficient selector)
Next, the BPF coefficient selection unit will be described.
3 is a data configuration diagram of a BPF coefficient table, FIG. 4 is a block diagram of a digital filter configured by an FIR (finite impulse response) filter, FIG. 6 is an operation flowchart of a BPF coefficient selection unit, and FIG. FIG. 8 is a frequency characteristic curve diagram of a real line, FIG. 9 is a frequency characteristic curve diagram of a BPF (1), and FIG. 10 is a frequency characteristic curve diagram of a BPF (2) and FIG. FIG. 3 is a frequency characteristic curve diagram (3) of the BPF.
When the reception level ratio (level correction amount) between the two characteristic frequencies f1 and f2 is output from the level correction amount calculation unit 35 of the frequency shift demodulation unit 34, the band limiting filter coefficient selection unit 36 generates the data based on the received data. The BPF coefficient selection table unit 37 selects a more appropriate BPF coefficient and replaces the band limiting filter unit 33 coefficient.
[0025]
The demodulating unit of the FSK modulation / demodulation apparatus usually removes unnecessary signals outside the band by giving the frequency characteristic as shown by the solid line in FIG. 9 as the characteristic of the BPF. However, as shown in FIG. , The reception level of the f2 frequency is attenuated from the reception level of the f1 frequency. Since the reception level ratio of f1 and f2 can be estimated to some extent depending on the line, BPF coefficients (1) and (2) corresponding to the frequency characteristics are prepared as shown in FIGS. 10 and 11, and the correction amount of the f1 / f2 signal I will make it correspond. In FIG. 10, since the attenuation amount of the high frequency is large (refer to the dotted characteristic curve), the signal level of f2 is raised from the signal level of f1 (refer to the characteristic curve of the solid line). In FIG. 11, since the attenuation amount of the high frequency is larger, the signal level of f2 is further raised than the signal level of f1 than in the case of FIG. 10 (refer to the solid characteristic curve).
That is, the functional block of the digital filter, which is the band limiting filter (BPF) 33 of the demodulator, connects a plurality of taps T and sets the coefficients of the filter coefficients h _{0 to} h _M as shown in FIG. It is set as. On the other hand, in the BPF coefficient table 37, filter coefficients h ₀ to h _M are prepared for each of the coefficient types C1 to Cn as shown in FIG. 3 and correspond to the frequency characteristics shown in FIGS. 10 and 11, respectively. ing.
[0026]
As described above, several BPF coefficients are prepared in the BPF coefficient table 37 and stored in the memory as table reference data.
Since the level correction value between f1 and f2 described above is input to the BPF coefficient selection unit 36, the closest one is selected from the coefficient table 37 based on this input value, and one set of coefficients is stored in the BPF 33. The group is loaded and the previous BPF coefficient data is replaced with the BPF coefficient data group selected from the table.
At this time, since the BPF 33 is composed of an FIR filter as shown in FIG. 4, there is no problem because it is stable even if the filter coefficient is changed at an arbitrary timing.
[0027]
In this way, by correcting the frequency characteristics of the line by the BPF unit 33 in the previous stage, normalization of the vector at the time of calculating the angle component described above is performed, and calculation processing for normalization performed in internal processing is performed. Since it can be omitted, the performance can be improved with a simple configuration.
By the way, each part of the embodiment of the present invention (FIGS. 1 and 2) is shown as a block, and it seems that all of them are configured in hardware, but in this embodiment, after the A / D converter, All processing blocks are processed by DSP (Digital Signal Processor) software. However, all of these may be configured by hardware, or a part may be configured by a hardware circuit.
[0028]
As shown in FIG. 6, the BPF coefficient selection unit 36 always detects whether or not a level correction value between f1 and f2 has been sent from the level correction amount calculation unit 35 (step 111). For example, referring to the BPF coefficient table 37, the nearest coefficient group is selected based on the level correction value sent (step 112). Next, the selected BPF coefficient group (Cn) is loaded into the band limiting filter (BPF) 33 to replace it with the BPF coefficient group (step 113).
[0029]
If the processing flowcharts of the level correction amount calculation unit and the BPF coefficient selection unit shown in FIGS. 5 and 6 are converted into programs and stored in a recording medium such as a CD-ROM, the recording medium is stored in a computer such as a personal computer. By mounting and loading and executing the program, the present invention can be easily realized. It can be easily realized by downloading the program of the present invention from an arbitrary computer to another computer via a network.
[0030]
【The invention's effect】
As described above, according to the present invention, when demodulating an FSK signal input via a line having frequency characteristics, a large scale for normalizing the reception level between the two frequencies f1 and f2 is obtained. Eliminates the need for hardware and software with a large amount of processing, and selectively changes the band-limiting filter (BPF) in front of the demodulator based on the ratio of the reception levels of the two frequencies, thereby correcting the frequency characteristics of the line Therefore, the same effect as the normalization process can be obtained with a small amount of processing.
In addition, since the gain is corrected before the processing, it is possible to obtain an advantageous effect that it is advantageous for the calculation accuracy of the subsequent stage.
[Brief description of the drawings]
FIG. 1 is a block diagram of a demodulator of a frequency shift modulator / demodulator according to an embodiment of the present invention.
FIG. 2 is a detailed block diagram of a level correction amount calculation unit in FIG. 1;
FIG. 3 is a data configuration diagram of a band limiting filter coefficient table showing an embodiment of the present invention.
4 is a functional block diagram of an FIR filter constituting the band limiting filter (BPF) in FIG. 1. FIG.
FIG. 5 is an operation flowchart of a level correction amount calculation unit showing an embodiment of the present invention.
FIG. 6 is an operation flowchart of a BPF coefficient selection unit showing an embodiment of the present invention.
FIG. 7 is an ideal frequency characteristic curve diagram of the FSK modulator / demodulator.
FIG. 8 is a frequency characteristic curve diagram similarly on the real line.
FIG. 9 is a frequency characteristic curve diagram (1) of a BPF according to the present invention.
FIG. 10 is a frequency characteristic curve diagram (2) of the BPF.
FIG. 11 is a frequency characteristic curve diagram (3) of the BPF.
FIG. 12 is a schematic block diagram of a modem device to which the present invention is applied.
FIG. 13 is a block diagram of a demodulation unit of an FSK modulation / demodulation apparatus to which the present invention is applied.
14 is a functional block diagram of an FSK demodulator in FIG.
[Explanation of symbols]
31 ... DAA circuit part, 32 ... A / D converter,
33: Band limiting filter (BPF) 34: Frequency shift demodulator
35 ... level correction amount calculation unit, 36 ... BPF coefficient selection unit,
37 ... BPF coefficient table, 41 ... complex vector generation processing unit,
42 ... Differential frequency vector extraction processing unit,
43. Difference frequency complex vector length calculation processing unit,
44 ... Amplitude level ratio calculation processing unit, 45 ... Reception level ratio storage processing unit,
46: Comparison processing unit for reception level ratio at each timing 48: Correction condition confirmation unit,
47 ... Stored content update processing unit, 49 ... Updated reception level ratio transmission processing unit,
51: Register, 52 ... Operation unit, 52 ... Memory, 1 ... Modulator / Demodulator,
2 ... Controller, 3 ... Modulation demodulation unit, 4 ... Modulation unit, 5 ... Demodulation unit.

Claims (7)

In the demodulator of the frequency shift modulation / demodulation device having a digital filter that can arbitrarily change the filter coefficient,
Means for calculating a reception level ratio between the f1 signal and the f2 signal of two frequencies used in frequency shift keying;
Means for changing the filter coefficient of the digital filter based on the reception level ratio calculated by the calculation means;
The means for calculating the reception level ratio of the two frequencies generates a center frequency for the two frequencies, and multiplies the input signal by the in-phase component and the quadrature component of the center frequency to generate a complex vector;
Means for extracting a complex vector related to a difference frequency from the center frequency from a generated complex vector by a band limiting filter;
Means for calculating the complex vector length of the difference frequency at the bit determination timing;
Means for calculating a reception level ratio from amplitude values of two frequencies;
Means for calculating a correction amount from the calculated reception level ratio, and storing the correction amount in a storage device;
Means for comparing the correction amount calculated every time the bit determination timing with the correction amount stored last time;
Means for updating the storage content of the storage device with the correction amount when the correction amount is larger than the correction amount stored from the comparison result;
A modulation / demodulation device, wherein the correction amount is sent to a band-limiting filter coefficient selection unit at a timing when the correction amount of the storage device is updated. The modem according to claim 1,
The complex vector generation means, the difference frequency vector extraction means and the difference frequency complex vector length calculation means calculate a plurality of vector A lengths at the time of detection of the first f1 signal, store the calculated value, and store the next f2 signal. At the time of detection, the complex vector A length is calculated, the ratio with the amplitude value of the previously stored f1 signal is calculated, the ratio is stored as a correction amount, and the timing at which the f2 signal is bit-determined Similarly, the ratio of the amplitude value of the f1 signal is calculated in the same manner as before, and the absolute value of the value obtained by adding the previously stored correction amount and the current correction amount is the previous stored correction amount. Updates the correction amount stored with the previously stored correction amount and the addition value of the current correction amount on condition that the absolute value is larger than the absolute value, and sends the updated correction amount to the band limiting filter coefficient selection unit A modulation / demodulation device. The modem according to claim 1,
Each of the means constituting the reception level ratio calculation means for the two frequencies is a program module. In a demodulation method of a frequency shift modulation / demodulation device in which a filter coefficient can be arbitrarily changed by a digital filter,
In a demodulation method for calculating a reception level ratio of two frequencies used in frequency shift keying and changing a filter coefficient of the digital filter based on the reception level ratio calculated by the calculation means,
The calculation process of the reception level ratio of the two frequencies generates a center frequency for the two frequencies, and multiplies the input signal by an in-phase component and a quadrature component of the center frequency to generate a complex vector;
Extracting a plurality of vectors related to a difference frequency with respect to the center frequency from a generated complex vector by a band limiting filter;
Calculating a complex vector length of the difference frequency at the bit determination timing;
Calculating a reception level ratio from amplitude values of two frequencies;
Calculating a correction amount from the calculated reception level ratio, and storing the correction amount in a storage device;
Comparing the correction amount calculated every time the bit determination timing is compared with the correction amount stored and updated last time;
Updating the storage content of the storage device with the correction amount when the correction amount is larger than the correction amount stored from the comparison result;
And a step of sending the correction amount to the band-limiting filter coefficient selection unit at a timing when the correction amount of the storage device is updated. The demodulation method according to claim 4, wherein
The complex vector generation step, the difference frequency vector extraction step, and the difference frequency complex vector length calculation step include a step of calculating a complex vector A length at the time of detection of the first f1 signal, a step of storing the calculated value, and a next f2 Calculating a complex vector A length at the time of signal detection, calculating a ratio between the calculated complex vector A length of f2 and the amplitude value of the previously stored f1 signal, and correcting the ratio And storing as a demodulation method. The demodulation method according to claim 5, wherein
After the processing of each step, the ratio of the amplitude value of the f1 signal is calculated in the same way as before for each timing at which the f2 signal is bit-determined, and the previously stored correction amount and the current correction amount are calculated. On the condition that the absolute value of the added value is larger than the absolute value of the previously stored correction amount, the correction amount stored as the sum of the previously stored correction amount and the current correction amount is A demodulation method comprising: updating and sending the updated correction amount to a band-limiting filter coefficient selection unit. In the demodulation method according to any one of claims 4 to 6,
Based on the calculated level correction amount, the processing for updating the coefficient of the band limiting filter is described in ITU recommendation V. This is implemented when two frequencies are separated as in the ITU Recommendation V.23. A demodulation method characterized by omitting implementation when two frequencies are relatively close to each other as in the 21 standard.

Images