JP3931071B2 - Semiconductor device and wireless communication device for data communication control - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a hardware configuration of a communication apparatus (base station, terminal) based on a communication method using an interleaving technique in the process of modulation / demodulation processing. In particular, it is suitable for a communication apparatus used in a code division multiple access (CDMA) type mobile communication system.
[0002]
[Prior art]
Interleaving is a technology that reduces the influence of errors that occur in bursts on a transmission path by rearranging the order according to a predetermined pattern when transmitting data, such as mobile communications and Internet communications. It is used in a wide range of communication fields.
[0003]
The interleaving technique is also adopted in a standard established by the international standardization organization 3GPP for wideband code multiple access (W-CDMA) mobile communication systems. A conventional RAM configuration based on the 3GPP standard is shown in FIG. 1, and an interleaving conceptual diagram and an explanation of the effect of error correction are shown in FIG.
[0004]
The 3GPP standard interleaving is characterized in that data is rearranged in a long cycle of up to 80 ms while the normal transmission frame unit is 10 ms. In order to change the data transmission order, the data sent from the data creator is once spooled in the RAM area 001. When writing to the RAM area 001, the addresses are incremented in the order of 1, 2, 3,. Here, as shown in FIG. 2, writing is performed by considering 30 rows as one row. When 80 ms is collected, the read address is changed to 1 , 3 1 , 6 1, ..., Data is read every 30 (in the column direction), and copied to another RAM area 002. The order of columns to be read is changed randomly with reference to a predetermined pattern.
[0005]
If the data order is changed in this way and transmitted, even if many errors occur locally due to noise or the like on the transmission line as shown in FIG. 2, if the data is rearranged based on the data order on the receiving side (this Is called de-interleaving processing), and error locations are distributed, so that the effect of error correction codes is easily exhibited. For example, when a rate 1/3 convolutional code is used, the information of the original data is stretched to 3 pieces of data, so that if all 3 pieces of errors occur, decoding becomes impossible, but 1 of 3 pieces If the error is up to a certain level, it can be repaired with high accuracy.
[0006]
[Problems to be solved by the invention]
While performing the interleaving process as described above, in order to continue transmission even during the process, it is necessary to prepare an area 003 for holding data currently being transmitted, in addition to the interleaving RAM area. In the deinterleaving process on the receiving side, as shown in FIG. 10, the received data is first written in the RAM area 001. When data is accumulated for the deinterleave unit, the next is written in the RAM area 003. While writing to the RAM area 003, deinterleaving is performed on the data in the RAM area 001, and the result is written to the RAM area 001. Therefore, since the same RAM configuration as that on the transmission side is necessary on the reception side, both the transmission system and the reception system require a RAM area of 80 ms × 3 planes. Specifically, when the RAM capacity is estimated, in the transmission interleave processing, the data before spreading processing is 1 bit wide, so when transmitting at a rate of 384 kbit / s, 384 kbit / s × 3 times (turbo coding rate) ) × 80 ms × 3 planes = about 300 kbit RAM is required. In the deinterleaving process of the receiving system, the data after the soft decision is processed. Since the data after the soft decision has a multi-bit width, if the bit width is 4 bits, 1.2 Mbit, which is four times that of the transmission system, is required. Since the combined transmission / reception system is very large at 1.5 Mbit, if an interleave / deinterleave processing RAM is built in an LSI, its capacity is large as described above, and the proportion of the entire chip area increases. It was a major obstacle to size reduction.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention focuses on the fact that the operating frequency (about 20 MHz to 150 MHz) of the baseband processing unit is sufficiently faster than the data transmission / reception rate (usually about 15 kHz to 384 kHz in W-CDMA). The RAM capacity is reduced by dividing the interleave RAM into a plurality of areas and using the common area on the read side and the write side in a time-sharing manner. By adopting the same configuration in the deinterleaving process, the RAM capacity on both the transmission side and the reception side is reduced.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Examples of the present invention will be described below.
[0009]
In the conventional example of FIG. 1, when the interleave processing unit is 80 ms, when the last 10 ms of data in 80 ms is being read, 70 ms of RAM area 003 has already been read. In this embodiment, paying attention to this point, as shown in FIG. 3, the RAM area 003 is divided into 70 ms (RAM area 004 in FIG. 3) and 10 ms (RAM area 006 in FIG. 3). Is 10 ms. That is, in this embodiment, when the number of data included in one transmission / reception frame is one unit, the RAM area 004, the RAM area 005, and the RAM area 006 are configured by the number of words that is an integral multiple of that unit.
[0010]
FIG. 4 shows the timing for performing the interleaving process and the selection state of the RAM. Of the 80 ms of the interleave processing unit, the next data is interleaved in the last 10 ms (section 401 in the figure), and the reading side uses 10 ms (RAM area 006 in FIG. 3), and the interleaving process side In this case, a total of 80 ms of 70 ms (RAM area 004 in FIG. 3) and another 10 ms (RAM area 005 in FIG. 3) are used. When the RAM area 006 has been read (section 402 in the figure), the read side selects the RAM area 004 and accesses the next 70 ms of data. Meanwhile, the interleaving process is not performed, and the RAM writing is stopped. In the last 10 ms of the next processing unit (section 403 in the figure), the reading side selects the RAM area 005 and the interleaving processing side writes data into the RAM area 004 and RAM area 006.
[0011]
By writing data while alternately changing the combination in this way, the RAM area which conventionally required 80 ms × 3 planes is reduced by about 30%.
[0012]
The RAM area 004, RAM area 005 and RAM area 006 may be constructed on different semiconductor chips, or these areas may be constructed on one semiconductor chip.
[0013]
Next, an embodiment of the deinterleaving side of the present invention will be shown. FIG. 11 shows the configuration of the embodiment, and FIG. In this embodiment, the data received from the RF unit is written in the RAM area 015 for the first 10 ms (section 411 in FIG. 12), and the next 70 ms (section 412 in FIG. 12) is written in the RAM area 014. Further, in the next 10 ms (section 413 in FIG. 12), de-interleave processing is performed on the data of a total of 80 ms stored in the RAM areas 015 and 014 while writing to the RAM area 016, and the result is written to the RAM area 011. . In the next 70 ms (section 414 in FIG. 12), the data is written in the RAM area 014, and in the next 10 ms (section 415 in FIG. 12), the data is written in the RAM area 015 and stored in the RAM areas 016 and 014. The data is deinterleaved and the result is written in the RAM area 011. By writing data while alternately changing the combinations in this way, the RAM area that conventionally required 80 ms × 3 planes in the deinterleave RAM is reduced by about 30%.
[ 0014 ]
The RAM area 014, the RAM area 015, and the RAM area 016 may be constructed on different semiconductor chips, or these areas may be constructed on one semiconductor chip. As described above, the deinterleaving RAM is often multi-bit after the soft decision processing and has a large RAM capacity. Since the proportion of the total area of the semiconductor chip is large, if these RAMs are constructed on different semiconductor chips as external memories, the area of the semiconductor chip can be reduced. By using existing components for the external memory, the area of a semiconductor chip (custom ASIC) dedicated to baseband processing, which is expensive to manufacture, can be reduced, yield can be improved, and overall cost can be reduced.
[0015]
FIG. 5 shows another embodiment of the present invention. The interleave processing unit is 80 ms as in the first embodiment, but the ratio of dividing the RAM area is changed from 70 ms: 10 ms to 40 ms: 40 ms. That is, in this embodiment, the RAM area 204 and the RAM area 205 are each 40 ms worth. The RAM area 201 may be the same as the RAM area 001 described in FIG. The RAM area 206 may be 40 ms. As described above, in the configuration in which the division ratio is almost equal, the reduction rate of the RAM capacity is reduced to about 16%. However, as shown in FIG. 6, the time for performing the interleaving process can be made longer than that in the first embodiment. Therefore, even if the operating frequency of the circuit that performs the interleaving process is about 2 to 3 times the data transmission rate, the present invention can be employed to reduce the RAM capacity.
[0016]
In the deinterleaving process, the RAM capacity can be reduced with the same configuration. FIG. 13 shows the configuration of the above-described embodiment when performing the deinterleaving process, and FIG. 14 shows the timing for performing the deinterleaving process and the selection state of the RAM.
[0017]
One of the points of the above-described embodiment is that when the interleaved data is written to the combination of the first RAM area and the second RAM area, and the next interleaved data is written, the first RAM area and the second RAM area are written. 3 is written in combination with the RAM area, and this is repeated alternately. The ratio of the amount of data that can be written to the first RAM area and the amount of data that can be written to the second RAM area may be set according to the ratio between the data transmission / reception rate and the operating frequency of the circuit that performs the interleaving process.
[0018]
FIG. 7 shows another embodiment of the present invention. In this embodiment, the interleave unit is an integral multiple of the transmission frame unit. The RAM area 301 may be the same as the RAM area 001 described in FIG. The RAM area 304, RAM area 305, and RAM area 306 are the same as the RAM area 004, RAM area 005, and RAM area 006 shown in FIG. 3, or the RAM area 204, RAM area 205, and RAM area 206 shown in FIG. is there.
[0019]
The selectors 308 and 309 select a RAM area. The selectors 308 and 309 select a RAM area according to the RAM switching signal output from the switching period counter 307. A transmission frame timing signal is input to the switching period counter 307. The switching cycle counter 307 generates a RAM switching signal by a counter that counts in a frame cycle. For example, assuming that the RAM period 304, the RAM area 305, and the RAM area 306 are the same as the RAM area 004, RAM 005, and RAM area 006 shown in FIG. Data for 10 ms and 10 ms are stored. Since they are an integral multiple of the transmission frame unit, the selector switching operation can be controlled by a RAM switching signal generated by a counter that counts in the frame period.
[0020]
The RAM area can also be selected by specifying the upper bits of the RAM read or write address. For example, if the RAM area 304 in FIG. 7 is 1024 words, the RAM area 305 is 512 words, and the RAM area 306 is also 512 words, the address of each RAM can be specified within 10 bits. Here, the address width may be expanded by 2 bits so that the RAM area to be selected is designated by the 11th and 12th bits.
[0021]
FIG. 15 shows an embodiment of a deinterleaver. The operations of the selectors 318 and 319 and the switching cycle counter 317 are the same as those of the selectors 308 and 309 and the switching cycle counter 307 in FIG.
[0022]
Examples of systems in which the above-described interleaving / deinterleaving scheme is used include mobile terminals and base stations. Hereinafter, configurations of the mobile terminal and the base station will be described.
[0023]
The configuration of a mobile terminal used in a CDMA mobile communication system according to the present invention will be described with reference to FIG. The received signal of the carrier frequency received from the antenna 808 is lowered in frequency by the radio unit 801, and the received signal of the baseband band is transmitted to the cell search unit 805 and the receiving unit 804 in the baseband processing unit 809 via the radio interface unit 802. Is input. The cell search unit 805 performs supplementary initial synchronization when power is turned on, and supplementary synchronization of other base station signals when the communication area changes due to movement and the base station to be communicated is switched (handover). The receiving unit 804 performs despreading, detection, RAKE combining, deinterleaving, and error correction of received data. The decoded transmission signal is output via the user interface unit 807 and used for the subsequent processing. A transmission signal to be transmitted to the base station is input to the transmission unit 803 via the user interface unit 807. The transmission unit 803 performs transmission signal encoding, interleaving, transmission format configuration, and spreading. The control unit 806 performs setting of initial values and timing management for each unit using a CPU or DSP.
[0024]
The above-described interleaving method is used in the interleaver 810 in the baseband processing unit 809, and the above-described deinterleaving method is used in the deinterleaver 811 in the baseband processing unit 809. The baseband processing unit 809 can be realized by one LSI.
In this case, the memory in which the above-described RAM area is constructed may be provided inside the LSI, or only the memory may be externally attached.
[0025]
Next, the configuration of a base station used in a CDMA mobile communication system will be described with reference to FIG. The reception signal in the carrier frequency band received from the antenna 900 is converted into a baseband reception signal in the radio unit 901 and input to the baseband processing unit 902. In the baseband processing unit 902, modulation / demodulation processing units 903-1 to 90-s that perform transmission / reception processing of one channel are prepared for the number of channels (s) used in the base station. One matched filter (MF) 904 and one peak detector 905 are provided for a plurality of channels, and the signal reception timing (path) is intermittently searched for each channel. The peak detection unit 905 selects a larger one of the peaks of the path correlation values output from the MF. The selected paths are set in the correlation calculation units 906-1 to 906-1 to n (n is the number of fingers) of the modulation / demodulation processing units 903-1 to 90s of the corresponding channels, respectively, and despreading processing is performed for each finger. The despread results are combined in phase by the detectors 907-1 to 907 -n and then combined by the RAKE combiner 908. The combined data is demodulated by a deinterleaver 909, an error correction decoder 910, and an error detection decoder 911, and output to the network side. On the other hand, transmission data input from the network side is encoded by an error detection encoder 912, an error correction encoder 913, and an interleaver 914. Thereafter, the transmission format generator 915 generates a transmission format together with a control signal such as a pilot signal, spreads it by a spread calculation unit 916, and adjusts the power ratio with other channels by a transmission power control unit 917. The baseband transmission signal of each channel output from the baseband unit 902 is superimposed in the output combining unit 918, converted into a carrier frequency band transmission signal in the radio unit 901, and transmitted from the antenna 900.
[0026]
The interleaving method described above is used by the interleaver 914 in the baseband processing unit 902. The deinterleaving method described above is used by the deinterleaver 909 in the baseband processing unit 902. The baseband processing unit 902 can be realized by one LSI. In this case, the memory in which the above-described RAM area is constructed may be provided inside the LSI, or only the memory may be externally attached.
[0027]
【The invention's effect】
The interleaving / deinterleaving RAM, which occupies a large proportion of the baseband area, is divided into multiple areas, and the RAM area is reduced by using the common area on the read side and write side in a time-sharing manner. The manufacturing cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of a conventional interleave RAM.
FIG. 2 is a diagram for explaining the contents of interleaving processing defined by the 3GPP standard and the effects thereof.
FIG. 3 is a diagram showing a configuration of an interleave RAM according to the present invention.
4 is a diagram for explaining interleaving process scheduling and a RAM selection method in the interleave RAM configuration of FIG. 3; FIG.
FIG. 5 is a diagram showing a configuration example of another interleave RAM of the present invention.
6 is a diagram for explaining scheduling of an interleave process and a RAM selection method in the interleave RAM configuration of FIG. 5. FIG.
FIG. 7 is a diagram showing a configuration example of another interleave RAM of the present invention.
FIG. 8 is a diagram illustrating a configuration of a mobile terminal used in a CDMA mobile communication system.
FIG. 9 is a diagram illustrating a configuration of a base station used in a CDMA mobile communication system.
FIG. 10 is a diagram illustrating a configuration example of a conventional interleave RAM.
FIG. 11 is a diagram showing a configuration of a deinterleave RAM according to the present invention.
12 is a diagram for explaining a deinterleave process scheduling and a RAM selection method in the interleave RAM configuration of FIG. 11; FIG.
FIG. 13 is a diagram showing a configuration example of another interleave RAM of the present invention.
14 is a diagram for explaining interleaving process scheduling and a RAM selection method in the interleave RAM configuration of FIG. 13;
FIG. 15 is a diagram showing a configuration example of another interleave RAM of the present invention.
[Explanation of symbols]
001, 201, 301 ... Data RAM area before interleaving, 002, 003, 004, 005, 006, 204, 205, 206, 304.305, 306 ... Data RAM area after interleaving, 401, 403, 601, 603 ... interleave processing section, 402,602 ... transmission data reading (interleave processing pause) section, 307 ... RAM selection switching period counter, 308,309 ... RAM selection selector, 011, 211, 311 ... Data RAM area after deinterleaving, 012, 013, 014, 015, 016, 214, 215, 216, 314.315, 316 ... Data RAM area before deinterleaving, 413, 415, 613, 615 ... deinterleave processing section, 411, 12,414,611,612,614 ... received data write (deinterleaving pause) interval, 317 ... RAM selection switching cycle counter, 318, 319 ... RAM selected selector. 801, 901 ... wireless unit, 802 ... wireless interface unit, 803 ... transmitting unit, 804 ... receiving unit, 805 ... cell search unit, 806 ... control unit, 807 ... User interface unit, 809, 902 ... baseband processing unit, 808, 900 ... antenna, 903-1 to s ... modulation / demodulation processing unit, 906-1 to n ... correlation calculation unit, 907-1 ˜n ... detection unit, 908 ... Rake combining unit, 909 ... deinterleaver, 910 ... error correction decoder, 911 ... error detection decoder, 912 ... error detection encoder, 913 ... Error correction encoder, 914 ... Interleaver, 915 ... Transmission format generator, 916 ... Spreading calculation unit, 917 ... Transmission power control unit, 918 ... Transmission output combining unit.

Claims (15)

A semiconductor device that performs data interleaving or deinterleaving,
Memory,
Control circuit,
The control circuit divides the first data for the processing unit of the interleaving process or the deinterleaving process into at least first and second partial data, and writes the first partial data to the first area of the memory The second partial data is written to the second area of the memory, the first partial data is read from the first area for the interleaving process or the deinterleaving process, and the interleaving process for the processing unit is performed. Alternatively, the first memory area is released before the end of the deinterleaving process, and the next interleaving process or deinterleaving process of the first data is performed in the released first memory area and third memory area. A semiconductor device in which second data for a unit is divided and written . The semiconductor device according to claim 1,
The partial data obtained by dividing the second data is written into the first memory area before the second partial data is read from the second memory area. The semiconductor device according to claim 1,
The semiconductor device, wherein the first memory area has a larger memory capacity than the second memory area. The semiconductor device according to claim 1,
The semiconductor device, wherein the first memory area and the second memory area have the same memory capacity. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first memory area is selected in accordance with a frame timing signal or an address signal. A wireless communication device,
An antenna for transmitting and receiving data;
A baseband processing unit,
The baseband processing unit
An interleaving circuit that performs interleaving processing on transmission data;
A transmitter for transmitting the transmission data subjected to the interleaving process,
The interleaving circuit divides first data for a processing unit of interleaving processing into at least first and second partial data, and writes the first partial data in a first area of a memory for interleaving processing, The second partial data is written to the second area of the memory, the first partial data is read from the first area for the interleaving process, and the interleaving process for the processing unit is completed before the end of the interleaving process. The first memory area is released, and the second data corresponding to the processing unit of the next interleaving process of the first data is divided and written in the released first memory area and third memory area. A wireless communication device. The wireless communication device according to claim 6 ,
The partial data obtained by dividing the second data is written to the third memory area before the second partial data is read from the second memory area. The wireless communication device according to claim 6 ,
The wireless communication apparatus, wherein the first memory area has a memory capacity larger than that of the second memory area. The wireless communication device according to claim 6 ,
The wireless communication apparatus, wherein the first memory area is selected according to a frame timing signal or an address signal. The wireless communication apparatus according to claim 6, wherein an operating frequency of the baseband processing unit is higher than a transmission rate of data transmitted by the antenna. A wireless communication device,
An antenna for transmitting and receiving data;
A baseband processing unit,
The baseband processing unit
A receiver for receiving data;
A deinterleaving circuit that performs a deinterleaving process on the received data,
The deinterleaving circuit divides first data for a deinterleaving processing unit into at least first and second partial data, and the first partial data is a first area of a memory for deinterleaving processing. , Write the second partial data to the second area of the memory, read the first partial data from the first area for the deinterleaving process, and perform the deinterleaving process for the processing unit. The first memory area is released before the end of the first data area, and the second data corresponding to the processing unit of the deinterleaving process next to the first data is released to the released first memory area and third memory area. A wireless communication device characterized by dividing and writing . The wireless communication apparatus according to claim 11 , wherein
The partial data obtained by dividing the second data is written to the third memory area before the second partial data is read from the second memory area. The wireless communication apparatus according to claim 11 , wherein
The wireless communication apparatus, wherein the first memory area has a memory capacity larger than that of the second memory area. The communication device according to claim 11 ,
The communication device, wherein the first memory area is selected according to a frame timing signal or an address signal. 12. The wireless communication apparatus according to claim 11, wherein an operating frequency of the baseband processing unit is higher than a transmission rate of data transmitted by the antenna.

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