JP3923563B2 - Disk cache system and disk cache method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a disk cache system that employs a write-back method, and relates to a disk cache system and a disk cache method that are suitable for protecting write-back cache data.
[0002]
[Prior art]
In a computer system, a disk cache is used to improve an effective access speed to an external connection device such as a hard disk device. By using the disk cache, the recently accessed disk block data is stored in a memory that can be accessed at high speed, and if the next requested data is stored in the memory, the data is immediately accessed without actually accessing the disk. Can be transferred.
[0003]
In recent years, a disk controller that employs a write-back method as a disk cache sometimes uses a nonvolatile memory in addition to the disk cache memory and stores data in the nonvolatile memory. By using a detachable non-volatile memory together, for example, when a failure occurs in the disk controller, the maintenance can be restored by attaching the non-volatile memory to a normal disk controller and replacing it. It becomes possible.
[0004]
As an affordable non-volatile memory for achieving these purposes, there is an SRAM card of JEIDA (Japan Electronic Industry Development Assosiation) (PCMCIA (Personal Computer Memory Card Interface)) standard. A cache system was sometimes configured.
[0005]
[Problems to be solved by the invention]
As described above, in the conventional disk cache system, the SRAM card is used as the nonvolatile memory in combination with the disk cache memory.
However, in the above-described prior art, a general JEIDA (PCMCIA) standard SRAM card does not have a parity bit, so that the reliability of stored data is insufficient for some system requirements. .
[0006]
In addition, regarding the battery life of the SRAM card, a signal to that effect is output when the replacement time is approaching due to voltage monitoring. By monitoring this signal, the write back operation is prohibited when the battery runs out. Data protection is possible. However, since there is no signal to know the remaining battery time before that, it is difficult to know when to replace the battery, and in an operation mode that has a regular maintenance period that is performed only once every several months, the regular maintenance period During this period, the battery runs out, and the operation in a performance degradation state where the write-back operation is prohibited may be forced.
[0007]
In addition, in a write-back type cache system using an SRAM card, it is assumed that a failure handling function is incorporated in the controller. However, the SRAM card itself does not have any function for this purpose. There has been a problem that erroneous data may be written in the apparatus and the original data may be destroyed due to an error of a worker who performs the work.
[0008]
The present invention has been made to solve the above-described problem, and is a disk cache capable of improving the reliability of data stored in a nonvolatile memory used in combination with a cache memory in the disk cache and ensuring protection. It is an object to provide a system and a disk cache method.
[0009]
[Means for Solving the Problems]
  The present invention relates to a disk cache system that employs a write-back method as a writing method for a disk device to be cached. The internal area is managed as a block, and a non-volatile data in which a write request to the disk device is written using a block as a basic unit. And the normal data to be written to the non-volatile storage means and the predetermined diagnostic data for at least one block used for determining the normality of the data transfer, and for each block, A data transfer unit that generates a check code based on data to be written to the block and writes the check code to the nonvolatile storage unit, and a check code based on the diagnostic data transferred by the data transfer unit corresponds to the predetermined diagnostic data Check code and And determining diagnostic data determining means for determining correct or not in, characterized by comprising a control means for inhibiting normal operation when it is determined that there is abnormal by the data determining unit.
[0010]
  By adding a check code to the data in units of blocks to enable the validity check, it is possible to check even non-volatile storage means that does not have a parity check function, ie, JEIDA / PCMCIA standard SRAM cards. Only by requiring a relatively small memory capacity for the code, the normality of the data stored in the SRAM card can be checked and the reliability can be improved.
  By adding predetermined diagnostic data to normal transfer data and transferring it, the check code generated for the diagnostic data is already known. Diagnosis during normal operation is possible, and the reliability of data stored in the nonvolatile storage means (SRAM card) can be improved.
[0013]
  Also,An apparatus for specifying a disk device connected to the system with respect to an area different from an area for data transfer to the disk apparatus provided in the nonvolatile storage means and a specific area of the disk device connected to the system A first writing means for writing information, device information stored in the non-volatile storage means by the first writing means at the appropriate time, and a specific area of the disk device actually connected to the system at this time It further comprises device determination means for comparing the written device information with each other to determine whether or not the connected disk device is correct, and the control means is determined to be abnormal by the device determination means. In this case, normal operation is prohibited.
[0014]
As a result, for example, when a system failure occurs, the disk device is removed for the purpose of pursuing the cause and the wrong disk device is connected at the time of restart, or the nonvolatile storage means to be used Even if there is a mistake, the disk device actually connected to the system is made consistent between the nonvolatile storage means and the device information to be written in the disk device (for example, there is consistency between both stored at the time of cache system initialization). Since the legitimacy can be determined from the serial number of the connection device, there is no possibility of destroying data due to incorrect operation.
[0015]
  Also,An apparatus for specifying a disk device connected to the system with respect to an area different from an area for data transfer to the disk apparatus provided in the nonvolatile storage means and a specific area of the disk device connected to the system A first writing means for writing information, device information stored in the non-volatile storage means by the first writing means at the appropriate time, and a specific area of the disk device actually connected to the system at this time It further comprises device determination means for comparing the written device information with each other to determine whether or not the connected disk device is correct, and the control means is determined to be abnormal by the device determination means. In this case, normal operation is prohibited.
[0016]
As a result, it is clearly determined that the data stored in the nonvolatile storage means (SRAM card) should not be used from information (for example, cache system initialization date and time) that can determine whether the data is new or old. Even if an incorrect SRAM card is connected during recovery after occurrence, data destruction can be avoided.
[0017]
  Also,A battery for backing up data written in the nonvolatile storage means, a writing means for writing a replacement date when the battery is replaced in a predetermined area in the nonvolatile storage means, and the nonvolatile storage by the writing means It further comprises reading means for reading and presenting an exchange date written in a predetermined area of the means.
[0018]
This makes it easy to determine the remaining battery life of the non-volatile storage means (SRAM card) whose data is backed up by the battery. For example, when an operation mode in which periodic maintenance is performed is adopted, the battery life is reached by the next maintenance period. It can be clearly determined that the battery will run out, and measures such as replacing the battery in advance can be taken. Therefore, the data stored in the nonvolatile storage means (SRAM card) can be reliably protected.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a computer system having a disk cache system according to the present embodiment. The disk cache system in the present embodiment employs a write back method as a write method.
[0020]
As shown in FIG. 1, the computer system comprises a host system 10, a disk controller 12, and a hard disk device 14 (hard disk devices (HDD0 to HDDn) 14-0 to 14-n). The host system 10 and the disk controller 12 are connected via a connection connector 16. The connection connector 16 corresponds to, for example, a PCI bus.
[0021]
The host system 10 includes a CPU 20, a CPU local memory 22, an external circuit connection bus conversion circuit 24, and the like.
The CPU 20 controls the entire system and operates based on programs and data stored in the CPU local memory 22. In this embodiment, the CPU 20 manages a diagnosis request command for checking the normality of data stored in an SRAM card 38 (described later) in the disk controller 12 at regular time intervals and when an idle state is entered. Issue to mechanism 44. Further, the CPU 20 issues a command for reading the battery replacement date / time data of the SRAM card 38 in the disk controller 12 to the data management mechanism 44.
[0022]
The CPU local memory 22 is a memory accessed by the CPU 20 and stores various data in addition to an OS (operating system) and application programs that define the operation of the CPU 20. The CPU local memory 22 includes diagnostic data for checking whether data transfer from the host system 10 to the disk controller 12 has been normally performed. In the present embodiment, two types of diagnostic data A and B are prepared.
[0023]
The external circuit connection bus conversion circuit 24 is an interface for inputting / outputting data and commands to / from an external circuit, and data between the CPU local memory 22 and the disk cache memory 36 of the disk controller 12 and the hard disk device 14. And a command path for inputting and outputting commands between the CPU 20 and the CPU 30 of the disk controller 12 are provided. The external circuit connection bus conversion circuit 24 is connected to the disk controller 12 via the connection connector 16.
[0024]
The disk controller 12 controls access from the host system 10 to the hard disk device 14, and includes a CPU 30, F / W (firmware) memory 32, a DMA (Direct Memory Access) controller 34, a disk cache memory 36, and a connector 37. , An SRAM card 38, an external circuit connection bus conversion circuit 40, and a SCSI (Small Computer System Interface) chip 42. The CPU 30 and the F / W memory 32 constitute a data management mechanism 44 to control the function of the disk cache for accessing the hard disk device 14 from the host system 10.
[0025]
The CPU 30 controls the disk controller 12 and controls access from the host system 10 to the hard disk device 14 based on a program stored in the F / W memory 32.
[0026]
The F / W memory 32 stores a program that defines the operation of the CPU 30, and includes a program that realizes access control from the host system 10 to the hard disk device 14 and a disk cache function.
[0027]
The DMA controller 34 (data transfer means) controls access to the disk cache memory 36 and the SRAM card 38 under the control of the data management mechanism 44 (CPU 30). Data is input / output from / to the SCSI chip 42. Further, the DMA controller 34 generates a check code based on the block data when writing each block data to the SRAM card 38 (data area), and also writes this check code to the SRAM card 38 (check code area). Further, the DMA controller 34, under the control of the data management mechanism 44, supplies one or more blocks of diagnostic data (in this embodiment, two blocks of diagnostic data A and B) in addition to normal transfer data when writing data. Write to the SRAM card 38 (diagnosis data area). In this embodiment, a block having 256 bytes as a basic unit of transfer is used.
[0028]
The data management mechanism 44 (control means, writing means) controls the writing of data written from the host system 10 to the disk cache memory 36 and the SRAM card 38, accesses to the hard disk device 14, and faults in the power supply and controller. It has a function of performing data recovery at the time of occurrence (restoration of data stored in the disk cache memory 36).
[0029]
In addition, the data management mechanism 44 in the present embodiment, in addition to various checks including a check of the normality of the data stored in the SRAM card 38 at startup (apparatus determination means), according to a command from the host system 10, Check normality of data transfer using diagnostic data when receiving a write command (diagnosis data determination means), and check normality using a check command for data stored in the SRAM card 38 when receiving a diagnosis request command (data determination) Means) and the like.
[0030]
The disk cache memory 36 is a memory used in the function of the disk cache, and is configured by a DRAM, for example.
The connector 37 is used to connect the SRAM card 38, and is configured according to specifications conforming to, for example, JEIDA (Japan Electronic Industry Development Assosiation) (PCMCIA (Personal Computer Memory Card Interface)) standard.
[0031]
The SRAM card 38 (nonvolatile storage means) is a storage medium that can be removed from the system by the connector 37 and is used for data writing from the host system 10. The SRAM card 38 has a configuration in which a battery for data backup is provided, and is used as a high-speed nonvolatile storage medium that can retain stored data even when it is removed from the system.
[0032]
The external circuit connection bus conversion circuit 40 is an interface for inputting / outputting data and commands to / from an external circuit, and data between the disk cache memory 36 and the hard disk device 14 and the CPU local memory 22 of the host system 10. And a command path for inputting and outputting commands between the CPU 30 and the CPU 20 of the host system 10 are provided. The external circuit connection bus conversion circuit 40 is connected to the host system 10 via the connection connector 16.
[0033]
The SCSI chip 42 is an interface for connecting the hard disk device 14.
The hard disk device 14 is used for storing data, programs, and the like. In addition to a disk area (hereinafter referred to as a user area) to be used for normal use, a serial number set for each apparatus. And a dedicated disk area (hereinafter referred to as a controller area) for storing the initialization date and time of the cache system. In the present embodiment, it is assumed that a plurality (n) of hard disk devices 14-0 to 14-n (HDD0 to HDDn) are connected.
[0034]
Next, the operation in this embodiment will be described.
First, the basic operation of data write processing (write command processing) from the host system 10 will be described with reference to the flowchart shown in FIG. FIG. 3 is a diagram for explaining an outline of processing for instructions and data from the host system 10.
[0035]
In the present embodiment, when a write command is received in the disk controller 12, a process for determining the normality of data transfer as shown in the flowchart of FIG. 8 is executed together with the process shown in the flowchart of FIG. . Details will be described later.
[0036]
First, when there is a write request (write command) of data stored in the CPU local memory 22 from the CPU 20 of the host system 10 to the hard disk device 14 via a command path, the data management mechanism 44 (CPU 30) of the disk controller 12 Activates write command processing for data obtained via the data path.
[0037]
The data management mechanism 44 checks whether an area for writing data can be acquired for both the disk cache memory 36 and the SRAM card 38 (step S1).
[0038]
If an area for writing data is acquired (step S2), the data management mechanism 44 writes data to both the disk cache memory 36 and the SRAM card 38 (step S3).
[0039]
At this time, the writing to the disk cache memory 36 is performed in accordance with a general write-back method, taking into account the simplicity of the subsequent search processing (during reading and writing) from a plurality of segment-managed areas. A segment is selected and executed.
[0040]
On the other hand, writing of data to the SRAM card 38 is executed by selecting an arbitrary area from the free area. At the same time, from the directory information for the written data, that is, the address indicating the write position (disk area) of the data to the hard disk device 14 and the address indicating the position (memory area) where the data is written to the disk cache memory 36. Write address information.
[0041]
Further, a flag used for processing for guaranteeing the validity of data is added to the directory information (or data). Specifically, when an area for writing data is acquired, a flag is set so as to indicate that a command is being executed, and when data is normally transferred from the host system 10, the flag is set to indicate that the data is valid. Rewrite.
[0042]
The data management mechanism 44 notifies the host system 10 of the end of the write command processing after successfully completing the flag writing.
Note that writing to the SRAM card 38 is performed in a format that allows efficient writing to the disk, regardless of whether an appropriate segment is selected and written to the disk cache memory 36. For example, the write data is continuous data (block data) serving as a data unit (for example, sector unit) when writing to the hard disk device 14.
[0043]
On the other hand, if an area for writing data cannot be acquired in step S2, the data management mechanism 44 writes the requested data to the corresponding area in the user area of the hard disk device 14, and after the writing is completed. The host system 10 is notified of the end of the write command process.
[0044]
When a predetermined state is reached while the write command processing as described above is performed a plurality of times (when idling or when a certain time has elapsed, etc.), it is stored in the disk cache memory 36 according to a normal write-back method. The process of writing the data to the write request address in the user area of the hard disk device 14 is performed.
[0045]
In the present embodiment, the disk controller 12 stores the data in the SRAM card 38 shown in the flowchart of FIG. 9 in response to a diagnosis request issued from the host system 10 when it is idle or when a certain time has elapsed. Processing for determining the normality of the data is executed. Details will be described later.
[0046]
FIG. 4 shows an example of the data form in the SRAM card 38. As shown in FIG. 4, a system area, a data area, and a check code area are provided in the memory space of the SRAM card 38, and data is stored for each block. A diagnostic data area is provided in a part of the data area.
[0047]
In the system area, data indicating the date when the battery for data backup of the SRAM card 38 is replaced (battery replacement date), and HDD serial numbers set in the hard disk devices 14-1 to 14-n (HDD0 to HDDn), respectively. , Data indicating the date and time when the cache system was initialized (cache system initialization date and time), and other cache control information such as directory information. A flag used for processing for guaranteeing the validity of the cache data stored in the data area is added to the directory information.
[0048]
In the data area, a plurality of data (cache data) is stored for each block (in FIG. 4, four cache data are shown). In the data area, two blocks of diagnostic data areas (diagnostic data 1 and 2) are provided.
[0049]
In the check code area, check codes corresponding to the data of each block managed in the system area and the data area are stored. The check code in this embodiment is obtained by performing an XOR (EXCLUSIVE-OR) operation on all data in the corresponding block with an initial value of “0” by the check code generation function of the DMA controller 34 during data transfer. However, since the data stored in the system area is not subject to DMA (Direct Memory Access) by the DMA controller 34, the data management mechanism 44 generates a check code corresponding to the data as needed. It is assumed that it is stored in the check code area of the SRAM card 38.
[0050]
In FIG. 4, the check code corresponding to the system area is “code0”, the check code corresponding to the cache data 0 is “code1”, and the check code corresponding to the diagnostic data 2 is “code6”. An area other than valid data in which no check code is stored in the check code area is an empty area, but it can also be assigned as a system area.
[0051]
Note that the data format shown in FIG. 4 is a simplified data format for the sake of simplicity of description. Actually, the capacity of the SRAM card 38 is about 1 MB or more, and there are thousands of blocks. For this reason, in FIG. 4, the check code area has only one block, but actually, a plurality of blocks corresponding to the check code corresponding to the amount of data stored in the system area and the data area are allocated as the check code area. In the system area, a plurality of blocks are allocated because the cache control information is large in capacity. On the other hand, since the diagnosis data area uses two diagnosis data A and B (details will be described later with reference to FIG. 4) in this embodiment, it consumes 2 blocks (diagnosis data 1 and 2). The ratio of the total capacity may be small.
[0052]
FIG. 5 shows an example of the diagnostic data A and B in the present embodiment. The diagnostic data A and B is a data pattern in which an abnormality can be detected when a certain bit of the data bus can take only a fixed value or is affected by the state of another bit.
[0053]
For example, as shown in FIG. 5A, the diagnostic data A is data in which the check code for the data is “AA” (1 word = 1 byte, hexadecimal notation) as shown in FIG. 5B. It is a pattern. Further, as shown in FIG. 5C, the diagnosis data B is data in which the check code for the data is “55” (1 word = 1 byte, hexadecimal notation) as shown in FIG. 5D. It is a pattern. Diagnostic data A and diagnostic data B, except for data that is “00”, are data in which the value of each bit is different from each other at the same byte position, and the probability of abnormality detection can be improved by using them simultaneously. it can.
[0054]
As shown in FIG. 6, the diagnostic data A and B are transmitted as diagnostic data 1 and 2 alternately with the transfer order changed every time data is transferred from the host system 10. That is, in transfer 1, diagnostic data A is used as diagnostic data 1 and diagnostic data B is used as diagnostic data 2. In transfer 2, diagnostic data B is used as diagnostic data 1 and diagnostic data A is used as diagnostic data 2. Similarly, for transfer 3 and later, the order of diagnostic data A and B is alternately changed as diagnostic data 1 and 2 for each data transfer.
[0055]
Next, the operation for improving the reliability of the data stored in the SRAM card 38 and reliably protecting the SRAM card 38 in this embodiment will be described with reference to the flowchart. The main operation according to the present invention is divided into two types, that is, during start-up processing and during normal operation (when a write command is received and when a diagnosis request is received). The respective processing procedures are shown in FIG. 7, FIG. 8, and FIG. ing.
[0056]
However, although not specifically shown in the flowchart, in order to implement the present invention, initialization processing of the cache system is necessary. In the initialization process of the cache system, the data management mechanism 44 determines the serial number, initialization date and time of each connection device (hard disk device 14-0 to 14-n) connected via the SCSI chip 42 at the time of initialization. Is stored in the system area of the SRAM card 38, and the serial number and the initialization date / time are written in the controller area of the hard disk devices 14-0 to 14-n, and the data in the SRAM card 38 and the data in the connection device are written. Keep them consistent. The initialization date / time data may be acquired from the host system 10 or may be generated by the data management mechanism 44.
[0057]
When the battery of the SRAM card 38 is replaced, it is necessary to write the replacement date in the system area on the SRAM card 38 in the same manner. For example, after the battery is replaced, the host system 10 executes the management program of the disk controller 12 and issues a command for writing the data indicating the battery replacement date to the SRAM card 38. Data indicating the battery replacement date is stored in 38 system areas.
[0058]
The data of the battery replacement date stored in the SRAM card 38 is, for example, the data management mechanism 44 when the host system 10 executes the management program for the SRAM card 38 and requests the battery replacement date to be displayed. Read out. The host system 10 displays the battery replacement date based on the battery replacement date data read by the data management mechanism 44.
[0059]
That is, by providing a function that can display the battery replacement date from the data stored in the system area of the SRAM card 38 in response to a request at an arbitrary time, the person who acquired the information can change the battery replacement date and the battery The remaining period can be accurately determined by comparing the lifetime (usually 1 or 2 years).
[0060]
Next, the operation when starting up the data management mechanism 44 will be described with reference to FIG.
In a cache system using the write-back method, if data cannot be written to the hard disk device 14 during normal operation (due to a power failure, controller failure, etc.), the data management mechanism 44 uses the SRAM card at the next startup. An attempt is made to execute a process for writing the data stored in the hard disk device 14 to the hard disk device 14.
[0061]
In the present invention, in order to ensure the reliability of data at this time, various checks are performed as shown in the flowchart of FIG.
First, the data management mechanism 44 determines the normality of the check code for each of all blocks on the SRAM card 38 (step A1). The data management mechanism 44 generates a check code from the data stored in each block stored in the system area and the data area of the SRAM card 38 (by XOR operation), and the target block already stored in the check code area Each check code corresponding to is compared to check whether it is the same. When power is cut off during data transfer, fraud occurs in one block of the system area / data area, but the block is regarded as valid.
[0062]
As a result of the check code comparison, if it can be determined that the data is not normal (step A2), the data management mechanism 44 notifies the host system 10 of the illegality of the data stored in the SRAM card 38 and stops ( Step A3). In response to the notification from the data management mechanism 44, the host system 10 displays a message indicating that the data stored in the SRAM card 38 is informed on a display device (not shown).
[0063]
If the data in the SRAM card 38 is invalid, the SRAM card 38 is inspected in the human system. Data can be prevented from being destroyed by appropriate measures taken by workers.
[0064]
On the other hand, if it is determined that the normality is determined by the check code, the data management mechanism 44 indicates the validity of the data added to the directory information in the cache control information written in the system area of the SRAM card 38. With reference to the flag, the presence or absence of data (write back data) to be discharged to the hard disk device 14 is checked (step A4). If there is no write-back data (step A5), the data management mechanism 44 ends the start-up process (step A6).
[0065]
When write-back data exists, the data management mechanism 44 checks the HDD serial number in the system area on the SRAM card 38 and actually connects the hard disk devices 14-0 to 14-n (HDD0 to HDDn). ) Is determined (step A7). That is, the data management mechanism 44 uses the serial number written in the system area of the SRAM card 38 and the serial number stored in the controller area of the hard disk devices 14-0 to 14-n during the initialization process of the cache system. To determine whether the serial numbers match.
[0066]
As a result, when the serial numbers do not match and it is determined that the current connection device is not valid (step A8), the data management mechanism 44 notifies the host system 10 of the connection device abnormality. (Step A9). In response to the notification from the data management mechanism 44, the host system 10 displays on the display device (not shown) that the connection device abnormality is notified.
[0067]
If there is an abnormality in the connection device, check whether the SRAM card 38 used in the human system is correct and check whether the connection device (hard disk device 14) currently connected is correct. Is done.
[0068]
On the other hand, if the connected hard disk device 14 is valid, the data management mechanism 44 sends the cache system initialization date and time (time stamp) written in the system area on the SRAM card 38 and the hard disk devices 14-0 to 14- The initialization date and time (connection device time stamp) stored in the n controller area is compared to determine whether or not the initialization date and time match (step A10).
[0069]
As a result, when the initialization date and time do not match and it is determined that the data stored in the SRAM card 38 is not valid, for example, when the data is old (step A11), the data management mechanism 44 determines that the host system 10 In response to this, the time stamp abnormality is notified and stopped (step A12). In response to the notification from the data management mechanism 44, the host system 10 causes a display device (not shown) to display a notification that a time stamp abnormality has been notified.
[0070]
When there is a time stamp abnormality, an inspection is performed to determine whether the SRAM card 38 used in the human system is correct.
On the other hand, if the initialization date written in the SRAM card 38 being used is valid, the data management mechanism 44 remains in the data area based on the cache control information (directory information, etc.) in the system area. The write-back cache operation is completed by discharging the valid data to the hard disk device 14 (step A13).
[0071]
Thus, when the data management mechanism 44 is started up, the data written in the SRAM card 38, that is, the check code written in the check code area and the cache system initialization date / time written in the system area are used. Data normality can be checked.
[0072]
In addition, since the battery replacement date and time can be written in the system area of the SRAM card 38 and arbitrarily read out and displayed, operation in a performance deterioration state in which the battery is inadvertently run out and the write back operation is prohibited. Can be avoided.
[0073]
Next, the operation at the time of receiving a write command during normal operation will be described with reference to the flowchart shown in FIG.
When there is a write request (write command) to the hard disk device 14 for data stored in the CPU local memory 22 from the host system 10 via the command path, the data management mechanism 44 sends a normal request to the DMA controller 34. It is set to transfer diagnostic data after data transfer (step B1).
[0074]
The DMA controller 34 transfers 256-byte block data under the control of the data management mechanism 44, and generates a check code by an XOR operation for each block of data transfer by the check code generation function. Is written in the check code area (step B2).
[0075]
Two diagnostic data 1 and 2 are transferred after normal data transfer, and a check code is generated in the same way for the diagnostic data 1 and 2. The data management mechanism 44 checks the check code for the diagnostic data 1 and 2 to determine the normality of the data transfer (step B3).
[0076]
That is, as described with reference to FIG. 6, the diagnosis data A and the diagnosis data B are alternately transferred as the diagnosis data 1 and 2 every time the data is transferred. Accordingly, it is already known whether the value of the check code for the diagnostic data 1 and 2 when the data transfer is normally performed is “AA” or “55” (see FIG. 5).
[0077]
The data management mechanism 44 reads the check code corresponding to the two diagnostic data 1 and 2 from the check code area of the SRAM card 38 and compares the check code with a known check code to determine normality.
[0078]
If the check code for the diagnostic data 1 and 2 is the same as the value of the valid check code, the data management mechanism 44 provides the entire system including the check code generation function of the DMA controller 34, all bits of the data bus, address lines, etc. The normal operation over the entire data transfer system is determined to be normal, and the process is terminated (step B4).
[0079]
On the other hand, when the check codes for the diagnostic data do not match and it is determined that the diagnosis data is not normal, the data management mechanism 44 executes a retry operation. If it still does not become normal, the data management mechanism 44 ejects valid data from the disk cache memory 36, and shifts to a state in which normal operation is prohibited, that is, an operation mode in which write back operation is prohibited (step B5).
[0080]
Further, the data management mechanism 44 updates the data of the initialization date (time stamp) stored in the controller area of the hard disk devices 14-1 to 14-n, and the data on the SRAM card 38 becomes out of date. Change to be explicit.
[0081]
Here, the initialization date and time stored in the controller area of the hard disk devices 14-1 to 14-n and the cache system initialization date and time stored in the system area of the SRAM card 38 are made inconsistent with each other. In step A10 of the process in FIG. 7, a time stamp abnormality is detected, and data can be protected.
[0082]
Next, the operation at the time of receiving a diagnosis request during normal operation will be described with reference to the flowchart shown in FIG.
The host system 10 issues a diagnosis request command for checking the normality of the data stored in the SRAM card 38 in the disk controller 12 to the data management mechanism 44 at regular time intervals and when the host system 10 becomes idle. .
[0083]
When receiving the diagnosis request command, the data management mechanism 44 reads the data of each block from the data area of the SRAM card 38 and generates a check code corresponding to each block by XOR operation (step C1).
[0084]
The data management mechanism 44 reads the check code corresponding to the data of each block written at the time of data transfer stored in the check code area of the SRAM card 38, and compares it with the check code generated in step C1 for each block. (Step C3).
[0085]
When the check codes of the respective blocks match (step C4), the data management mechanism 44 determines that the data stored in the SRAM card 38 is normal and ends the diagnosis process.
[0086]
On the other hand, if the check codes do not match (step C4), the data management mechanism 44 ejects valid data from the disk cache memory 36 and shifts to a state in which normal operation is prohibited, that is, an operation mode in which write back operation is prohibited. (Step C5).
[0087]
Further, the data management mechanism 44 updates the data of the initialization date (time stamp) stored in the controller area of the hard disk devices 14-1 to 14-n, and the data on the SRAM card 38 becomes out of date. Change to be explicit. In this case as well, similar to the process at the time of receiving the write command, the time stamp abnormality is detected at step A10 of the process in FIG. 7, and the data can be protected.
[0088]
In this way, the transfer of diagnostic data is added during normal data transfer, and the normality of the data transfer is verified by determining the check code required from the diagnostic data, so that the reliability can be improved. .
[0089]
Further, by adding a check code to the data of each block stored in the SRAM card 38, the host system 10 explicitly issues a diagnosis request for the data at regular time intervals and when it enters an idle state. Since the abnormality of data can be detected, the reliability can be improved.
[0090]
Hereinafter, an example of a specific situation that can be assumed to exhibit the effect of the present invention will be described.
For example, in normal operation, if a failure occurs in the disk controller 12, the system is immediately stopped, and after replacement with a normal disk controller 12, the SRAM card 38 is replaced with the replaced disk controller 12, and the system is restarted. Return to normal operation by executing. At this time, an arbitrary device may be removed from the hard disk devices 14-1 to 14-n to pursue the cause of the failure, but it is assumed that the wrong hard disk device is reconnected by mistake.
[0091]
In addition, an access abnormality to the SRAM card 38 is detected by a check code diagnosis, and the system operation is performed with the write-back cache operation stopped. After that, after investigating the cause of failure, preparing another SRAM card and executing the cache operation check, it was eventually found that the problem was on the controller side, and the original SRAM card 38 was joined to the new controller and restarted. It can be assumed that the raising is performed.
[0092]
In such a case, according to the present invention, at the time of restart, various checks are performed as shown in the flowchart of FIG. 7, and the above is detected and the processing is stopped. The problem is determined from the middle steps A3, A9, A10). As a result, the normal operation can be restored by implementing measures such as correct connection of the SRAM card 38 or re-initialization of the cache system.
[0093]
In this way, the SRAM card 38 is provided with a redundant code (check code) in place of the parity bit, and the reliability of the stored data is improved by checking the validity of the data written using this check code, In addition, the reliability of data transfer during normal operation can be improved by using the redundant code.
[0094]
In addition, by explicitly displaying the battery replacement date, it is possible to estimate the battery replacement time, and by making it possible to replace the battery before the battery runs out, the write-back operation prohibition period is minimized. You can
[0095]
Further, by providing some protection functions, even when a work mistake or the like at the time of maintenance work occurs, an abnormality notification is given, so that the inspection by a human system can be promoted and data protection can be performed.
[0096]
In the above-described embodiment, the connection device to be cached is the hard disk device 14, but may be a storage device using another storage medium.
[0097]
【The invention's effect】
As described in detail above, according to the present invention, it is possible to improve the reliability of data stored in a nonvolatile memory used in combination with a cache memory in a disk cache and to reliably protect the data.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a computer system having a disk cache according to an embodiment of the present invention.
FIG. 2 is a flowchart for explaining a basic operation of data write processing (write command processing) from the host system 10 in the present embodiment.
FIG. 3 is a diagram for explaining an outline of processing for instructions and data from the host system 10 in the present embodiment;
FIG. 4 is a diagram showing an example of a data form in an SRAM card 38 in the present embodiment.
FIG. 5 is a diagram showing an example of diagnostic data A and B in the present embodiment.
FIG. 6 is a diagram for explaining a transfer order of diagnostic data A and B in the present embodiment.
FIG. 7 is a flowchart for explaining an operation at the time of start-up of the data management mechanism 44 in the embodiment.
FIG. 8 is a flowchart for explaining an operation when a write command is received during a normal operation in the embodiment.
FIG. 9 is a flowchart for explaining an operation when a diagnosis request is received during a normal operation in the embodiment.
[Explanation of symbols]
10 ... Host system
12 ... Disk controller
14, 14-0 to 14-n... Hard disk device
16 ... Connector for connection
20, 30 ... CPU
22 ... CPU local memory
24, 40 ... Bus conversion circuit for external circuit connection
32 ... F / W memory
34 ... DMA controller
36 ... Memory for disk cache
37 ... Connector
38 ... SRAM card
38, bus conversion circuit for external circuit connection
42. SCSI chip
44 ... Data management mechanism

Claims (5)

In a disk cache system that adopts a write-back method as a writing method for a disk device to be cached,
Non-volatile storage means in which block management of the internal area is performed, and data for which a write request has been made to the disk device as a basic unit is written;
The normal data to be written to the nonvolatile storage means and the predetermined diagnostic data for at least one block used for determining the normality of the data transfer are transferred, and the data to be written to the block for each block A data transfer unit that generates a check code based on the non-volatile storage unit and
Diagnostic data determination means for determining whether a check code based on the diagnostic data transferred by the data transfer means is correct as a check code according to the predetermined diagnostic data;
A disk cache system comprising: control means for prohibiting normal operation when the data judging means judges that there is an abnormality. An apparatus for specifying a disk device connected to the system with respect to an area different from an area for data transfer to the disk apparatus provided in the nonvolatile storage means and a specific area of the disk apparatus connected to the system A first writing means for writing information;
  Compare the device information stored in the non-volatile storage means by the first writing means at the appropriate time with the device information written in a specific area of the disk device actually connected to the system at this time. And a device determination means for determining whether or not the connected disk device is correct,
  2. The disk cache system according to claim 1, wherein the control unit prohibits a normal operation when the device determination unit determines that there is an abnormality. The data stored in the non-volatile storage means is stored in an area different from the area for data transfer to the disk apparatus provided in the non-volatile storage means and a specific area of the disk device connected to the system. A second writing means for writing information capable of determining old and new;
  The information stored in the non-volatile storage means by the second writing means at the appropriate time is compared with the information actually written in a specific area of the disk device currently connected to the system at this time. And determining means for determining the legitimacy of
  2. The disk cache system according to claim 1, wherein the control unit prohibits a normal operation when the determination unit determines that the information is not valid. A battery for backing up data written in the nonvolatile storage means;
  Writing means for writing a replacement date when the battery was replaced in a predetermined area in the nonvolatile storage means;
  Reading means for reading and presenting the replacement date written in a predetermined area of the nonvolatile storage means by the writing means;
The disk cache system according to claim 1, further comprising: In a disk cache method that adopts a write-back method as a writing method for a disk device to be cached,
Used to determine the normal data to be written and the normality of data transfer to the non-volatile storage means in which the internal area is managed as a block and the data requested to be written to the disk unit is written using the block as a basic unit Along with predetermined diagnostic data for at least one block, a check code is generated and written for each block based on data to be written to the block,
It is determined whether the check code generated based on the written diagnostic data is correct as a check code according to the predetermined diagnostic data,
A disk cache method characterized by prohibiting normal operation when it is determined by this determination that there is an abnormality.

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