JP3922553B2 - Charge / discharge protection circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charge / discharge protection circuit for various portable devices using a secondary battery, or a charge / discharge protection circuit used as a battery pack for a secondary battery.
[0002]
[Prior art]
As a conventional charge / discharge protection circuit, for example, as in a charge / discharge control circuit and a rechargeable power supply device described in Japanese Patent Laid-Open No. 7-13138, a secondary battery is divided into a voltage divider circuit and one of the voltage divider circuits. A voltage detection circuit for charging and a voltage detection circuit for overdischarge are connected in parallel to each other, and the control circuit detects the state of the secondary battery from the voltage detection circuit for overcharge and overdischarge, and supplies power to the external device. Alternatively, charging by an external power source is controlled. Further, the control circuit controls a switch element provided in series with the voltage dividing circuit to reduce the current flowing through the voltage dividing circuit.
[0003]
However, in the charge / discharge protection circuit or the battery pack having the above configuration, a high breakdown voltage structure is required for the transistor connected to the terminal to which the charger is connected. Thus, if all the transistors are realized by an integrated circuit, a terminal that does not require a high breakdown voltage structure also has a high breakdown voltage structure, and as a result, the chip area of the charge / discharge protection circuit increases. There was a problem.
[0004]
Therefore, for example, in the charge / discharge protection circuit and the battery pack described in JP-A-11-103528, among the transistors constituting the level shift circuit, a transistor that may receive a high voltage as a source level or a drain level is high. Use a pressure-resistant structure. All other transistors that do not require high withstand voltage have a low withstand voltage structure, thereby reducing the chip area and realizing a charge / discharge protection circuit having high withstand voltage characteristics with a small circuit scale.
[0005]
[Patent Document 1]
Japanese Patent Laid-Open No. 7-131938 [Patent Document 2]
JP-A-11-103528 [0006]
[Problems to be solved by the invention]
As described above, the overcurrent detection function of the charge / discharge protection circuit or the battery pack described in the above publication includes a so-called overcurrent detection circuit (first detection level) having a relatively long detection delay time and a delay time of the first. There is a short circuit detection circuit (second detection level) shorter than the detection level of 1. The first detection level is generally set according to the ON resistance of the FET, but the second detection level is fixedly set regardless of the ON resistance of the FET.
However, in the above conventional semiconductor device for a protection circuit, the second detection level of the discharge overcurrent is always a constant value regardless of the ON resistance of the FET. Therefore, even if a large current flows, the detection delay time is long and the FET may be destroyed or the current fuse may be blown. It was.
[0007]
For example, if a FET with an ON resistance of 20 mΩ per FET is used, the first detection level is set to 0.2 V and the second detection level is set to 0.5 V according to the characteristics of the FET. As a value of overcurrent, since two FETs are connected in series, the ON resistance is 40 mΩ,
0.2V ÷ 40mΩ = 5A
0.5V ÷ 40mΩ = 12.5A
Thus, the normal state is from 0 to 5A, the first overcurrent state is from 5A to 12.5A, and the second overcurrent state (short circuit state) is from 12.5A.
[0008]
However, when the first detection level is set to 0.1 V in accordance with a FET having an ON resistance per FET of 10 mΩ, the second detection level is fixed even in this case.
0.1V ÷ 20mΩ = 5A
0.5V ÷ 20mΩ = 25A
Thus, the normal state is 0 to 5 A, which is the same as the above case, but the first overcurrent state spreads from 5 A to 25 A, the second overcurrent state is 25 A or more, and a current near 25 A However, the delay time until the FET is turned off becomes the first overcurrent delay time, and there is a problem that the FET is broken or the fuse is blown.
[0009]
The object of the present invention is to eliminate such problems, without fixing the reference voltage of the discharge overcurrent detection comparator, and even when the ON resistance of the control FET is lowered, the FET is not destroyed or the current fuse is not blown. An object of the present invention is to provide a safer charge / discharge protection circuit that can set an appropriate short-circuit detection current.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the charge / discharge protection circuit of the present invention does not fix the reference voltage of the short-circuit comparator, but sets it in association with the reference voltage of the overcurrent detection comparator as described above. The problem is solved.
That is, a feature of the present invention is that the reference voltage of the short-circuit comparator and the reference voltage of the overcurrent detection comparator are set in association with each other. As shown in FIG. 2, the reference voltage (Vref) and the current detection terminal (V− terminal) are set. ), The first resistor (R1), the second resistor (R2), and the third resistor (R3) are connected in series, and the detection level for detecting the discharge overcurrent of the secondary battery is the second resistance. The detection level obtained from the connection point of the resistor (R2) and the third resistor (R3) is obtained from the connection point of the first resistor (R1) and the second resistor (R2). And a reference voltage generating means capable of adjusting a resistance value of the first resistor (R1).
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a block configuration diagram of a semiconductor device using the present invention and a protection circuit in a battery pack using the semiconductor device.
The semiconductor device inside the thick line generally includes an overcharge detector 15, an overdischarge detector 21, a discharge overcurrent detector 20, a short circuit detector 18, a charge overcurrent detector 16, a delay circuit 17, and an oscillator. 11, a counter 14, logic circuits 12 and 19, and a level shift 13.
[0012]
In the battery pack 10, a battery cell 25 and a capacitor 26 are connected in parallel, via the current fuse 21 to the + terminal of the overcurrent / short-circuit load 22, and via the discharge control FET 24 and the charge control FET 23. Are connected to the negative terminal of the overcurrent / short-circuit load 22, respectively.
A battery cell 25 is connected between VDD (drain terminal) and VSS (source terminal) of the semiconductor device. The divided resistors between the VDD and VSS terminals are connected to the input sides of the overcharge detector 15 and the overdischarge detector 21, and the output side of these detectors 15, 21 includes the oscillator 11, the logic circuit 12, 19 is connected. A counter 14 is connected to the oscillator 11, and the counter 14 is connected to the logic circuits 12 and 19.
[0013]
A short circuit detector 18 is connected with the V-terminal of the semiconductor device and the power supply Vref2 as inputs, and a delay circuit 17 is connected to the output side. Further, the discharge overcurrent detector 20 is connected with the V-terminal and the power supply Vref1 as inputs, and the oscillator 11 and the logic circuit 19 are connected on the output side. Similarly, the charge overcurrent detector 16 is connected with the V− terminal and the power supply Vref3 as inputs, and the oscillator 11 and the logic circuit 12 are connected on the output side. A Dout terminal is connected to the discharge control FET 24 of the battery pack 10, and a logic circuit 19 in the semiconductor device is connected to the Dout terminal. The charge control FET 23 is connected to the Cout terminal, and the level shift 13 is connected to the Cout terminal.
[0014]
Overcharge is detected by the overcharge detector 15, overdischarge is detected by the overdischarge detector 21, discharge overcurrent is detected by the discharge overcurrent detector 20, or short-circuit is detected by the short-circuit detector 18, and charging is performed by the charge overcurrent detector 16. When each overcurrent is detected, the oscillator 11 starts operating and the counter 14 starts operating. Then, when the counter 14 counts the delay time set at the time of each detection, the Cout output becomes a low level in the case of overcharge or charge overcurrent through the logic circuit 19, and overdischarge, overcurrent, or short circuit is detected. In this case, the Dout output becomes a low level.
[0015]
FIG. 2 is a detailed circuit diagram of the discharge overcurrent detector 20 and the short circuit detector 18 in FIG.
In FIG. 2, the names and symbols of the discharge overcurrent detection comparator 35 and the short circuit detection comparator 36 are changed.
The V-terminal voltage is connected to the negative inputs of the discharge overcurrent detection comparator 35 and the short circuit detection comparator 36, Vref 1 (B input) is connected to the positive input of the discharge overcurrent detection comparator 35, and the short circuit detection comparator 36 Vref2 (C input) is connected to the + input.
[0016]
The FET 27 of the semiconductor device in FIG. 1 is indicated by FETs 31 to 34 in FIG. Further, in FIG. 2, reference voltages Vref1 and Vref2 in FIG. 1 are indicated by a voltage B and a voltage C acquired by the divided resistors R1, R2, and R3 connected to the V− terminal. If the resistance value R1 = R2 = R3 is set, it is convenient because the short circuit detection voltage can be expressed as a multiple of the discharge overcurrent detection voltage.
[0017]
When an overcurrent flows, the V-terminal voltage rises. When the voltage rises to the level of Vref1 or Vref2, the comparators 35 and 36 are inverted to detect a discharge overcurrent or a short circuit and output an OFF signal. Therefore, Vref1 is the discharge overcurrent detection voltage, and Vref2 is the short circuit detection voltage.
The discharge overcurrent detection voltage adjusts the value of Vref1 in FIG. 2 to a desired voltage by trimming the resistor R1 in accordance with the ON resistance of the FET. At this time, Vref1 is
Vref1 = Vref × R3 / (R1 + R2 + R3)
It becomes.
[0018]
At this time, If left R2 = R 3, short-circuit detection voltage,
Vref2 = Vref × (R2 + R3) / (R1 + R2 + R3)
= Vref × R2 × R3) / (R1 + R2 + R3)
= 2 × Vref1
Thus, the discharge overcurrent detection voltage can be doubled.
Similarly, the short-circuit detection voltage can be freely set to n times the discharge overcurrent detection voltage by changing the ratio of R2 and R3.
[0019]
Although FIG. 1 shows an example in which the charge / discharge protection circuit of the present invention is housed in a battery pack, the charge / discharge protection circuit is housed in various portable devices using secondary batteries, or otherwise. The present invention can be applied to various fields, for example, in the case of being housed in an electric device.
[0020]
【The invention's effect】
As described above, according to the present invention, since the short circuit detection voltage can be set by a multiple of the discharge overcurrent detection voltage, the short circuit detection can be performed regardless of the set value of the discharge overcurrent detection voltage as in the prior art. Compared to the case where the voltage is kept constant, an appropriate short-circuit detection current can be set without destroying the FET or melting the current fuse, so that a safer battery pack can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram of a charge / discharge protection circuit and a battery pack according to an embodiment of the present invention.
FIG. 2 is a detailed circuit diagram of a discharge overcurrent detector and a short-circuit detector in FIG.
[Explanation of symbols]
10 ... battery pack, 11 ... oscillator, 12 ... logic circuit,
13 ... Level shift circuit, 14 ... Counter, 15 ... Overcharge detector,
16 ... Charge overcurrent detector, 15 ... Overcharge detector, 17 ... Delay circuit,
18 ... short circuit detector, 19 ... logic circuit, 20 ... discharge overcurrent detector,
21 ... Current fuse, 22 ... Overcurrent / short-circuit load, 23 ... Charge control FET,
24 ... discharge control FET, 25 ... battery cell, 26 ... capacitor,
17 ... Control FET, 31-34 ... Control FET,
35 ... discharge overcurrent detection comparator, 36 ... short circuit detection comparator,
V -... V-terminal, R1, R2, R3 ... resistor, Vref1 ... first reference voltage,
Vref2: Second reference voltage.

Claims (1)

A semiconductor in which two or more detection levels of the overcurrent exist when the secondary battery is protected from overcharge, overdischarge or overcurrent by detecting overcharge, overdischarge or overcurrent of the secondary battery. In the charge / discharge protection circuit of the device,
A first resistor, a second resistor, and a third resistor are connected in series between a reference voltage and a current detection terminal, and a detection level for detecting a discharge overcurrent of the secondary battery is set to the second resistor and the first resistor. 3 is obtained from the connection point of the three resistors, the detection level for detecting the short-circuit current is obtained from the connection point of the first resistor and the second resistor, and the resistance value of the first resistor is adjustable. A charge / discharge protection circuit comprising a reference voltage generating means.

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