JP3918828B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device , and more particularly to a semiconductor device suitable for multilayering.

  In recent years, printed circuit boards having a multilayer wiring layer in which a plurality of wiring layers and insulating resin layers are alternately stacked and via layers are connected via vias have progressed with the increase in density of electronic devices. ing. As the number of printed wiring boards increases, the wiring is broken or short-circuited due to irregularities on the surface of the printed wiring board, resulting in a problem that the printed wiring board becomes defective and yield decreases. In order to solve such a problem, a technique for flattening unevenness on the surface of a printed wiring board has been proposed. For example, after blackening and reducing a substrate with a bottomed via hole, an epoxy resin filler is applied to the bottomed via hole by screen printing, and vacuuming is performed to remove bubbles in the bottomed via hole, and the filler is thermally cured. Then, there is a method for filling a bottomed via hole in which the surface is polished and flattened. According to this, when the upper layer is further built up, the depression of the bottomed via hole is not hindered, the pattern processing accuracy of the upper layer is ensured, and it is convenient for component mounting ( Patent Document 1).

JP 2000-133937 A

  However, the above-described method has problems that the inner layer conductor thickness varies due to polishing, and that the inner layer substrate has large dimensional variations. Further, as the number of printed wiring boards is further increased, there is a limit to flattening the printed wiring boards.

  Furthermore, with a printed wiring board with a build-up layer formed on the surface of the core substrate, the core substrate is wasted if a failure occurs in the build-up layer during the manufacturing process even if the core substrate is a good product. Yield reduction is a problem.

A first object of the present invention is to provide a semiconductor device having a printed wiring board suitable for multilayering.

A second object of the present invention is to provide a semiconductor device capable of improving yield, reducing lead time, and improving tact.

In one aspect of the present invention, in a semiconductor device, a semiconductor element, wherein the bump is connected to the electrode terminals of the semiconductor element, a first conductive pad connected to the bump, the plurality of wiring layers and insulating layers Are alternately stacked, the wiring layers are connected by vias, and the vias are on the second surface side opposite to the first surface than the diameter on the first surface side where the semiconductor element is disposed. And a first buildup layer in which a via closest to the semiconductor element among the vias is connected to the first conductive pad , a plurality of wiring layers, and Insulating layers are alternately stacked, the wiring layers are connected by vias, and the vias are configured such that the diameter on the first surface side is larger than the diameter on the second surface side, And before the first build-up layer A second buildup layer bonded to the second surface, with arranged on the second surface of the second buildup layer, most of the vias in the second buildup layer A second conductive pad connected to a via disposed on the second surface side; and a second conductive pad disposed on the first surface of the first buildup layer and for housing the semiconductor element A metal plate having an opening , wherein the via in the first buildup layer is integrally formed with the wiring layer adjacent to the second surface side, and the second buildup The via in the layer is formed integrally with the wiring layer adjacent in the first surface side portion, and the insulating layer of the first buildup layer and the via of the second buildup layer One or both of the insulating layers can be glass cloth, Scan nonwoven, aramid nonwoven fabric, aramid film, and characterized by comprising an insulating resin containing any one or more reinforcing materials polyimide film.

In the semiconductor device according to the present invention, the wiring layer of the first buildup layer and the second buildup are arranged between the first buildup layer and the second buildup layer. A bonding metal material layer for bonding a wiring layer, a first buildup layer and a second buildup layer, and an insulating layer of the first buildup layer and the first buildup layer It is preferable to include a bonding adhesive layer that bonds the insulating layer of the second buildup layer.

In the semiconductor device according to the present invention, the wiring layer of the first buildup layer and the second buildup are arranged between the first buildup layer and the second buildup layer. It is preferable to provide an anisotropic conductive film that electrically connects the wiring layers.

In the semiconductor device according to the present invention, the wiring layer of the first buildup layer and the second buildup are arranged between the first buildup layer and the second buildup layer. It is preferable to provide a conductive paste that electrically connects the wiring layers of the layers.

In the semiconductor device of the present invention, the semiconductor device is disposed between the first buildup layer and the second buildup layer, and contains powdered solder, resin, solvent, and the like, and the first It is preferable that a solder paste layer for electrically connecting the wiring layer of the build-up layer and the wiring layer of the second build-up layer is provided.

In the semiconductor device of the present invention, the land portion in the wiring layer closest to the second surface of the first buildup layer is the wiring closest to the first surface of the second buildup layer. It is preferable that the size is different from the land portion in the layer.

  According to the present invention (claims 1 to 5), since the first buildup layer and the second buildup layer are separately manufactured and bonded, the yield can be improved.

  According to the present invention (Claims 1 to 5), since the first buildup layer and the second buildup layer can be bonded together after being manufactured at the same time, the tact can be improved and the lead time can be shortened. it can.

  According to the present invention (Claims 6 and 7), the semiconductor element is arranged in the opening region of the metal plate, and there is no warp and a flat multilayer wiring layer (first buildup layer and second buildup). Therefore, the connecting portion between the multilayer wiring layer and the semiconductor element is stable and highly reliable. Moreover, since the multilayer wiring layer is provided on the flat metal plate, the flatness of the multilayer wiring layer is good.

(Embodiment 1)
A semiconductor device and a printed wiring board according to Embodiment 1 of the present invention will be described with reference to the drawings. 1A is a perspective view from the front side, FIG. 1B is a perspective view from the back side, and FIG. 1C is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention. is there. The semiconductor device according to the first embodiment applies a flip chip ball grid array (FCBGA).

  Referring to FIG. 1A, the semiconductor device 1 includes a printed wiring board 10 and a semiconductor element 60. The printed wiring board 10 includes a multilayer wiring layer 11 and a metal plate 21. The multilayer wiring layer 11 is a build-up layer without a substrate serving as a core. The multilayer wiring layer 11 has a plurality of wiring layers and insulating layers alternately stacked, and the wiring layers are via-connected, and can be formed by a known build-up method. The metal plate 21 is laminated on the multilayer wiring layer 11 and has an opening 21a penetrating in a region excluding a region where the semiconductor element 60 is mounted. The semiconductor element 60 is mounted in the region of the opening 21 a of the metal plate 21 on the multilayer wiring layer 11.

  Referring to FIG. 1B, a first bump 80 is mounted on the surface (back surface) opposite to the surface (front surface) on which the metal plate 21 is disposed in the multilayer wiring layer 11.

  Referring to FIG. 1C, the semiconductor device 1 includes a printed wiring board 10, a semiconductor element 60, a sealing resin 70, a first bump 80, and a second bump 90. The printed wiring board 10 includes a first buildup layer 20 and a second buildup layer 40. The multilayer wiring layer 11 is a portion of the first buildup layer 20 and the second buildup layer 40 excluding the metal plate 21.

  First, the first buildup layer 20 will be described. The first buildup layer 20 includes a metal plate 21, a first conductive pad 22, a first insulating layer 23, a first wiring layer 24 via-connected to the first conductive pad 22, Second insulating layer 25, second wiring layer 26 via-connected to first wiring layer 24, third insulating layer 27, and third wiring layer 28 via-connected to second wiring layer 26 And a bonding metal material layer 29 and a bonding adhesive layer 30.

  The metal plate 21 is a frame-shaped reinforcing plate (stiffener) having an opening 21 a penetrating in a region excluding a region where the semiconductor element 60 is mounted. Further, since the metal plate 21 is made of metal, it may have a function as the ground of the outermost layer. For the metal plate 21, for example, at least one metal selected from the group consisting of stainless steel, iron, nickel, copper and aluminum can be used, and an alloy thereof can be used. If so, copper is optimal. Moreover, the thickness of the metal plate 21 can be 0.1-1.5 mm, for example.

  The first conductive pad 22 is a conductive medium formed on the via surface connected to the first wiring layer 24 formed in the opening of the first insulating layer 23. The first conductive pad 22 includes at least a first wiring layer 24, a second wiring layer 26, a third wiring layer 28, a bonding metal material layer 29, a sixth wiring layer 48, and a fifth wiring layer. 46, the fourth wiring layer 44, and the corresponding second conductive pads 42 through vias connecting the wiring layers. For the first conductive pad 22, for example, at least one metal selected from gold, tin, nickel, and solder by electroless plating, electrolytic plating, or the like can be used, and an alloy thereof can be used. it can. The first conductive pad 22 may have not only a single-layer structure but also two or more layers. In consideration of adhesion to the second bump 90 and the like, the first conductive pad 22 may be nickel in order from the first wiring layer 24 side. A two-layer structure of a plating layer and a gold plating layer is optimal.

  The first insulating layer 23 is an insulating resin layer that is bonded to the metal plate 21. The first insulating layer 23 has an opening at a position corresponding to each electrode terminal (not shown) formed in the semiconductor element 60. At least the opening of the first insulating layer 23 in which the first conductive pad 22 is formed has a larger diameter on the second insulating layer 25 side than the diameter on the first conductive pad 22 side. It is configured. As the first insulating layer 23, for example, epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, bismaleimide triazine resin, polyphenylene ether resin, fluorine resin, benzocyclobutene resin, liquid crystal polymer, etc. 1 type or 2 or more types of insulating resins selected from these insulating resins may be used, and may be a thermosetting resin or a photosensitive resin. For example, a photosensitive solder resist (manufactured by Taiyo Ink Manufacturing Co., Ltd.) PSR4000 NAS-90-TY, Tamura Kaken DSR 2200 BGX-8, etc.) can be used. In order to increase the substrate strength, a glass cloth, a glass nonwoven fabric, an aramid nonwoven fabric, an aramid film, a polyimide film, or the like may be laminated on the insulating resin as a reinforcing material. Further, a resin film or a copper foil with resin (RCC) can be used for the first insulating layer 23.

  The first wiring layer 24 is a conductive layer patterned on the surface of the first insulating layer 23 on the first bump 80 side. For the first wiring layer 24, for example, at least one metal selected from gold, silver, copper, nickel, etc. by electroless plating, electrolytic plating, or the like or an alloy thereof can be used. From the viewpoint of cost, Copper is optimal.

  The second insulating layer 25 is an insulating resin layer formed on the surface (on the first bump 80 side) of the first insulating layer 23 including the first wiring layer 24. The second insulating layer 25 has an opening, and a via that connects the first wiring layer 24 and the second wiring layer 26 is formed in the opening. The via is filled with a conductive metal such as copper or a conductive paste. The opening of the second insulating layer 25 is configured such that the diameter on the third insulating layer 27 side is larger than the diameter on the first wiring layer 24 side at least in the portion where the via is filled. ing. The second insulating layer 25 can be made of the same material as that of the first insulating layer 23, or can be made of a material different from that of the first insulating layer 23.

  The second wiring layer 26 is a conductive layer patterned on the surface (on the first bump 80 side) of the second insulating layer 25, and passes through a via formed in the opening of the second insulating layer 25. The first wiring layer 24 is electrically connected (via connection). The second wiring layer 26 may further be formed in multiple layers via the second insulating layer 25 to connect vias between the layers. The second wiring layer 26 can be made of the same material as the first wiring layer 24, and copper is optimal from the viewpoint of cost.

  The third insulating layer 27 is an insulating resin layer formed on the surface (on the first bump 80 side) of the second insulating layer 25 including the second wiring layer 26. The third insulating layer 27 has an opening that communicates with the second wiring layer 26. The opening of the third insulating layer 27 has a diameter on the side of the bonding adhesive layer 30 rather than a diameter on the second wiring layer 26 side, at least in a portion where a via connected to the third wiring layer 28 is filled. Is configured to be wide. The third insulating layer 27 can be formed using a material similar to that of the first insulating layer 23, and may be formed of a material different from that of the first insulating layer 23 and the second insulating layer 25.

  The third wiring layer 28 is a conductive layer patterned on the surface (on the first bump 80 side) of the third insulating layer 27, and passes through vias formed in the openings of the third insulating layer 27. The second wiring layer 26 is electrically connected (via connection). The third wiring layer 28 can be made of the same material as the first wiring layer 24, and copper is optimal from the viewpoint of cost.

  The joining metal material layer 29 is a conductive layer for metal joining the third wiring layer 28 and the sixth wiring layer 48, and is at least between the third wiring layer 28 and the sixth wiring layer 48. Intervene. The bonding metal material layer 29 may be any metal that can be metal-bonded to the sixth wiring layer 48 and can be electrically connected. For example, a silver paste, a copper paste, A conductive paste such as a mixed paste of silver and copper, a mixed paste of copper and solder, a metal bump such as copper, or solder can be used. Among the solders, it is preferable to use a solder composed of at least two of Sn, In, or Sn, Ag, Cu, Zn, Bi, Pd, Sb, Pb, In, and Au. More preferably, it is an environment-friendly Pb-free solder. Also, a solder paste containing powdered solder, resin, solvent, etc. disclosed in JP-A-8-174264 can be used. If the solder paste is used, there is an advantage that it is not necessary to perform cleaning.

  The bonding adhesive layer 30 is in a state in which the third wiring layer 28 and the sixth wiring layer 48 are bonded (electrically connected) via the bonding metal material layer 29 (the first build-up layer 20 (the first bonding layer 30). 3 insulating layer 27) and second buildup layer 40 (sixth insulating layer 47). For the bonding adhesive layer 30, for example, a prepreg, an anisotropic conductive film (ACF), an insulating film (NCF), an anisotropic conductive paste (ACP), an insulating paste (NCP), or the like can be used. You may use the solder paste shown by Kaihei 8-174264 gazette.

  Next, the second buildup layer 40 will be described. The second buildup layer 40 includes a second conductive pad 42, a fourth insulating layer 43, a fourth wiring layer 44, a fifth insulating layer 45, a fifth wiring layer 46, A sixth insulating layer 47 and a sixth wiring layer 48 are included.

  The second conductive pad 42 is a conductive medium that is an opening of the fourth insulating layer 43 and is formed on the via surface connecting the fourth wiring layer 44 and the fifth wiring layer 46. . The second conductive pad 42 includes at least a fourth wiring layer 44, a fifth wiring layer 46, a sixth wiring layer 48, a bonding metal material layer 29, a third wiring layer 28, and a second wiring layer. 26, the first wiring layer 24, and the corresponding first conductive pads 22 through vias connecting the wiring layers. For the second conductive pad 42, the same material as that of the first conductive pad 22 can be used. From the viewpoint of the adhesion to the first bump 80 and the like, from the fourth wiring layer 44 side. In order, a two-layer structure of a nickel plating layer and a gold plating layer is optimal.

  The fourth insulating layer 43 is an insulating resin layer disposed on the most first bump 80 side. The fourth insulating layer 43 has an opening at a position corresponding to the first bump 80, the opening is filled with a conductive material, and a connection via is formed. The opening of the fourth insulating layer 43 is such that the diameter on the fifth insulating layer 45 side is wider than the diameter on the second conductive pad 42 side at least in the portion filled with the conductive material. It is configured. The fourth insulating layer 43 can be made of the same material as that of the first insulating layer 23, and may be a solder resist in consideration of the surface layer of the multilayer wiring layer 11.

  The fourth wiring layer 44 is a conductive layer patterned on the surface (on the second bump 90 side) of the fourth insulating layer 43 including the second conductive pad 42. The fourth wiring layer 44 can be made of the same material as that of the first wiring layer 24, and copper is optimal from the viewpoint of cost.

  The fifth insulating layer 45 is an insulating resin layer formed on the surface (on the second bump 90 side) of the fourth insulating layer 43 including the fourth wiring layer 44. The fifth insulating layer 45 has an opening that communicates with the fourth wiring layer 44. The opening of the fifth insulating layer 45 is such that the diameter on the sixth insulating layer 47 side is larger than the diameter on the fourth wiring layer 44 side at least in the portion filled with the conductive material and connected to the via. It is configured. For the fifth insulating layer 45, a material similar to that of the first insulating layer 23 can be used.

  The fifth wiring layer 46 is a conductive layer patterned on the surface (on the second bump 90 side) of the fifth insulating layer 45, and the fourth wiring layer passes through the opening of the fifth insulating layer 45. 44 is electrically connected (via connection). The fifth wiring layer 46 may further be formed in multiple layers via the fifth insulating layer 45 to connect vias between the layers. For the fifth wiring layer 46, the same material as that of the first wiring layer 24 can be used, and copper is optimal from the viewpoint of cost.

  The sixth insulating layer 47 is an insulating resin layer formed on the surface (on the second bump 90 side) of the fifth insulating layer 45 including the fifth wiring layer 46. The sixth insulating layer 47 has an opening that communicates with the fifth wiring layer 46. The opening of the sixth insulating layer 47 is configured so that the diameter on the bonding adhesive layer 30 side is larger than the diameter on the fifth wiring layer 46 side at least in the portion filled with the conductive material and connected to the via. Has been. For the sixth insulating layer 47, the same material as that of the first insulating layer 23 can be used. When the bonding metal material layer 29 is formed on the surface of the sixth wiring layer 48, a solder resist is used. desirable.

  The sixth wiring layer 48 is a conductive layer patterned on the surface (on the second bump 90 side) of the sixth insulating layer 47, and the fifth wiring layer through the opening of the sixth insulating layer 47. 46 is electrically connected (via connection). For the sixth wiring layer 48, the same material as that of the first wiring layer 24 can be used, and copper is optimal from the viewpoint of cost.

  The semiconductor element 60 is, for example, a semiconductor chip such as an LSI, and the electrode terminals of the semiconductor element 60 are connected to the first conductive pads 22 via the corresponding second bumps 90. The second bump 90 can be made of the same material as that of the first bump 80, and solder is optimal from the viewpoint of handling and the like.

  The sealing resin 70 is an insulating resin (underfill) that seals the gap between the semiconductor element 60 and the first insulating layer 23. A known sealing material (for example, an epoxy resin) can be selected and used for the sealing resin 70 according to required characteristics.

  The first bump 80 is a conductive protrusion medium that is formed on the surface of the second conductive pad 42 and is electrically connected to an external electronic component (not shown). For the first bump 80, a metal material such as gold, copper, solder (Sn—Pb eutectic solder, Sn—Ag—Cu solder, etc.), a conductive resin, a composite material in which the surface of the resin member is coated with a metal material From the viewpoint of handling and the like, solder balls are most suitable.

  Next, a method for manufacturing a semiconductor device and a printed wiring board according to Embodiment 1 of the present invention will be described with reference to the drawings. 2 and 3 are partial cross-sectional views schematically showing, in the order of steps, the main manufacturing process of the cross section of the first buildup layer in the printed wiring board according to Embodiment 1 of the present invention. FIG. 4 is a partial cross-sectional view schematically showing, in the order of steps, the main manufacturing process of the cross section of the second buildup layer in the printed wiring board according to Embodiment 1 of the present invention. 5 and 6 are partial cross-sectional views schematically showing the cross-section of the printed wiring board according to Embodiment 1 of the present invention in the order of the manufacturing processes. FIG. 7 is a plan view schematically showing the division of the first buildup layer in the printed wiring board according to Embodiment 1 of the present invention. 2 and 3 and FIGS. 5 and 6 are simply divided for the convenience of drawing. The semiconductor device manufacturing method according to the first embodiment is roughly divided into three steps: (1) a first buildup layer manufacturing stage, (2) a second buildup layer manufacturing stage, and (3) a bonding stage. be able to.

  The manufacturing stage of the first buildup layer will be described.

  First, a plating resist 31 having an opening 31a for forming the first conductive pad 22 is formed on the surface of a metal plate 21 (for example, a copper plate) (step A1; see FIG. 2A). Here, the plating resist 31 is formed by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like if the plating resist 31 is liquid, and a lamination method or the like if the plating resist 31 is a dry film. Then, it is hardened by performing a treatment such as drying, and if the plating resist 31 is photosensitive, it is patterned by a photolithography process or the like, and if it is non-photosensitive, it is patterned by a laser processing method or the like.

  Next, a first conductive pad 22 (for example, gold) is formed in the opening 31a of the plating resist 31 (step A2; see FIG. 2B). In addition, after forming the 1st electroconductive pad 22, the plating resist 31 is peeled off (step A3; refer FIG.2 (C)).

  Next, after the first insulating layer 23 is formed on the surfaces of the metal plate 21 and the first conductive pad 22, the opening 23 a communicating with the first conductive pad 22 is formed in the first insulating layer 23. (Step A4; see FIG. 2D). Here, as a method for forming the first insulating layer 23, for example, (1) a method in which a resin film is attached and the opening 23 a is formed by a laser beam such as a YAG laser or a carbon dioxide gas laser; A method of removing the unnecessary copper foil by attaching a copper foil (RCC), etching the copper foil of the opening 23a, forming the opening 23a by laser processing or plasma processing, and (3) thermosetting resin A method of forming the opening 23a with a laser beam such as a YAG laser or a carbon dioxide gas laser by printing, coating, etc., (4) As the first insulating layer 23, a photosensitive resin is printed, coated, etc., and cured. There is a method of forming the opening 23a by a photolithography method. By these methods, the first conductive pad is formed in a portion where a via formed by filling the opening 23a of the first insulating layer 23 with at least a conductive material connected to the first wiring layer 24 is formed. The diameter on the second insulating layer 25 side can be made wider than the diameter on the 22 side. In addition, when the opening 23a is formed by laser light, it is preferable to wash with a permanganic acid solution in order to remove contamination attached to the wall surface of the opening 23a.

  Next, on the surface of the first insulating layer 23 including the first conductive pad 22, the first wiring layer 24, the second insulating layer 25, the second wiring layer 26, the third insulating layer 27, The third wiring layer 28 is formed in this order, and a multilayer wiring layer in which the wiring layers are via-connected is formed (step A5; see FIG. 3A). Here, the first wiring layer 24 (for example, copper plating) performs, for example, chemical roughening (desmearing, resin roughening, etc.) on the surface of the first insulating layer 23, and then the assembly surface (via). After the seed layer is formed by electroless copper plating on the bottom (including the bottom), a circuit-forming dry film is laminated to the substrate, mask exposure and development processes are performed, and a desired wiring pattern is formed, followed by electrolytic plating. The wiring pattern can be formed by the method, the dry film is peeled off, and then the seed layer is removed by etching. The second wiring layer 26 and the third wiring layer 28 (for example, copper plating) can also be formed by the same method as the first wiring layer 24. The second insulating layer 25 (for example, a copper foil with resin) can be formed by the same method as the first insulating layer 23 (for example, a method using a copper foil with resin). The via can be formed by a method such as metal plating, a method of filling a conductive material made of metal, or a method of filling a conductive paste by screen printing. A plurality of wiring layers and insulating layers may be formed between the second wiring layer 26 and the third wiring layer 28 and the layers may be via-connected. The third insulating layer 27 can be formed by a method similar to that of the first insulating layer 23 (for example, a method using a photosensitive resin (solder resist)).

  Next, a bonding metal material layer 29 is formed on the surface (tip) of the third wiring layer 28 (step A6; see FIG. 3B). Here, the method of forming the bonding metal material layer 29 includes a method of forming by electroless plating, a method of forming the metal plate 21 by electrolytic plating using an electrolytic plating lead (power supply electrode), and a bonding metal material. The method of printing a paste is mentioned. In the printing method, it is necessary to align the printing mask with respect to the third wiring layer 28 with high accuracy. However, in the method using electroless plating or electrolytic plating, bonding is performed in addition to the surface of the third wiring layer 28. Since the metal material layer 29 is not formed, the third wiring layer 28 can be easily miniaturized and densified. In particular, the electrolytic plating method requires less time than the electroless plating method, and the layer thickness can be increased. Moreover, since there are a wide variety of metals that can be plated and the management of chemicals is easy, it is very suitable. In FIG. 3B, the bonding metal material layer 29 is formed on the surface of the third wiring layer 28. The purpose of forming the bonding metal material layer 29 is the same as that of the third wiring layer 28. Since a sixth wiring layer (48 in FIG. 4E) to be described later is bonded, a bonding metal material layer 29 is formed on the surface of the sixth wiring layer (48 in FIG. 4E). Alternatively, they may be formed on both surfaces of the third wiring layer 28 and the sixth wiring layer (48 in FIG. 4E).

  Next, the bonding adhesive layer 30 is formed on the surface of the third insulating layer 27 including the bonding metal material layer 29 (step A7; see FIG. 3C). Here, the bonding adhesive layer 30 may be formed by a method suitable for the resin to be used, and a metal bonding adhesive varnish may be directly applied by printing, curtain coating, bar coating, or a dry film with a support film. The bonding adhesive layer 30 is laminated by a method such as vacuum lamination or vacuum press. FIG. 3C shows an example in which the bonding adhesive layer 30 is formed on the surface of the third insulating layer 27, but bonding bonding is performed on the surface of the sixth insulating layer (47 in FIG. 4E). The layer 30 may be formed, or may be formed on both surfaces of the third insulating layer 27 and the sixth insulating layer (47 in FIG. 4E).

  As mentioned above, the intermediate body of the 1st buildup layer 20 before bonding is made by step A1-A7. When mass-producing the first buildup layer 20, a unit (for example, a strip shape) that is formed by imposing a plurality of first buildup layers 20 on a single metal plate 21 and imposing them together. Unit). Then, at the time of bonding with the second buildup layer (40 in FIG. 4E) at a predetermined position in a region other than the portion used as the first buildup layer 20 in the cut unit. A positioning hole 21b for alignment is formed (see FIG. 7). The positioning hole 21b may be formed at a position on the diagonal line of the strip unit, for example, and the positioning hole 21b may also serve as a sprocket hole for conveyance.

  Next, the manufacturing stage of the second buildup layer will be described.

  First, the plating resist 49 which has the opening part 49a for forming the 2nd conductive pad 42 is formed in the surface of the metal plate 41 (for example, copper plate) (step B1; refer FIG. 4 (A)). Here, the plating resist 49 can be formed by the same method as in Step A1.

  Next, a second conductive pad 42 (for example, gold) is formed in the opening 49a of the plating resist 49 (step B2; see FIG. 4B). Note that after the second conductive pad 42 is formed, the plating resist 49 is peeled off (step B3; see FIG. 4C).

  Next, after a fourth insulating layer 43 is formed on the surfaces of the metal plate 41 and the second conductive pad 42, an opening 43 a that communicates with the second conductive pad 42 is formed in the fourth insulating layer 43. (Step B4; see FIG. 4D). Here, the fourth insulating layer 43 can be formed by a method similar to the first insulating layer (23 in FIG. 2D) (for example, a method using a copper foil with resin).

  Next, on the surface of the fourth insulating layer 43 including the second conductive pad 42, a fourth wiring layer 44, a fifth insulating layer 45, a fifth wiring layer 46, a sixth insulating layer 47, A sixth wiring layer 48 is formed in this order to form a multilayer wiring layer in which the wiring layers are via-connected (step B5; see FIG. 4E). Here, the fourth wiring layer 44, the fifth wiring layer 46, and the sixth wiring layer 48 (for example, copper plating) are the first wiring layer (24 in FIG. 3A; see step A5). It can be formed by the same method. The fifth insulating layer 45 can be formed by a method similar to the first insulating layer (23 in FIG. 3A; see step A5) (for example, a method using a copper foil with resin). The sixth insulating layer 47 can be formed by the same method (for example, a method using a photosensitive resin (solder resist)) as the first insulating layer (23 in FIG. 3A; see step A5). . Note that a plurality of wiring layers and insulating layers may be formed between the fifth wiring layer 46 and the sixth wiring layer 48, and the layers may be via-connected.

  As mentioned above, the intermediate body of the 2nd buildup layer 40 before bonding is made by step B1-B5. When the second buildup layer 40 is mass-produced, a plurality of second buildup layers 40 are formed on one metal plate 41 and bonded together as in the first buildup layer 20. Cut into easy-to-use units (eg strip units). Then, at the time of bonding with the first buildup layer (20 in FIG. 3C) at a predetermined position in a region other than the portion used as the second buildup layer 40 in the cut unit. A positioning hole (similar to 21b in FIG. 7 or a symmetric hole) is formed for alignment.

  Next, the bonding step will be described.

  First, the first buildup layer 20 and the second buildup layer 40 are aligned and face each other such that the metal plates 21 and 41 are directed outward (step C1; see FIG. 5A). Here, alignment is performed by positioning holes (21b in FIG. 7) of the first buildup layer 20 and positioning holes (holes similar to 21b in FIG. 7) of the second buildup layer 40 corresponding thereto. Can be read and aligned by an image recognition device (not shown), and a method of aligning with a positioning pin or the like may also be used. Further, when the solder paste disclosed in Japanese Patent Laid-Open No. 8-174264 is used for the bonding adhesive layer 30, it is possible to perform positioning by self-alignment by the tension between the buildup layer 20 and the core substrate 40.

  Next, the aligned first buildup layer 20 and second buildup layer 40 are bonded together (step C2; see FIG. 5B). As a bonding method, for example, using a vacuum press, the third wiring layer 28 is heated and removed until the bonding adhesive layer 30 is removed and bonded to the sixth wiring layer 48 by the bonding metal material layer 29. The third wiring layer 28 and the sixth wiring layer 48 are metal-bonded by applying pressure. Subsequently, the first buildup layer 20 and the second buildup layer 40 are further bonded by heating. The final heating temperature needs to be equal to or higher than the melting point of the bonding metal material layer 29. As another method, a pierced opening for filling the conductive paste 101 in advance is formed in the prepreg 100 (or a resin sheet in a B-suge state), and after filling the conductive paste 101 in the opening, the first The prepreg 100 may be sandwiched between the build-up layer 20 and the second build-up layer 40, and vacuum pressing may be performed (see FIG. 8).

  In FIG. 8, the size of the portion (land portion) connected to the conductive paste 101 of the sixth wiring layer 48 is the size of the portion (land portion) connected to the conductive paste 101 of the third wiring layer 28. Although it is larger than the size, it is not limited to this, and the size of the opposing land portions may be the same. However, for the following reason, it is desirable that the size of one land portion is larger than the size of the opposite land portion. That is, the prepreg filled with the conductive paste 101 in the penetrating portion is a thin sheet. For this reason, when the prepreg is stacked on the first buildup layer 20 because the alignment hole provided in the first buildup layer 20 can be visually recognized through the thin prepreg, the third wiring layer 28 It is easy to align the conductive paste 101 on the land portion. However, when the second buildup layer 40 is further stacked on the prepreg, it can be said that it is difficult to align the land portion of the sixth wiring layer 48 with the conductive paste 101. Therefore, if the size of the land of the sixth wiring layer 48 is increased, the sixth wiring layer 48 can be obtained even if the land portion of the sixth wiring layer 48 and the position of the conductive paste 101 are slightly shifted. This land portion and the conductive paste 101 can be connected. In other embodiments, the size of the opposing land portions of the first buildup layer 20 and the second buildup layer 40 may be the same, but the bonding metal material layer and the land portion may be the same. It can be said that it is desirable to increase the size of one land portion in order to prevent connection failure due to misalignment.

  Next, an opening 21a is formed in the metal plate 21 in a region including the region where the first conductive pad 22 is formed to expose the first insulating layer 23, and the metal facing the metal plate 21 The plate (41 in FIG. 5B) is removed (step C3; see FIG. 6A). Here, the opening 21a is formed by forming an etching resist 32 having an opening on the surface of the metal plate 21 on the surface opposite to the surface on which the multilayer wiring layer is disposed, and then using the etching resist 32 as a mask. It can be formed by etching only the portion of the metal plate 21 exposed from the opening of the etching resist 32. At this time, the first conductive pad 22 remains by forming the first conductive pad 22 from a metal insoluble in the etching solution used for etching the metal plate 21. Further, the removal of the metal plate (41 in FIG. 5B) does not form an etching resist on the surface of the metal plate (41 in FIG. 5B), but the entire metal plate (41 in FIG. 5B). This is achieved by etching. At this time, the second conductive pad 42 is left by forming the second conductive pad 42 with a metal insoluble in an etching solution used for etching the metal plate 41. The etching resist 32 can be formed by (1) a method of laminating the etching resist 32 by a spin coating method, a die coating method, a curtain coating method, a printing method, or the like when the etching resist 32 is liquid, and (2) an etching resist. When 32 is a dry film, the etching resist 32 is laminated by a laminating method or the like, and then the etching resist 32 is hardened by performing a treatment such as drying. (3) When the etching resist 32 is photosensitive, by a photolithography method or the like There are a method of patterning the etching resist 32, and (4) a method of patterning the etching resist 32 by a laser processing method or the like when the etching resist 32 is non-photosensitive. Note that after the opening 21a is formed (the metal plate (41 in FIG. 5B) is removed), the etching resist 32 is removed.

  Next, the semiconductor element 60 is flip-chip connected to the first conductive pad 22 by the second bump 90, and the sealing resin 70 is poured into the space between the semiconductor element 60 and the first insulating layer 23 and cured. (Step C4; see FIG. 6B).

  Finally, the first bump 80 is mounted on the second conductive pad 42 (step C5; see FIG. 6C).

  According to the printed wiring board configured as described above, since the multilayer wiring layer 11 is provided on the flat metal plate 21, the flatness of the multilayer wiring layer 11 is good. In the semiconductor device, since the semiconductor element 60 is disposed in the opening 21a region of the metal plate 21 and connected to the outermost surface of the flat multilayer wiring layer 11 without warping, the multilayer wiring layer 11 and the semiconductor element 60 are connected. The connection part is stable and reliable. Moreover, since the 1st buildup layer 20 and the 2nd buildup layer 40 are manufactured separately, a yield can be improved. Furthermore, since the first buildup layer 20 and the second buildup layer 40 can be bonded together after being manufactured at the same time, the lead time can be shortened and the tact can be improved. Depending on the specifications of the printed wiring board, the metal plate 21 may be entirely removed by etching.

(Embodiment 2)
Next, a semiconductor device and a printed wiring board according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 9 is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to Embodiment 2 of the present invention. FIG. 10 is a partial cross-sectional view schematically showing, in the order of steps, the main manufacturing process of the cross section of the first buildup layer in the printed wiring board according to Embodiment 2 of the present invention. FIG. 11: is the fragmentary sectional view which showed typically the cross section of the 2nd buildup layer in the printed wiring board concerning Embodiment 2 of this invention about the manufacturing process mainly in order of a process. FIG. 12 is a partial cross-sectional view schematically showing, in the order of steps, the main manufacturing process of the cross section of the printed wiring board according to Embodiment 2 of the present invention. The configuration of the semiconductor device according to the second embodiment is the same as that of the semiconductor device according to the first embodiment, but the manufacturing method is different.

  The manufacturing stage of the first buildup layer 20 will be described. First, a first conductive pad 22, a first insulating layer 23, a first wiring layer 24, a surface of a metal plate 21 (for example, a copper plate), The second insulating layer 25, the second wiring layer 26, the third insulating layer 27, the third wiring layer 28, and vias connecting the respective wiring layers are formed (step D1; see FIG. 10A). ). In addition, the process of step D1 is based on the process of step A1-A5 of Embodiment 1. FIG.

  Next, a pin-shaped bonding metal material layer 29 (for example, solder) is formed on the surface of the third wiring layer 28 (step D2; see FIG. 10B). Here, as a method for making the bonding metal material layer 29 into a pin shape, a molten bonding metal material is attached to the surface of the third wiring layer 28, and then a needle-shaped jig is brought into contact with the bonding metal material. Then, it can be formed by pulling up the jig. In FIG. 10B, the pin-shaped bonding metal material layer 29 is formed on the surface of the third wiring layer 28. The purpose of forming the bonding metal material layer 29 is to provide the third wiring layer 28. Since the layer 28 and the sixth wiring layer (48 in FIG. 11A) are bonded, a pin-shaped bonding metal material is formed on the surface of the sixth wiring layer (48 in FIG. 11A). Layer 29 may be formed.

  Next, the manufacturing stage of the second buildup layer will be described. First, the second conductive pad 42, the fourth insulating layer 43, and the fourth wiring layer are formed on the surface of the metal plate 41 (for example, a copper plate). 44, a fifth insulating layer 45, a fifth wiring layer 46, a sixth insulating layer 47, and a sixth wiring layer 48 are formed (step E1; see FIG. 11A). In addition, the process of step E1 is based on the process of step B1-B5 of Embodiment 1. FIG.

  Next, the bonding adhesive layer 50 is formed on the surface of the sixth insulating layer 47 including the sixth wiring layer 48 (step E2; see FIG. 11B). The method for forming the bonding adhesive layer 50 is the same as in step A7 of the first embodiment. In FIG. 11B, an example in which the bonding adhesive layer 50 is formed on the surface of the sixth insulating layer 47 is shown. However, the bonding adhesion is performed on the surface of the third insulating layer (27 in FIG. 10A). The layer 50 may be formed, or may be formed on both surfaces of the third insulating layer (27 in FIG. 10A) and the sixth insulating layer 47.

  Next, the bonding stage will be described. First, the first buildup layer 20 and the second buildup layer 40 are aligned and face each other so that the metal plates 21 and 41 face outward (step F1; FIG. 12 (A)). The alignment method is the same as step C1 in the first embodiment.

  Next, the aligned first buildup layer 20 and second buildup layer 40 are bonded together (step F2; see FIG. 12B). In addition, about the bonding method, it is the same as that of step C2 of Embodiment 1. FIG. The processes after step F2 are the same as steps C3 to C5 (see FIG. 6) of the first embodiment. Since the bonding metal material 29 has a pin shape, the bonding adhesive layer 50 is pierced and the bonding adhesive layer 50 is pushed away, so that the electrical bonding between the pads is ensured.

  According to the second embodiment, the same effect as the first embodiment is obtained.

1A is a perspective view from the front surface side, FIG. 2B is a perspective view from the back surface side, and FIG. 2C is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention. It is the fragmentary sectional view which showed typically the cross section of the 1st buildup layer in the printed wiring board concerning Embodiment 1 of this invention about the first half of the main manufacturing processes in order of the process. It is the fragmentary sectional view which showed typically the cross section of the 1st buildup layer in the printed wiring board which concerns on Embodiment 1 of this invention about the second half of the main manufacturing processes in order of the process. It is the fragmentary sectional view which showed typically the cross section of the 2nd buildup layer in the printed wiring board which concerns on Embodiment 1 of this invention mainly on the manufacturing process in order of the process. It is the fragmentary sectional view which showed typically the cross section of the printed wiring board which concerns on Embodiment 1 of this invention about the first half of the main manufacturing processes in order of the process. It is the fragmentary sectional view which showed typically the cross section of the printed wiring board which concerns on Embodiment 1 of this invention about the latter half of the main manufacturing processes in order of the process. It is the top view shown typically about the division of the 1st buildup layer in the printed wiring board concerning Embodiment 1 of the present invention. It is the fragmentary sectional view which showed typically the structure of the modification of the semiconductor device which concerns on Embodiment 1 of this invention. It is the fragmentary sectional view which showed typically the structure of the semiconductor device which concerns on Embodiment 2 of this invention. It is the fragmentary sectional view which showed typically the cross section of the 1st buildup layer in the printed wiring board concerning Embodiment 2 of this invention about the main manufacturing process in order of the process. It is the fragmentary sectional view which showed typically the cross section of the 2nd buildup layer in the printed wiring board which concerns on Embodiment 2 of this invention mainly on the manufacturing process in order of a process. It is the fragmentary sectional view which showed typically the cross section of the printed wiring board which concerns on Embodiment 2 of this invention about the main manufacturing process in order of the process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Printed wiring board 11 Multilayer wiring layer 20 1st buildup layer 21 Metal plate 21a Opening part 21b Positioning hole 22 1st electroconductive pad 23 1st insulating layer 23a Opening part 24 1st wiring layer 25 2nd insulating layer 26 2nd wiring layer 27 3rd insulating layer 28 3rd wiring layer 29 Joining metal material layer 30 Bonding adhesion layer 31 Plating resist 31a Opening part 32 Etching resist 40 2nd buildup layer 41 Metal plate 41a Positioning hole 42 Second conductive pad 43 Fourth insulating layer 43a Opening 44 Fourth wiring layer 45 Fifth insulating layer 46 Fifth wiring layer 47 Sixth insulating layer 48 Sixth wiring Layer 49 Plating resist 49a Opening 50 Bonding adhesive layer 60 Semiconductor element 70 Sealing resin 80 First bump 90 Second bump 100 Prepre 101 conductive paste

Claims (6)

A semiconductor element;
Bumps connected to the electrode terminals of the semiconductor element;
A first conductive pad connected to the bump;
A plurality of wiring layers and insulating layers are alternately stacked, the wiring layers are connected by vias, and the vias are closer to the first surface than the diameter on the first surface side where the semiconductor element is disposed. A first buildup layer configured such that the diameter on the opposite second surface side is wider , and the via closest to the semiconductor element among the vias is connected to the first conductive pad When,

A plurality of wiring layers and insulating layers are alternately stacked, the wiring layers are connected by vias, and the vias have a larger diameter on the first surface side than the diameter on the second surface side. And a second buildup layer bonded to the second surface side of the first buildup layer,
The second buildup layer is disposed on the second surface side of the second buildup layer, and is connected to the via disposed in the second surface side among the vias in the second buildup layer. Conductive pads of
A metal plate disposed on the first surface of the first buildup layer and having an opening for accommodating the semiconductor element;
Equipped with a,
The via in the first buildup layer is configured integrally with the wiring layer adjacent in the portion on the second surface side,
The via in the second buildup layer is configured integrally with the wiring layer adjacent in the portion on the first surface side,
One or both of the insulating layer of the first buildup layer and the insulating layer of the second buildup layer are any one of glass cloth, glass nonwoven fabric, aramid nonwoven fabric, aramid film, and polyimide film. A semiconductor device comprising an insulating resin including the above reinforcing material . Disposed between the first buildup layer and the second buildup layer, and for joining the wiring layer of the first buildup layer and the wiring layer of the second buildup layer A metal material layer;
Bonding adhesion between the first buildup layer and the second buildup layer, and bonding the insulating layer of the first buildup layer to the insulating layer of the second buildup layer Layers,
The semiconductor device according to claim 1, further comprising: It is arranged between the first buildup layer and the second buildup layer, and electrically connects the wiring layer of the first buildup layer and the wiring layer of the second buildup layer. The semiconductor device according to claim 1, further comprising an anisotropic conductive film. It is arranged between the first buildup layer and the second buildup layer, and electrically connects the wiring layer of the first buildup layer and the wiring layer of the second buildup layer. The semiconductor device according to claim 1, further comprising a conductive paste. It is arranged between the first buildup layer and the second buildup layer, contains powdered solder, resin, solvent, and the wiring layer of the first buildup layer and the second The semiconductor device according to claim 1, further comprising a solder paste layer that electrically connects the wiring layer of the build-up layer. The land portion in the wiring layer closest to the second surface of the first buildup layer is different in size from the land portion in the wiring layer closest to the first surface of the second buildup layer. The semiconductor device according to claim 1, wherein:

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