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JP3918566B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP3918566B2
JP3918566B2 JP2002016566A JP2002016566A JP3918566B2 JP 3918566 B2 JP3918566 B2 JP 3918566B2 JP 2002016566 A JP2002016566 A JP 2002016566A JP 2002016566 A JP2002016566 A JP 2002016566A JP 3918566 B2 JP3918566 B2 JP 3918566B2
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Prior art keywords
circuit board
printed circuit
resin
mold
semiconductor device
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JP2003218365A (en
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孝広 堂原
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12043—Photo diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Led Device Packages (AREA)
  • Light Receiving Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, and its manufacturing method, in which the quality of a product is enhanced by preventing the leakage of resin from a die at the time of filling it with resin. <P>SOLUTION: In the semiconductor device 1 where a required wiring pattern 2 and a resist pattern 3 are formed on both sides of a printed board 10, a photodiode chip 4 and an IC chip 5 are mounted on the surface of the printed board 10, a first die 14 abutting against the printed board 10 while covering the photodiode chip 4 and the IC chip 5 is filled with resin which eventually cures to form a resin package 7, a plurality of terminal patterns 11 are formed at positions on the rear surface of the printed board 10 facing abutting lines 8 and 9 of the first die 14, and dummy patterns 12 and 13 are formed along the abutting lines 8 and 9 in the gap between the plurality of terminal patterns 11. <P>COPYRIGHT: (C)2003,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、プリント基板上に面実装される半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
従来、プリント基板上に半導体チップを搭載し、これをトランスファー樹脂モールドによりパッケージする技術が多く行われている。また、樹脂モールド時の樹脂漏れを防止する方法も公開されている。
【０００３】
図５に示すように、特開２００１−１４８５０６には、以下の製造方法が開示されている。
【０００４】
この方法は、基板８０の表面に、発光素子８１および受光素子８２の組を各組ごとに区画化して搭載するためのチップエリア８３を設けるとともに、これらのチップエリア８３に上記基板の厚み方向に貫通するスルーホール８４を設けておき、各チップエリア８３に搭載された発光素子８１および受光素子８２を封止する際には、基板８０の表面に樹脂成形用の金型を用いて樹脂パッケージ８５を形成する、赤外線データ通信モジュールの製造方法であって、基板８０の表面に樹脂パッケージ８５を形成する前、基板８０の裏面にあってチップエリア８３と対極する各箇所には、そのチップエリア８３と同大のダミーエリア８６を区画形成しておくことを特徴とするものである。
【０００５】
ダミーエリアを設けることによって、基板の表面側に樹脂を充填したときに、スルーホールを通じて樹脂の一部が裏面へ廻り込むことを防止できるとしている。
【０００６】
【発明が解決しようとする課題】
しかしながら、チップエリアは基板の表側の中央付近にあるため、ダミーエリアも基板の裏側の中央付近に形成され、基板の周辺部は、中央部より厚みが薄くなる。樹脂を充填するときに基板の裏側に当接する金型は、基板の中央部のダミーエリアに当接し、周辺部は浮いた状態になっている。この状態で表側の金型を基板に当接させ、圧力を加えて樹脂を注入すると、基板の周辺部が裏側に曲がってしまい、金型が当接する基板の表側から樹脂が漏れてしまうという問題が発生する。
【０００７】
そこで本発明は、樹脂を充填するときに金型から樹脂が漏れることを防止して製品の品質を向上させる半導体装置及びその製造方法を提供することを目的とする。
【０００８】
【課題を解決するための手段】
本発明の半導体装置においては、プリント基板の裏面の複数の端子パターンの間に、当接ラインに沿ってダミーパターンを形成したものである。
【０００９】
この発明によれば、樹脂を充填するときに金型から樹脂が漏れることを防止して製品の品質を向上させる半導体装置が得られる。
【００１０】
【発明の実施の形態】
本発明の請求項１に記載の発明は、両面に必要な配線パターン及びレジストパターンを形成したプリント基板と、前記プリント基板の表面に搭載された半導体チップと、この半導体チップを覆って前記プリント基板に表側から当接し、内部に樹脂を充填する第１の金型及び前記プリント基板の裏側に当接する第２の金型を用いて形成された樹脂パッケージとを備えた半導体装置において、前記プリント基板の裏面の配線パターンは、前記第１の金型の当接ラインに対向する位置に形成された複数の端子パターンを備え、しかも前記複数の端子パターンの間には、前記当接ラインに沿って形成され、樹脂充填時の前記プリント基板の曲がりを防止するダミーパターンを有していることを特徴とする半導体装置としたものであり、端子パターンの間の隙間がダミーパターンによって塞がれるので、端子パターン及びダミーパターンが裏側の第２の金型に当接し、樹脂の充填を行うときに基板が裏側に曲がることがなくなり、樹脂が漏れることが防止されるという作用を有する。
【００１１】
請求項２に記載の発明は、前記プリント基板の表面の、前記ダミーパターンに対向する位置に、前記プリント基板と前記第１の金型との間の隙間を埋める補助ダミーパターンを形成したことを特徴とする請求項１に記載の半導体装置であり、表側の第１の金型とプリント基板との間の隙間を塞いで、樹脂漏れを確実に防止するという作用を有する。
【００１２】
請求項３に記載の発明は、プリント基板の両面に必要な配線パターン及びレジストパターンを形成する工程と、前記プリント基板の表面に半導体チップを搭載し、電気的に接続する工程と、この半導体チップを覆って前記プリント基板に当接する第１の金型内に、樹脂を充填して固化させ、樹脂パッケージを形成する工程とを有する半導体装置の製造方法において、前記プリント基板に配線パターンを形成する工程では、前記プリント基板の裏面の、前記第１の金型の当接ラインに対向する位置に、複数の端子パターンを形成し、前記複数の端子パターンの間の隙間に、前記当接ラインに沿ってダミーパターンを形成し、前記樹脂パッケージを形成する工程では、前記端子パターン及び前記ダミーパターンで前記プリント基板の裏面を支持することを特徴とする半導体装置の製造方法であり、ダミーパターンの形成を、必要な配線パターンを形成する工程と同時に行うことができるという作用を有する。また、樹脂パッケージを形成するときにプリント基板の裏面を支持するので、通常の作業条件で基板の曲がりを防止して樹脂漏れが防止されるという作用を有する。
【００１３】
以下、本発明の実施の形態について、図１から図３を用いて説明する。
【００１４】
（実施の形態１）
図１（Ａ）は本発明の第１の実施の形態に係る半導体装置の平断面図、（Ｂ）は同半導体装置の側面図、図２は同半導体装置の底面図である。図１、図２においてプリント基板１０の両面には、必要な配線パターン２及び斜線で示すレジストパターン３が形成されている。
【００１５】
プリント基板１０の表面には、３台の半導体装置１が一列に並んで形成されている。各半導体装置１は、ホトダイオードチップ４およびこれを駆動するＩＣチップ５を搭載しており、このホトダイオードチップ４およびＩＣチップ５は、所定の配線パターン２にワイヤ６によりボンディングされ、電気的に接続されている。
【００１６】
プリント基板１０の表側には、長手方向に沿った両側にそれぞれ少しの隙間をあけて、樹脂パッケージ７が、ホトダイオードチップ４およびＩＣチップ５を覆うと共に台形状に形成されている。
【００１７】
樹脂パッケージ７は、プリント基板１０の長手方向に沿った両側に当接ライン８，９のそれぞれ外側に当接する第１の金型１４（図３参照）内に、樹脂を充填して固化させることによって形成されている。
【００１８】
なお、樹脂パッケージ７を形成するときには、プリント基板１０の裏側には、図示しない平板状の第２の金型１５（図３参照）が当接し、充填時の樹脂の圧力を受けている。
【００１９】
図２に示すように、プリント基板１０の裏面の、第１の金型１４の当接ライン８，９に対向する位置には、複数の端子パターン１１が形成されている。各端子パターン１１は、３台の半導体装置１の四隅にそれぞれ配置されている。
【００２０】
プリント基板１０の長手方向に沿った両側にそれぞれ設けられた複数の端子パターン１１の間の隙間には、当接ライン８，９に沿ってダミーパターン１２，１３がそれぞれ形成されている。
【００２１】
図３（Ａ）は半導体装置の部分拡大正面図、（Ｂ）は同半導体装置の側断面図である。
【００２２】
ダミーパターン１２，１３の厚みは、端子パターン１１の厚みとほぼ同じ３０μｍ程度に形成されている。かかる構成によって、ダミーパターン１２，１３は、樹脂の充填時に、端子パターン１１と共に第２の金型１５に当接する。
【００２３】
図３（Ｂ）に示すように、プリント基板１０にはレジストパターン３が設けられているが、レジストは、固化するまでに基板の周辺部から側方に流れるため、プリント基板１０の上面の周辺部の膜厚は１０μｍ程度になり、中央部より厚みが薄くなっている。しかし、下面には、ダミーパターン１２，１３が形成されているので、レジストの膜厚が中央部と同程度となるように形成されている。レジストの膜厚が均一になるので、プリント基板１０の平面状態を均一にして、製品の品質を安定させることができる。
【００２４】
また、樹脂パッケージ７を形成するときには、第２の金型１５でプリント基板１０の裏面を押さえ、第１の金型１４でプリント基板１０の表面を押さえる。このとき、プリント基板１０の裏面にはダミーパターン１２，１３が形成されているので、レジストパターン３の厚みと、少なくとも端子パターン１１とダミーパターン１２，１３を第２の金型１５に当接させることができる。
【００２５】
第１の金型１４は、プリント基板１０の表側の当接ライン８，９の外側部分に当接した状態で、内部に樹脂を充填し、固化させるので、プリント基板１０が変形すると、当接ライン８，９の外側に樹脂が漏れることになる。本実施の形態においては、ダミーパターン１２，１３が設けられているので、プリント基板１０に加わる力を第２の金型１５で確実に受けてプリント基板１０の変形を防止することができ、樹脂漏れを防止することができる。
【００２６】
次に、半導体装置の製造方法について説明する。
【００２７】
（プリント基板形成工程）
エッチング等を用いて、プリント基板１０の両面に必要な配線パターン２及びレジストパターン３を形成する。このとき、プリント基板１０の裏面の、第１の金型１４の当接ライン８，９に対向する位置に、複数の端子パターン１１を形成し、複数の端子パターン１１の間の隙間に、当接ライン８，９に沿ってダミーパターン１２，１３を形成する。
【００２８】
ダミーパターン１２，１３は、配線パターン２及び端子パターン１１と同時に形成することができるので、時間や手間を増加させずにプリント基板１０を製造することができる。
【００２９】
（チップ搭載工程）
プリント基板１０の表面にホトダイオードチップ４およびＩＣチップ５を搭載し、ワイヤボンディングを行い、プリント基板１０とホトダイオードチップ４およびＩＣチップ５とを電気的に接続する。
【００３０】
（樹脂パッケージ形成工程）
端子パターン１１及びダミーパターン１２，１３でプリント基板１０の裏面を第２の金型１５に当接させて支持し、プリント基板１０上のホトダイオードチップ４およびＩＣチップ５を覆ってプリント基板１０に当接する第１の金型１４内に、樹脂を充填して固化させ、樹脂パッケージ７を形成する。
【００３１】
端子パターン１１及びダミーパターン１２，１３でプリント基板１０の裏面を第２の金型１５に当接させて支持するので、製造装置と部品の精度を緩和すると共に型締め圧力を小さくして製品にかかる負担を減らし、また、プリント基板１０の曲がり及び樹脂漏れを防止するので、長期間連続的に安定して製造を行うことができる。
【００３２】
（実施の形態２）
図４に本発明の第２の実施の形態に係る半導体装置の部分拡大正面図を示す。半導体装置１６は、前述した第１の実施の形態に係る半導体装置１のプリント基板１０の表面の、ダミーパターン１２，１３に対向する位置に、補助ダミーパターン１７を形成したものである。なお、他の部分の構成は同じであるので、同一部材には同一符号を付して説明は省略する。
【００３３】
補助ダミーパターン１７が表側の第１の金型１４に当接するので、隙間をさらに小さくして樹脂漏れを確実に防止できる。
【００３４】
本実施の形態では半導体チップの一例としてホトダイオードを用いて説明したが、ホトダイオードに限定されるものではなく、発光ダイオード等の他の半導体チップでもかまわない。
【００３５】
【発明の効果】
以上のように本発明によれば、端子パターンの間の隙間に第１の金型の当接ラインに沿ってダミーパターンが形成されているので、端子パターン及びダミーパターンが裏側の第２の金型に当接し、樹脂の充填を行うときに基板が裏側に曲がることがなくなり、樹脂が漏れることが防止され、製品の品質を向上させることができる。
【００３６】
また、補助ダミーパターンを形成すると、表側の第１の金型とプリント基板との間の隙間を塞いで、樹脂漏れを確実に防止して、製品の品質をさらに向上させることができる。
【図面の簡単な説明】
【図１】（Ａ）は本発明の第１の実施の形態に係る半導体装置の平断面図
（Ｂ）は同半導体装置の側面図
【図２】同半導体装置の底面図
【図３】（Ａ）は同半導体装置の部分拡大正面図
（Ｂ）は同半導体装置の側断面図
【図４】本発明の第２の実施の形態に係る半導体装置の部分拡大正面図
【図５】従来例に係る赤外線データ通信モジュールの製造方法を示す説明図
【符号の説明】
１ 半導体装置
２ 配線パターン
３ レジストパターン
４ ホトダイオードチップ
５ ＩＣチップ
６ ワイヤ
７ 樹脂パッケージ
８，９ 当接ライン
１０ プリント基板
１１ 端子パターン
１２，１３ ダミーパターン
１４ 第１の金型
１５ 第２の金型
１６ 半導体装置
１７ 補助ダミーパターン[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device surface-mounted on a printed circuit board and a manufacturing method thereof.
[0002]
[Prior art]
Conventionally, many techniques for mounting a semiconductor chip on a printed circuit board and packaging it with a transfer resin mold have been performed. A method for preventing resin leakage during resin molding is also disclosed.
[0003]
As shown in FIG. 5, Japanese Patent Laid-Open No. 2001-148506 discloses the following manufacturing method.
[0004]
In this method, on the surface of the substrate 80, a chip area 83 for partitioning and mounting a set of the light emitting element 81 and the light receiving element 82 for each set is provided, and the chip area 83 is provided in the thickness direction of the substrate. When a through hole 84 is provided so as to seal the light emitting element 81 and the light receiving element 82 mounted in each chip area 83, a resin package 85 is used by using a mold for resin molding on the surface of the substrate 80. Before forming the resin package 85 on the surface of the substrate 80, the chip area 83 is provided at each position on the back surface of the substrate 80 opposite to the chip area 83. And a dummy area 86 having the same size as that of the first and second sections.
[0005]
By providing the dummy area, when the resin is filled on the front side of the substrate, it is possible to prevent a part of the resin from going to the back side through the through hole.
[0006]
[Problems to be solved by the invention]
However, since the chip area is near the center on the front side of the substrate, the dummy area is also formed near the center on the back side of the substrate, and the peripheral portion of the substrate is thinner than the central portion. The mold that abuts on the back side of the substrate when the resin is filled abuts on the dummy area at the center of the substrate, and the peripheral portion is in a floating state. In this state, when the front mold is brought into contact with the substrate and pressure is applied to inject the resin, the peripheral portion of the substrate is bent to the back side, and the resin leaks from the front side of the substrate in contact with the mold. Occurs.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that prevent the resin from leaking from the mold when filling the resin and improve the quality of the product.
[0008]
[Means for Solving the Problems]
In the semiconductor device of the present invention, a dummy pattern is formed along the contact line between the plurality of terminal patterns on the back surface of the printed circuit board.
[0009]
According to the present invention, it is possible to obtain a semiconductor device that improves the quality of a product by preventing the resin from leaking from the mold when the resin is filled.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
According to the first aspect of the present invention, there is provided a printed circuit board on which necessary wiring patterns and resist patterns are formed on both sides, a semiconductor chip mounted on the surface of the printed circuit board, and the printed circuit board covering the semiconductor chip. In the semiconductor device, the printed circuit board includes: a first mold that contacts from the front side and a resin mold that is formed using a second mold that contacts the back side of the printed board; The wiring pattern on the back surface of the substrate includes a plurality of terminal patterns formed at positions facing the contact line of the first mold, and between the plurality of terminal patterns, along the contact line. A semiconductor device characterized by having a dummy pattern that is formed and has a dummy pattern that prevents bending of the printed circuit board during resin filling, The gap between the terminal pattern and the dummy pattern is closed by the dummy pattern, so that the terminal pattern and the dummy pattern are in contact with the second mold on the back side, so that the substrate is not bent to the back side when the resin is filled and the resin is prevented from leaking. Has the effect of being
[0011]
According to the second aspect of the present invention, an auxiliary dummy pattern that fills a gap between the printed circuit board and the first mold is formed on the surface of the printed circuit board at a position facing the dummy pattern. The semiconductor device according to claim 1, wherein the semiconductor device has an action of blocking a gap between the first mold on the front side and the printed circuit board and reliably preventing resin leakage.
[0012]
According to a third aspect of the present invention, there are provided a step of forming a wiring pattern and a resist pattern necessary on both sides of a printed circuit board, a step of mounting a semiconductor chip on the surface of the printed circuit board and electrically connecting the semiconductor chip, and the semiconductor chip. A wiring pattern is formed on the printed circuit board in a method of manufacturing a semiconductor device, the method comprising: filling a resin in a first mold that is in contact with the printed circuit board and solidifying the resin mold to form a resin package In the process, a plurality of terminal patterns are formed on the back surface of the printed circuit board at positions facing the contact lines of the first mold, and the contact lines are formed in the gaps between the plurality of terminal patterns. In the step of forming a dummy pattern along the resin package, the back surface of the printed circuit board is supported by the terminal pattern and the dummy pattern. It is a method of manufacturing a semiconductor device according to claim, has the effect of the formation of the dummy pattern can be carried out simultaneously with the step of forming a required wiring pattern. Further, since the back surface of the printed circuit board is supported when the resin package is formed, it has an effect of preventing the leakage of the resin by preventing the board from being bent under normal working conditions.
[0013]
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.
[0014]
(Embodiment 1)
1A is a plan sectional view of the semiconductor device according to the first embodiment of the present invention, FIG. 1B is a side view of the semiconductor device, and FIG. 2 is a bottom view of the semiconductor device. 1 and 2, a necessary wiring pattern 2 and a resist pattern 3 indicated by oblique lines are formed on both surfaces of the printed circuit board 10.
[0015]
Three semiconductor devices 1 are formed in a line on the surface of the printed circuit board 10. Each semiconductor device 1 includes a photodiode chip 4 and an IC chip 5 that drives the photodiode chip 4. The photodiode chip 4 and the IC chip 5 are bonded to a predetermined wiring pattern 2 by wires 6 and are electrically connected. ing.
[0016]
On the front side of the printed circuit board 10, a resin package 7 is formed in a trapezoidal shape while covering the photodiode chip 4 and the IC chip 5 with a small gap on each side along the longitudinal direction.
[0017]
The resin package 7 is solidified by filling the resin into a first mold 14 (see FIG. 3) that contacts the outside of the contact lines 8 and 9 on both sides along the longitudinal direction of the printed circuit board 10. Is formed by.
[0018]
When the resin package 7 is formed, a flat plate-shaped second mold 15 (see FIG. 3) (not shown) is in contact with the back side of the printed circuit board 10 and receives the pressure of the resin during filling.
[0019]
As shown in FIG. 2, a plurality of terminal patterns 11 are formed on the back surface of the printed circuit board 10 at positions facing the contact lines 8 and 9 of the first mold 14. Each terminal pattern 11 is arranged at each of the four corners of the three semiconductor devices 1.
[0020]
Dummy patterns 12 and 13 are formed along the contact lines 8 and 9 in the gaps between the plurality of terminal patterns 11 respectively provided on both sides along the longitudinal direction of the printed circuit board 10.
[0021]
3A is a partially enlarged front view of the semiconductor device, and FIG. 3B is a side sectional view of the semiconductor device.
[0022]
The thickness of the dummy patterns 12 and 13 is approximately 30 μm, which is substantially the same as the thickness of the terminal pattern 11. With this configuration, the dummy patterns 12 and 13 come into contact with the second mold 15 together with the terminal pattern 11 when the resin is filled.
[0023]
As shown in FIG. 3B, the printed circuit board 10 is provided with a resist pattern 3. However, since the resist flows laterally from the periphery of the substrate until it is solidified, the periphery of the upper surface of the printed circuit board 10 is used. The film thickness of the part is about 10 μm, and the thickness is thinner than the central part. However, since the dummy patterns 12 and 13 are formed on the lower surface, the resist is formed so that the thickness of the resist is approximately the same as that of the central portion. Since the resist film thickness becomes uniform, the plane state of the printed circuit board 10 can be made uniform, and the product quality can be stabilized.
[0024]
Further, when forming the resin package 7, the back surface of the printed circuit board 10 is pressed by the second mold 15, and the front surface of the printed circuit board 10 is pressed by the first mold 14. At this time, since the dummy patterns 12 and 13 are formed on the back surface of the printed circuit board 10, the thickness of the resist pattern 3 and at least the terminal pattern 11 and the dummy patterns 12 and 13 are brought into contact with the second mold 15. be able to.
[0025]
The first mold 14 is filled with resin and solidified in a state where the first mold 14 is in contact with the outer side portions of the contact lines 8 and 9 on the front side of the printed circuit board 10. Resin leaks outside the lines 8 and 9. In the present embodiment, since the dummy patterns 12 and 13 are provided, the force applied to the printed board 10 can be reliably received by the second mold 15 to prevent the printed board 10 from being deformed. Leakage can be prevented.
[0026]
Next, a method for manufacturing a semiconductor device will be described.
[0027]
(Printed circuit board formation process)
The necessary wiring pattern 2 and resist pattern 3 are formed on both surfaces of the printed circuit board 10 using etching or the like. At this time, a plurality of terminal patterns 11 are formed on the back surface of the printed circuit board 10 at positions facing the contact lines 8 and 9 of the first mold 14 and the gaps between the plurality of terminal patterns 11 are applied. Dummy patterns 12 and 13 are formed along the tangent lines 8 and 9.
[0028]
Since the dummy patterns 12 and 13 can be formed simultaneously with the wiring pattern 2 and the terminal pattern 11, the printed circuit board 10 can be manufactured without increasing time and labor.
[0029]
(Chip mounting process)
The photodiode chip 4 and the IC chip 5 are mounted on the surface of the printed circuit board 10 and wire bonding is performed to electrically connect the printed circuit board 10 to the photodiode chip 4 and the IC chip 5.
[0030]
(Resin package forming process)
The terminal pattern 11 and the dummy patterns 12 and 13 support the back surface of the printed circuit board 10 in contact with the second mold 15, cover the photodiode chip 4 and the IC chip 5 on the printed circuit board 10 and contact the printed circuit board 10. A resin package 7 is formed by filling and solidifying the resin in the first mold 14 in contact therewith.
[0031]
The terminal pattern 11 and the dummy patterns 12 and 13 support the back surface of the printed circuit board 10 in contact with the second mold 15, thereby reducing the precision of the manufacturing apparatus and parts and reducing the mold clamping pressure. This burden is reduced, and the printed circuit board 10 is prevented from bending and leaking, so that it can be manufactured stably for a long period of time.
[0032]
(Embodiment 2)
FIG. 4 shows a partially enlarged front view of a semiconductor device according to the second embodiment of the present invention. In the semiconductor device 16, auxiliary dummy patterns 17 are formed at positions facing the dummy patterns 12 and 13 on the surface of the printed circuit board 10 of the semiconductor device 1 according to the first embodiment described above. In addition, since the structure of another part is the same, the same code | symbol is attached | subjected to the same member and description is abbreviate | omitted.
[0033]
Since the auxiliary dummy pattern 17 comes into contact with the first mold 14 on the front side, the gap can be further reduced to reliably prevent resin leakage.
[0034]
In this embodiment, a photodiode is used as an example of the semiconductor chip. However, the present invention is not limited to the photodiode, and other semiconductor chips such as a light emitting diode may be used.
[0035]
【The invention's effect】
As described above, according to the present invention, since the dummy pattern is formed along the contact line of the first mold in the gap between the terminal patterns, the terminal pattern and the dummy pattern are the second metal on the back side. When the resin is in contact with the mold and the resin is filled, the substrate is not bent to the back side, the resin is prevented from leaking, and the quality of the product can be improved.
[0036]
In addition, when the auxiliary dummy pattern is formed, the gap between the first mold on the front side and the printed board can be closed, and resin leakage can be reliably prevented, thereby further improving the quality of the product.
[Brief description of the drawings]
1A is a plan sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 1B is a side view of the semiconductor device, FIG. 2 is a bottom view of the semiconductor device, and FIG. FIG. 4A is a partially enlarged front view of the semiconductor device. FIG. 4B is a side sectional view of the semiconductor device. FIG. 4 is a partially enlarged front view of the semiconductor device according to the second embodiment of the invention. Demonstrating the manufacturing method of the infrared data communication module according to the above
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Wiring pattern 3 Resist pattern 4 Photodiode chip 5 IC chip 6 Wire 7 Resin package 8 and 9 Contact line 10 Printed circuit board 11 Terminal pattern 12 and 13 Dummy pattern 14 1st metal mold 15 2nd metal mold 16 Semiconductor device 17 Auxiliary dummy pattern

Claims (3)

両面に必要な配線パターン及びレジストパターンを形成したプリント基板と、前記プリント基板の表面に搭載された半導体チップと、この半導体チップを覆って前記プリント基板に表側から当接し、内部に樹脂を充填する第１の金型及び前記プリント基板の裏側に当接する第２の金型を用いて形成された樹脂パッケージとを備えた半導体装置において、
前記プリント基板の裏面の配線パターンは、前記第１の金型の当接ラインに対向する位置に形成された複数の端子パターンを備え、
しかも前記複数の端子パターンの間には、前記当接ラインに沿って形成され、樹脂充填時の前記プリント基板の曲がりを防止するダミーパターンを有していることを特徴とする半導体装置。A printed circuit board on which wiring patterns and resist patterns necessary on both sides are formed, a semiconductor chip mounted on the surface of the printed circuit board, and abuts on the printed circuit board from the front side so as to cover the semiconductor chip and fills the inside with resin In a semiconductor device comprising a first mold and a resin package formed using a second mold that contacts the back side of the printed circuit board,
The wiring pattern on the back surface of the printed board includes a plurality of terminal patterns formed at positions facing the contact line of the first mold,
In addition, the semiconductor device has a dummy pattern which is formed along the contact line between the plurality of terminal patterns to prevent the printed circuit board from being bent during resin filling. 前記プリント基板の表面の、前記ダミーパターンに対向する位置に、前記プリント基板と前記第１の金型との間の隙間を埋める補助ダミーパターンを形成したことを特徴とする請求項１に記載の半導体装置。The auxiliary dummy pattern which fills the clearance gap between the said printed circuit board and the said 1st metal mold | die in the position which opposes the said dummy pattern on the surface of the said printed circuit board is formed. Semiconductor device. プリント基板の両面に必要な配線パターン及びレジストパターンを形成する工程と、前記プリント基板の表面に半導体チップを搭載し、電気的に接続する工程と、この半導体チップを覆って前記プリント基板に当接する第１の金型内に、樹脂を充填して固化させ、樹脂パッケージを形成する工程とを有する半導体装置の製造方法において、
前記プリント基板に配線パターンを形成する工程では、前記プリント基板の裏面の、前記第１の金型の当接ラインに対向する位置に、複数の端子パターンを形成し、前記複数の端子パターンの間の隙間に、前記当接ラインに沿ってダミーパターンを形成し、
前記樹脂パッケージを形成する工程では、前記端子パターン及び前記ダミーパターンで前記プリント基板の裏面を支持することを特徴とする半導体装置の製造方法。Forming a necessary wiring pattern and resist pattern on both sides of the printed circuit board, mounting a semiconductor chip on the surface of the printed circuit board, and electrically connecting the semiconductor chip; covering the semiconductor chip and contacting the printed circuit board In a method for manufacturing a semiconductor device, the method includes: filling a resin into a first mold and solidifying the resin to form a resin package;
In the step of forming a wiring pattern on the printed circuit board, a plurality of terminal patterns are formed on the back surface of the printed circuit board at a position facing the contact line of the first mold, and between the plurality of terminal patterns. Forming a dummy pattern along the contact line in the gap,
In the step of forming the resin package, a back surface of the printed board is supported by the terminal pattern and the dummy pattern.
JP2002016566A 2002-01-25 2002-01-25 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3918566B2 (en)

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