JP3899784B2 - Clock control device, semiconductor integrated circuit device, microcomputer and electronic device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock control device, a semiconductor integrated circuit device including the clock control device, a microcomputer, and an electronic apparatus.
[0002]
[Background Art and Problems to be Solved by the Invention]
2. Description of the Related Art Conventionally, microcomputers that control electronic devices (particularly portable electronic devices) such as PDAs and mobile communication terminals have been improved not only in circuit technology and process technology, but also in architecture and improved integration technology. Low power consumption is achieved.
[0003]
Such a microcomputer includes a CPU core that realizes performance and code size suitable for the application, and peripheral circuits (macro blocks such as a direct memory access circuit (DMA) and a memory control circuit) in which necessary functions are macroized in advance. ). Therefore, many of the microcomputers up to now can reduce the development man-hours and maintain the design quality, but have had to use the CPU core and the macro block as a block box. For this reason, when improving various performances of the microcomputer, it is difficult to change the inside of these cores and macro blocks.
[0004]
In particular, when improving the power consumption of an integrated microcomputer, it is often related to the architecture and circuit configuration of the CPU core and macro block, so the power consumption is reduced in parts other than the CPU core and macro block. It was necessary to plan.
[0005]
For example, the power consumption can be reduced most simply and efficiently by stopping a clock signal supplied to each unit dynamically or statically in a microcomputer.
[0006]
Or, for example, when a clock signal supplied to a given unit is stopped by a signal from the outside, or when a CPU operation is temporarily stopped by a HALT instruction executed by the CPU core, a cache device that does not require operation is used. In some cases, the supplied clock signal is stopped.
[0007]
In many microcomputers, in addition to the CPU core, a cache device (comprising a cache memory and a cache control device) and a memory control circuit are integrated.
[0008]
The cache device temporarily speeds up the access time of the memory circuit connected to the outside by temporarily buffering data accessed locally and locally by the CPU core.
[0009]
The memory control circuit has a memory interface function that performs complex memory control such as address decoding, DRAM RAS / CAS control, and refresh control in accordance with a directly connected memory device (ROM, SRAM, DRAM, etc.). Further, the memory control circuit includes a programmable wait controller (or a wait control device), and performs wait control of bus cycles necessary for data access performed on the memory device according to the address area. In this way, the microcomputer can be directly connected to a general-purpose memory device that stores data to be accessed, and the number of parts can be reduced, resulting in a reduction in cost.
[0010]
In a cache device incorporated in such a microcomputer, when a cache miss occurs, data is acquired by an external bus cycle issued by the memory control circuit to the memory device storing data corresponding to the corresponding address. Is done.
[0011]
However, during this time, although the CPU core is in a stalled state, it is necessary to restart the operation as soon as data is acquired by the external bus cycle, so the clock signal supplied to the CPU core has not been stopped. . Therefore, wasteful power is consumed even when the CPU core is in a stalled state.
[0012]
The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide a clock signal supplied to each part in a stalled state that occurs during data access without causing performance degradation. To provide a clock control device, a semiconductor integrated circuit device including the clock control device, a microcomputer, and an electronic device that effectively and simply reduce power consumption.
[0013]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention provides a clock control device for controlling a clock signal supplied to a given circuit, the means for receiving an address accessed by the given circuit, and the address And a means for outputting to the given circuit a clock supply stop signal for stopping the supply of the clock signal by the number of clocks corresponding to the address area specified by.
[0014]
According to the present invention, in the clock control device, the clock supply stop signal for stopping the clock signal for the given circuit is stopped by the number of clocks corresponding to the address area specified by the address accessed by the given circuit. Was generated as follows. As a result, even if a stall occurs due to data access with different access times depending on the address area, the clock supply can be stopped for a given number of clocks, reducing the data processing capacity as before. Therefore, the power consumption can be reduced effectively and simply.
[0015]
The present invention also provides a clock control device for controlling a clock signal supplied to a cache device and a given circuit that accesses the cache device, the address being accessed by the given circuit, and based on the address And a means for receiving the cache miss signal determined in response, and supplying the cache miss signal to at least one of the given circuit and the cache device by the number of clocks corresponding to the address area specified by the address when the cache miss signal is received. And a means for outputting a clock supply stop signal for stopping the clock signal.
[0016]
According to the present invention, when a cache miss occurs due to data access to the cache device, the clock controller stops the clock supply stop signal for stopping the clock signal for the given circuit by the address accessed by the given circuit. One of the given circuits or the cache device described above is generated so as to be stopped by the number of clocks corresponding to the specified address area. As a result, the clock supply could not be stopped because it is unknown when the data will be returned even if it is in a stall state when a cache miss occurs, but the clock supply is stopped for a given number of clocks. Therefore, it is possible to effectively and simply reduce the power consumption in the stalled state without reducing the data processing capacity as in the prior art.
[0017]
The clock control device according to the present invention includes means for storing a given number of waits corresponding to an address area, and the number of clocks according to the number of waits stored corresponding to the address area specified by the address A clock supply stop signal for stopping the supply of the clock signal by the amount is output.
[0018]
By doing so, it is possible to accurately control the number of clocks for stopping the clock supply, and thus it is possible to realize more effective power consumption reduction and cost reduction.
[0019]
The present invention also includes a wait control device for storing the number of waits for accessing the data stored in the memory device corresponding to the address area to be accessed, and includes a cache device and a given circuit for accessing the cache device. A clock control device for controlling a clock signal supplied to the device, wherein the cache circuit is configured to receive an address accessed by the given circuit and a cache miss signal determined based on the address; When received, the memory device storing the data corresponding to the address is accessed based on the number of waits corresponding to the address area specified by the address, and the number of waits stored corresponding to the address area is set. At least the given circuit and the cache device by the number of clocks according to Characterized in that it comprises a said clock signal supplied to one and means for outputting the clock supply stopping signal for stopping.
[0020]
According to the present invention, the number of clocks to be stopped when a cache miss occurs is determined from the number of waits set by the wait control device often used for data access. Effective power consumption can be reduced without providing an additional circuit.
[0021]
The clock control device according to the present invention is characterized in that it includes a weight number varying means for varying the stored number of waits. In this way, even when the access time associated with data access is changed by software control such as the OS, it is possible to perform power consumption control with high accuracy with a simple configuration.
[0022]
A semiconductor integrated circuit device according to the present invention includes any one of the clock control devices described above.
[0023]
A microcomputer according to the present invention includes at least the clock control device according to any one of the above, the given circuit, a CPU, and the cache device accessed by the given circuit or the CPU. It is characterized by.
[0024]
A microcomputer according to the present invention includes at least the clock control device according to any one of the above, a CPU as the given circuit, and the cache device accessed by the CPU.
[0025]
In the microcomputer according to the present invention, the given circuit is a DMA for generating the address.
[0026]
Here, as a given circuit, address data is output by performing data access, and a CPU that may be in a stalled state due to access time required at that time, or a bus master such as DMA that cannot access data during that period. I tried to think. As a result, it is possible to inexpensively provide a microcomputer that can reduce power consumption by an effective and simple method in a stalled state that occurs during data access.
[0027]
The microcomputer according to the present invention further includes means for storing the number of waits for each given peripheral circuit, and the peripheral circuit is provided for each peripheral circuit by the number of clocks corresponding to the stored number of waits. A clock supply stop signal for stopping the supply of the supplied clock signal is output.
[0028]
In this way, the number of clocks to be stopped is set for each peripheral circuit that constitutes the microcomputer, so that optimum power consumption control determined by the operation timing of each part constituting the microcomputer is realized with a very simple configuration. can do.
[0029]
An electronic apparatus according to the present invention comprises any one of the microcomputers described above, data input means to be processed by the microcomputer, and output means for outputting data processed by the microcomputer. It is characterized by including. Thus, an electronic device with low power consumption and low cost can be provided.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0031]
1. Outline of the configuration of the microcomputer of the present embodiment
FIG. 1 shows an outline of the configuration of a microcomputer to which the clock control device of this embodiment is applied.
[0032]
The microcomputer 10 according to the present embodiment includes a CPU core 11, a cache device 12, a clock generator (CG) 13, a programmable wait controller (clock controller in a broad sense) 14, and peripheral circuits. It is integrated with.
[0033]
In this embodiment, a direct memory access controller (DMAC) 15 and a debug unit 16 are included as peripheral circuits.
[0034]
The CG 13 generates an original clock signal SCLK having a given frequency using, for example, an externally connected crystal oscillator. The CG 13 supplies the original clock signal SCLK to the first and second clock drivers 18 and 19 via the original clock signal line 17.
[0035]
The first clock driver 18 performs amplification (or waveform shaping) of the received original clock signal SCLK and uses this as the reference clock signal CLK. ₁ , CLK ₂ Are supplied to the CPU core 11 and the cache device 12 via the reference clock signal lines 20 and 21, respectively.
[0036]
The second clock driver 19 performs amplification (or waveform shaping) of the received original clock signal SCLK, and uses this as the reference clock signal CLK. _Three Are supplied to other peripheral circuits (programmable wait controller 14, DMAC 15, debug unit 16 and other peripheral circuit components).
[0037]
The CPU core 11 and the cache device 12 are respectively connected to the reference clock signal CLK. ₁ , CLK ₂ Or reference clock signal CLK ₁ , CLK ₂ It operates in synchronization with the internal clock generated based on the above.
[0038]
Each of the DMAC 15 and the debug unit 16 has a reference clock signal CLK _Three Any one of these, or each reference clock signal CLK _Three It operates in synchronization with the internal clock generated based on any one of the above.
[0039]
The CPU core 11 performs various processes on data stored in the cache device 12 or a memory device connected to the outside. More specifically, the CPU core 11 decodes fetch data stored in the cache device 12 or a memory device connected to the outside, and executes an instruction corresponding to the decoding result (instruction fetch and instruction decode). Further, the CPU core 11 performs data processing (execution) as it is using the fetch data according to the decoded instruction (data fetch and instruction execution).
[0040]
The DMAC 15 serves as a bus master and controls transfer of data stored in a memory device or the like in place of the CPU core 11. For this reason, prior to the DMAC 15 taking over the bus use right and starting the given data transfer, the DMA request signal 35 is output to the CPU core 11 performing the given process internally. The CPU core 11 outputs a DMA acknowledge signal 36 to the DMAC 15 when the processing is completed and the right to use the bus is transferred. The DMA acknowledge signal 36 is also output to the cache device 12.
[0041]
The DMAC 15 that has received the DMA acknowledge signal 36 transfers the right to use the bus and transfers data between the set address areas. Thereby, the load accompanying the data transfer process by the CPU core 11 can be omitted.
[0042]
The debug unit 16 monitors the address data, traces the access data in the debug memory space, and is used for software and hardware debugging. For this reason, the debug unit 16 includes an address monitoring unit, an interrupt generation unit, a data trace unit, and a communication unit. When address data is monitored by the address monitoring unit and access to a specific address is detected, the interrupt generation unit interrupts the CPU core 11 to temporarily stop the operation of the CPU core 11. As a result, the debugger is activated, and the trace data including the address data and the access data detected by the address monitoring unit are stored in the debug memory. Input / output to / from the debugger and trace data are performed with the outside via the communication unit. By using such a debugger as a bus master to generate address data and make it possible to access the data in the memory and I / O space, it can be operated from the outside without operating the debugger on the CPU. become.
[0043]
The cache device 12 caches data accessed by the CPU core 11 in association with addresses. That is, the cache device 12 buffers part or all of the data stored in the memory device connected to the outside. When the cache device 12 is buffering data corresponding to the internal address data output by the CPU core 11 (when a cache hit occurs), the CPU core 11 to access. This greatly reduces the data access time.
[0044]
On the other hand, when the cache device 12 is not buffering data corresponding to the internal address data output by the CPU core 11 (when a cache miss occurs), the CPU core 11 passes through the programmable wait controller 14 to Access to data stored in an externally connected memory device. At that time, the cache device 12 buffers the access data in a given storage location according to a given replacement algorithm to prepare for the next access (cache fill).
[0045]
Further, when the cache device 12 receives the DMA acknowledge signal 36 from the CPU core 11, the cache device 12 flushes the cache contents. That is, when a DMA transfer started after the DMA acknowledge signal 36 is output, the cache device 12 invalidates the cached contents.
[0046]
Further, the cache device 12 notifies the cache hit determination signal as to whether or not the accessed data is buffered.
[0047]
The programmable wait controller (clock controller in a broad sense) 14 performs wait control necessary for a bus cycle issued for accessing data for each given address area. Here, the programmable weight controller 14 has a function as a bus control device or a memory control device, and is an external device for accessing the first to third memory devices 25 to 27 connected to the external address bus 14. A bus cycle shall be issued.
[0048]
The microcomputer 10 is provided with an internal address bus 23, to which a CPU core 11, a cache device 12, a programmable wait controller 14, a DMAC 15, and a debug unit 16 are connected. The CPU core 11, the DMAC 15, or the debug unit 16 outputs 32-bit internal address data for specifying a storage location of data to be accessed using the internal address bus 23 as a common bus.
[0049]
An external address bus 24 is provided outside the microcomputer 10, and a programmable weight controller 14 of the microcomputer 10 and first to third memory devices 25 to 27 as memory devices are connected thereto. Yes.
[0050]
The first to third memory devices 25 to 27 store data to be accessed for each address area. Further, these first to third memory devices 25 to 27 have different access times. For this reason, the microcomputer 10 accesses each of these memory devices by wait control corresponding to the memory device storing the data to be accessed, which is performed by the programmable wait controller 14.
[0051]
Next, the operation of the microcomputer 10 having such a configuration will be described.
[0052]
The microcomputer 10 according to the present embodiment is characterized in that the programmable wait controller 14 uses the reference clock CLK when a cache miss occurs based on the cache hit determination signal output from the cache device 12. ₁ , CLK ₂ One of these is stopped, and the operation of either the CPU core 11 or the cache device 12 is stopped to reduce power consumption.
[0053]
Here, the cache hit determination signal is generated by the cache device 12. The cache device 12 supplies a cache hit determination signal to the programmable wait controller 14 via the cache hit determination signal line 28.
[0054]
When the programmable wait controller 14 determines the occurrence of a cache miss in the cache device 12 based on the cache hit determination signal received via the cache hit determination signal line 28, the programmable clock controller 14 ₁ , CLK ₂ A clock supply stop signal for stopping at least one of the signals is output to the first clock driver 18.
[0055]
The clock supply stop signal is supplied to the first clock driver 18 via the clock supply stop signal line 29.
[0056]
Furthermore, the clock supply stop signal generated by the programmable wait controller 14 of the present embodiment is the above-described only during a period corresponding to the stall period when accessing a memory device connected to the outside when a cache miss occurs. The operation of the reference clock is stopped. This period is generated according to a weight control table set by the programmable weight controller 14 functioning as a weight control device.
[0057]
FIG. 2 shows an example of a weight control table for performing weight control by the programmable weight controller 14 in the present embodiment.
[0058]
This wait control table 40 has the number of waits 42 necessary for accessing a memory device storing access data for each address area 41 connected to the internal address bus 23 of the microcomputer 10 and accessed by each unit that can be a bus master. It is remembered.
[0059]
When a cache miss occurs, the programmable wait controller 14 determines, for example, when accessing any address in the address area from “A0000000H” to “A000FFFFH” for an externally connected memory device. A given external bus cycle in which wait cycles corresponding to the number of waits “3” corresponding to the address area is inserted is issued.
[0060]
At this time, the programmable wait controller 14 sets the reference clock CLK by the number of clocks corresponding to the number of waits “3”. ₁ , CLK ₂ A clock supply stop signal for stopping at least one of the above is generated. As a result, the operation of at least one of the CPU core 11 and the cache device 12 is stopped, and power consumption can be reduced for the stopped period.
[0061]
Thus, when a cache miss occurs, it is not possible to stop the clock signal of the CPU core or the like that has been in a stalled state because it is unclear when data will be returned. In contrast, in this embodiment, the clocks are stopped by the number of clocks corresponding to the number of waits set in the programmable wait controller 14 for accessing the memory device connected to the outside. As a result, it is possible to effectively and simply reduce the power consumption of each part in the stalled state without causing a decrease in performance as in the prior art.
[0062]
Hereafter, the principal part of the microcomputer 10 of this embodiment mentioned above is demonstrated.
[0063]
2. Clock control device of this embodiment
FIG. 3 shows a configuration main part of a programmable wait controller to which the clock control device of the present embodiment is applied.
[0064]
Here, the same parts as those of the microcomputer 10 shown in FIG.
[0065]
The programmable wait controller 14 includes first to eighth wait control register groups 50. ₁ ~ 50 ₈ A MUX unit 51, a MUX control unit 52, a weight number control counter 53, and a zero detector 54.
[0066]
Here, eight sets of wait control registers are used, but the number of sets is not limited.
[0067]
First to eighth wait control register group 50 ₁ ~ 50 ₈ Includes a register group for determining an address area to be accessed based on address data supplied via the internal address bus 23, and a register in which the number of waits corresponding to the determined address area is set.
[0068]
The MUX unit 51 includes each wait control register group 50 ₁ ~ 50 ₈ Number of waits set and read for each 55 ₁ ~ 55 ₈ And a selector for selecting one of the default values “0”.
[0069]
The MUX control unit 52 includes each wait control register group 50 ₁ ~ 50 ₈ Address area discrimination result 56 from each ₁ ~ 56 ₈ Based on the above, a selector control signal 57 for performing selector control of the MUX unit 51 is generated.
[0070]
The wait number control counter 53 decrements the number of waits alternatively selected by the MUX unit 51 every clock.
[0071]
The zero detector 54 detects whether or not the count decremented by the wait number control counter 53 is “0” when it is detected by the cache hit determination signal 28 that a cache miss has occurred in the cache device 12. .
[0072]
The zero detector 54 generates a clock supply stop signal based on the zero detection signal indicating whether or not the count value is “0”.
[0073]
First to eighth wait number control register group 50 ₁ ~ 50 ₈ In each address area, the number of waits required for a bus cycle issued for accessing a plurality of externally connected memory devices is set.
[0074]
First wait number control register group 50 ₁ The wait number setting register 60 ₁ And comparison address setting register 61 ₁ And comparison address mask setting register 62 ₁ And address comparator 63 ₁ Including.
[0075]
Second to eighth wait number control register group 50 ₂ ~ 50 ₈ Is the first wait number control register group 50 ₁ It has the same configuration as
[0076]
Wait number setting register 60 ₁ ~ 60 ₈ Is set to the number of waits corresponding to the address area set for each wait control register group.
[0077]
Comparison address setting register 61 ₁ ~ 61 ₈ Is set with address data corresponding to the head address of the address area.
[0078]
Comparison address mask setting register 62 ₁ ~ 62 ₈ Includes a comparison address setting register 61. ₁ ~ 61 ₈ A mask value corresponding to the area size of the address area from the head address set by is set.
[0079]
Address comparator 63 ₁ ~ 63 ₈ The address data input via the internal address bus 23 and the comparison address setting register 61 ₁ ~ 61 ₈ Compare with the address data set in. At that time, the address comparator 63 ₁ ~ 63 ₈ Compare address mask setting register 62 ₁ ~ 62 ₈ By masking with the mask value set to, it is determined whether or not the address area specified by the address data on the internal address bus 23 is an address area set in each wait control register group. The determination result is the address area determination result 56. ₁ ~ 56 ₈ Is output as
[0080]
For example, the first wait control register group 50 ₁ In addition, when 3 weights are set in the 64 KB (kilobyte) address area from the address “A00000000H” to the address “A000FFFFH” as shown in FIG.
[0081]
Wait number setting register 60 ₁ Is set to the number of waits “3”.
[0082]
Comparison address setting register 61 ₁ Is set with 32-bit hexadecimal data “A000xxxxH” (where “x” is arbitrary 4-bit data).
[0083]
Comparison address mask setting register 62 ₁ Is set with 32-bit hexadecimal data “0000FFFFH”.
[0084]
When the 32-bit address data is supplied via the internal address bus 23 to the programmable wait controller 14 having such a configuration, each wait control register group 50 ₁ ~ 50 ₈ Address comparator 63 ₁ ~ 63 ₈ Is input.
[0085]
Address comparator 63 ₁ ~ 63 ₈ As described above, each of the comparison address setting registers 61 ₁ ~ 61 ₈ And the address data on the internal address bus 23 are compared bit by bit. At this time, the address comparator 63 ₁ ~ 63 ₈ Compare address mask setting register 62 ₁ ~ 62 ₈ The comparison result is masked with respect to the bit in which “1” is set, and is treated as a matched bit.
[0086]
In this way, the address comparator 63 ₁ ~ 63 ₈ Each of them is determined to be an address area set in its own wait control register group when all the bits of the supplied address data match. On the other hand, when even one bit does not match, it is determined that the address area is not set in the own wait control register group. This discrimination result is obtained as an address area discrimination signal 56. ₁ ~ 56 ₈ Is output to the MUX control unit 52.
[0087]
The MUX control unit 52 receives the address area determination signal 56. ₁ ~ 56 ₈ Thus, the wait control register group determined to be the address area set in each wait control register group is alternatively selected.
[0088]
Here, the set value of each address of each wait control register group is controlled by software (OS or the like) so that the address areas by each wait control register group do not overlap.
[0089]
A selector control signal 57 indicating a wait control register group alternatively selected by the MUX control unit 52 is supplied to the MUX unit 51.
[0090]
The MUX unit 51 selects the number of waits of the wait number setting register output from the wait control register group that is alternatively selected by the selector control signal 57.
[0091]
Note that the MUX unit 51 selects the default value “0” by the selector control signal 57 when the address area is not set in each of the first to eighth wait control register groups.
[0092]
The number of waits in the wait number setting register thus selected by the MUX unit 51 is input to the wait number control counter 53.
[0093]
The number of waits input to the wait number control counter 53 is first detected by the zero detector 54 as to whether or not it is “0”.
[0094]
When the zero detector 54 detects “0”, the wait number control counter 53 does not operate. For example, assuming that the clock supply stop signal is instructed when the logic level of the clock supply stop signal is “H”, the zero detector 54 detects that it is “0” and the logic level is “H”. This is reset in synchronization with a clock (not shown).
[0095]
When it is detected by the zero detector 54 that it is not “0”, for example, when the clock supply stop signal is at the logic level “L”, it is set in synchronization with a clock (not shown). Further, the wait number control counter 54 performs a decrement operation in synchronization with a clock (not shown).
[0096]
Whether or not the decrement result is “0” is again detected by the zero detector 54.
[0097]
In this way, by detecting whether the count value of the wait number control counter 53 is “0” by the zero detector 54 at every clock, the counter value “decremented by the wait number control counter 53“ A clock supply stop signal that is at the logic level “H” only during the corresponding period until “0” is detected is generated.
[0098]
The counter value controlled by the wait number control counter 53 is referred to for wait control by an external bus cycle generation unit (not shown), and data stored in a memory device connected to the outside is accessed.
[0099]
FIG. 4 shows an example of the operation timing of the programmable wait controller 14 of the present embodiment.
[0100]
In the following, a case where the number of waits is “0” at the operation timing in the two-phase non-overlapping clock system is shown.
[0101]
Here, the two-phase non-overlapping clock system is a system in which the clock system is configured by non-overlapping two-phase clocks called PH1 and PH2. Thus, the flip-flop for synchronizing the sequential circuit can be a transparent (transparent data type) latch, and the circuit configuration of the flip-flop can be reduced.
[0102]
Further, it is assumed that the external bus cycle of the microcomputer 10 of this embodiment is one bus cycle for two clocks. Further, it is determined whether or not a wait cycle is inserted at the end of each bus cycle, and the bus cycle is extended.
[0103]
That is, as shown in FIG. 4, when the number of waits is “0”, the bus cycle is a clock cycle T defined by PH1 and PH2 that do not overlap each other. ₀ , T ₁ Consists of
[0104]
In the microcomputer of this embodiment, the clock cycle T ₀ Address data is output in synchronism with PH1 and a bus cycle is started.
[0105]
At the same time, the first to eighth wait control register groups 50 of the programmable wait controller 14 ₁ ~ 50 ₈ Address comparator 63 ₁ ~ 63 ₈ In addition, a memory address 70 which is address data on the internal address bus 23 is input.
[0106]
Address comparator 63 ₁ ~ 63 ₈ Then, as described above, the address area is determined. The result is the clock cycle T as the address area discrimination result 71. ₀ Is output in synchronization with PH2.
[0107]
The MUX control unit 52 and the MUX unit 51 select the number of waits in the corresponding wait control register group using the address area determination result.
[0108]
As described above, control is performed so that each wait control register group does not output an address area determination result indicating that the address area is determined by the same address by software. However, the priority circuit automatically determines a plurality of address area determination results. Even when it is determined as an address area set in the register group, it is desirable to select only the register group having the highest priority.
[0109]
The number of waits thus selected is input to the wait number control counter 53.
[0110]
The number-of-waits control counter 53 has a clock cycle T ₁ Is set to “0” as the counter value CNT (counter value 72).
[0111]
Whether or not the counter value set in the wait number control counter 53 is “0” by the zero detector 54 is detected.
[0112]
Zero detector 54 has a clock cycle T ₁ The zero detection signal indicating the detection result 73 is output in synchronization with PH2. Here, since “0” is detected, the external bus cycle controlled by the external bus cycle generation unit (not shown) is terminated, and the counting operation thereafter is stopped.
[0113]
Therefore, the clock cycle T ₂ Thereafter, the next bus cycle is newly started.
[0114]
FIG. 5 shows another example of the operation timing of the programmable wait controller 14 of the present embodiment.
[0115]
In the following, a case where the number of waits is “N (N is a natural number)” at the operation timing in the two-phase non-overlapping clock system similar to FIG.
[0116]
That is, as shown in FIG. 5, when the number of waits is “N”, the bus cycle is a clock cycle T defined by PH1 and PH2 that do not overlap each other. ₀ , T _{N + 1} Consists of
[0117]
Clock cycle T ₀ The address data is output in synchronization with PH1 of the memory and the bus cycle is started. At the same time, the memory address 80 which is the address data on the internal address bus 23 is supplied to the first to eighth waits of the programmable wait controller 14. Control register group 50 ₁ ~ 50 ₈ Address comparator 63 ₁ ~ 63 ₈ Is input.
[0118]
Address comparator 63 ₁ ~ 63 ₈ Then, as described above, the address area is determined, and the address area determination result 82 is used as the clock cycle T. ₀ Is output in synchronization with PH2.
[0119]
The MUX control unit 52 and the MUX unit 51 use this address area determination result to select the number of waits in the corresponding wait control register group, and the selected number of waits is input to the wait number control counter 53.
[0120]
The number-of-waits control counter 53 has a clock cycle T ₁ Is set to “N” as the counter value CNT (counter value 84).
[0121]
Whether or not the counter value set in the wait number control counter 53 is “0” by the zero detector 54 is detected.
[0122]
Zero detector 54 has a clock cycle T ₁ The zero detection signal indicating the detection result 86 is output in synchronization with PH2.
[0123]
Here, since the counter value set in the wait number control counter 53 is “N”, the clock cycle T ₁ The clock supply stop signal of logic level “L” is set 88 until then in synchronization with PH2.
[0124]
The wait number control counter 53 decrements the counter value in synchronization with PH1 every clock cycle.
[0125]
Therefore, the clock cycle T ₂ The counter value is set to “N−1” in synchronization with PH1 (counter value 90).
[0126]
Every time the counter value is updated, it is detected by the zero detector 54 whether or not it is “0”.
[0127]
Clock cycle T ₂ Also, since the counter value set in the wait number control counter 53 is “N−1”, the clock supply stop signal remains at the logic level “H”.
[0128]
In the same manner, the process is repeated until CNT becomes “0”.
[0129]
As a result, clock cycle T _{N + 1} At PH1, the wait number control counter 53 sets “0” as the counter value CNT (counter value 92).
[0130]
Whether or not the counter value set in the wait number control counter 53 is “0” by the zero detector 54 is detected.
[0131]
Zero detector 54 has a clock cycle T ₁ The zero detection signal indicating the detection result 86 is output in synchronization with PH2.
[0132]
The wait number control counter 53 decrements the counter value in synchronization with PH1 every clock cycle, and each time the counter value is updated, it is detected by the zero detector 54 whether or not it is “0”.
[0133]
Here, since “0” is detected, the external bus cycle controlled by the external bus cycle generation unit (not shown) is terminated, and the counting operation beyond that is stopped.
[0134]
Clock cycle T _{N + 2} As for the clock supply stop signal, the clock supply stop signal of logic level “H” is reset (reset 94).
[0135]
That is, here, the clock supply stop signal is generated as follows.
[0136]
If the clock supply stop signal is instructed to stop the clock supply when the logic level of the clock supply stop signal is “H”, when the counter value decremented by the wait number control counter 53 is “0”, the clock supply stop signal is It does not change when the logic level is “L”, but is reset when the logic level is “H”. When the counter value decremented by the wait number control counter 53 is not “0”, it is set to the logic level “H” when the logic level is “L”, but does not change when the logic level is “H”.
[0137]
By doing so, the zero detector 54 supplies the clock of the logic level “H” until a counter value “0” decremented by the wait number control counter 53 is detected, for example, when a cache miss occurs. A stop signal can be generated. Such a clock supply stop signal can be generated at the same timing as the zero detection result.
[0138]
By the way, the clock supply stop signal is set to the logic level “H” when the address area is determined on the assumption that the way and the cycle are always required when the address area is determined, and the zero detector 54 is set. The clock supply stop signal can be generated at a timing earlier than the zero detection timing by resetting the logic level to “L” upon zero detection.
[0139]
In this case, the clock supply stop signal is the clock cycle T ₁ Becomes a logic level “H” in synchronization with PH1 of the clock cycle T _{N + 2} The logic level becomes “L” in synchronization with PH1.
[0140]
Furthermore, as a reset timing, when the counter value becomes “1” or “2” instead of “0”, the clock supply stop signal is set to the logic level “L”, so that the clock supply restart is slightly advanced. It is also possible.
[0141]
The generation timing of such various clock supply stop signals depends on the operation timing of each part of the microcomputer, and is not limited to this generation timing.
[0142]
In short, it is only necessary that the programmable wait controller 14 refers to the number of waits set in the wait control table and can generate a clock supply stop signal having a logic level “H” by the number of clocks corresponding to the number of waits.
[0143]
3. Microcomputer of this embodiment
Next, the clock supply stop operation in the microcomputer of this embodiment will be specifically described.
[0144]
Therefore, first, the configuration and operation timing of the cache device that supplies the cache hit determination signal to the programmable wait controller (clock controller in a broad sense) 14 according to the present embodiment will be described, and then the clock according to the present embodiment. The supply stop operation will be described.
[0145]
(1) Configuration example of cache device
FIG. 6 shows an example of the configuration of the cache device 12 of this embodiment.
[0146]
Here, it is assumed that the cache device 12 is a two-way set associative system in which instructions / data are mixed, has a line size of 8 bytes, and a capacity of 4 Kbytes (= 8 bytes × 256 entries × 2 ways).
[0147]
The cache device 12 has a comparator 100 for each way. ₀ , 100 ₁ And tag RAM read / write control circuit 102 ₀ , 102 ₁ And tag array 104 ₀ , 104 ₁ And a data RAM read / write control circuit 106 ₀ , 106 ₁ And data array 108 ₀ , 108 ₁ And MUX110.
[0148]
Comparator 100 ₀ , 100 ₁ Are the upper bits of the address data and the tag RAM read / write control circuit 102 ₀ , 102 ₁ Is compared with the tag address data read out by, and the comparison result is compared with the tag comparison result 112. ₀ , 112 ₁ To the MUX 110.
[0149]
At that time, the comparator 100 ₀ , 100 ₁ The comparison result is determined to match only when the Valid bit indicating whether or not each entry of the tag array is valid is “1”.
[0150]
Tag RAM read / write control circuit 102 ₀ , 102 ₁ Are tag arrays 104 identified by the middle bits of the address data, respectively. ₀ , 104 ₁ For each of these entries, reading and writing control of the upper bits of the address data are performed, and a valid bit indicating a valid entry is controlled.
[0151]
Tag array 104 ₀ , 104 ₁ Stores as many upper bits of the address data as the number of entries specified by the middle bits.
[0152]
Data RAM read / write control circuit 106 ₀ , 106 ₁ Are data arrays 108 respectively identified by the middle bits of the address data. ₀ , 108 ₁ For each entry, read and write control of one line of cache data is performed.
[0153]
Data array 108 ₀ , 108 ₁ Stores one line size data corresponding to the address data by the number of entries specified by the middle bit of the address data.
[0154]
MUX 110 is tag comparison result 112 ₀ , 112 ₁ Then, one line data of the matched way is selected, and the data specified by the address data lower bits is output to a data bus (not shown).
[0155]
Here, it is assumed that 32-bit address data 120 is supplied to the cache device 12 via the internal address bus 23.
[0156]
The upper 21 bits 122 of the 32-bit address data 120 are stored in the comparator 100. ₀ , 100 ₁ Is input. That is, the comparator 100 ₀ , 100 ₁ The upper 21 bits 122 and the tag array 104 ₀ , 104 ₁ The tag address read from is compared.
[0157]
The middle 8 bits 124 of the 32-bit address data 120 are stored in the tag array 104. ₀ , 104 ₁ , Data array 108 ₀ , 108 ₁ Is input. That is, the middle 8 bits 124 indicate the tag array 104. ₀ , 104 ₁ , Data array 108 ₀ , 108 ₁ Any of the 256 entries is specified.
[0158]
The lower 3 bits 126 of the 32-bit address data 120 are the data RAM read / write control circuit 106. ₀ , 106 ₁ By the data array 108 ₀ , 108 ₁ Designation within the line of 8-byte data read out from.
[0159]
Comparator 100 ₀ , 100 ₁ Tag array 104 ₀ , 104 ₁ From the Valid bits read from the entry specified by the middle 8 bits 124 together with the tag address, the tag address is matched and the Valid bit is “1”, and the comparison is made. Results 1120 and 1121 are output.
[0160]
The MUX 110 includes a data RAM read / write control circuit 106. ₀ , 106 ₁ The 8-byte data of one line size of the entry specified by the middle 8 bits 124 of the address data 120 read from the data arrays 1080 and 1081 by the tag comparison result 112 ₀ , 112 ₁ Select alternatively based on.
[0161]
Further, the MUX 110 outputs the selected 1-line data to the data bus (not shown) as 32-bit data at the position specified by the lower 3 bits 126 of the address data 120.
[0162]
Here, if the data bus is 32 bits, only the most significant 1 bit of the lower 3 bits 126 is used. That is, when the most significant bit of the lower 3 bits 126 is “0”, the lower 4 bytes of 1 line size are selected, and when the most significant bit of the lower 3 bits 126 is “1”, the upper 4 bytes of 1 line size are selected. To do.
[0163]
The cache hit determination signal is a tag comparison result 112. ₀ , 112 ₁ Is output to the programmable weight controller 14 as a result of the logical sum operation.
[0164]
FIG. 7 shows an example of the operation timing of the cache device 12 of this embodiment.
[0165]
Here, the operation timing in the case of a cache hit is shown as the operation timing in the two-phase non-overlap clock system.
[0166]
That is, as shown in FIG. ₀ When the address data ADR1 is output in synchronization with PH1 of the tag RAM, the tag RAM read / write control circuit 102 of the cache device 12 is output. ₀ , 102 ₁ The tag address is read out and compared.
[0167]
Result of tag comparison 112 ₀ , 112 ₁ The cache hit determination signal obtained by performing an OR operation on the clock cycle T ₀ Is output in synchronization with PH2.
[0168]
If the address data ADR1 has a cache hit, the tag comparison result 112 is stored in the MUX 110. ₀ , 112 ₁ The 32-bit Data1 selected by the ₀ Is output in synchronization with PH2.
[0169]
Subsequently, clock cycle T ₁ When the address data ADR2 is output in synchronization with PH1 of the tag RAM, the tag RAM read / write control circuit 102 of the cache device 12 is output. ₀ , 102 ₁ The tag address is read out and compared.
[0170]
In the same manner, the cache hit determination signal and Data2 corresponding to the cache hit address data ADR2 are clock cycles T ₀ Is output in synchronization with PH2.
[0171]
(2) Clock supply stop operation timing
Next, the clock supply stop operation timing in the microcomputer of the present embodiment including the programmable wait controller 14 and the cache device 12 having the above-described configuration will be described with reference to FIG.
[0172]
FIG. 8 shows an example of the clock supply stop operation timing in the microcomputer of this embodiment.
[0173]
Here, it is assumed that the clock supply stop signal is generated in synchronization with the address area determination signal and PH1, and reset in synchronization with the zero detection signal and PH1. Depends on computer configuration. The point is to generate a clock supply stop signal for stopping at least the reference clock supplied to the CPU core or the cache device 12 by the number of clocks based on the number of waits corresponding to the address area set in the programmable wait controller 14. I can do it.
[0174]
Further, the cache device 12 according to the present embodiment starts the read operation of the tag array and the data array at the same time when the address is supplied for speeding up.
[0175]
Clock cycle T ₀ Address data ADR1 output in synchronism with PH1 of the cache device 12, assuming that a cache hit occurs in the cache device 12, the clock cycle T ₀ The cache hit determination signal, which is the tag comparison result at PH2, is at a logic level “H” meaning “hit”.
[0176]
As described with reference to FIG. ₀ The hit data Data1 is output at PH2.
[0177]
Subsequently, clock cycle T ₁ Address data ADR2 output in synchronization with PH1 of the cache device 12, assuming that a cache miss has occurred in the cache device 12, the clock cycle T ₁ The cache hit determination signal, which is the tag comparison result at PH2, is at the logic level “L” meaning “miss”.
[0178]
Along with this, the cache device 12 performs a reel operation on a memory device connected to the outside.
[0179]
That is, the external address bus has clock cycle T ₁ In synchronization with PH1, the memory address (2a) corresponding to ADR2 is output to fill the 32-bit data, and then the memory address (2b) is output to fill the other 32-bit data. As described above, data of one line size of 64 bits is filled by two bus cycles.
[0180]
Here, assuming that ADR2 is, for example, an address “A0000000H”, a clock cycle T ₁ In synchronism with PH2, the address area discrimination result is a logic level “H” indicating coincidence. In accordance with this, as shown in FIG. 2, the clock number “3” corresponding to the address area from the address “A000000H” to the address “A000FFFFH” is read.
[0181]
Subsequently, the clock supply stop signal is set to the logic level “H” at PH1 of the clock cycle T2 in synchronization with the address area determination result and PH1, as described above, and the counter of the programmable wait controller 14 The value CNT is set to “3”.
[0182]
This counter value is decremented and updated with PH1 of each clock cycle.
Clock cycle T _Five When the counter value CNT is updated to “0” at PH1, the zero detector 54 detects “0” and the clock cycle T _Five The logic level is “H” indicating zero detection at PH2.
[0183]
Since the clock supply stop signal is reset in synchronization with the zero detection signal and PH1 as described above, the clock cycle T ₆ The logic level becomes “L” at PH1.
[0184]
Therefore, the clock cycle T during which the clock supply stop signal is at the logic level “H”. ₂ To clock cycle T _Five In the meantime, in the first clock driver 18, for example, the operation of the reference clock supplied from the cache device 12 is stopped. In some cases, the reference clock supplied to the CPU core 11 may be similarly stopped.
[0185]
And clock cycle T ₆ Then, the operation stop of the reference clock of the CPU core 11 or the cache device 12 is released.
[0186]
As a result, the desired access data is transferred from the externally connected memory device to the data bus by the external bus cycle in which the wait cycle is inserted according to the number of waits stored in the wait control table of the programmable wait controller 14. Is output.
[0187]
In this way, the clock cycle T _Five ~ T ₆ The external data output from the externally connected memory device is filled as part of one line data of the tag address corresponding to ADR2 of the cache device 12 on which the clock signal is operating.
[0188]
Then clock cycle T ₆ Thereafter, an external bus cycle is issued by the memory address (2b) for filling other data of one line data of the tag address corresponding to ADR2.
[0189]
As described above, in the present embodiment, in the microcomputer 10 including the CPU core 11 and the cache device 12, when a cache miss occurs in the cache device 12, a programmable program for accessing an externally connected memory device. The wait controller 14 generates a clock supply stop signal for stopping the operation of the reference clock by the number of clocks corresponding to the number of waits set corresponding to the address area to be accessed. The clock supply stop signal stops at least one of the reference clocks supplied from the first clock driver 18 to the CPU core 11 and the cache device 12. As a result, it is possible to effectively and simply reduce the power consumption of each part in the stalled state without degrading the performance.
[0190]
In the microcomputer according to the present embodiment, referring to the number of waits set in the wait control table of the programmable weight controller 14, the clock supply stop signal is the number of clocks corresponding to the number of waits (for example, only one clock). The stop of clock supply is instructed only for a short number of clocks). This can be realized by a logic composed of a simple sequential circuit such as a flip-flop. However, the number of clocks is not limited to this.
[0191]
For example, the number of clocks for stopping clock supply may be set in the wait control table shown in FIG.
[0192]
FIG. 9 shows another example of a weight control table for performing weight control by the programmable weight controller 14 in the present embodiment.
[0193]
This wait control table 180 has an external bus cycle necessary for accessing a memory device storing access data for each address area 182 accessed by each unit that can be a bus master connected to the internal address bus 23 of the microcomputer 10. The number of waits 184 and the number of waits 186 of the cache device 12 required for external access when a cache miss occurs are stored.
[0194]
When the programmable wait controller accesses any address in the address area from the address “A0000000H” to the address “A000FFFFH”, for example, when a cache miss occurs, the address area determined A given external bus cycle in which the number of waits corresponding to “3” is waited is issued.
[0195]
At this time, the programmable wait controller 14 sets the reference clock CLK by the cache wait number “2”. ₂ A clock supply stop signal for stopping the operation is generated. As a result, the number of clocks to stop the operation of the cache device 12 can be made variable according to the access time of the memory device connected to the outside, and optimal power consumption control is performed by software (such as an OS) Will be able to.
[0196]
4). Configuration example of microcomputer of other embodiment
In this embodiment, when a cache miss occurs from the cache device, a programmable weight controller that generates a clock supply stop signal based on a wait control table for accessing an externally connected memory device (in a broad sense, It is conceivable that the function of the clock control device is included in another peripheral circuit.
[0197]
FIG. 10 shows an example of a hardware block diagram of a microcomputer according to another embodiment.
[0198]
The microcomputer 1700 includes the function of the clock control device of the present embodiment in the bus controller 1600 and includes the cache device 1520 of the present embodiment, and includes a CPU 1510, a reset circuit 1540, a programmable timer 1550, a real-time clock. (RTC) 1560, DMA 1570, interrupt controller 1580, serial interface 1590, A / D converter 1610, D / A converter 1620, input port 1630, output port 1640, I / O port 1650, clock generator 1560, prescaler 1570 , And various buses 1680 for connecting them, various pins 1690, and the like.
[0199]
By incorporating the clock control device of this embodiment into a microcomputer, it is possible to provide a microcomputer that can reduce power consumption by an effective and simple method at low cost.
[0200]
5). Electronic device of this embodiment
FIG. 11 shows an example of a block diagram of the electronic apparatus of this embodiment. The electronic apparatus 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an image output unit 850, and a sound output 860.
[0201]
The microcomputer (or ASIC) 810 or the memory 830 includes the clock control device of this embodiment.
[0202]
Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The image output unit 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device, and the function can be realized by hardware such as an LCD or a CRT. The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.
[0203]
FIG. 12A illustrates an example of an external view of a mobile phone 950 which is one of electronic devices. The mobile phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that functions as an image output unit and displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.
[0204]
FIG. 12B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that functions as an image output unit and displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound. Prepare.
[0205]
FIG. 12C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that functions as an image output unit and displays characters, numbers, graphics, and the like, and a sound output unit 976.
[0206]
By incorporating the clock control device of this embodiment into the electronic devices in FIGS. 12A to 12C, an electronic device with low power consumption and low cost can be provided.
[0207]
As electronic devices that can use this embodiment, in addition to those shown in FIGS. 12A, 12B, and 12C, a portable information terminal, a pager, an electronic desk calculator, a device including a touch panel, Various electronic devices such as a projector, a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, and a printer can be considered.
[0208]
In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.
[0209]
In this embodiment, the reference clock supplied to the CPU core or the cache device is stopped. However, the present invention is not limited to this. For example, a reference clock supplied from the second clock driver 19 to the DMAC 15 or the debug unit 16 is stopped by a clock supply stop signal generated by the programmable wait controller (clock controller in a broad sense) 14. May be.
[0210]
Furthermore, for example, when the CPU core 11 accesses the cache device 12 and a cache miss occurs and the cache device 12 snoops the address to maintain cache coherency, the clock stop period of the cache device 12 is If the setting is made excluding the number of clocks required for the snoop, it can be easily applied even when the bus snoop function is provided.
[0211]
Further, the internal address buses in the cache device 12, the programmable wait controller 14, the DMAC 15, and the debug unit 16 are not limited to the bus width.
[0212]
Furthermore, in this embodiment, the clock supply stop signal is stopped for the number of clocks corresponding to the number of waits, but the reference clock may be stopped for the number of waits as it is depending on the internal configuration.
[0213]
Further, the number of clocks for stopping the clock supply for each part (CPU core, cache device, DMAC, debug unit, etc.) constituting the microcomputer of this embodiment is shown in FIG. 2 or FIG. 9 for each address area to be accessed. The weight control table may be stored. Thereby, optimal power consumption control determined by the operation timing of each part constituting the microcomputer can be realized with a very simple configuration.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an outline of a configuration of a microcomputer to which a clock control device according to an embodiment is applied.
FIG. 2 is an explanatory diagram showing an example of a weight control table in the present embodiment.
FIG. 3 is a block diagram showing a main configuration part of a programmable wait controller to which the clock control device of the present embodiment is applied.
FIG. 4 is a timing chart showing an example of operation timing of the programmable wait controller of the present embodiment.
FIG. 5 is a timing chart showing another example of the operation timing of the programmable wait controller of the present embodiment.
FIG. 6 is a block diagram illustrating an example of a configuration of a cache device according to the present embodiment.
FIG. 7 is a timing chart illustrating an example of operation timing of the cache device according to the embodiment.
FIG. 8 is a timing chart showing an example of clock supply stop operation timing in the microcomputer of the present embodiment.
FIG. 9 is an explanatory diagram showing another example of the weight control table in the present embodiment.
FIG. 10 is a block diagram showing an example of the configuration of a microcomputer according to another embodiment.
FIG. 11 is a block diagram illustrating an example of a configuration of an electronic apparatus according to the present embodiment.
12A, 12B, and 12C are examples of external views of various electronic devices.
[Explanation of symbols]
10 Microcomputer
11 CPU core
12 Cache device
13 CG
14 Programmable wait controller (clock controller)
15 DMAC
16 Debug unit
17 Original clock signal line
18 First clock driver
19 Second clock driver
20, 21 Reference clock signal line
23 Internal address bus
24 External address bus
25 First memory device
26 Second memory device
27 Third memory device
28 Cache hit judgment signal line
29 Clock supply stop signal line
35 DMA request signal
36 DMA acknowledge signal

Claims (10)

A clock controller for controlling a clock signal supplied to a given circuit,
Means for receiving an address to be accessed by the given circuit;
Means for storing a number of waits corresponding to a stall period when the given circuit accesses each address area specified by the address;
Means for outputting to the given circuit a clock supply stop signal for stopping supply of the clock signal by the number of clocks corresponding to the number of waits stored in the means for storing the number of waits corresponding to the address When,
A clock control apparatus comprising: A clock control device for controlling a clock signal supplied to a cache device and a given circuit for accessing the cache device,
Means for receiving an address accessed by the given circuit and a cache miss signal determined based on the address;
Means for storing a number of waits corresponding to a stall period when the given circuit accesses each address area specified by the address;
When the cache miss signal is received, it is supplied to at least one of the given circuit and the cache device by the number of clocks corresponding to the number of waits stored in the means for storing the number of waits corresponding to the address. Means for outputting a clock supply stop signal for stopping the clock signal;
A clock control apparatus comprising: In claim 2,
The means for storing the number of waits stores, for each address area, the number of waits for accessing the memory at the time of a cache miss and the number of waits for accessing the cache device at the time of a cache hit,
When the cache miss signal is received, a clock supply stop signal is output to stop the supply of the clock signal by the number of clocks corresponding to the number of waits stored corresponding to the address in order to access the cache device. ,
When the cache miss signal is received, a clock supply stop signal for stopping the supply of the clock signal by the number of clocks corresponding to the number of waits stored corresponding to the address to access the memory is output. A clock control device. In claim 3,
A clock control apparatus comprising: a weight number varying means for varying the stored number of waits.   A semiconductor integrated circuit device comprising the clock control device according to claim 1.   5. The clock control device according to claim 1, comprising at least the given circuit, a CPU, and the cache device accessed by the given circuit or the CPU. Microcomputer.   5. A microcomputer comprising at least the clock control device according to claim 1, a CPU as the given circuit, and the cache device accessed by the CPU. In claim 6,
The microcomputer according to claim 1, wherein the given circuit is a DMA for generating the address. In any of claims 6 to 8,
Means for storing the number of waits for each given peripheral circuit, and stopping the supply of the clock signal supplied to each peripheral circuit by the number of clocks corresponding to the stored number of waits for the peripheral circuit A microcomputer for outputting a clock supply stop signal to be output. A microcomputer according to any one of claims 6 to 9,
Means for inputting data to be processed by the microcomputer;
Output means for outputting data processed by the microcomputer;
An electronic device comprising:

Images