JP3895120B2 - Programmable sequencer built-in ASIC and image forming apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an ASIC with built-in programmable sequencer and an image forming apparatus for controlling power supply in a power saving mode in a copying machine, a printer, and a complex machine thereof.
[0002]
[Prior art]
In recent years, copiers, printers, and their multifunction devices have been increasingly attracting attention to environmental problems, and there is a strong demand for power saving for these devices. Management is performed. When this power management is performed, the type of power supply and the management method vary depending on the configuration of the device. Therefore, it is common to perform power on / off control by software. In other words, software is easy to change / modify according to the specifications of the device. When control by software cannot be performed in this way, for example, power control at a level that turns off the power of the CPU itself can be performed by software, but power must be restored by hardware. In addition, the programmable sequencer is generally executed by software, and is limited to a specific operation without a CPU.
[0003]
[Problems to be solved by the invention]
In the advanced power saving mode, since the CPU also cuts off the power, it is necessary to use hardware to restore the power. However, since the number of power supplies to be controlled and the control method differ depending on the configuration of the device, it is necessary to design each time according to the device. In addition, in this method, it is necessary to start over from the hardware design when the design is defective or the control method is corrected.
[0004]
The present invention provides an ASIC with a built-in programmable sequencer and an image forming apparatus using the same that can improve power supply control without software intervention by improving the disadvantages and configuring a programmable control circuit inside. It is for the purpose.
[0005]
[Means for Solving the Problems]
The ASIC with a programmable sequencer according to the present invention includes a plurality of input selection blocks for selecting a plurality of external input signals and a plurality of internally generated trigger signals and selecting a logic inversion / non-inversion by setting one register. , delay and arithmetic block outputs by different register settings and the register select logic product or logical sum of the outputs of said plurality of input selection block, a different register settings and the respective registers output from the calculation block A plurality of basic structure blocks having a timer block to be output and an output selection block for inverting and outputting the output from the timer block by setting a register different from each of the registers, and the basic structure block is included in the input selection block. Various information indicating that the image forming apparatus is turned on as an external input signal When the information is input, the power source of the image forming apparatus is controlled.
[0006]
The basic structure block controls the power supply of the image forming apparatus when information from the network is input as an external input signal to the input selection block.
[0007]
The basic structure block controls the power supply of the image forming apparatus when a trigger signal indicating reception of a specific packet in communication is input as an external input signal to the input selection block.
[0008]
The image forming apparatus according to the present invention is characterized by the above-mentioned ASIC with a programmable sequencer.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The copying machine of the present invention has an ASIC for controlling the power supply. The ASIC has a plurality of basic structure blocks that have a plurality of external input signals, a plurality of internally generated trigger signals, and inputs from a register that can be controlled by software, and operate according to the contents set in the register by software. Then, a predetermined operation is executed without requiring control by software to control the transfer sequence of the copying machine to the power saving mode and the return sequence from the power saving mode.
【Example】
FIG. 1 is a block diagram showing the configuration of an ASIC with a programmable sequencer according to an embodiment of the present invention. The ASIC 1 controls a power source of an image forming apparatus such as a copying machine, and controls a shift to a power saving mode and a return sequence from the power saving mode, and includes three basic structure blocks 2a, 2b, and 2c.
[0011]
Each basic structure block 2 has a block A, a block B, a block C, and a block D as shown in the block diagram of FIG. The block A of the basic structure block 2 is an input selection block, which selects an ASIC external signal or internal signal and a set value by a register and selects logic inversion / non-inversion. Four input selection blocks A are arranged. Note that the input selection block A may be four or more or the following depending on the number of external signals and internal signals. The signal that can be selected in the input selection block A may be arbitrarily changed by the designer depending on the situation. In FIG. 1, three external signal inputs EXT-IN are described, and the sequencer block output OUT and register output reg are described as internal signals. The input signal of the input selection block A is selected by register setting. At the same time, it is set whether to logically invert the selected signal. As a result, a signal is input from the input selection block A to the block B. Block B is an arithmetic block, and selects the logical product or logical sum of signals from the input selection blocks A1 to A4. That is, the logical OR and AND of the signals from the four input selection blocks A1 to A4 are selected by register setting. Block C is a timer block, and has a function of detecting the rising or falling of the signal from the operation block B, adding a delay by a delay timer, and generating / latching an output signal. When the rise / fall of the signal from the calculation block B is detected, the delay timer starts operating. When the count is finished, a signal is output to the block D. Rising / falling is selected by register setting. The delay timer can be reset (initialized) by selecting any one of an ASIC external signal, an ASIC internal signal, and a register output. The output is only positive logic. Block D is an output selection block for selecting the positive logic / negative logic of the output signal. The output from block C is inverted / inverted according to the set contents of the register and output from the output terminal to the outside of the block. .
[0012]
Setting / selection of each of the blocks A to D is performed by register setting from software. Therefore, the function as a sequencer is not lost unless the power supply of the ASIC 1 is cut off or the ASIC 1 itself is reset. The basic structure block 2 inside the ASIC 1 may be increased in number when performing complex control.
[0013]
An example of the register configuration of the basic structure block 2 is shown in FIG. The registers 3 to 6 of the input selection block A select one of the input from the external pins EXT-IN1 to EXT-IN3 determined in advance by the ASIC1, the output signals OUT1 to OUT3 of the ASIC1, and a fixed value by software. Then, inversion / non-inversion of the value can be set. The registers 3 to 6 are each composed of 8 bits for each input selection block A, and there are four in the basic structure block 1. When other signals inside the ASIC 1 are used, the corresponding signals are added to the registers 3-6. The register 7 of the arithmetic block B uses a 1-bit register to select whether to perform a logical sum or logical product of signals from the input selection block A. The register 8 of the timer block C uses a register for setting a timer count value and a register for setting whether a trigger signal for resetting the counter is selected and the count is started at the rising edge or falling edge of the input signal. The counter is set to 16 to 32 bits, depending on the count base clock and the required maximum count time. Selection of the trigger signal and trigger selection are controlled by an 8-bit register. The register 9 of the output selection block D uses a 1-bit register for logical selection of the output signal. In the ASIC 1, these registers are prepared according to the number of basic structure blocks 2 to be mounted. The initial value loaded into the register can be changed by setting the input to the external pin of the ASIC 1. This is because the ASIC 1 checks the input setting during reset and changes the register initial value.
[0014]
In FIG. 1, Vdd1 is a primary power supply linked to a power switch, and Vdd2 and Vdd3 are secondary power supplies controlled by software / ASIC1. The ASIC 1 is supplied with power from the primary power supply Vdd1 by turning on the power switch. At this time, the secondary power supply Vdd2 is turned on after a lapse of a certain time after the primary power supply Vdd1 is turned on, and the secondary power supply Vdd3 is turned on after a lapse of a certain time after the secondary power supply Vdd2 is turned on. By connecting the CPU / memory or the like to the secondary power supply Vdd2, the power supply can be turned off leaving the ASIC1 and very few peripheral circuits, and the energy saving effect can be enhanced.
[0015]
In the basic configuration block 2a, the logical sum of the input from the outside and the register of the input selection block A may be used as a trigger, and the trigger may be applied with the initial value of the register. Then, power supply to the secondary power source Vdd2 is started at the output of OUT1 after the count of the delay timer is completed. As for the secondary power supply Vdd3, the output of OUT1 may be input, or the level of the secondary power supply Vdd2 may be directly input. If one delay counter is not used, two basic building blocks 2b and 2c may be used in series as shown in FIG. In addition, when the primary power supply Vdd1 is supplied and the secondary power supplies Vdd2 and Vdd3 are off, a specific operation, for example, pressing a switch on the operation panel or opening the device cover is used as a trigger to activate the secondary power supplies Vdd2 and Vdd3. You can also turn it on .
[0016]
Further, since the delay counter also has a latch function for edge detection, when it is desired to turn off a specific power source, for example, when it is desired to turn off only the two-time power source Vdd3, the software performs a delay timer of the basic configuration blocks 2b and 2c. Can be reset. When it is desired to turn it on again, the register setting of the input selection block A of the basic configuration blocks 2a and 2c is set as a trigger.
[0017]
Further, if the basic configuration block 2 is arranged in the ASIC 1 in anticipation of an increase or decrease in the number of power supplies to be controlled, it is not necessary to change the design of the ASIC 1 every time the configuration of the device is changed. Further, by making it possible to select the initial value of the basic configuration block 2 by an external signal, it is possible to cope with changes in parameters and equipment configuration when the primary power supply Vdd1 is turned on.
[0018]
FIG. 4 shows a case where a signal from another module inside the ASIC 1 is used as a trigger. By outputting the reception of a signal or packet as a trigger signal at the communication interface 10 including the network, it is possible to turn on the power. Further, if an extended external input block or the like is arranged, the input to the basic configuration block 2 can be apparently increased.
[0019]
As described above, by disposing the basic configuration block 2 inside the ASIC 1, a programmable control circuit can be easily configured, and power saving of the device can be facilitated. In addition, since it is programmable, even if there is a change in the design of the device, the influence on the ASIC 1 is unlikely to occur, and the ASIC 1 can be diverted to many models, and the development cost and period can be shortened.
[0020]
【The invention's effect】
As described above, the present invention can cope with different power supply sequences by software or ASIC initial input setting without redesigning hardware such as ASIC according to the system. The period can be reduced and power saving can be promoted.
[0021]
Moreover, it becomes possible to cut off all the power supplies except ASIC, and a power-saving effect can be improved more. Furthermore, since it is programmable, it is possible to change the control circuit by changing the software even if there is a change in the configuration or control method of the device, and the frequency of making hardware changes can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a configuration diagram of a basic structure block of the embodiment.
FIG. 3 is a configuration diagram of a register.
FIG. 4 is a block diagram showing a configuration of another embodiment.
[Explanation of symbols]
1; ASIC, 2; basic structure block, 3-9; register.

Claims (4)

The input selection block for a plurality of external input signals and selection of a plurality of trigger signals generated within the logic of inversion / non-inversion selecting one register setting of the plurality, the different registers of the configuration and the register An arithmetic block that selects and outputs a logical product or logical sum of outputs of a plurality of input selection blocks, a timer block that delays output from the arithmetic block by setting a register different from the registers, and a register different from the registers A plurality of basic structure blocks having an output selection block for inverting and outputting the output from the timer block by the setting of
The above-mentioned basic structure block controls the power supply of the image forming apparatus when various information indicating that the power supply of the image forming apparatus is turned on as an external input signal is input to the input selection block. . 2. The ASIC with built-in programmable sequencer according to claim 1, wherein the basic structure block controls a power source of the image forming apparatus when information from a network is input as an external input signal to the input selection block. 3. The ASIC with built-in programmable sequencer according to claim 1, wherein the basic structure block controls a power supply of the image forming apparatus when a trigger signal indicating reception of a specific packet in communication is input as an external input signal to the input selection block. .   An image forming apparatus for controlling a shift sequence to a power saving mode and a return sequence from the power saving mode by the ASIC with a programmable sequencer according to claim 1.

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