JP3892323B2 - Logic circuit for handshake protocol conversion and input / output interface circuit for asynchronous LSI chip - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a logic circuit for handshake protocol conversion in an asynchronous digital logic LSI chip, and an input / output interface circuit for an asynchronous LSI chip using the logic circuit.
[0002]
[Prior art]
As a typical configuration method of the asynchronous circuit, two methods of a bundle data transfer method and a two-wire encoding method are mainly known.
[0003]
A configuration method of the bundle data transfer method is shown in FIG. In the bundle data transfer system, two signal lines, a request signal line and an acknowledge signal line, are provided between the data sender 10 and the receiver 20. When the sender 10 transfers data to the receiver 20 through the combinational logic circuit 30, the sender 10 also sends a request signal to notify the receiver 20 of the occurrence of data transfer. The receiver 20 notifies the sender 10 by the acknowledge signal that the data has been received. In the receiver 20, the delay element 1 is inserted in the request signal line so as to ensure a sufficient delay time in order to guarantee the context that the request signal arrives after the data is determined.
[0004]
On the other hand, the two-line encoding method uses two signal lines to send 1-bit data, and gives the data signal line the information itself as information. That is, 1-bit data is coded into 2 bits and sent so that it is possible to determine not only the value of the data but also whether it is valid or invalid. Similar to the bundle data transfer system, the sender is notified of the data reception using the acknowledge signal line. In this method, it is possible to take the timing of data transfer without using a delay element, but in principle, the bandwidth of the data path is twice that of the bundle data transfer method.
[0005]
Further, there are two bundle data transfer methods, a two-cycle bundle data transfer method (also called a micropipeline) and a four-cycle bundle data transfer method, depending on the data transfer protocol. The cycle represents the number of signal transitions related to the transfer of one data, and is sometimes called a two-phase bundle data transfer method or a four-phase bundle data transfer method.
[0006]
FIG. 12 shows a data transfer protocol of the 4-cycle bundle data transfer system. In the 4-cycle bundle data transfer method, data transfer is performed only when the request signal rises or falls. On the other hand, in the 2-cycle bundle data transfer system, as shown in FIG. 13, since the data transfer is performed at both the rising and falling edges of the request signal, the 4-cycle bundle data transfer system is performed in one handshake. Can transfer twice as much data. However, in an asynchronous circuit based on a two-cycle bundle data transfer system, a register used for data transmission / reception must perform writing without distinguishing the rising edge and falling edge of a request signal. Such a register is more complicated in configuration than that in which data is written by one signal transition, and is not usually provided as a standard cell by an LSI chip manufacturing vendor. In addition, the handshake circuit necessary for a practical circuit configuration that switches the data transfer partner according to the internal state is complicated in the 2-cycle bundle data transfer system. For this reason, at present, as a configuration method of the asynchronous circuit in the chip, the 4-cycle bundle data transfer method is more feasible.
[0007]
[Problems to be solved by the invention]
In synchronous LSI chips that control the timing of data transfer with a clock, the maximum performance of data transmission / reception between chips or between chips and peripheral devices is the maximum operating frequency of I / O buffers, transmission line impedance, etc. It depends mainly on the physical characteristics of On the other hand, in the asynchronous LSI chip, the data transmission / reception performance is mainly determined by the sum of delays generated on the transmission path of the request signal and the acknowledge signal.
[0008]
FIG. 14 shows a direct chip-to-chip connection method of asynchronous LSI chips based on the bundle data transfer method and a delay factor generated in signal transmission. In the figure, 100A and 100B represent LSI chip boundaries, 110A and 110B represent logic mounting areas (logic circuits) inside the chips, and terminals 120A and 120B on the LSI chip boundaries 110A and 110B represent I / O pads. On the transmission path of the request signal from the logic circuit 110A on the transmission side to the logic circuit 110B on the reception side, a delay D1 due to the output buffer of the transmission side chip, a signal transmission delay D3 due to wiring delay or RC delay between chips, Furthermore, a delay D2 due to the input buffer of the receiving chip occurs. A similar delay occurs on the transmission path of the acknowledge signal from the logic circuit 110B on the receiving side to the logic circuit 110A in the transmission example. The same applies to the data signal transmission path from the logic circuit 110A in the transmission example to the logic circuit 110B in the reception example. These delays are larger than the gate delay and wiring delay in the chip, and the inter-chip delay D3 increases in accordance with the distance between the chips.
[0009]
The data transfer cycle in such an interchip connection cannot exceed the total delay time of the request signal and the acknowledge signal as described above. In a pipeline of an asynchronous circuit, the data transfer performance may be different in each part of the pipeline, but the throughput of the pipeline is determined by the slowest part of the data transfer performance. Therefore, there is a problem that the data transfer performance between chips becomes a bottleneck and the throughput of the LSI chip is suppressed. This problem becomes more prominent as the distance between chips increases.
[0010]
In particular, when the logic circuits 110A and 110B are configured by a four-cycle bundle data transfer method, it takes time for the transfer of the request signal and the acknowledge signal to reciprocate twice for transferring one data. Prone to bottleneck in performance. A device for improving data transfer efficiency between chips is desired.
[0011]
An object of the present invention is to provide a logic circuit for handshake protocol conversion and an input / output interface circuit for an asynchronous LSI chip capable of improving data transfer efficiency between LSI chips.
[0012]
[Means for Solving the Problems]
The invention according to claim 1 is a handshake protocol conversion logic circuit having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal, and when the request input terminal transitions from a low level to a high level, When the request output terminal is inverted, and then the acknowledge input terminal is inverted, the acknowledge output terminal is changed from low level to high level, and when the request input terminal is changed from high level to low level, the acknowledge output terminal is changed from high level. The logic circuit for handshake protocol conversion is characterized by transitioning to a low level.
[0013]
The invention according to claim 2 is a logic circuit for handshake protocol conversion having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal. When the request input terminal is inverted, the request output terminal is set to a low level. When the acknowledge input terminal transitions from low level to high level, the request output terminal transitions from high level to low level, and when the acknowledge input terminal transitions from high level to low level, the acknowledge The logic circuit for handshake protocol conversion is characterized in that the output terminal is inverted.
[0014]
The invention according to claim 3 is a handshake protocol conversion logic circuit having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal when the request input terminal changes from a low level to a high level. , Transition the acknowledge output terminal from low level to high level and invert the request output terminal, and then wait for the request input terminal to change from high level to low level when the acknowledge input terminal is inverted, The handshake protocol conversion logic circuit is characterized in that the acknowledge output terminal is shifted from a high level to a low level.
[0015]
The invention according to claim 4 is a handshake protocol conversion logic circuit having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal, wherein the acknowledge input terminal is low when the request input terminal is inverted. The request output terminal is changed from a low level to a high level after waiting for the level to change, and then the acknowledge output terminal is inverted when the acknowledge input terminal changes from a low level to a high level, and the request output terminal Is a logic circuit for converting a handshake protocol characterized in that is changed from a high level to a low level.
[0016]
The invention according to claim 5 is a handshake protocol conversion logic circuit comprising a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal, comprising a first and a second D latch and a logic element. The acknowledge input terminal is connected to the data input terminal of the first D latch, and the request input terminal is used as a write enable input terminal of the first D latch so that writing is performed when the request input terminal is at a low level. And connecting the data output terminal of the first D latch to the data input terminal of the second D latch so that the signal is inverted and transmitted, and the request input terminal is at a high level. Connected to the write enable input terminal of the second D-latch so that the write is performed when A data output terminal of the D latch is connected to the request output terminal, and an exclusive OR of the data output terminal of the first D latch and the acknowledge input terminal is connected to the acknowledge output terminal. This is a logic circuit for handshake protocol conversion.
[0017]
The invention according to claim 6 is a logic circuit for handshake protocol conversion comprising a third and a fourth D latch and a logic element, and having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal, The request input terminal is connected to the data input terminal of the third D latch, and the acknowledge input terminal is connected to the write enable input terminal of the third latch so that writing is performed when the acknowledge input terminal is at a high level. The data output terminal of the third latch is connected to the data input terminal of the fourth latch, and the acknowledge input terminal is connected to the data input terminal of the fourth latch so that writing is performed when the acknowledge input terminal is at a low level. Connected to the write enable input terminal, the data output of the fourth latch is Connect to Norwich output terminal, and said third logic circuit for converting the handshake protocol with the data output terminal of the exclusive OR of the request input terminal and characterized by being connected to the request output terminal of the latch.
[0018]
The invention according to claim 7 is a handshake protocol converting logic circuit comprising a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal, comprising an edge trigger type flip-flop and a logic element, wherein the flip-flop The flip-flop inverts and holds the value of the request output terminal at the rising edge of the request input terminal, connects the data output terminal of the flip-flop to the request output terminal, and outputs the data of the acknowledge input terminal and the flip-flop. A handshake protocol conversion logic circuit characterized in that an exclusive OR result with a terminal and the request input terminal are logically summed and connected to the acknowledge output terminal.
[0019]
The invention according to claim 8 is a logic circuit for handshake protocol conversion, comprising a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal, comprising an edge trigger type flip-flop and a logic element. Inverts and holds the value of the acknowledge output terminal at the rising edge of the acknowledge input terminal, connects the data output terminal of the flip-flop to the acknowledge output terminal, the request input terminal and the data output terminal of the flip-flop The handshake protocol conversion logic circuit is characterized in that a negative logical sum of the result of the exclusive negative logical sum and the acknowledge input terminal is obtained and connected to the request output terminal.
[0020]
The invention according to claim 9 is an asynchronous LSI chip input / output interface circuit in an LSI chip on which an asynchronous circuit of a 4-cycle bundle data transfer system is mounted, and a request output terminal for data output from an on-chip circuit and an acknowledge input The terminal is connected to the request input terminal and the acknowledge output terminal of the logic circuit of the invention according to claim 1, 3, 5, or 7, respectively, and the request output of the logic circuit of the invention according to claim 1, 3, 5, or 7 is provided. 9. A terminal and an acknowledge input terminal are respectively connected to a request output terminal and an acknowledge input terminal to the outside of the chip, and a request input terminal and an acknowledge output terminal for data input from the outside of the chip are defined in claim 2, 4, 6, or 8. Connected to the request input terminal and the acknowledge output terminal of the logic circuit of this invention, respectively. The request output terminal and the acknowledge input terminal of the logic circuit of the invention according to claim 2, 4, 6, or 8 are respectively connected to the request input terminal and the acknowledge output terminal for data input of the circuit in the chip. When outputting data to the outside, the handshake protocol is converted from 4 cycles to 2 cycles. When inputting data from outside the chip, the handshake protocol is converted from 2 cycles to 4 cycles. An input / output interface circuit for an LSI chip.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
First Embodiment (Claims 1 and 5)
FIG. 1A is a diagram showing a handshake protocol conversion logic circuit 130 according to an embodiment corresponding to claims 1 and 5. The D latches 131 and 132 in the figure are general elements given in the truth table of FIG. 1B, and when the value of the terminal G is at a high level (“1”), the value of the terminal Din is output to the terminal Dout. When the value of the terminal G is low level (“0”), the previous value is held and output to the terminal Dout. The initial values (output values) of these D latches 131 and 132 are both low. Further, it is assumed that the D latches 131 and 132, the XOR element 133, and the inverters 134 and 135 of the logic circuit 130 do not cause a glitch (hazard) in the output when the input signal changes monotonously. Further, when the signal at the request input terminal changes, the delay of the path through the inverter 134, the D latch 131, and the inverter 135 to the data input terminal Din of the D latch 132 is caused by the signal change at the request input terminal. Is sufficiently longer than the time required to invert the write enable input terminal G of the D latch 132. Further, it is assumed that the inside of the logic circuit 130 is stable from when the signal at the request output terminal or the acknowledge output terminal changes until when the signal at the request input terminal or the acknowledge input terminal changes.
[0022]
At this time, the logic circuit 130 externally changes the request input terminal to low level after the acknowledge output terminal becomes high level, and changes the request input terminal to high level after the acknowledge output terminal becomes low level. When the external control is performed so that the acknowledge input terminal is changed to high level after the request output terminal becomes high level, and the acknowledge input terminal is changed to low level after the request output terminal becomes low level, This circuit operates as shown in the timing chart of FIG.
[0023]
In FIG. 2, a solid arrow indicates a causal relationship of signal transitions by the logic circuit 130, and a dotted arrow indicates a signal transition by external control. That is, the logic circuit 130 inverts the request output terminal when the request input terminal transitions from the low level to the high level, and subsequently transitions the acknowledge output terminal from the low level to the high level when the acknowledge input terminal inverts. When transitioning from the high level to the low level, the acknowledge output terminal operates to transition from the high level to the low level.
[0024]
As can be seen from FIG. 2, in the logic circuit 130 of the first embodiment, a pair of request input terminal and acknowledge output terminal is a handshake receiving side, and a pair of request output terminal and acknowledge input terminal is a handshake sending side. It implements a protocol conversion function that converts a 4-cycle handshake into a 2-cycle handshake.
[0025]
Note that various equivalent circuits can be realized from the logic circuit 130 shown in FIG. 1 by a logic conversion operation such as changing the connection position of the inverter 135. FIG. 3 is a diagram showing a logic circuit 130 'as an example of an equivalent circuit obtained by such a logic conversion operation. In the logic circuit 130 ′ of FIG. 3, the XOR element 133 is changed to the XNOR element 133 ′ and connected, and the inverter 135 is changed to an inverter 135 ′ connected to the data output terminal of the D latch 131. Other logic conversion operations include applying the de Morgan's theorem, expanding the XOR element 133 in FIG. 1 into an AND element and a NOR element, and the like. Of course, the equivalent circuit obtained by such an operation can be used in the same manner as in the first embodiment as long as the above-described timing constraint and the condition that no glitch occurs are observed.
[0026]
Second Embodiment (Claims 2 and 6)
FIG. 4 is a diagram showing a handshake protocol conversion logic circuit 140 according to an embodiment corresponding to claims 2 and 6. The initial values of the D latches 141 and 142 are both low. Similarly to the logic circuit 130, the D latches 141 and 142, the XOR element 143, and the inverter 144 do not cause a glitch due to a monotonous change in the input signal. Further, when the signal at the acknowledge input terminal changes, the delay in the path from the D latch 141 to the data input terminal Din of the D latch 142 is caused by the delay of the acknowledge input terminal signal via the inverter 144. It is assumed that the constraint that it is sufficiently longer than the time required to invert the write enable input terminal G is satisfied. Further, it is assumed that the inside of the logic circuit 140 is stable after the signal at the request output terminal or the acknowledge output terminal changes until the signal at the request input terminal or the acknowledge input terminal changes.
[0027]
At this time, the logic circuit 140 externally changes the request input terminal to low level after the acknowledge output terminal becomes high level, and changes the request input terminal to high level after the acknowledge output terminal becomes low level. When the external control is performed so that the acknowledge input terminal is changed to high level after the request output terminal becomes high level, and the acknowledge input terminal is changed to low level after the request output terminal becomes low level, This circuit operates as shown in the timing chart of FIG.
[0028]
In FIG. 5, a solid arrow indicates a causal relationship of signal transitions by the logic circuit 140, and a dotted arrow indicates a signal transition by external control. That is, the logic circuit 140 changes the request output terminal from the low level to the high level when the request input terminal is inverted, and then changes the request output terminal from the high level to the low level when the acknowledge input terminal changes from the low level to the high level. Further, when the acknowledge input terminal transitions from the high level to the low level, the operation is performed to invert the acknowledge output terminal.
[0029]
As can be seen from FIG. 5, the logic circuit 140 performs a two-cycle handshake when the pair of request input terminal and acknowledge output terminal is a handshake receiving side and the pair of request output terminal and acknowledge input terminal is a handshake sending side. It realizes a protocol conversion function that converts to cycle handshake.
[0030]
In the logic circuit 140 of the present embodiment, the equivalent circuit of FIG. 4 can be used as described with reference to FIG.
[0031]
[Third Embodiment] (Claim 9)
FIG. 6 is a diagram showing an asynchronous LSI chip input / output interface circuit according to an embodiment corresponding to claim 9. Here, the logic circuit 130 of the first embodiment shown in FIG. 1A and the logic circuit 140 of the second embodiment shown in FIG. 4 are used. In FIG. 6, 100A and 100B are LSI chip boundaries, 110A and 110B are logic mounting areas (logic circuits) in the chip on which a 4-cycle bundle data transfer asynchronous circuit is mounted, and LSI chip boundaries 100A and 100B. The upper terminals 120A and 120B represent I / O pads. The logic circuit 130 is provided on the LSI chip 100A side, and the logic circuit 140 is provided on the LSI chip 100B side.
[0032]
R1 represents a request input terminal of the logic circuit 130, A1 represents an acknowledge output terminal, R2 represents a request output terminal, and A2 represents an acknowledge input terminal. R3 represents a request input terminal of the logic circuit 140, A3 represents an acknowledge output terminal, R4 represents a request output terminal, and A4 represents an acknowledge input terminal. Although not shown in the figure, the output signals on the I / O pads 120A and 120B are driven by an output buffer having sufficient driving power, and the input signals are input to the LSI chip via the input buffer having sufficient driving power. Shall be supplied.
[0033]
When outputting data outside the LSI chip, this interface circuit converts a 4-cycle protocol handshake (H1 portion in FIG. 6) for controlling data transfer timing into a 2-cycle protocol (H2 portion in FIG. 6). When inputting data from outside the LSI chip, the handshake of the 2-cycle protocol (H2 ′ portion in FIG. 6) is converted to the 4-cycle protocol (H3 portion in FIG. 6).
[0034]
In this configuration, it is guaranteed that the request output terminal R4 changes from the low level to the high level after the request input terminal R1 changes from the low level to the high level. Further, when the acknowledge output terminal A1 changes from the low level to the high level, it is guaranteed that the request output terminal R4 changes from the low level to the high level and returns from the high level to the low level. Therefore, the sender-side logic circuit 110A may output the next data either when A1 changes from low level to high level or when it returns to low level, and the receiver-side logic circuit 110B. Then, the received data is stable and can be captured during the period when R4 is at the high level.
[0035]
In FIG. 6, 100A is drawn corresponding to the output side, and 100B is drawn corresponding to the input side. However, an implementation method having both input and output functions with a single LSI chip is of course possible. In addition, it is possible to implement a method in which a single LSI chip has a plurality of independent input ports or output ports by dividing and bundling data lines with a plurality of handshake signal line pairs (request signal line and acknowledge signal line pairs). is there.
[0036]
[Fourth Embodiment] (Claims 3 and 7)
FIG. 7 is a diagram showing a handshake protocol conversion logic circuit 150 according to an embodiment corresponding to claims 3 and 7. The flip-flop 151 holds the value of the request output terminal and inverts the value when the signal of the request input terminal rises. The holding value is inverted by feeding back the data output terminal Dout of the flip-flop 151 to the data input terminal Din via the inverter 154. This can also be realized by supplying the value of the acknowledge input terminal to the data input terminal Din of the flip-flop 151 via an inverter or replacing the flip-flop 151 with a T flip-flop. The initial holding value of the flip-flop 151 is set to a low level. The flip-flop 151, the XOR element 152, the OR element 153, and the inverter 154 of the logic circuit 150 do not generate a glitch in the output when the input signal changes. Furthermore, the inside of the logic circuit 150 is assumed to be stable from when the signal at the request output terminal or the acknowledge output terminal changes until the signal at the request input terminal or acknowledge input terminal changes.
[0037]
The XOR element 152 compares the output value of the flip-flop 151, that is, the value of the request output terminal with the value of the acknowledge input terminal, and outputs a low level when they match, and outputs a high level otherwise. The OR element 153 sets the acknowledge output terminal to a high level when the request input terminal is at a high level or when the output value of the XOR element 152 is at a high level, that is, when the values of the acknowledge input terminal and the request output terminal do not match. At other times, a low level is output.
[0038]
The logic circuit 150 is externally controlled so that the request input terminal changes to low level after the acknowledge output terminal becomes high level, and the request input terminal changes to high level after the acknowledge output terminal becomes low level. If the external control is performed so that the acknowledge input terminal is changed to high level after the request output terminal becomes high level, and the acknowledge input terminal is changed to low level after the request output terminal becomes low level, this circuit The operation is as shown in the timing chart of FIG.
[0039]
In FIG. 8, a solid arrow indicates a causal relationship of signal transition by the logic circuit 150, and a dotted arrow indicates a signal transition by external control. That is, when the request input terminal changes from the low level to the high level, the logic circuit 150 sets the acknowledge output terminal to the high level and inverts the request output terminal, and then the values of the request output terminal and the acknowledge input terminal match. In addition, it waits for the request input terminal to change from high level to low level, and operates to make the acknowledge output terminal low level.
[0040]
When the request input terminal and acknowledge output terminal pair is the handshake receiver, and the request output terminal and acknowledge input terminal pair is the handshake sender, these circuits also convert the 4-cycle handshake into a 2-cycle handshake. The function is realized. However, unlike the logic circuit 130 of the first embodiment shown in FIG. 1B, the fact that the acknowledge input terminal is inverted corresponding to the request output terminal means that the acknowledge output terminal changes from low level to high level. It is not guaranteed at the time of operation, and is guaranteed when returning from the high level to the low level.
[0041]
Note that, in the logic circuit 150 of the present embodiment, the equivalent circuit of FIG. 7 can be used as described with reference to FIG.
[0042]
[Fifth Embodiment] (Claims 4 and 8)
FIG. 9 is a diagram showing a handshake protocol conversion logic circuit 160 according to an embodiment corresponding to claims 4 and 8. The flip-flop 161 holds the value of the acknowledge output terminal, and inverts the value when the acknowledge input terminal rises. The inversion of the hold value is the same as that of the logic circuit 150. The initial value held by the flip-flop 161 is set to a low level, and other mounting conditions are the same as those of the logic circuit 150.
[0043]
The XNOR element 162 compares the output value of the flip-flop 161, that is, the value of the acknowledge output terminal with the value of the request input terminal, and outputs a high level when they match, and outputs a low level otherwise. The NOR element 163 has a high level at the request output terminal when the acknowledge input terminal is at a low level and the output value of the XNOR element 162 is at a low level, that is, the request input terminal and the acknowledge output terminal do not match. Output low level.
[0044]
The logic circuit 160 is externally controlled so that the request input terminal changes to low level after the acknowledge output terminal becomes high level, and the request input terminal changes to high level after the acknowledge output terminal becomes low level. If the external control is performed so that the acknowledge input terminal is changed to high level after the request output terminal becomes high level, and the acknowledge input terminal is changed to low level after the request output terminal becomes low level, this circuit The operation is as shown in the timing chart of FIG.
[0045]
In FIG. 10, a solid arrow indicates a causal relationship of signal transition by the logic circuit 160, and a dotted arrow indicates a signal transition by external control. That is, the logic circuit 160 waits for the acknowledge input terminal to become low level when the request input terminal is inverted, changes the request output terminal from low level to high level, and then changes the acknowledge input terminal from low level to high level. When this occurs, the acknowledge output terminal is inverted and the request output terminal is changed from the high level to the low level.
[0046]
If the request input terminal and acknowledge output terminal pair is the handshake receiving side, and the request output terminal and acknowledge input terminal pair is the handshake sending side, these circuits also convert the 2-cycle handshake into a 4-cycle handshake. The conversion function is realized. However, unlike the logic circuit 140 according to the second embodiment shown in FIG. 4, when the acknowledge output terminal is inverted, it is guaranteed that the request output terminal and the acknowledge input terminal are changed from the low level to the high level. It is not guaranteed until the request output terminal and the acknowledge input terminal return from the high level to the low level.
[0047]
Note that, in the logic circuit 160 of this embodiment, the equivalent circuit of FIG. 9 can be used in the same manner as described with reference to FIG.
[0048]
[Sixth Embodiment] (Claim 9)
The logic circuit 130 in FIG. 6 is replaced with the logic circuit 150 of the fourth embodiment shown in FIG. 7, and the logic circuit 140 is replaced with the logic circuit 160 of the fifth embodiment shown in FIG. The asynchronous LSI chip input / output interface circuit according to the embodiment corresponding to Item 9 can be configured. In other words, when outputting data outside the chip, the 4-cycle protocol handshake that controls the timing of data transfer is converted into a 2-cycle protocol. When inputting data from outside the chip, the 2-cycle protocol handshake is converted. It can be configured to convert to a 4-cycle protocol.
[0049]
However, in this configuration, the request output terminal R4 changes from low level to high level after the request input terminal R1 changes from low level to high level, and the acknowledge output terminal A1 changes from high level to low level. Although it is guaranteed that R4 and A4 change from low level to high level at the time, R4 and A4 change from low level to high level when the acknowledge output terminal A1 changes from low level to high level. Neither is it guaranteed to return from high level to low level.
[0050]
Therefore, in order to perform data transfer correctly, the logic circuit 110A on the sender side cannot output the next data until A1 changes from low level to high level and returns from high level to low level. The logic circuit 110B on the receiver side must capture data only at the rising edge of R4.
[0051]
On the other hand, the signal transition of the interface circuit of the third embodiment described with reference to FIG. 6 is completely sequential, whereas in the signal transition of the interface circuit of the present embodiment, R1 is set after A1 becomes high level. And the transition from R2 inversion to A2 inversion can occur independently, and the transition from R4 to low level until A4 goes to low level and A3 Transitions from inversion to R3 inversion can also occur independently. That is, a partial transition of the handshake H1 of the sender side logic circuit 110A, the handshake H3 of the receiver side logic circuit 110B, and the handshakes H2 and H2 'between the chips can be performed simultaneously in parallel. For this reason, in this embodiment, the time required for one handshake of data transfer can be shortened compared with the third embodiment described with reference to FIG.
[0052]
[Other Embodiments]
As the asynchronous LSI chip input / output interface circuit of the embodiment corresponding to claim 9, the logic circuit 130 of the input / output interface circuit of the third embodiment shown in FIG. 6 is replaced with the logic of the fourth embodiment. A configuration in which only the circuit 140 is replaced or only the logic circuit 140 is replaced with the logic circuit 160 of the fifth embodiment may be employed, and both operate in the same manner.
[0053]
【The invention's effect】
As described above, according to the first, third, fifth, or seventh aspect of the invention, a logic circuit that converts a four-cycle handshake into a two-cycle handshake can be configured. According to the invention, a logic circuit that converts a 2-cycle handshake into a 4-cycle handshake can be configured.
[0054]
Further, according to the invention of claim 9, in an asynchronous LSI chip that employs the 4-cycle bundle data transfer system for internal circuit mounting, the handshake for inter-chip communication and data transfer with peripheral devices is converted into a 2-cycle protocol. Therefore, the number of round trips between the request signal and the acknowledge signal can be halved, that is, the delay due to the I / O buffer and the wiring delay between chips can be reduced by half, and in principle, the time required for one data transfer is a maximum of 2 minutes. Can be shortened to 1. As a result, in the asynchronous LSI chip of the 4-cycle bundle data transfer method, the problem that the data transfer outside the chip becomes a bottleneck and the chip performance is lowered can be alleviated.
[Brief description of the drawings]
FIG. 1A is a block diagram of a handshake protocol conversion logic circuit according to a first embodiment, and FIG. 1B is an explanatory diagram of truth values that define the function of a D latch.
FIG. 2 is a timing chart showing the operation of the handshake protocol conversion logic circuit of the first embodiment;
FIG. 3 is a block diagram of a modified example of the logic circuit for handshake protocol conversion according to the first embodiment.
FIG. 4 is a block diagram of a handshake protocol conversion logic circuit according to a second embodiment;
FIG. 5 is a timing chart showing the operation of the handshake protocol conversion logic circuit according to the second embodiment;
FIG. 6 is a block diagram of an input / output interface circuit for an asynchronous LSI chip according to a third embodiment.
FIG. 7 is a block diagram of a handshake protocol conversion logic circuit according to a fourth embodiment.
FIG. 8 is a timing chart showing an operation of the handshake protocol conversion logic circuit according to the fourth embodiment;
FIG. 9 is a block diagram of a logic circuit for handshake protocol conversion according to a fifth embodiment.
FIG. 10 is a timing chart showing the operation of the handshake protocol conversion logic circuit of the fifth embodiment;
FIG. 11 is an explanatory diagram of a configuration method of an asynchronous circuit using a bundle data transfer method.
FIG. 12 is a timing chart for explaining a data transfer protocol of a 4-cycle bundle data transfer method.
FIG. 13 is a timing chart for explaining a data transfer protocol of a two-cycle bundle data transfer method.
FIG. 14 is an explanatory diagram of a delay that occurs in an inter-chip connection of an asynchronous circuit using a bundle data transfer method.
[Explanation of symbols]
130, 130 ', 150: logic circuit for handshake protocol conversion for converting a 4-cycle handshake into a 2-cycle handshake
140, 160: logic circuit for handshake protocol conversion that converts a 2-cycle handshake into a 4-cycle handshake

Claims (9)

A handshake protocol conversion logic circuit having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal,
When the request input terminal transitions from low level to high level, the request output terminal is inverted, and when the acknowledge input terminal is inverted thereafter, the acknowledge output terminal is transitioned from low level to high level, and the request input terminal is high level. A logic circuit for handshake protocol conversion, wherein the acknowledge output terminal is transitioned from a high level to a low level when transitioning from a low level to a low level. A handshake protocol conversion logic circuit having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal,
When the request input terminal is inverted, the request output terminal is changed from a low level to a high level, and when the acknowledge input terminal is changed from a low level to a high level, the request output terminal is changed from a high level to a low level. A logic circuit for handshake protocol conversion, wherein the acknowledge output terminal is inverted when the acknowledge input terminal transitions from a high level to a low level. A handshake protocol conversion logic circuit having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal,
When the request input terminal changes from a low level to a high level, the acknowledge output terminal is shifted from a low level to a high level and the request output terminal is inverted, and then the request input terminal is inverted when the acknowledge input terminal is inverted. A handshake protocol conversion logic circuit, wherein the acknowledge output terminal is shifted from a high level to a low level after waiting for the terminal to change from a high level to a low level. A handshake protocol conversion logic circuit having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal,
When the request input terminal is inverted, the request input terminal is changed from low level to high level after waiting for the acknowledge input terminal to become low level, and then the acknowledge input terminal is changed from low level to high level. A logic circuit for handshake protocol conversion, wherein the acknowledge output terminal is inverted and the request output terminal is changed from a high level to a low level. A handshake protocol conversion logic circuit comprising a first and second D latches and a logic element, and having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal,
The acknowledge input terminal is connected to the data input terminal of the first D latch, and the request input terminal is used as a write enable input terminal of the first D latch so that writing is performed when the request input terminal is at a low level. And connecting the data output terminal of the first D latch to the data input terminal of the second D latch so that the signal is inverted and transmitted, and the request input terminal is at a high level. The write output is connected to the write enable input terminal of the second D latch, the data output terminal of the second D latch is connected to the request output terminal, and the data output terminal of the first D latch And the acknowledge output terminal are connected to the acknowledge output terminal. Col conversion logic circuit. A handshake protocol conversion logic circuit comprising a third and a fourth D latch and a logic element, and having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal;
The request input terminal is connected to the data input terminal of the third D latch, and the acknowledge input terminal is connected to the write enable input terminal of the third latch so that writing is performed when the acknowledge input terminal is at a high level. The data output terminal of the third latch is connected to the data input terminal of the fourth latch, and the acknowledge input terminal is connected to the data input terminal of the fourth latch so that writing is performed when the acknowledge input terminal is at a low level. Connected to the write enable input terminal, connected the data output of the fourth latch to the acknowledge output terminal, and exclusive OR of the data output terminal of the third latch and the request input terminal to the request output terminal A logic circuit for handshake protocol conversion characterized by being connected. A handshake protocol conversion logic circuit consisting of an edge trigger type flip-flop and a logic element, having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal,
The flip-flop inverts and holds the value of the request output terminal at the rising edge of the request input terminal,
Connecting the data output terminal of the flip-flop to the request output terminal;
A logic for handshake protocol conversion, wherein the logical sum of the exclusive OR result of the acknowledge input terminal and the data output terminal of the flip-flop and the request input terminal is obtained and connected to the acknowledge output terminal circuit. A handshake protocol conversion logic circuit consisting of an edge trigger type flip-flop and a logic element, having a request input terminal, an acknowledge output terminal, a request output terminal, and an acknowledge input terminal,
The flip-flop inverts and holds the value of the acknowledge output terminal at the rising edge of the acknowledge input terminal,
Connecting the data output terminal of the flip-flop to the acknowledge output terminal;
A handshake protocol conversion characterized in that an exclusive logical sum of the request input terminal and the data output terminal of the flip-flop and a negative logical sum of the acknowledge input terminal are connected to the request output terminal. Logic circuit. In an input / output interface circuit for an asynchronous LSI chip in an LSI chip on which an asynchronous circuit of a 4-cycle bundle data transfer system is mounted,
8. A request output terminal and an acknowledge input terminal for outputting data from an on-chip circuit are connected to the request input terminal and the acknowledge output terminal of the logic circuit according to claim 1, 3, 5, or 7, respectively. Or the request output terminal and the acknowledge input terminal of the logic circuit 7 are respectively connected to the request output terminal and the acknowledge input terminal outside the chip,
A request input terminal and an acknowledge output terminal for inputting data from outside the chip are connected to a request input terminal and an acknowledge output terminal of the logic circuit according to claim 2, 4, 6, or 8, respectively. Alternatively, the request output terminal and the acknowledge input terminal of the logic circuit 8 are connected to the request input terminal and the acknowledge output terminal for data input of the circuit in the chip, respectively.
When outputting data outside the chip, the handshake protocol is converted from 4 cycles to 2 cycles, and when inputting data from outside the chip, the handshake protocol is converted from 2 cycles to 4 cycles. Input / output interface circuit for asynchronous LSI chip.

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