JP3888463B2 - Memory cell and magnetic random access memory - Google Patents

Description

  The present invention relates to a magnetic memory cell and a magnetic random access memory, and more particularly to a magnetic memory cell and a magnetic random access memory in which a transistor is combined with a tunnel magnetoresistive element.

  A technique of a magnetic random access memory (hereinafter referred to as “MRAM”) is known. The MRAM will be described with reference to a technique disclosed in US Pat. No. 6,191,989 (see Patent Document 1).

  FIG. 93 is a diagram showing the principle of the magnetoresistive element included in the magnetic memory cell. The magnetoresistive element 107 includes a free layer 121 having reversible spontaneous magnetization, a pinned layer 123 having fixed spontaneous magnetization, and a tunnel insulating layer 122 intervened between the pinned layer 123 and the free layer 121. Is provided. The free layer 121 is formed so that the direction of the spontaneous magnetization can be parallel or antiparallel to the direction of the spontaneous magnetization of the pinned layer 123.

  The magnetoresistive element 107 has an electric resistance that changes depending on whether the direction of the spontaneous magnetization of the free layer 121 is parallel or antiparallel to the direction of the spontaneous magnetization of the pinned layer 123. Change. The magnetoresistive element 107 associates “1” with one of a “parallel” state in which the directions of spontaneous magnetization are parallel to each other and an “anti-parallel” state with antiparallel to each other, and “0” with the other. For example, in FIG. 93A, if the direction of spontaneous magnetization is antiparallel, the resistance of the magnetoresistive element 107 is R + ΔR, and the applied voltage is constant, the amount of current is small. This state is associated with “1”. On the other hand, in FIG. 93B, the direction of spontaneous magnetization is parallel, the resistance of the magnetoresistive element 107 becomes R, and the amount of current increases. This state is associated with “0”.

  A semiconductor memory device using the magnetic memory cell including the magnetoresistive element 107 as the memory cell 102 is called an MRAM. The magnetization direction of the pinned layer 123 is fixed at the time of manufacture. The pinning is often performed using the antiferromagnetic material layer 124.

FIG. 94 is a diagram showing a cross section of the memory cell. The memory cell 102 includes a magnetoresistive element 107, a MOS transistor 106, a contact wiring 126, a contact wiring 127, a contact wiring 128, and a lead wiring 129.
The MOS transistor 106 includes a first diffusion layer 106a, a second diffusion layer 106c, and a semiconductor substrate between the first diffusion layer 106a and the second diffusion layer 106c provided in the semiconductor substrate via an insulating layer. And a first gate 106b provided. The first diffusion layer 106 a is connected to the GND wiring 124 through the contact wiring 128. The second diffusion layer 106 c is connected to one end of the lead wiring layer 129 through the contact wiring 127. The gate 106b is connected to the read word line 104. The lead wiring layer 129 is connected to one end side of the magnetoresistive element 107 at the other end. The magnetoresistive element 107 is connected to the bit line 105 via the contact wiring 126 on the other end side. Further, a write word line 103 is provided on the opposite side of the bit line 105 with respect to the magnetoresistive element 107 via a lead wiring layer 129 and an interlayer insulating layer 125 so as to be orthogonal to the bit line 105.

  The spontaneous magnetization of the free layer 121 in the magnetoresistive element 107 is caused by a combined magnetic field induced by a current flowing through the bit line 105 passing over the memory cell 102 and a current flowing through the write word line 103 passing under the memory cell 102. Inverted in the desired orientation.

FIG. 95 is a diagram showing the principle of writing data to the magnetoresistive element. The vertical axis is the magnetic field in the Y-axis direction (corresponding to FIGS. 93 and 94), and the horizontal axis is the magnetic field in the X-axis direction. The coercive force of the free layer 121 exhibits a characteristic called an asteroid curve (magnetization reversal magnetic field curve). Applying a magnetic field in the region outside the asteroid curve means that the magnetic field exceeds the coercive force and thus the spontaneous magnetization of the free layer 121 is reversed. The asteroid curve in FIG. 95 is obtained when a synthetic magnetic field H _{0 that} is oriented at 45 ° with respect to both the X axis and the Y axis is applied to the free layer 121 by the bit line 105 and the write word line 103 that are orthogonal to each other. It is shown that the spontaneous magnetization of the free layer 121 is most easily reversed.
The current flowing through the bit line 105 and the write word line 103 is a magnetic field H in which the combined magnetic field H ₀ of the magnetic fields generated by these currents is in the region outside the asteroid curve and each current is generated independently. _Y0 and _HX0 are selected to be in the area inside the asteroid curve. By selecting each current in this way, data can be written to the magnetoresistive element 107.

  FIG. 96 is a diagram showing a conventional MRAM using memory cells. The conventional MRAM includes a memory cell array 101, a plurality of write word lines 103, a plurality of read word lines 104, a plurality of bit lines 105, an X selector 108, an X side current source circuit 109, an X side current termination circuit 110, and a Y selector 111. , A Y-side current source circuit 112, a read current load circuit 113, a Y-side current termination circuit 114, and a sense amplifier 115.

  In the memory cell array 101, memory cells 102 are arranged in a matrix. The X selector 108 selects a desired selected read word line 104s during a read operation from a plurality of read word lines 104 and a plurality of write word lines 103 extending in the X-axis direction (word line direction), and a desired read word line 104s during a write operation. The selective write word line 103s is selected. The X-side current source circuit 109 is a constant current source that supplies a constant current during a data write operation to the memory cell 102. The X-side current termination circuit 110 terminates the plurality of write word lines 103. The Y selector 111 selects a desired selected bit line 105 s from a plurality of bit lines 105 extending in the Y-axis direction (bit line direction). The Y-side current source circuit 112 is a constant current source that supplies a constant current during a data write operation to the memory cell 102. The read current load circuit 113 is a constant current source that supplies a predetermined current to the selected memory cell and the reference memory cell 102r during a data read operation from the memory cell 102. The Y-side current termination circuit 114 terminates the plurality of bit lines 105. The sense amplifier 115 is based on the difference between the voltage of the reference bit line 105r connected to the reference memory cell 102r and the voltage of the bit line 105 connected to the selected memory cell 102 (hereinafter, selected cell 102s). The data of the selected cell 102s is output.

  The memory cell 102 is provided corresponding to the intersection of the read word line 104, the write word line 103, and the bit line 105. The memory cell 102 includes a MOS transistor 106 that is turned on when the memory cell 102 is selected, and a magnetoresistive element 107, which are connected in series. The magnetoresistive element 107 is indicated by a variable resistance symbol because the effective resistance value changes between data “1” and “0” (R + ΔR and R).

  Reading data from the memory cell 102 is performed as follows. That is, the read current load circuit 113 applies the magnetoresistive element 107 of the selected cell 102s corresponding to the intersection of the selected read word line 104s selected by the X selector 108 and the selected bit line 105s selected by the Y selector. A constant current is supplied. As a result, the selected bit line 105s becomes a voltage having a magnitude corresponding to the state of the free layer 121 of the magnetoresistive element 107 (resistance value of the magnetoresistive element 107). On the other hand, a constant current is similarly supplied to the reference memory cell 102r selected by the bit line 105r and the selected read word line 104s, and the bit line 105r becomes a predetermined reference voltage. Then, the sense amplifier 115 compares the magnitudes of both voltages. For example, if the voltage of the selected bit line 105s is larger than the reference voltage, the data of the selected cell 102s is determined to be “1”, and if it is smaller, it is determined to be “0”.

Data is written to the memory cell 102 as follows. That is, the magnetic field H _Y0 and the magnetic field H are applied to the magnetoresistive element 107 of the selected cell 102s corresponding to the intersection of the selected write word line 103s selected by the X selector 108 and the selected bit line 105s selected by the Y selector. _X0 and occurs to generate a composite magnetic field _{H 0.} However, the magnetic field H _Y0 is generated when a current flows through the selective write word line 103 by the X-side current source circuit 109. The magnetic field H _X0 is generated when a current having a direction corresponding to data written by the Y-side current source circuit 112 flows through the selected bit line 105. The magnetoresistive element 107 receives the combined magnetic field H ₀ and reverses the direction of spontaneous magnetization so as to correspond to the data to be written.

In the MRAM shown here, data is written to the memory cell by the combined magnetic field H ₀ formed by the current flowing through the selected write word line and the current flowing through the selected bit line. If the current used for writing is too small, data cannot be written. On the other hand, if it is too large, data may be written not only to the selected cell but also to other memory cells connected to the same selected write word line or the same selected bit line. Accordingly, high accuracy is required for the current values of the current flowing through the selected write word line and the current flowing through the selected bit line.

  There is a need for a technique that does not affect other memory cells when data is written to a selected memory cell. In data writing, there is a demand for a technique capable of further increasing a write current margin. There is a need for a memory cell configuration that is highly selective when selecting cells from the memory cell array. A technique capable of manufacturing a nonvolatile memory with a high yield is desired. A technique for manufacturing a nonvolatile memory at low cost is desired.

Further, as a related technique, Japanese Patent Application Laid-Open No. 2002-230965 (Patent Document 2) discloses a technique of a nonvolatile memory device. The nonvolatile memory device of this technology is a nonvolatile memory device that includes a magnetoresistive element whose resistance value changes depending on the magnetization direction in a memory cell, and records 1-bit information in the memory cell. Here, the memory cell has a plurality of subcells including at least one magnetoresistive element. The subcells are connected in series or in parallel. However, the subcell includes one subcell in which a plurality of magnetoresistive elements are connected in parallel or in series and one selection transistor. The memory cell may be a plurality of subcells connected in series or in parallel.
This technique improves the recording reliability of the MRAM, realizes highly reliable reading of information even when a certain amount of resistance value variation is assumed, and bias voltage of MR ratio of the magnetoresistive element Its purpose is to alleviate dependence.

Japanese Laid-Open Patent Publication No. 2002-140889 (Patent Document 3) discloses a technique of a ferromagnetic memory and an information reproducing method thereof. The ferromagnetic memory according to this technique includes a variable resistor, a magnetic field generation unit, a holding circuit, and a signal detection circuit. Here, the variable resistor is made of a magnetic material, and includes a hard layer for storing information according to the direction of magnetization, a nonmagnetic layer, and a soft layer made of a magnetic material having a smaller coercive force than the hard layer. The magnetic field generating means initializes the magnetization of the soft layer and reverses it from the initialized state. The holding circuit holds the resistance value in the initialized state. The signal detection circuit compares the resistance value of the inverted variable resistor with the resistance value held in the holding circuit, and outputs a reproduction signal.
This technique aims to reduce the cell area and stably detect stored information in the 1T1R type MRAM.

Japanese Unexamined Patent Publication No. 2002-1000018 (Patent Document 4) discloses a magnetic random access memory technology. A magnetic random access memory according to this technology includes a plurality of sense lines, a plurality of word lines provided orthogonal to the plurality of sense lines, and unit storage cells arranged in an array at each intersection of the sense lines and the word lines It comprises. Here, in the unit memory cell, a cell selection switch and a magnetoresistive element are connected in series. Furthermore, it has a capacitor connected to the power supply through a switch, and a voltage drop element that connects between one end of the capacitor and the sense line. One end of the capacitor is used as a voltage change detection end corresponding to information stored in the unit memory cell.
This technology eliminates variations in the characteristics of magnetoresistive elements, widens operating margins, and leads to voltage drops due to wiring connected in series with the magnetoresistive elements and transistor resistance. Sensitivity of the readout circuit (sense amplifier) It is intended to prevent the decrease in the resistance, the bias effect of the magnetic resistance, and the destruction of the tunnel barrier.

US Pat. No. 6,191,989 JP 2002-230965 A JP 2002-140889 A JP 2002-1000018 A

  Accordingly, an object of the present invention is to provide a magnetic memory cell and a magnetic random access memory that do not affect the remaining memory cells when data is written to selected memory cells.

  Another object of the present invention is to provide a magnetic memory cell and a magnetic random access memory capable of further increasing a write current margin when data is written to the memory cell.

  Still another object of the present invention is to provide a magnetic memory cell and a magnetic random access memory having high selectivity when selecting a memory cell from a memory cell array.

  Another object of the present invention is to provide a magnetic memory cell and a magnetic random access memory that can be manufactured at a high yield.

  Still another object of the present invention is to provide a magnetic memory cell and a magnetic random access memory that can be manufactured at low cost while suppressing manufacturing costs.

  Still another object of the present invention is to provide a magnetic memory cell and a magnetic random access memory capable of reducing parasitic capacitance and improving processing speed.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the best mode for carrying out the invention. These numbers and symbols are added with parentheses to clarify the correspondence between the description of the claims and the best mode for carrying out the invention. However, these numbers and symbols should not be used for interpreting the technical scope of the invention described in the claims.

  Therefore, in order to solve the above problem, the memory cell of the present invention includes the first transistor (6) and the magnetoresistive element (7). The first transistor (6) includes a first gate (6b), a first terminal (6a) as one terminal other than the first gate (6b), and a second terminal (6c) as the other terminal. Including. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, and includes a third terminal as one terminal and a fourth terminal as the other terminal. The first terminal (6a) is connected to the first bit line (4). The second terminal (6c) is connected to the second bit line (5). The first gate (6b) is connected to the first word line (3W). The third terminal is connected to the second word line (3R). The fourth terminal is connected to the second terminal (6c).

  Here, in the data write operation to the memory cell, the current (Iw) flowing between the first bit line (4) and the second bit line (5) when the first transistor (6) is turned on. Based on (1), Iw (0)), data is written to the magnetoresistive element (7). In the data read operation, data is read from the magnetoresistive element (7) based on the current (Is) passing through the second bit line (5) and the magnetoresistive element (7).

  The memory cell further includes a second transistor (16). The second transistor (16) is provided between the first transistor (6) and the second bit line (5). It includes a second gate (16b), a fifth terminal (16a) as one terminal other than the second gate (16b), and a sixth terminal (16c) as the other terminal. The fifth terminal (16a) is connected to the second bit line (5). The sixth terminal (16c) is connected to the second terminal (6c). The second gate (16b) is connected to the first word line (3). The third terminal is connected to the ground (24) instead of the second word line.

  Here, in the data write operation to the memory cell, the first transistor (6) and the second transistor (16) are turned on by turning on the first transistor (6) and the second transistor (16). Is written to the magnetoresistive element (7) based on the currents (Iw (1), Iw (0)) flowing between the two. In the data read operation, the data from the magnetoresistive element (7) is based on the current (Is) passing through the first transistor (6) and the magnetoresistive element (7) when the first transistor (6) is turned on. Is read out.

  In the above memory cell, a fifth gate provided between the first transistor (6) and the second bit line (5) and serving as one terminal other than the second gate (16b) and the second gate (16b). A second transistor (16) including a terminal (16a) and a sixth terminal (16c) as the other terminal is further provided. The fifth terminal (16a) is connected to the second bit line (5). The sixth terminal (16c) is connected to the second terminal (6c). The second gate (16b) is connected to the first word line (3). The third terminal is connected to the third bit line (35) instead of the second word line (5).

  Here, in the data write operation to the memory cell, the first transistor (6) and the second transistor (16) are turned on by turning on the first transistor (6) and the second transistor (16). Is written to the magnetoresistive element (7) based on the currents (Iw (1), Iw (0)) flowing between the two. In the data read operation, the data from the magnetoresistive element (7) is based on the current (Is) passing through the first transistor (6) and the magnetoresistive element (7) when the first transistor (6) is turned on. Is read out.

  The memory cell further includes a diode (31). The diode (31) is provided between the magnetoresistive element (7) and the second word line (3R). A seventh terminal having a first polarity and an eighth terminal having a second polarity different from the first polarity are included. The seventh terminal is connected to the third terminal. The eighth terminal is connected to the second word line (3R).

  Here, in the data write operation to the memory cell, the current (Iw) flowing between the first bit line (4) and the second bit line (5) when the first transistor (6) is turned on. Based on (1), Iw (0)), data is written to the magnetoresistive element (7). Also, in the data read operation, the magnetoresistive element (6) is turned on based on the current (Is) passing through the first bit line (4) and the magnetoresistive element (7). Data is read from 7).

  The memory cell further includes a second diode (32) and a third diode (33). The second diode (32) is provided between the first transistor (6) and the second bit line (5), and has a ninth terminal having a first polarity and a tenth terminal having a second polarity different from the first polarity. Including. The third diode (32) is provided between the first transistor and the second bit line, and includes an eleventh terminal having a first polarity and a twelfth terminal having the second polarity. The ninth terminal is connected to the second bit line (5). The tenth terminal is connected to the second terminal. The eleventh terminal is connected to the second terminal. The twelfth terminal is connected to the second bit line (5). The third terminal is connected to a predetermined voltage source (24a) instead of the second word line.

  Here, in the data write operation to the memory cell, the current (Iw) flowing between the first bit line (4) and the second bit line (5) when the first transistor (6) is turned on. Based on (1), Iw (0)), data is written to the magnetoresistive element (7). Also, in the data read operation, the magnetoresistive element (6) is turned on based on the current (Is) passing through the first bit line (4) and the magnetoresistive element (7). Data is read from 7).

  The memory cell further includes a second diode (32) and a third diode (33). The second diode (32) is provided between the first transistor (6) and the second bit line (5). It includes a ninth terminal having a first polarity and a tenth terminal having a second polarity different from the first polarity. The third diode (33) is provided between the second bit line (5) and the first diode (32). An eleventh terminal having a first polarity and a twelfth terminal having a second polarity are included. The tenth terminal is connected to the second terminal. The ninth terminal is connected to the eleventh terminal. The twelfth terminal is connected to the second bit line (5). The third terminal is connected to a predetermined voltage source instead of the second word line. The reverse voltage applied to either the second diode (32) or the third diode (32) during the write operation is equal to or higher than the breakdown voltage (Vbd).

  Here, in the data write operation to the memory cell, the current (Iw) flowing between the first bit line (4) and the second bit line (5) when the first transistor (6) is turned on. Based on (1), Iw (0)), data is written to the magnetoresistive element (7). Also, in the data read operation, the magnetoresistive element (6) is turned on based on the current (Is) passing through the first bit line (4) and the magnetoresistive element (7). Data is read from 7).

  The memory cell further includes a third transistor (6-2) and a fourth transistor (16-2). The third transistor (6-2) includes a third gate, a seventh terminal as one terminal other than the third gate, and an eighth terminal as the other terminal. The fourth transistor (16-2) includes a fourth gate, a ninth terminal as one terminal other than the fourth gate, and a tenth terminal as the other terminal. The third gate and the fourth gate branch from the first word line (3a) and are connected to the third word line (3b) having substantially the same potential as the first word line (3a). The seventh terminal is connected to the first bit line (4). The eighth terminal is connected to the second terminal. The ninth terminal is connected to the second bit line (5). The tenth terminal is connected to the sixth terminal.

  Here, in the data write operation to the memory cell, the first transistor (6-1), the second transistor (16-1), the third transistor (6-2), and the fourth transistor (16-2). Each of the transistors is turned on to flow between the first transistor (6-1) and the third transistor (6-2) and the second transistor (16-1) and the fourth transistor (16-2). Data is written to the magnetoresistive element (7) based on the current (Iw (1), Iw (0)). In the data read operation, the first transistor (6-1) and the third transistor (6-2) and the magnetoresistive element (6-2) are turned on by turning on the first transistor (6-1) and the third transistor (6-2). 7), data is read from the magnetoresistive element (7) based on the current (Is) that passes through (7).

  In addition, the memory cell of the present invention includes a second diode (32), a third diode (33), and a magnetoresistive element (7). The second diode (32) includes a first terminal having a first polarity and a second terminal having a second polarity different from the first polarity. The third diode (33) includes a third terminal having a first polarity and a fourth terminal having a second polarity. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, and includes a fifth terminal as one terminal and a sixth terminal as the other terminal. The second terminal and the third terminal are connected to the first word line (3W). The first terminal, the fourth terminal, and the fifth terminal are connected to the bit line (4). The sixth terminal is connected to the second word line (3R).

  Here, in the data write operation to the memory cell, the first word line (3W) and the bit line (4) are based on the potential difference between the first word line (3W) and the bit line (4). Data is written to the magnetoresistive element (7) based on the currents flowing between (Iw (1), Iw (0)). In the data read operation, data is read from the magnetoresistive element (7) based on the current (Is) passing through the bit line (4) and the magnetoresistive element (7).

  The memory cell further includes a first diode (31) including a seventh terminal having a first polarity and an eighth terminal having a second polarity. The first diode (31) is provided between the magnetoresistive element (7) and the second word line (3R). The eighth terminal is connected to the second word line (3R), and the seventh terminal is connected to the sixth terminal.

  Furthermore, the memory cell of the present invention includes a transistor (6), a magnetoresistive element (7), and a capacitor (19). The transistor (6) includes a gate (6b), a first terminal (6a) as one terminal other than the gate (6b), and a second terminal (6c) as the other terminal. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, the third terminal as one terminal is grounded (24), and the fourth terminal as the other terminal Is connected to the second terminal (6c) through the wiring (29). The capacitor (19) has a fifth terminal as one terminal connected to the ground (24) and a sixth terminal as the other terminal connected to the second terminal (6c) via a wiring (29). The first terminal (6a) is connected to the bit line (4) selected during the write operation and the read operation. The first gate (6b) is connected to the word line (3) selected during the write operation and the read operation.

  Here, in the above-described data write operation to the memory cell, when the capacitor (19) is charged or discharged by turning on the first transistor (6), a current (Iw (1) flowing through the wiring (29) is obtained. ), Iw (0)), data is written to the magnetoresistive element (7). In the data read operation, the data from the magnetoresistive element (7) is based on the current (Is) passing through the first transistor (6) and the magnetoresistive element (7) when the first transistor (6) is turned on. Is read out.

In order to solve the above-described problem, a magnetic random access memory according to the present invention includes a plurality of memory cells (2) according to any one of the above provided in a matrix and a plurality of rows included in the matrix. A plurality of s first word lines (3) provided in correspondence with each other and an X selector (8) for selecting a selected word line (3s) from the plurality of first word lines (3). In the case of the write operation, the word line corresponding to one memory cell (2) is one of the first word lines (3).
That is, there is one word line for write operation.

  In order to solve the above problems, a magnetic random access memory according to the present invention includes a plurality of memory cells (2) and a memory selection unit (8). Here, each of the plurality of memory cells (2) includes a magnetoresistive element (7) having spontaneous magnetization whose magnetization direction is reversed according to stored data, and at least one switching element (6, 16). Is provided. The memory selection unit (8) puts at least one switching element (6, 16) into one of an on state and an off state. During the data write operation to the selected cell (2s) selected from among the plurality of memory cells (2), the memory selection unit (8) includes at least one switching element (6, 6) of the selected cell (2s). 16) is turned on. As a result, a write current flows through the selected cell (2s). At the time of the read operation, at least one switching element (6, 16) of the selected cell (2s) is turned on. As a result, a read current flows through the selected cell (2s).

The magnetic random access memory according to the present invention includes a plurality of bit line (4 and 5) pairs, a plurality of word lines (3), a first selector (11), a second selector (14), and a third A selector (8) and a plurality of memory cells (2) are provided. The plurality of bit line pairs (4 and 5) include a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of word lines (3) extend in a second direction (X) substantially perpendicular to the first direction (Y). The first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (8) selects the selected word line (3s) from the plurality of word lines (3). The plurality of memory cells (2) are provided corresponding to the positions where the plurality of bit line pairs (4 and 5) and the plurality of word lines (3) intersect.
Here, each of the plurality of memory cells (2) includes a first transistor (6), a second transistor (16), and a magnetoresistive element (7). The first transistor (6) has a first gate (6b) connected to the word line (3) and a first terminal as one terminal other than the first gate (6b) connected to the first bit line (4). One terminal (6a) and a second terminal (6c) as the other terminal are included. The second transistor (16) includes a second gate (16b) connected to the word line (3) and a fifth terminal (one terminal other than the second gate connected to the second bit line (5)). 16a) and a sixth terminal (16c) as the other terminal connected to the second terminal (6c). The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, the third terminal as one terminal is grounded (24), and the fourth terminal as the other terminal Is connected to the second terminal (6c).

In the magnetic random access memory, data is written to the memory cell (2) as follows.
First, the first selector (11) and the second selector (14) select a pair of the selected first bit line (4s) and the selected second bit line (5s) from the plurality of bit line pairs (4 and 5). . At this time, the second selector (14) fixes the selected second bit line (5s) to a predetermined voltage (Vterm). At the same time, the third selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on both the first transistor (6) and the second transistor (16). . Then, data is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s), the selected second bit line (5s), and the selected word line (3s). A predetermined current (Iw (1), Iw (0)) based on the above is passed through a path including the selected first bit line (4s), the selected cell (2s), and the selected second bit line (5s).

In the magnetic random access memory, data is read from the memory cell (2) as follows.
First, the first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). At the same time, the third selector (8) selects the selected word line (3s) from the plurality of word lines (3) and turns on the first transistor (6). Then, a predetermined current (Is) is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s) and the selected word line (3s). The current flows through a path including the 1-bit line (4s) and the magnetoresistive element (7) of the selected cell (2s), and data is read based on the potential of the selected cell (2s) at that time.

The magnetic random access memory according to the present invention includes a plurality of bit line (4 and 5) pairs, a plurality of third bit lines (35), a plurality of word lines (3), and a first selector (11-1). A second selector (14), a third selector (11-2), a fourth selector (8), and a plurality of memory cells (2). The plurality of bit line pairs (4 and 5) include a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of third bit lines (35) extend in the first direction (Y). The plurality of word lines (3) extend in a second direction (X) substantially perpendicular to the first direction (Y). The first selector (11-1) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (11-2) selects the selected third bit line (35s) from the plurality of third bit lines (35). The fourth selector (8) selects the selected word line (3s) from the plurality of word lines (3). The plurality of memory cells (2) are provided corresponding to the positions where the plurality of bit line pairs (4 and 5) and the plurality of word lines (3) intersect.
Here, each of the plurality of memory cells (2) includes a first transistor (6), a second transistor (16), and a magnetoresistive element (7). The first transistor (6) has a first gate (6b) connected to the word line (3) and a first terminal as one terminal other than the first gate (6b) connected to the first bit line (4). One terminal (6a) and a second terminal (6c) as the other terminal are included. The second transistor (16) includes a second gate (16b) connected to the word line (3) and a fifth terminal (one terminal other than the second gate connected to the second bit line (5)). 16a) and a sixth terminal (16c) as the other terminal connected to the second terminal (6c). The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, and the third terminal as one terminal is connected to the third bit line (35) and the other terminal is used as the other terminal. The fourth terminal is connected to the second terminal (6c).

  In the magnetic random access memory, data is written to the memory cell (2) as follows. First, the first selector (11-1) and the second selector (14) select a pair of the selected first bit line (4s) and the selected second bit line (5s) from the plurality of bit line pairs (4 and 5). select. At this time, the second selector (14) fixes the selected second bit line (5s) to a predetermined voltage (Vterm). At the same time, the fourth selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on both the first transistor (6) and the second transistor (16). . Then, data is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s), the selected second bit line (5s), and the selected word line (3s). A predetermined current (Iw (1), Iw (0)) based on the above is passed through a path including the selected first bit line (4s), the selected cell (2s), and the selected second bit line (5s). At this time, the third bit line (35) is set to a potential such that the potential of the fourth terminal is substantially the same as the potential of the third terminal.

  In the magnetic random access memory, data is read from the memory cell (2) as follows. First, the first selector (11-1) selects the selected first bit line (4s) from the plurality of first bit lines (4). The third selector (11-2) selects the selected third bit line (35s) from the plurality of third bit lines (35). The fourth selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the first transistor (6). Then, a predetermined current (Is) is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s) and the selected word line (3s). The current flows through a path including the magnetoresistive element (7) of the 3-bit line (35s), the selected cell (2s), and the selected first bit line (4s). Read.

  In the magnetic random access memory according to any one of the above, each of the plurality of bit line pairs (4 and 5) includes a first transistor (6) and a second transistor (16) of the corresponding memory cell (2a). It is provided to pass between.

  In the magnetic random access memory according to any one of the above items, the memory cell (2) further includes wirings (27, 29, and 37) that connect the first transistor (6) and the second transistor (16). The lead-out wiring (29) included is provided. The magnetoresistive element (7) is formed on the lead wiring (29). One terminal is connected to the lead-out wiring (29), and the other terminal is connected to the ground (24). And it is easy to magnetize in the direction inclined by the element arrangement angle (θ) as an angle with respect to the wiring current direction as the direction of the current (Iw (0), Iw (1)) flowing in the lead wiring (29). Has a shape.

  In the above magnetic random access memory, the element arrangement angle (θ) is 30 ° to 60 °.

  In the magnetic random access memory according to any one of the above, the direction in which each diffusion layer forming the first terminal (6a) and the second terminal (6c) of the first transistor (6) is disposed, and the first The directions in which the respective diffusion layers forming the fifth terminal (16a) and the sixth terminal (16c) of the two transistors (16) are arranged are substantially parallel to each other and are angled with respect to the first direction (Y). It is inclined by the diffusion layer arrangement angle (φ).

  In the magnetic random access memory according to any one of the above, a plurality of ground wirings (24) provided in pairs with each of the plurality of word lines (3) and extending in the second direction (X). In addition. The memory cell (2d) further includes a lead wiring (29) included in wirings (27, 29, and 37) that connect the first transistor (6) and the second transistor (16). The magnetoresistive element (7) is formed on the ground wiring (24). One terminal is connected to the ground wiring (24), and the other terminal is connected to the lead wiring (29).

The magnetic random access memory according to the present invention includes a first transistor (6), a first bit line (4), a second transistor (16), a second bit line (5), and a word line (3). And a lead wiring layer (29) and a magnetoresistive element (7).
The first transistor (6) includes a first diffusion layer (6a), a second diffusion layer (6c), a first diffusion layer (6a), and a second diffusion layer (6c) provided in the semiconductor substrate. And a first gate (6b) provided on the semiconductor substrate with an insulating layer interposed therebetween. The first bit line (4) is connected to the first diffusion layer (6a) via a first contact wiring (28) extending from the first diffusion layer (6a) in a direction away from the semiconductor substrate. The second transistor (16) includes a third diffusion layer (16a), a fourth diffusion layer (16c), a third diffusion layer (16a), and a fourth diffusion layer (16c) provided in the semiconductor substrate. And a second gate (16b) provided on the semiconductor substrate with an insulating layer interposed therebetween. The second bit line (5) is connected to the third diffusion layer via a third contact wiring (38) extending from the third diffusion layer (16a) in a direction away from the semiconductor substrate. The word line (3) is connected to the first gate (6b) and the second gate (16b). The lead-out wiring layer (29) is connected to the second diffusion layer (6c) at one end via a second contact wiring (27) extending from the second diffusion layer (6c) in a direction away from the semiconductor substrate. The other end is connected to the fourth diffusion layer (16c) via a fourth contact wiring (37) extending from the fourth diffusion layer (16c) in the direction of leaving. The magnetoresistive element (7) is provided on the lead wiring layer (29), and one terminal is connected to the lead wiring layer (29), and the other terminal is connected to the ground (24) via the fifth contact wiring (26). It is connected.

Furthermore, the plurality of magnetic random access memories of the present invention comprise a plurality of memory cell arrays (41, 41a) and an array selector (17, 44).
The array selector (17, 44) selects the selected cell array (41s, 41as) from the plurality of memory cell arrays (41, 41a). Each of the plurality of memory cell arrays (41, 41a) includes a plurality of bit line pairs (4 and 5), a plurality of word lines (3), a plurality of memory cells (2), and a first selector (11 ′). And a second selector (14) and a third selector (8).
Here, the plurality of bit line pairs (4 and 5) include a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of word lines (3) extend in a second direction (X) substantially perpendicular to the first direction (Y). The plurality of memory cells (2) are provided corresponding to the positions where the plurality of bit line pairs (4 and 5) and the plurality of word lines (3) intersect. The first selector (11 ′) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (8) selects the selected word line (3s) from the plurality of word lines (3).
However, each of the plurality of memory cells (2) includes a first transistor (6), a second transistor (16), and a magnetoresistive element (7). The first transistor (6) has a first gate (6b) connected to the word line (3) and a first terminal as one terminal other than the first gate (6b) connected to the first bit line (4). One terminal (6a) and a second terminal (6c) as the other terminal are included. The second transistor (16) has a second gate (16b) connected to the word line (3) and a second terminal as one terminal other than the second gate (16b) connected to the second bit line (5). 5 terminal (16a) and the 6th terminal (16c) as the other terminal connected to the 2nd terminal (6c) are included. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, the third terminal as one terminal is grounded (24), and the fourth terminal as the other terminal Is connected to the second terminal (6c).
At least one of the first selector (11 ′) and the second selector (14) is connected to the array selector (17, 44).

Here, in the magnetic random access memory, data is written to the memory cell (2) as follows.
First, a selected cell array (41s, 41as) is selected from a plurality of memory cell arrays (41, 41a). Next, a pair of the selected first bit line (4s) and the selected second bit line (5s) are selected from the plurality of bit line pairs (4 and 5) in the selected cell array (41s, 41as), and the selected first bit line (5s) is selected. The 2-bit line (5s) is fixed to a predetermined voltage (Vterm, GND). At the same time, the selected word line (3s) is selected from the plurality of word lines (3), and both the first transistor (6) and the second transistor (16) are turned on. Then, data is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s), the selected second bit line (5s), and the selected word line (3s). A predetermined current (Iw (0), Iw (1)) based on the selection is selected from the array selector (17, 44), the first selector (11 ′), the selected first bit line (4s), and the selected cell (5s). The current flows through a path including the second bit line (5s) and the second selector (14).

Here, in the above magnetic random access memory, data is read from the memory cell (2) as follows.
First, a selected cell array (41s, 41as) is selected from a plurality of memory cell arrays (41, 41a). Next, the selected first bit line (4s) is selected from the plurality of first bit lines (4) in the selected cell array (41s, 41as). At the same time, the selected word line (3s) is selected from the plurality of word lines (3), and the first transistor (6) is turned on. Then, a predetermined current (Is) is applied to the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s) and the selected word line (3s). (17, 44), the first selector (11 '), the selected first bit line (4s), and the magnetoresistive element (7) of the selected cell (2s). Data is read based on the potential.

Furthermore, the plurality of magnetic random access memories of the present invention comprise a plurality of memory cell arrays (41h) and an array selector (44a). The array selector (44a) selects the selected cell array (41hs) from the plurality of memory cell arrays (41h). Each of the plurality of memory cell arrays (41h) includes a plurality of bit line pairs (4 and 5) and a plurality of third bit lines (35), a plurality of word lines (3), and a plurality of memory cells (2). , A first selector (11-1a), a second selector (14a ′), a third selector (11-2a), and a fourth selector (8).
Here, the plurality of bit line pairs (4 and 5) include a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of third bit lines (35) extend in the first direction (Y). The plurality of word lines (3) extend in a second direction (X) substantially perpendicular to the first direction (Y). The plurality of memory cells (2) are provided corresponding to the positions where the plurality of bit line pairs (4 and 5) and the plurality of word lines (3) intersect. The first selector (11-1a) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14 ′) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (11-2a) selects the selected third bit line (35s) from the plurality of third bit lines (35). The fourth selector (8) selects the selected word line (3s) from the plurality of word lines (3).
However, each of the plurality of memory cells (2) includes a first transistor (6), a second transistor (16), and a magnetoresistive element (7). The first transistor (6) has a first gate (6b) connected to the word line (3) and a first terminal as one terminal other than the first gate (6b) connected to the first bit line (4). One terminal (6a) and a second terminal (6c) as the other terminal are included. The second transistor (16) has a second gate (16b) connected to the word line (3) and a second terminal as one terminal other than the second gate (16b) connected to the second bit line (5). 5 terminal (16a) and the 6th terminal (16c) as the other terminal connected to the 2nd terminal (6c) are included. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, and the third terminal as one terminal is connected to the third bit line (35) and the other terminal is used as the other terminal. The fourth terminal is connected to the second terminal (6c).
At least one of the first selector (11-1a), the second selector (14), and the third selector (11-2a) is connected to the array selector (44a).

  Here, in the magnetic random access memory, data is written to the memory cell (2) as follows. First, a selected cell array (41hs) is selected from a plurality of memory cell arrays (41h). Next, a pair of a selected first bit line (4s) and a selected second bit line (5s) are selected from a plurality of bit line pairs (4 and 5) in the selected cell array (41hs). At this time, the second selector (14a ') fixes the selected second bit line (5s) to a predetermined voltage (Vterm, GND). At the same time, the selected word line (3s) is selected from the plurality of word lines (3), and both the first transistor (6) and the second transistor (16) are turned on. Then, data is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s), the selected second bit line (5s), and the selected word line (3s). A predetermined current (Iw (0), Iw (1)) based on the data is selected from the array selector (44a), the first selector (11-1a), the selected first bit line (4s) and the selected cell (5s). It flows through a path including the 2-bit line (5s) and the second selector (14a ′). At this time, the third bit line (35) is set to a potential such that the potential of the fourth terminal is substantially the same as the potential of the third terminal.

  Here, in the above magnetic random access memory, data is read from the memory cell (2) as follows. First, a selected cell array (41hs) is selected from a plurality of memory cell arrays (41h). Next, the selected first bit line (4s) is selected from the plurality of first bit lines (4) in the selected cell array (41hs). The selected third bit line (35s) is selected from the plurality of third bit lines (35). The selected word line (3s) is selected from the plurality of word lines (3), and the first transistor (6) is turned on. Then, a predetermined current (Is) is applied to the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s) and the selected word line (3s). (44a), the second selector (11-2a), the selected third bit line (35s), the magnetoresistive element (7) of the selected cell (2s), and the selected first bit line (4s). Data is read based on the potential of the selected cell (7).

In the magnetic random access memory, each of the plurality of word lines (3) is a plurality of word line pairs (3) of a first word line (3a) and a second word line (3b). The third selector (8) selects the selected word line pair (3s) from the plurality of word line pairs (3). Each of the plurality of memory cells (2h) further includes a third transistor (6-2) and a fourth transistor (16-2). The third transistor (6-2) includes a third gate connected to the second word line (3b) and a seventh terminal as one terminal other than the third gate connected to the first bit line (4). And an eighth terminal as the other terminal connected to the second terminal. The fourth transistor (16-2) has a fourth gate connected to the second word line (3b) and a ninth terminal as one terminal other than the fourth gate connected to the second bit line (5). And a tenth terminal as the other terminal connected to the sixth terminal.
The first gate and the second gate are connected to the first word line (3a).

  In the magnetic random access memory, data is written to the memory cell (2h) as follows. First, the first selector (11) and the second selector (12) select a pair of a selected first bit line (4s) and a selected second bit line (5s) from a plurality of bit line pairs. The third selector (8) selects a pair of the selected first word line (3as) and the selected second word line (3bs) from the plurality of word line pairs (3), and the first transistor (6-1) ), The second transistor (16-1), the third transistor (6-2), and the fourth transistor (16-2). The selected first bit line (4s) and the selected second bit line (5s), and the selected first word line (3as) and the selected second word line (3bs) are selected from the plurality of memory cells (2h). A predetermined current (Iw (1), Iw (0)) based on data is applied to the selected first bit line (4s), the selected cell (2hs), and the selected second bit line ( 5s).

  In the magnetic random access memory described above, data (2h) is read from the memory cell as follows. First, the first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). The third selector (8) selects a pair of the selected first word line (3as) and the selected second word line (3bs) from the plurality of word line pairs (3), and the first transistor (6-1) ) And the third transistor (6-2) are turned on. A selected cell (2hs) selected from the plurality of memory cells (2h) by the selected first bit line (4s), the selected first word line (3as), and the selected second word line (3bs). , Based on the potential of the selected cell (2s) when a predetermined current (Is) is passed through a path including the selected first bit line (4s) and the magnetoresistive element (7) of the selected cell (2s). .

In the magnetic random access memory, each of the plurality of word lines (3) is a plurality of word line pairs (3) of a first word line (3a) and a second word line (3b). The fourth selector (8) selects the selected word line pair (3s) from the plurality of word line pairs (3). Each of the plurality of memory cells (2) further includes a third transistor (6-2) and a fourth transistor (16-2). The third transistor (6-2) includes a third gate connected to the second word line (3b) and a seventh terminal as one terminal other than the third gate connected to the first bit line (4). And an eighth terminal as the other terminal connected to the second terminal. The fourth transistor (16-2) has a fourth gate connected to the second word line (3b) and a ninth terminal as one terminal other than the fourth gate connected to the second bit line (5). And a tenth terminal as the other terminal connected to the sixth terminal.
The first gate and the second gate are connected to the first word line (3a).

  In the magnetic random access memory, data is written to the memory cell (2) as follows. First, the first selector (11-1) and the second selector (14) select a pair of the selected first bit line (4s) and the selected second bit line (5s) from the plurality of bit line pairs (4 and 5). select. At this time, the second selector (14) fixes the selected second bit line (5s) to a predetermined voltage (Vterm). The third selector (8) selects a pair of the selected first word line (3as) and the selected second word line (3bs) from the plurality of word line pairs (3), and the first transistor (6-1) ), The second transistor (16-1), the third transistor (6-2), and the fourth transistor (16-2). The selected first bit line (4s) and the selected second bit line (5s), and the selected first word line (3as) and the selected second word line (3bs) are selected from the plurality of memory cells (2). A predetermined current (Iw (1), Iw (0)) based on data is applied to the selected first bit line (4s), the selected cell (2s) and the selected second bit line ( 5s). At this time, the third bit line (35) is set to a potential such that the potential of the fourth terminal is substantially the same as the potential of the third terminal.

  In the magnetic random access memory, the reading of the data (2) to the memory cell is performed as follows. First, the first selector (11-1) selects the selected first bit line (4s) from the plurality of first bit lines (4). The third selector (11-2) selects the selected third bit line (35s) from the plurality of third bit lines (35). The fourth selector (8) selects a pair of the selected first word line (3as) and the selected second word line (3bs) from the plurality of word line pairs (3), and the first transistor (6-1) ) And the third transistor (6-2) are turned on. The selected cell (2hs) selected from the plurality of memory cells (2) by the selected first bit line (4s), the selected first word line (3as), and the selected second word line (3bs). The selected cell when a predetermined current (Is) is passed through a path including the selected third bit line (35s), the magnetoresistive element (7) of the selected cell (2s), and the selected first bit line (4s). This is performed based on the potential of (2s).

  In the magnetic random access memory, two memory cells (2h, 2) adjacent in the direction of the plurality of bit line pairs (3) are connected to the first terminal and the fifth terminal of one memory cell (2h, 2). The diffusion layers are respectively common to the diffusion layers of the seventh terminal and the ninth terminal of the other memory cell (2h, 2).

  In the magnetic random access memory described above, in the memory cells (2h, 2), the diffusion layers of the second terminal and the eighth terminal are common, and the diffusion layers of the sixth terminal and the tenth terminal are common.

The magnetic random access memory of the present invention includes a plurality of bit line pairs (4 and 5), a plurality of word line pairs,
The first selector (11), the second selector (14), the third selector (8), the fourth selector (8-1), the fifth selector (8-2), and a plurality of memory cells (20 ).
The plurality of bit line pairs (4 and 5) include a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of word line pairs (3W and 3R) include a first word line (3W) and a second word line (3R) extending in a second direction (X) substantially perpendicular to the first direction (Y). Including. The first selector (11-1) selects the selected first bit line (4s) from the plurality of first bit lines (4) during the write operation. The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5) during the write operation. The third selector (11-2) selects the selected second bit line (5s) during the read operation from the plurality of second bit lines (5). The fourth selector (8-1) selects the selected first word line (3Ws) from the plurality of first word lines (3W). The fifth selector (8-2) selects the selected second word line (3Rs) from the plurality of second word lines (3R). The plurality of memory cells (20) are provided corresponding to the positions where the plurality of bit line pairs (4 and 5) and the plurality of word line pairs (3W and 3R) cross each other.
Here, each of the plurality of memory cells (20) includes a first transistor (6) and a magnetoresistive element (7). The first transistor (6) has one terminal other than the first gate (6b) connected to the first word line (3W) and the first gate (6b) connected to the first bit line (4). The first terminal (6a) and the second terminal (6c) as the other terminal connected to the second bit line (5). The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed in accordance with stored data. The third terminal as one terminal is used as the second word line (3R) and the other terminal is used as the other terminal. The fourth terminal is connected to the second terminal (6c).

  Here, in the magnetic random access memory, data is written to the memory cell (20) as follows. First, the first selector (11-1) and the second selector (14) select a pair of the selected first bit line (4s) and the selected second bit line (5s) from the plurality of bit line pairs (4 and 5). select. At this time, the second selector (14) fixes the selected second bit line (5s) to a predetermined voltage (Vterm). At the same time, the fourth selector (8-1) selects the selected first word line (3Ws) from the plurality of first word lines (3W), and turns on the first transistor (6). Then, for the selected cell (20s) selected from the plurality of memory cells (20) by the selected first bit line (4s), the selected second bit line (5s), and the selected first word line (3Ws). A predetermined current (Iw (1), Iw (0)) based on the data is passed through a path including the selected first bit line (4s), the selected cell (20s), and the selected second bit line (5s).

Here, in the above magnetic random access memory, data is read from the memory cell (20) as follows.
First, the third selector (11-2) selects the selected second bit line (5s) from the plurality of second bit lines (5). At the same time, the fifth selector (8-2) selects the selected second word line (3Rs) from the plurality of second word lines (3R). A predetermined current (Is) is applied to the selected cell (20s) selected from the plurality of memory cells (20) by the selected second bit line (5s) and the selected second word line (3Rs). The current flows through a path including the selected second bit line (5s) and the magnetoresistive element (7) of the selected cell (20s), and data is read based on the potential of the selected cell (20s) at that time.

The magnetic random access memory of the present invention includes a plurality of bit lines (4), a plurality of word lines (3), a first selector (11), a second selector (8), a plurality of memory cells (2f), It comprises.
The plurality of bit lines (4) extend in the first direction (Y). The plurality of word lines (3) extend in a second direction (X) substantially perpendicular to the first direction (Y). The first selector (11) selects the selected bit line (4s) from the plurality of bit lines (4). The second selector (8) selects the selected word line (3s) from the plurality of word lines (3). The plurality of memory cells (2f) are provided corresponding to respective positions where the plurality of bit lines (4) and the plurality of word lines (3) intersect.
Here, each of the plurality of memory cells (2f) includes a transistor (6), a capacitor (19), and a magnetoresistive element (7). The transistor (6) includes a gate (6b) connected to the word line (3), a first terminal (6a) as one terminal other than the gate (6b) connected to the bit line (4), and the other And a second terminal (6c) as a terminal. The capacitor (19) includes a fifth terminal as one terminal connected to the ground (24) and a sixth terminal as the other terminal connected to the second terminal (6c). The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, the third terminal as one terminal is grounded (24), and the fourth terminal as the other terminal Is connected to the second terminal (6c).

  In the magnetic random access memory, data is written to the memory cell (2f) as follows. First, the first selector (11) selects the selected bit line (4s) from the plurality of bit lines (4), and charges the capacitor (19) with the selected bit line (4s) set to a predetermined voltage. Next, the second selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the first transistor (6). The selected bit line (4s) and the selected word line (3s) are used to select the selected cell (2fs) selected from the plurality of memory cells (2f), after the capacitor (19) is charged, 4s) is set to a predetermined voltage based on the data, and currents (Iw (1), Iw (0)) are passed between the capacitor (19) and the selected bit line (4s).

  In the magnetic random access memory, data is read from the memory cell (2f) as follows. First, the first selector (11) selects the selected bit line (4s) from the plurality of bit lines (4), and charges the capacitor (19) with the selected bit line (4s) set to a predetermined voltage. Next, the second selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the first transistor (6) at a predetermined speed or less. Then, after the capacitor (19) is charged to the selected cell (2fs) selected from the plurality of memory cells (2f) by the selected bit line (4s) and the selected word line (3s), a predetermined current ( Is) is passed through a path including the selected first bit line (4s) and the magnetoresistive element (7) of the selected cell (2fs), and data is read based on the potential of the selected cell (2fs) at that time. .

The magnetic random access memory of the present invention includes a plurality of bit lines (4), a plurality of word line pairs (3W, 3R), a first selector (11), a second selector (8), And a memory cell (30). The plurality of bit lines (4) extend in the first direction (Y). The plurality of word line pairs (3W, 3R) extend in the second direction (X) substantially perpendicular to the first direction (Y), and the first word line (3W) and the second word line (3R) including. The first selector (11) selects a selected bit line (4s) from the plurality of bit lines (4) during a write operation and a read operation. The second selector (8) selects the selected first word line (3Ws) from the plurality of first word lines (3W) during the write operation, and selects the second word line (3R) from the plurality of second word lines (3R) during the read operation. A word line (3Rs) is selected. The plurality of memory cells (30) are provided corresponding to respective positions where the plurality of bit lines (4) and the plurality of word line pairs (3W, 3R) intersect.
Each of the plurality of memory cells (30) includes a second diode (32), a third diode (33), and a magnetoresistive element (7). The second diode (32) includes a first terminal having a first polarity and a second terminal having a second polarity different from the first polarity. The third diode (33) includes a third terminal having the first polarity and a fourth terminal having the second polarity. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, and includes a fifth terminal as one terminal and a sixth terminal as the other terminal. The second terminal and the third terminal are connected to the first word line (3W). The first terminal, the fourth terminal, and the fifth terminal are connected to the bit line (4). The sixth terminal is connected to the second word line (3R).

  In the magnetic random access memory, data is written to the memory cell (30) as follows. First, the first selector (11) selects a selected bit line (4s) from the plurality of bit lines (4). The second selector (8) selects the selected first word line (3Ws) from the plurality of word line pairs (3W, 3R). Then, a current based on the data is supplied to the selected bit line (30s) selected from the plurality of memory cells (30) by the selected bit line (4s) and the first selected word line (3Ws). 4s) and the second diode (32) or the third diode (33) of the selected cell (30s) and the selected first word line (3Ws).

  In the magnetic random access memory, data is read from the memory cell (30) as follows. First, the first selector (11) selects a selected bit line (4s) from the plurality of bit lines (4). The second selector (8) selects the selected second word line (3Rs) from the plurality of word line pairs (3W, 3R). Then, a predetermined current is applied to the selected bit line (4s) to the selected cell (30s) selected from the plurality of memory cells (30) by the selected bit line (4s) and the selected second word line (3Rs). ), The magnetoresistive element (7) of the selected cell (30s), and the selected second word line (3Rs), based on the potential of the selected cell (30s).

The magnetic random access memory according to the present invention includes a plurality of memory cell arrays (41d) and an array selector (17a) for selecting a selected cell array (41ds) from the plurality of memory cell arrays (41d).
Each of the plurality of memory cell arrays (41d) includes a plurality of bit lines (4), a plurality of word line pairs (3W, 3R), a first selector (11), a second selector (8), And a memory cell (30). The plurality of bit lines (4) extend in the first direction (Y). The plurality of word line pairs (3W, 3R) extend in the second direction (X) substantially perpendicular to the first direction (Y), and the first word line (3W) and the second word line (3R) including. The first selector (11) selects a selected bit line (4s) from the plurality of bit lines (4) during a write operation and a read operation. The second selector (8) selects the selected first word line (3Ws) from the plurality of first word lines (3W) during the write operation, and selects the second word line (3R) from the plurality of second word lines (3R) during the read operation. A word line (3Rs) is selected. The plurality of memory cells (30) are provided corresponding to the positions where the plurality of bit lines (4) and the plurality of word line pairs (3) intersect.
Each of the plurality of memory cells (30) includes a second diode (32), a third diode (33), and a magnetoresistive element (7). The second diode (32) includes a first terminal having a first polarity and a second terminal having a second polarity different from the first polarity. The third diode (33) includes a third terminal having the first polarity and a fourth terminal having the second polarity. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, and includes a fifth terminal as one terminal and a sixth terminal as the other terminal. The second terminal and the third terminal are connected to the first word line (3W). The first terminal, the fourth terminal, and the fifth terminal are connected to the bit line (4). The sixth terminal is connected to the second word line (3R). The first selector (11) is connected to the array selector (17a).

  In the magnetic random access memory, the memory cell (30) further includes a first diode (31) including a seventh terminal having the first polarity and an eighth terminal having the second polarity. The first diode (31) is provided between the magnetoresistive element (7) and the second word line (3R), its eighth terminal is the second word line (7), and its seventh terminal is It is connected to the sixth terminal.

  In the magnetic random access memory, the first diode (31), the second diode (32), and the third diode (33) are formed by film formation at a position away from the substrate (10).

  In the magnetic random access memory, the memory cell (30) is stacked in a direction away from the substrate (10).

Furthermore, the magnetic random access memory of the present invention includes a bit line (4), a lead wiring layer (29), a second diode (32), a third diode (33), a magnetoresistive element (7), A first diode (31), a first word line (3W), and a second word line (3R) are provided.
The bit line (4) is provided on the substrate (10) via an insulating layer (35), and is parallel to the surface of the substrate (10). The lead-out wiring layer (29) is connected to the bit line (4) at one end via a first contact wiring (53) extending from the bit line (4) in a direction away from the substrate (10). Parallel to the surface. The second diode (32) includes a first terminal having a first polarity and a second terminal having a second polarity different from the first polarity, and extends from the lead wiring layer (29) in a direction away from the substrate (10). It is provided in the middle of the extended second contact wiring (55). The third diode (33) includes a third terminal having the first polarity and a fourth terminal having the second polarity, and extends from the lead-out wiring layer (29) in a direction away from the substrate (10). (56) is provided in the middle. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, includes a fifth terminal and a sixth terminal, and the fifth terminal is connected to the lead wiring layer (29). It is connected. The first diode (31) includes a seventh terminal of the first polarity and an eighth terminal of the second polarity, and from the sixth terminal of the magnetoresistive element (7) in a direction away from the substrate (10). It is provided in the middle of the extended fourth contact wiring (54). The first word line (3W) is connected to the second terminal of the second diode (32) via the second contact wiring (55), and is connected to the third diode via the third contact wiring (56). It is connected to the third terminal of (33) and is parallel to the substrate (10). The second word line (3R) is connected to the seventh terminal of the first diode (31) via the fourth contact wiring (54) and is parallel to the substrate (10).
The position of the fifth terminal in the lead wiring layer (29) is more than the position where each of the second contact wiring (55) and the third contact wiring (56) is connected to the lead wiring layer (29). It is close to the position where the one-contact wiring (53) and the lead-out wiring layer (29) are connected.

Further, the magnetic random access memory of the present invention includes a plurality of bit line pairs (4, 5), a plurality of word line line pairs (3W, 3R), a first selector (11), and a second selector (14). And a third selector (8) and a plurality of memory cells (20j). The plurality of bit line pairs (4, 5) extend in the first direction (Y) and are a set of the first bit line (4) and the second bit line (5). The plurality of word line pairs (3W, 3R) are formed by a first word line (3W) and a second word line (3R) extending in a second direction (X) substantially perpendicular to the first direction (Y). It is a pair. The first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (8) selects at least one of the selected first word line (3Ws) and the selected second word line (3Rs) from the plurality of word line pairs (3W, 3R). The plurality of memory cells (20j) are provided corresponding to respective positions where the plurality of bit line pairs (4, 5) and the plurality of word line pairs (3W, 3R) intersect.
Each of the memory cells (20j) includes a transistor (6), a magnetoresistive element (7), and a diode (31). The transistor (6) includes a gate connected to the first word line (3W), a first terminal as one terminal other than the first gate connected to the first bit line (4), and a second bit And a second terminal as the other terminal connected to the line (5). The magnetoresistive element (7) has a spontaneous magnetization whose magnetization direction is reversed according to stored data, the fourth terminal as one terminal connected to the second bit line (5), and the other terminal It includes a third terminal as a terminal. The diode (31) includes a fifth terminal having a first polarity connected to the third terminal, and a sixth terminal having a second polarity different from the first polarity connected to the second word line (3R). .

  In the magnetic random access memory, data is written to the memory cell (20j) as follows. First, the first selector (11) and the second selector (14) select a pair of the selected first bit line (4s) and the selected second bit line (5s) from the plurality of bit line pairs (4, 5). . The third selector (8) selects the selected first word line (3Ws) from the plurality of first word lines (3W), and turns on the transistor (6). For the selected cell (20js) selected from the plurality of memory cells (20j) by the selected first bit line (4s), the selected second bit line (5s), and the selected first word line (3Ws), A current based on the data is passed through a path including the selected first bit line (4s), the selected cell (20j), and the selected second bit line (5s).

  In the magnetic random access memory according to claim 36, the data is read from the memory cell (20j) as follows. First, the first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). The third selector (8) selects the selected first word line (3Ws) and the selected second word line (3Rs) from the plurality of word line pairs (3W, 3R), and turns on the transistor (6). To do. Then, a predetermined current is selected for the selected cell (20js) selected from the plurality of memory cells (20j) by the selected first bit line (4s) and the selected first word line (3Ws). This is performed based on the potential of the selected cell (20js) when flowing through a path including the bit line (4s), the magnetoresistive element (7) of the selected cell (20js), and the selected second word line (3Rs).

Furthermore, the magnetic random access memory of the present invention includes a plurality of memory cell arrays (41e) and an array selector (17a) for selecting a selected cell array (41es) from the plurality of memory cell arrays (41e).
Each of the plurality of memory cell arrays (31e) includes a plurality of bit line pairs (4, 5), a plurality of word line line pairs (3W, 3R), a first selector (11), and a second selector (14). And a third selector (8) and a plurality of memory cells (20j). The plurality of bit line pairs (4, 5) extend in the first direction (Y) and are a set of the first bit line (4) and the second bit line (5). The plurality of word line pairs (3W, 3R) are formed by a first word line (3W) and a second word line (3R) extending in a second direction (X) substantially perpendicular to the first direction (Y). It is a pair. The first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (8) selects at least one of the selected first word line (3Ws) and the selected second word line (3Rs) from the plurality of word line pairs (3W, 3R). The plurality of memory cells (20j) are provided corresponding to respective positions where the plurality of bit line pairs (4, 5) and the plurality of word line pairs (3W, 3R) intersect.
Each of the memory cells (20j) includes a transistor (6), a magnetoresistive element (7), and a diode (31). The transistor (6) includes a gate connected to the first word line (3W), a first terminal as one terminal other than the first gate connected to the first bit line (4), and a second bit And a second terminal as the other terminal connected to the line (5). The magnetoresistive element (7) has a spontaneous magnetization whose magnetization direction is reversed according to stored data, the fourth terminal as one terminal connected to the second bit line (5), and the other terminal It includes a third terminal as a terminal. The diode (31) includes a fifth terminal having a first polarity connected to the third terminal, and a sixth terminal having a second polarity different from the first polarity connected to the second word line (3R). .
The first selector (11) and the second selector (14) are connected to the array selector (17a).

Furthermore, the magnetic random access memory of the present invention comprises a plurality of bit line pairs (4 and 5), a plurality of word lines (3), a precharge word line (3p), a precharge line (45), a plurality of Precharge voltage line (48), precharge unit (49), a plurality of memory cells (2), a first selector (11 ′), a second selector (14), and a third selector (8). It comprises.
Here, the plurality of bit line pairs (4 and 5) include a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of word lines (3) extend in a second direction (X) substantially perpendicular to the first direction (Y). The precharge word line (3p) extends in the second direction (X). The precharge line (45) extends in the second direction (X) and supplies a precharge voltage (Vpr). The plurality of precharge voltage lines (48) extend in the second direction (X), are provided corresponding to the plurality of word lines (3), and supply a precharge voltage (Vpr). The precharge unit (49) is connected to the precharge word line (3p), the precharge line (45), the first bit line (4), and the second bit line (5), and the precharge word line (3p). The first bit line (4) and the second bit line (5) are precharged to a precharge voltage (Vpr) based on the signal from The plurality of memory cells (2) are provided corresponding to the positions where the plurality of bit line pairs (4 and 5) and the plurality of word lines (3) intersect. The first selector (11 ′) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (8) selects the selected word line (3s) from the plurality of word lines (3).
Each of the plurality of memory cells (2) includes a first transistor (6), a second transistor (16), and a magnetoresistive element (7).
However, the first transistor (6) has one terminal other than the first gate (6b) connected to the word line (3) and the first gate (6b) connected to the first bit line (4). The first terminal (6a) and the second terminal (6c) as the other terminal. The second transistor (16) has a second gate (16b) connected to the word line (3) and a second terminal as one terminal other than the second gate (16b) connected to the second bit line (5). 5 terminal (16a) and the 6th terminal (16c) as the other terminal connected to the 2nd terminal (6c) are included. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed in accordance with stored data. The third terminal as one terminal is connected to the precharge voltage line (48) and the other terminal as the other terminal. The fourth terminal is connected to the second terminal (6c).
The precharge voltage (Vpr) is connected to the first transistor (6), the second transistor (16), and the magnetoresistive element (7) when a current is passed through the memory cell (2) during the write operation. It is set to be the same as the voltage generated at the node.

  In the magnetic random access memory, the first bit line (4) and the second bit line (5) are precharged to the precharge voltage (Vpr) when not selected.

  Here, in the magnetic random access memory, data is written to the memory cell (2) as follows. First, a pair of a selected first bit line (4s) and a selected second bit line (5s) are selected from a plurality of bit line pairs (4 and 5), and the selected second bit line (5s) is set to a predetermined value. It is fixed to voltage (GND). At the same time, the selected word line (3s) is selected from the plurality of word lines (3), and both the first transistor (6) and the second transistor (16) are turned on. Then, data is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s), the selected second bit line (16s), and the selected word line (3s). The predetermined current (Iw (0), Iw (1)) based on the first selector (11 ′), the selected first bit line (4s), the selected cell (2), and the selected second bit line (5s) It flows on the route passing through the second selector (14).

  Here, in the above magnetic random access memory, data is read from the memory cell (2) as follows. First, the selected first bit line (4s) is selected from the plurality of first bit lines (4). Next, the selected word line (3s) is selected from the plurality of word lines (3), and the first transistor (6) is turned on. Then, a predetermined current (Is) is applied to the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s) and the selected word line (3s). Data is read based on the potential of the selected cell (2s) when flowing through a path including the selector (11 ′), the selected first bit line (4s), and the magnetoresistive element (7) of the selected cell (2s). Do.

Furthermore, the magnetic random access memory of the present invention includes a plurality of bit line pairs (4 and 5), a plurality of word lines (3), a plurality of memory cells (2), and a first read selector (11′a). A first write selector (11′b), a second selector (14), and a third selector (8).
Here, the plurality of bit line pairs (4 and 5) include a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of word lines (3) extend in a second direction (X) substantially perpendicular to the first direction (Y). The plurality of memory cells (2) are provided corresponding to the positions where the plurality of bit line pairs (4 and 5) and the plurality of word lines (3) intersect. The first read selector (11′a) selects the selected first bit line (4s) from the plurality of first bit lines (4) during the read operation. The first write selector (11′b) selects the selected first bit line (4a) from the plurality of first bit lines (4) during the write operation. The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (8) selects the selected word line (3s) from the plurality of word lines (3).
However, each of the plurality of memory cells (2) includes a first transistor (6), a second transistor (16), and a magnetoresistive element (7). The first transistor (6) has a first gate (6b) connected to the word line (3) and a first terminal as one terminal other than the first gate (6b) connected to the first bit line (4). One terminal (6a) and a second terminal (6c) as the other terminal are included. The second transistor (16) has a second gate (16b) connected to the word line (3) and a second terminal as one terminal other than the second gate (16b) connected to the second bit line (5). 5 terminal (16a) and the 6th terminal (16c) as the other terminal connected to the 2nd terminal (6c) are included. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, the third terminal as one terminal is grounded (24), and the fourth terminal as the other terminal Is connected to the second terminal (6c).

  Here, in the magnetic random access memory described above, data is written to the memory cell (2) as follows. First, a pair of a selected first bit line (4s) and a selected second bit line (5s) are selected from a plurality of bit line pairs (4 and 5), and the selected second bit line (5s) is set to a predetermined value. It is fixed to voltage (GND). At the same time, the selected word line (3s) is selected from the plurality of word lines (3), and both the first transistor (6) and the second transistor (16) are turned on. Then, data is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s), the selected second bit line (5s), and the selected word line (3). A predetermined current (Iw (0), Iw (1)) based on the first write selector (11′a), the selected first bit line (4s), the selected cell (2s), and the selected second bit line (5s). ) And the second selector (14).

  Here, in the above magnetic random access memory, data is read from the memory cell (2) as follows. First, the selected first bit line (4s) is selected from the plurality of first bit lines (4). At the same time, the selected word line (3s) is selected from the plurality of word lines (3), and the first transistor (6) is turned on. Then, a predetermined current (Is) is applied to the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s) and the selected word line (3s). The data flows based on the potential of the selected cell (2s) at that time through a path including the read selector (11′b), the selected first bit line (4s), and the magnetoresistive element (7) of the selected cell (2s). Is read out.

Furthermore, the magnetic random access memory of the present invention includes a plurality of bit line pairs (4 and 5), a plurality of word lines (3), a plurality of memory cells (2), and a first selector (11 ''). , A second selector (14 ″) and a third selector (8).
Here, the plurality of bit line pairs (4 and 5) include a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of word lines (3) extend in a second direction (X) substantially perpendicular to the first direction (Y). The plurality of memory cells (2) are provided corresponding to the positions where the plurality of bit line pairs (4 and 5) and the plurality of word lines (3) intersect. The first selector (11 ″) is connected to the array selector (44), and selects a first bit line (4s) or a plurality of second bit lines (5) from the plurality of first bit lines (4) during a write operation. Then, one of the selected second bit lines (5) is selected, and the selected first bit line (4s) and the selected second bit line (5) are selected during the read operation. The second selector (14 ″) is connected to the array selector (44), and the selected first bit line (4s) or the selected second bit line (5s) selected by the first selector (11 ″) during the write operation. The selected second bit line (5s) or the selected first bit line (4s) which is paired with the first bit line is selected. The third selector (8) selects the selected word line (3s) from the plurality of word lines (3).
However, each of the plurality of memory cells (2) includes a first transistor (6), a second transistor (16), and a magnetoresistive element (7). The first transistor (6) has a first gate (6b) connected to the word line (3) and a first terminal as one terminal other than the first gate (6b) connected to the first bit line (4). One terminal (6a) and a second terminal (6c) as the other terminal are included. The second transistor (16) has a second gate (16b) connected to the word line (3) and a second terminal as one terminal other than the second gate (16b) connected to the second bit line (5). 5 terminal (16a) and the 6th terminal (16c) as the other terminal connected to the 2nd terminal (6c) are included. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, the third terminal as one terminal is grounded (24), and the fourth terminal as the other terminal Is connected to the second terminal (6c).

  Here, in the magnetic random access memory, data is written to the memory cell (2) as follows. First, a pair of a selected first bit line (4) and a selected second bit line (5) are selected from a plurality of bit line pairs (4 and 5). At the same time, the selected word line (3s) is selected from the plurality of word lines (3), and both the first transistor (6) and the second transistor (16) are turned on. Then, data is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s), the selected second bit line (5s), and the selected word line (3s). A predetermined current (Iw (0), Iw (1)) based on the first selector (11 ″), the selected first bit line (4s), the selected cell (2s), and the selected second bit line (5s) Or the second selector (14 ″), or the first selector (11 ″), the selected second bit line (5s), the selected cell (2s), the selected first bit line (4s), and the first selector. It flows on the route passing through 2 selectors (14 ″).

  Here, in the above magnetic random access memory, data is read from the memory cell (2) as follows. First, the selected first bit line (4s) is selected from the plurality of first bit lines (4). At the same time, the selected word line (3s) is selected from the plurality of word lines (3), and both the first transistor (6) and the second transistor (16) are turned on. Then, a predetermined current (Is) is applied to the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s) and the selected word line (3s). It flows through a path including the selector (11 ″), the selected first bit line (4s), the selected second bit line (5s), and the magnetoresistive element (7) of the selected cell (2s). Data is read based on the potential of 2s).

Furthermore, the magnetic random access memory of the present invention includes a plurality of bit line pairs (4 and 5), a plurality of word lines (3), a plurality of memory cells (2), a first selector (71), a first selector, 2 selector (72), 3rd selector (8), and sense amplifier (81) are comprised.
The plurality of bit line pairs (4 and 5) include a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of word lines (3) extend in a second direction (X) substantially perpendicular to the first direction (Y). The plurality of memory cells (2) are provided corresponding to the positions where the plurality of bit line pairs (4 and 5) and the plurality of word lines (3) intersect. The first selector (71) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (72) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (8) selects the selected first word line (3s) from the plurality of first word lines (3). The plurality of sense amplifiers (81) include a plurality of extended first bit lines (4 in 90) connected to each of the plurality of first bit lines (4) extending from the first selector (71), and a plurality of first amplifiers. Connected to a plurality of extended second bit lines (5 in 90) connected to each of a plurality of second bit lines (5) extending from a second selector (72) corresponding to each of the 1 bit lines (4). The potential difference between the extended first bit line (4 in 90) and the extended second bit line (5 in 90) is amplified.
However, each of the plurality of memory cells (2) includes a first transistor (6), a second transistor (16), and a magnetoresistive element (7). The first transistor (6) has a first gate (6b) connected to the word line (3) and a first terminal as one terminal other than the first gate (6b) connected to the first bit line (4). One terminal (6a) and a second terminal (6c) as the other terminal are included. The second transistor (16) has a second gate (16b) connected to the word line (3) and a second terminal as one terminal other than the second gate (16b) connected to the second bit line (5). 5 terminal (16a) and the 6th terminal (16c) as the other terminal connected to the 2nd terminal (6c) are included. The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed according to stored data, the third terminal as one terminal is grounded (24), and the fourth terminal as the other terminal Is connected to the second terminal (6c).

  In the above magnetic random access memory, data writing (batch writing) to the memory cell (2) is performed as follows. First, a pair of extension selected first bit lines (4s in 90) are sequentially selected from the plurality of extension first bit lines (4 in 90) and the plurality of extension second bit lines (5 in 90). ) And the extension selection second bit line (5s in 90), and signals based on the data in the extension selection first bit line (4s in 90) and the extension selection second bit line (5s in 90) Enter. Next, the sense amplifier (81) amplifies the signal and outputs it to the extension selection first bit line (4s in 90) and the extension selection second bit line (5s in 90). Subsequently, the third selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on both the first transistor (6) and the second transistor (16). To do. Next, the first selector (71) and the second selector (72) select a plurality of bit line pairs (4 and 5). A plurality of selected cells connected to the same selected word line (3s) selected from the plurality of memory cells (2) by each of the plurality of bit line pairs (4 and 5) and the selected word line (3s). In contrast to (2s), a current (Iw (0), Iw (1)) based on the amplified signal is supplied to the plurality of selected cells (2s).

  In the magnetic random access memory, data writing (one data) to the memory cell (2) is performed as follows. First, the selected word line (3s) is selected from the plurality of word lines (3), and both the first transistor (6) and the second transistor (16) are turned on. At the same time, a plurality of bit line pairs (4 and 5) are selected. Next, a pair of extension selected first bit lines (4s in 90) and extensions out of the plurality of extension first bit lines (4 in 90) and the plurality of extension second bit lines (5 in 90). Select the selected second bit line (5s in 90) and input a signal based on the data to the extension selected first bit line (4 in 90) and the extension selected second bit line (5s in 90) To do. Subsequently, the first bit line (4) and the second bit line (5) corresponding to the extension selection first bit line (4s in 90) and the extension selection second bit line (5s in 90) are selected. A current (Iw (0), Iw (1)) based on the signal is applied to the selected cell (2s) for the selected cell (2s) selected from the plurality of memory cells (2) by the word line (3s). This is done by flowing it through.

  In the magnetic random access memory, data reading (batch reading) from the memory cell (2) is performed as follows. First, the first selector (71) selects a plurality of first bit lines (4). At the same time, the third selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the first transistor (6). A plurality of selected cells (3s) connected to the same selected word line (3s) selected from the plurality of memory cells (2) by each of the plurality of first bit lines (4) and the selected word line (3s). 2s), a predetermined current (Is) is passed through a path including each of the plurality of first bit lines (4) and each of the magnetoresistive elements (7) of the corresponding plurality of selected cells (2s). This is performed based on the potential of the selected cell (2s) when it is flowed.

  In the magnetic random access memory, data reading (one data) from the memory cell (2) is performed as follows. First, the selected first bit line (4s) is selected from the plurality of first bit lines (4). Next, the selected word line (3s) is selected from the plurality of word lines (3), and the first transistor (6) is turned on. Then, a predetermined current (Is) is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s) and the selected word line (3s). The current flows through a path including the 1 bit line (4s) and the magnetoresistive element (7) of the selected cell (2s), and data is read based on the potential of the selected cell (2s) at that time.

Further, the magnetic random access memory of the present invention includes a plurality of bit line pairs (4 and 5), a plurality of word line pairs (3c and 3d), and a plurality of memory cells (2e).
The plurality of bit line pairs (4 and 5) include a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of word line pairs (3c and 3d) include a first word line (3c) and a second word line (3d) extending in a second direction (X) substantially perpendicular to the first direction (Y). Including. The plurality of memory cells (2e) are provided corresponding to respective positions where the plurality of bit line pairs (4 and 5) and the plurality of word line pairs (3c and 3d) intersect.
Each of the plurality of memory cells (2e) includes a first transistor (6), a second transistor (16), and a magnetoresistive element (7).
However, the first transistor (6) has the gate electrode (6b) as the first word line (3c), the remaining one terminal (6a) as the first bit line (4), and the other terminal (6c). The magnetoresistive element (7) is connected. The second transistor (16) has the gate electrode (16c) as the second word line (3d), the remaining one terminal (16c) as the other terminal (6c) of the first transistor (6), and the other terminal. (16a) is connected to the second bit line (5). The magnetoresistive element (7) has spontaneous magnetization whose magnetization direction is reversed in accordance with stored data, one terminal being grounded (24) and the other terminal being the other of the first transistor (6). It is connected to the terminal (6c).
The second bit line (5) paired with the first bit line (4) is shared by the two first bit lines (4) adjacent to the second bit line (5).

  Here, in the magnetic random access memory, data is written to the memory cell (2e) as follows. First, a pair of a selected first bit line (4s) and a selected second bit line (5s) are selected from a plurality of bit line pairs (4 and 5), and the selected second bit line (5s) is set to a predetermined value. Fix to voltage (Vterm). At the same time, a pair of a selected first word line (3cs) and a selected second word line (3ds) are selected from a plurality of word line pairs (3c and 3d), and a first transistor (6) and a second transistor ( 16) and both are turned on. The selected first bit line (4s) and the selected second bit line (5s), and the selected first word line (3cs) and the selected second word line (3ds) are selected from the plurality of memory cells (2e). A predetermined current (Iw (0), Iw (1)) based on data is applied to the selected first bit line (4s), the selected cell (2es), and the selected second bit line ( 5s).

  On the other hand, in the above magnetic random access memory, data is read from the memory cell (2e) as follows. First, the selected first bit line (4s) is selected from the plurality of first bit lines (4). At the same time, the selected first word line (3cs) is selected from the plurality of first word lines (3c), and the first transistor (6) is turned on. Then, a predetermined current (Is) is applied to the selected cell (2es) selected from the plurality of memory cells (2e) by the selected first bit line (4s) and the selected first word line (3cs). Data is read based on the potential of the selected cell (2es) when flowing through the path including the selected first bit line (4s) and the magnetoresistive element (7) of the selected cell (2es).

Furthermore, the magnetic random access memory of the present invention includes a plurality of bit line pairs (4, 5), a word line (3), a first selector (11), a second selector (14), and a third selector ( 8) and a plurality of memory cells (20f). The plurality of bit line pairs (4, 5) are a set of a first bit line (4) and a second bit line (5) extending in the first direction (Y). The word line (3) extends in a second direction (X) substantially perpendicular to the first direction (Y). The first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (8) selects the selected word line (3s) from the plurality of word lines (3). The plurality of memory cells (20f) are provided corresponding to respective positions where the plurality of bit line pairs (4, 5) and the plurality of word lines (3) intersect.
Each of the plurality of memory cells (20f) includes a transistor (6), a magnetoresistive element (7), a second diode (32), and a third diode (33). The transistor (6) includes a gate connected to the word line (3), a first terminal other than the gate connected to the first bit line (4), and a second terminal as the other terminal. Terminal. The magnetoresistive element (7) has a spontaneous magnetization whose magnetization direction is reversed according to stored data, and supplies a predetermined voltage to the third terminal as one terminal connected to the second terminal. And a fourth terminal as the other terminal connected to the voltage source (24a). The second diode (32) includes a fifth terminal having a first polarity connected to the second terminal, and a sixth terminal having a second polarity different from the first polarity connected to the second bit line (5). including. The third diode (33) includes a seventh terminal of the first polarity connected to the second bit line (5) and an eighth terminal of the second polarity connected to the second terminal.

  In the magnetic random access memory, data is written to the memory cell (20f) as follows. First, the first selector (11) and the second selector (14) select a pair of the selected first bit line (4s) and the selected second bit line (5s) from the plurality of bit line pairs (4, 5). . The third selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the transistor (6). For the selected cell (20fs) selected from the plurality of memory cells (20f) by the selected first bit line (4s), the selected second bit line (5s), and the selected first word line (3s). The current based on the data is caused to flow through a path including the selected first bit line (4s), the selected cell (20fs), and the selected second bit line (5s).

  In the magnetic random access memory, the data is read from the memory cell (20f) as follows. First, the first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). The third selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the transistor (6). A predetermined current is applied to the selected first bit line for the selected cell (20fs) selected from the plurality of memory cells (20f) by the selected first bit line (4s) and the selected word line (3s). (Based on the potential of the selected cell (20fs) when flowing through a path including 4s and the magnetoresistive element (7) of the selected cell (20fs)).

Furthermore, the magnetic random access memory of the present invention includes a plurality of bit line pairs (4, 5) and a plurality of third bit lines (35), a word line (3), a first selector (11-1), A second selector (14), a third selector (11-2), a fourth selector (8), and a plurality of memory cells (2) are provided. The plurality of bit line pairs (4, 5) are a set of a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of third bit lines (35) extend in the first direction (Y). The word line (3) extends in a second direction (X) substantially perpendicular to the first direction (Y). The first selector (11-1) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (11-2) selects the selected third bit line (35s) from the plurality of third bit lines (35). The fourth selector (8) selects the selected word line (3s) from the plurality of word lines (3). The plurality of memory cells (2) are provided corresponding to respective positions where the plurality of bit line pairs (4, 5) and the plurality of word lines (3) intersect.
Each of the plurality of memory cells (2) includes a transistor (6), a magnetoresistive element (7), a second diode (32), and a third diode (33). The transistor (6) includes a gate connected to the word line (3), a first terminal other than the gate connected to the first bit line (4), and a second terminal as the other terminal. Terminal. The magnetoresistive element (7) has a spontaneous magnetization whose magnetization direction is reversed in accordance with stored data, a fourth terminal as one terminal connected to the second terminal, and a third bit line ( 35) and the third terminal as the other terminal connected. The second diode (32) includes a fifth terminal having a first polarity connected to the second terminal, and a sixth terminal having a second polarity different from the first polarity connected to the second bit line (5). including. The third diode (33) includes a seventh terminal of the first polarity connected to the second bit line (5) and an eighth terminal of the second polarity connected to the second terminal.

  In the magnetic random access memory, data is written to the memory cell (2) as follows. First, the first selector (11-1) and the second selector (14) select a pair of the selected first bit line (4s) and the selected second bit line (5s) from the plurality of bit line pairs (4, 5). select. At this time, the second selector (14) fixes the selected second bit line (5s) to a predetermined voltage (Vterm). The fourth selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the transistor (6). A selected cell (2s) selected from the plurality of memory cells (20f) by the selected first bit line (4s), the selected second bit line (5s), and the selected first word line (3s). A predetermined current (Iw (1), Iw (0)) based on the data is passed through a path including the selected first bit line (4s), the selected cell (2s), and the selected second bit line (5s). To do. At this time, the third bit line (35) is set to a potential such that the potential of the fourth terminal is substantially the same as the potential of the third terminal.

  In the above magnetic random access memory, reading of the data from the memory cell (2) is performed as follows. First, the first selector (11-1) selects the selected first bit line (4s) from the plurality of first bit lines (4). The third selector (11-2) selects the selected third bit line (35s) from the plurality of third bit lines (35). The fourth selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the transistor (6). Then, a predetermined current (Is) is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s) and the selected word line (3s). This is performed based on the potential of the selected cell (2s) when flowing through a path including the magnetoresistive element (7) of the 3-bit line (35s), the selected cell (2s), and the selected first bit line (4s).

The magnetic random access memory according to the present invention further includes a plurality of memory cell arrays (41f) and an array selector (17a) for selecting a selected cell array (41fs) from the plurality of memory cell arrays (41f).
Each of the plurality of memory cell arrays (41f) includes a plurality of bit line pairs (4, 5), a word line (3), a first selector (11), a second selector (14), and a third selector ( 8) and a plurality of memory cells (20f). The plurality of bit line pairs (4, 5) are a set of a first bit line (4) and a second bit line (5) extending in the first direction (Y). The word line (3) extends in a second direction (X) substantially perpendicular to the first direction (Y). The first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (8) selects the selected word line (3s) from the plurality of word lines (3). The plurality of memory cells (20f) are provided corresponding to respective positions where the plurality of bit line pairs (4, 5) and the plurality of word lines (3) intersect.
Each of the plurality of memory cells (20f) includes a transistor (6), a magnetoresistive element (7), a second diode (32), and a third diode (33). The transistor (6) includes a gate connected to the word line (3), a first terminal as one terminal other than the first gate connected to the first bit line (4), and a terminal as the other terminal. A second terminal. The magnetoresistive element (7) has a spontaneous magnetization whose magnetization direction is reversed according to stored data, and supplies a predetermined voltage to the third terminal as one terminal connected to the second terminal. And a fourth terminal as the other terminal connected to the voltage source (24a). The second diode (32) includes a fifth terminal having a first polarity connected to the second terminal, and a sixth terminal having a second polarity different from the first polarity connected to the second bit line (5). including. The third diode (33) includes a seventh terminal of the first polarity connected to the second bit line (5) and an eighth terminal of the second polarity connected to the second terminal.
The first selector (11) and the second selector (14) are connected to the array selector (17a).

Furthermore, the magnetic random access memory of the present invention includes a plurality of bit line pairs (4, 5), a word line (3), a first selector (11), a second selector (14), and a third selector ( 8) and a plurality of memory cells (20g). The plurality of bit line pairs (4, 5) are a set of a first bit line (4) and a second bit line (5) extending in the first direction (Y). The word line (3) extends in a second direction (X) substantially perpendicular to the first direction (Y). The first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (8) selects the selected word line (3s) from the plurality of word lines (3). The plurality of memory cells (20g) are provided corresponding to the positions where the plurality of bit line pairs (4, 5) and the plurality of word lines (3) intersect.
Each of the plurality of memory cells (20g) includes a transistor (6), a magnetoresistive element (7), a second diode (32), and a third diode (33). The transistor (6) includes a gate connected to the word line (3), a first terminal as one terminal other than the first gate connected to the first bit line (4), and a terminal as the other terminal. A second terminal. The magnetoresistive element (7) has a spontaneous magnetization whose magnetization direction is reversed according to stored data, and supplies a predetermined voltage to the third terminal as one terminal connected to the second terminal. And a fourth terminal as the other terminal connected to the voltage source (24a). The second diode (32) includes a fifth terminal having a first polarity connected to the second bit line (5) and a sixth terminal having a second polarity different from the first polarity. The third diode (33) includes a seventh terminal of the first polarity connected to the second terminal and an eighth terminal of the second polarity connected to the sixth terminal.

  In the magnetic random access memory, data is written to the memory cell (20g) as follows. First, the first selector (11) and the second selector (14) select a pair of the selected first bit line (4s) and the selected second bit line (5s) from the plurality of bit line pairs (4, 5). . The third selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the transistor (6). Then, for the selected cell (20gs) selected from the plurality of memory cells (20g) by the selected first bit line (4s), the selected second bit line (5s), and the selected word line (3s), A current based on data is caused to flow through a path including the selected first bit line (4s), the selected cell (20gs), and the selected second bit line (5s). At this time, the reverse voltage applied to either the second diode (32) or the third diode (33) based on the data is equal to or higher than the breakdown voltage.

  In the above magnetic random access memory, reading of the data from the memory cell (20g) is performed as follows. First, the first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). The third selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the transistor (6). Then, a predetermined current is applied to a selected cell (20gs) selected from a plurality of memory cells (20g) by the selected first bit line (4s) and the selected word line (3s). (4 s) and the selected cell (20 gs) based on the potential of the selected cell (20 gs) when flowing through a path including the magnetoresistive element (7).

Furthermore, the magnetic random access memory of the present invention includes a plurality of bit line pairs (4, 5), a plurality of third bit lines, a word line (3), a first selector (11-1), a second A selector (14), a third selector (11-2), a fourth selector (8), and a plurality of memory cells (2) are provided. The plurality of bit line pairs (4, 5) are a set of a first bit line (4) and a second bit line (5) extending in the first direction (Y). The plurality of third bit lines (35) extend in the first direction (Y). The word line (3) extends in a second direction (X) substantially perpendicular to the first direction (Y). The first selector (11-1) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The second selector (11-2) selects the selected first bit line (35s) from the plurality of third bit lines (35). The fourth selector (8) selects the selected word line (3s) from the plurality of word lines (3). A plurality of memory cells (20 are provided corresponding to positions where a plurality of bit line pairs (4, 5) and a plurality of word lines (3) cross each other.
Each of the plurality of memory cells (2) includes a transistor (6), a magnetoresistive element (7), a second diode (32), and a third diode (33). The transistor (6) includes a gate connected to the word line (3), a first terminal other than the gate connected to the first bit line (4), and a second terminal as the other terminal. Terminal. The magnetoresistive element (7) has a spontaneous magnetization whose magnetization direction is reversed in accordance with stored data, a fourth terminal as one terminal connected to the second terminal, and a third bit line ( 35) and the third terminal as the other terminal connected. The second diode (32) includes a fifth terminal having a first polarity connected to the second bit line (5) and a sixth terminal having a second polarity different from the first polarity. The third diode (33) includes a seventh terminal of the first polarity connected to the second terminal and an eighth terminal of the second polarity connected to the sixth terminal.

  In the magnetic random access memory, data is written to the memory cell (2) as follows. First, the first selector (11-1) and the second selector (14) select a pair of the selected first bit line (4s) and the selected second bit line (5s) from the plurality of bit line pairs (4, 5). select. At this time, the second selector (14) fixes the selected second bit line (5s) to a predetermined voltage (Vterm). The fourth selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the transistor (6). Then, for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s), the selected second bit line (5s), and the selected word line (3s), The current based on the data is performed by passing the current through a path including the selected first bit line (4s), the selected cell (2s), and the selected second bit line (5s). At this time, the reverse voltage applied to either the second diode (32) or the third diode (33) based on the data is equal to or higher than the breakdown voltage. The third bit line (35) is set to a potential such that the potential of the fourth terminal is substantially the same as the potential of the third terminal.

  In the above magnetic random access memory, reading of the data from the memory cell (2) is performed as follows. First, the first selector (11-1) selects the selected first bit line (4s) from the plurality of first bit lines (4). The third selector (11-2) selects the selected third bit line (35s) from the plurality of third bit lines (35). The fourth selector (8) selects the selected word line (3s) from the plurality of word lines (3), and turns on the transistor (6). Then, a predetermined current (Is) is selected for the selected cell (2s) selected from the plurality of memory cells (2) by the selected first bit line (4s) and the selected word line (3s). This is performed based on the potential of the selected cell (20gs) when flowing through a path including the magnetoresistive element (7) of the 3-bit line (35s), the selected cell (20gs), and the selected first bit line (4s).

The magnetic random access memory according to the present invention further includes a plurality of memory cell arrays (41g) and an array selector (17a) for selecting a selected cell array (41gs) from the plurality of memory cell arrays (41g).
Each of the plurality of memory cell arrays (41g) includes a plurality of bit line pairs (4, 5), a word line (3), a first selector (11), a second selector (14), and a third selector ( 8) and a plurality of memory cells (20g). The plurality of bit line pairs (4, 5) are a set of a first bit line (4) and a second bit line (5) extending in the first direction (Y). The word line (3) extends in a second direction (X) substantially perpendicular to the first direction (Y). The first selector (11) selects the selected first bit line (4s) from the plurality of first bit lines (4). The second selector (14) selects the selected second bit line (5s) from the plurality of second bit lines (5). The third selector (8) selects the selected word line (3s) from the plurality of word lines (3). The plurality of memory cells (20g) are provided corresponding to the positions where the plurality of bit line pairs (4, 5) and the plurality of word lines (3) intersect.
Each of the plurality of memory cells (20g) includes a transistor (6), a magnetoresistive element (7), a second diode (32), and a third diode (33). The transistor (6) includes a gate connected to the word line (3), a first terminal as one terminal other than the first gate connected to the first bit line (4), and a terminal as the other terminal. A second terminal. The magnetoresistive element (7) has a spontaneous magnetization whose magnetization direction is reversed according to stored data, and supplies a predetermined voltage to the third terminal as one terminal connected to the second terminal. And a fourth terminal as the other terminal connected to the voltage source (24a). The second diode (32) includes a fifth terminal having a first polarity connected to the second bit line (5) and a sixth terminal having a second polarity different from the first polarity. The third diode (33) includes a seventh terminal of the first polarity connected to the second terminal and an eighth terminal of the second polarity connected to the sixth terminal.
The first selector (11) and the second selector (14) are connected to the array selector (41g). Based on the data, the reverse voltage applied to either the second diode (32) or the third diode (33) during the write operation is equal to or higher than the breakdown voltage.

In the magnetic random access memory, the threshold voltage (Vtw) of the transistor on the path through which the write current (Iw) for writing the data to the magnetoresistive element (7) flows is ½ or less of the power supply voltage (Vdd). This is a magnetic random access memory designed on the premise that a voltage of 1 is applied between the source and drain of the transistor.

  In the above magnetic random access memory, the gate length (Lw) of the transistor is designed to be smaller than that of a standard transistor. Here, the standard transistor is designed on the assumption that a voltage larger than ½ of the power supply voltage (Vdd) is applied between the source and the drain.

In the magnetic random access memory described above, the magnetism provided on the opposite side of the magnetoresistive element (7) across the layer (29) through which the write current (Iw) for writing data to the magnetoresistive element (7) flows. A structure (7-1) is further provided. The magnetic structure (7-1) has a magnetic field (H _I ) generated in the vicinity of the magnetoresistive element (7) by the write current (Iw) and a magnetic field (H _I ) generated by its own magnetization by the write current (Iw). _J ) is superimposed.

  In the magnetic random access memory, the shape of the magnetoresistive element (7) is asymmetric with respect to the easy axis of magnetization of the magnetoresistive element (7).

  The magnetic random access memory according to the present invention has first (and second) transistors, and only the selected cell has a current flowing through a node to which one terminal of the magnetoresistive element is connected. Therefore, the magnetic field applied to the non-selected cell by the write current is very small, and a highly selective memory cell can be obtained. In the magnetic random access memory according to the present invention, the row selection is performed only by activation of the word line in both the read state and the write state. Therefore, the configuration of the X selector can be simplified and the area of the X selector is small. As a result, an MRAM with a small chip size can be obtained.

  Hereinafter, embodiments of a magnetic memory cell and a magnetic random access memory according to the present invention will be described with reference to the accompanying drawings.

(First embodiment)
A magnetic memory cell and a magnetic random access memory according to a first embodiment of the present invention will be described.

  First, the configuration of the magnetic memory cell and the magnetic random access memory according to the first embodiment of the present invention will be described. FIG. 1 is a diagram showing a configuration of a first embodiment of a magnetic random access memory (MRAM) including a magnetic memory cell of the present invention. The MRAM of this embodiment includes a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4, a plurality of second bit lines 5, an X selector 8, a Y selector 11, a Y-side current source circuit 12, A side power supply circuit 19, a read current load circuit 13, a Y side current termination circuit 14, and a sense amplifier 15 are provided.

In the memory cell array 1, memory cells 2 are arranged in a matrix. Here, the memory cell 2 includes a first MOS transistor 6, a second MOS transistor 16, and a magnetoresistive element 7. The reference memory cell 2 is referred to as a reference cell 2r.
The first MOS transistor 6 as the first transistor has a gate (first gate) as the word line 3, a source (first terminal) as the first bit line 4, and a drain (second terminal) as one end of the magnetoresistive element 7. Side (fourth terminal) and the drain (sixth terminal) of the second MOS transistor 16.
The second MOS transistor 16 has a gate (second gate) as the word line 3, a source (fifth terminal) as the second bit line 5, and a drain (sixth terminal) as one end side (fourth terminal) of the magnetoresistive element 7. And the drain (second terminal) of the first MOS transistor 6.
During the read operation, the first MOS transistor 6 is used to connect the magnetoresistive element 7 to the first bit line 4 and to pass a current from the magnetoresistive element 7 to the first bit line 4. During the write operation, the first MOS transistor 6 and the second MOS transistor 16 are used to connect the first bit line 4 and the second bit line 5 and to allow a current to flow in the vicinity of the magnetoresistive element 7.
The magnetoresistive element 7 has one end side (fourth terminal) connected to each of the transistors and the other end side (third terminal) connected to the ground wiring 24. It has spontaneous magnetization whose magnetization direction is reversed according to stored data.

The first bit line 4 is provided so as to extend in the Y-axis direction (bit line direction) as the first direction, and is connected to the Y selector 11. The reference first bit line 4 is referred to as a reference first bit line 4r.
The second bit line 5 is paired with the first bit line 4, is provided extending in the Y-axis direction, and is connected to the Y-side current termination circuit 14. The reference second bit line 5 is referred to as a reference second bit line 5r.
The word line 3 is provided so as to extend in the X-axis direction (word line direction) as a second direction substantially perpendicular to the Y-axis direction, and is connected to the X selector 8.
Each of the memory cells 2 is provided corresponding to each of the positions where the plurality of sets of the first bit line and the second bit line intersect with the plurality of word lines.

The X selector 8 selects one word line 3 as the selected word line 3s from the plurality of word lines 3 in both the data read operation and the write operation.
The Y selector 11 selects one first bit line 4 from the plurality of first bit lines 4 as the selected first bit line 4s in both the data read operation and the data write operation.
Here, the memory cell 2 selected by the selected word line 3s and the selected first bit line 4s is referred to as a selected cell 2s.

The Y-side current source circuit 12 is a current source that supplies or draws a predetermined current to the selected first bit line 4s during a data write operation. A current selector unit 12b that determines the direction of current and a constant current source 12a that supplies a constant current are provided.
The Y-side current termination circuit 14 selects one second bit line 5 that forms a pair with the selected first bit line 4s as the selected second bit line 5s from the plurality of second bit lines 5 during the data write operation. .
The Y-side power supply circuit 19 supplies a predetermined voltage to the Y-side current termination circuit 14 during a data write operation.
Here, the predetermined current from the Y-side current source circuit 12 flows in the path of the selected first bit line 4 s -selected cell 2 s -selected second bit line 5 s into the Y selector 11 according to the data to be written, or Y It flows in the direction of flowing out from the selector 11.

The read current load circuit 13 supplies a predetermined current to the selected first bit line 4s during a data read operation. Similarly, a predetermined current is supplied to the reference first bit line 4r during a data read operation.
The sense amplifier 15 reads data from the selected cell 2s based on the difference between the voltage of the reference first bit line 4r connected to the reference cell 2r and the voltage of the selected first bit line 4s connected to the selected cell 2s. Is output.

  Here, the basic structure of the reference cell 2r is the same as that of the normal memory cell 2. However, the resistance value is predetermined (the voltage drop of the magnetoresistive element 7 having data “1” and the voltage drop of the magnetoresistive element 7 having data “0” due to the predetermined current flowing through the read current load circuit 13. And has a voltage drop that is intermediate to the minute) and is referred to during the read operation of the other memory cell 2. Such setting can be made by setting the value of the current passed through the reference cell 2r or changing the film characteristics (film thickness, material) of the magnetoresistive element 7 of the reference cell 2r.

2 is a view of the memory cell array of the MRAM shown in FIG. 1 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, 2 × 2 memory cells 2 in the memory cell array 1 are shown as representatives.
In the first MOS transistor 6 of the memory cell 2, the source 6 a (first terminal) is connected to the first bit line 4 via the contact wiring 28. The gate 6b (first gate terminal) uses the word line 3-1 branched from the word line 3 in the Y-axis direction. The drain 6c (second terminal) is connected to the drain 16c (sixth terminal) of the second MOS transistor 16 through the contact wiring 27, the lead-out wiring layer 29, and the contact wiring 37. The second MOS transistor 16 uses a word line 3-2 in which a gate 16b (second gate terminal) branches from the word line 3 in the Y-axis direction. The source 16 a (fifth terminal) is connected to the second bit line 5 through the contact wiring 38.

  The magnetoresistive element 7 is provided on the lead wiring layer 29. The direction of spontaneous magnetization is reversed by the current flowing through the lead wiring layer 29. Here, since the current flowing through the lead wiring layer 29 flows in the X-axis direction, the direction of the magnetic field felt by the magnetoresistive element 7 is the Y-axis direction. Therefore, it is provided in a shape that facilitates magnetization in the Y-axis direction. For example, an ellipse having a long axis parallel to the Y-axis direction or a shape similar to an ellipse. One end (fourth terminal) of the magnetoresistive element 7 is connected to the lead wiring layer 29 and the other end (third terminal) is connected to the ground wiring 24 (not shown in FIG. 2). The ground wiring 24 on the other end side (third terminal) does not need to be separated for each memory cell 2 and is formed integrally. This is shown in FIG.

  FIG. 3 is a diagram illustrating the ground wiring. The ground (GND) wiring 24 is provided above the memory cell array 1 shown in FIG. 2 so as to cover the entire memory cell array. However, in FIG. 3, one memory cell 2 is represented by one magnetoresistive element 7.

FIG. 4A shows the structure of the memory cell 2 and shows a cross section taken along the line AA ′ in FIG.
The first MOS transistor 6 is formed on the surface portion of the semiconductor substrate. A source 6a as a first diffusion layer provided in the semiconductor substrate is connected to the first bit line 4 via a contact wiring 28 extending in the Z-axis direction. The drain 6c as the second diffusion layer is connected to one end of the lead-out wiring layer 29 via a contact wiring 27 extending in the Z-axis direction. The gate 6 b as the first gate uses the word line 3-1 branched from the word line 3. However, the drain 6c is provided inside the memory cell 2 with respect to the source 6a.
The second MOS transistor 16 is formed on the surface portion of the semiconductor substrate. A source 16a as a third diffusion layer provided in the semiconductor substrate is connected to the second bit line 5 through a contact wiring 38 extending in the Z-axis direction. The drain 16c as the fourth diffusion layer is connected to the other end of the lead-out wiring layer 29 via a contact wiring 37 extending in the Z-axis direction. The gate 16 b as the second gate uses the word line 3-2 branched from the word line 3. However, the drain 16c is provided inside the memory cell 2 with respect to the source 16a.
The magnetoresistive element 7 is connected to the lead wiring layer 29 on one end side. The other end side is connected to a ground (GND) line 24 via a contact wiring 26.

  FIG. 4B is a cross-sectional view showing the structure of the magnetoresistive element 7. The magnetoresistive element 7 includes a free layer 21, a pinned layer 23, and a tunnel insulating layer 22. The pinned layer 23 is formed on the lead wiring layer 29, the tunnel insulating layer 22 is formed on the pinned layer 23, and the free layer 21 is formed on the tunnel insulating layer 22. Both the pinned layer 23 and the free layer 21 are formed of a ferromagnetic material, and each has spontaneous magnetization. The direction of spontaneous magnetization of the pinned layer 23 is fixed in the + X direction. The direction of the spontaneous magnetization of the free layer 21 can be reversed, and can be directed in two directions, the + X direction and the −X direction. Data stored in the memory cell 2 is stored as the direction of spontaneous magnetization of the free layer 21. Then, data is read based on the difference in resistance value of the magnetoresistive element 7 due to the difference in the direction of spontaneous magnetization. The tunnel insulating layer 22 is formed of an insulator. The film thickness of the tunnel insulating layer 22 is so thin that a tunnel current flows.

FIG. 70 is a graph showing the relationship between the transistor gate length and the threshold voltage. The vertical axis represents the threshold voltage Vt, and the horizontal axis represents the gate length Lw.
In general, the gate length Lw of a transistor is determined with a minimum gate length Lwa from which a stable threshold voltage Vtw can be obtained unless otherwise specified. The drain-source voltage Vds at that time is the power supply voltage Vdd (curve A). However, when considering only the write current path (... -First bit line 4 -memory cell 2 -second bit line 5-...), There are selection elements including transistors at both terminals of the memory cell 2. To do. These elements have element resistance. If each element is regarded as a resistance element, it is more efficient to divide the resistance element equally between the power supply (Vdd) side and the ground (Gnd) side. In that case, the potential of the memory cell 2 is about Vdd / 2 or less.
Therefore, in the present invention, the gate length Lw of the transistor in the write current path, particularly the transistor of the memory cell 2 (the first MOS transistor 6 and the second transistor 16) is optimized with Vds / 2 of Vdd / 2 (curve B). . With a lower Vds, a stable threshold voltage Vtw is obtained at a thinner Lwb. Thereby, Lwb can be made thinner than Lwa. By reducing Lw, the cell area can be directly reduced.

FIG. 71 is a graph showing the relationship between the current capability of a transistor and the gate length. The vertical axis represents the current capability Ion, and the horizontal axis represents the gate length Lw.
The current capability Ion of the transistor monotonously decreases as the gate length Lw increases. That is, as described in FIG. 70, by reducing the gate length Lw, a larger write current can be supplied with the same memory cell area. As a result, it is possible to increase the operation margin without increasing the chip area.

FIG. 72 is a graph showing the relationship between the gate length of a transistor and the threshold voltage. The vertical axis represents the threshold voltage Vt, and the horizontal axis represents the gate length Lw.
In general, the stable threshold voltage Vtw of a transistor is controlled by the impurity implantation concentration of the silicon substrate. When the threshold voltage Vtw is set low, the current capability of the transistor is improved as derived from the formula Ion∝ (Vgs−Vtw) ² : (where Vgs is the gate-source voltage) of a general transistor. I can do it. However, on the other hand, when Vtw is lowered, Lw is increased. That is, Lwa <Lwc is not necessarily advantageous with respect to Lwa of curve A in FIG. 70, as Lwc in curve C in FIG. Therefore, Vtw is comprehensively optimized.
Here, as described with reference to FIG. 70, if Vds is set to Vdd / 2, a low Vtw can be set while Lw is kept low. Thereby, as shown by the curve D, a lower gate length Lwd can be obtained with a low Vtw. Therefore, a larger write current can be passed with the same memory cell area. As a result, it is possible to increase the operation margin without increasing the chip area.

  The description of FIGS. 70 to 72 can be similarly applied to other memory cells and memory cell arrays having transistors in the path of the write current.

Next, the operation of the first embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.
FIG. 5 is a diagram for explaining the operation of the first embodiment of the magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. That is, FIG. 5 is a circuit diagram illustrating the circuit of the write and read paths, taking one memory cell 2 as an example.

Reading data from the memory cell 2 is performed as follows.
(1) Step S01
The X selector 8 selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address (2 bits: X0 and X1). The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(2) Step S02
The Y selector 11 selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address (2 bits: Y0 and Y1). Then, in response to the read active signal RA, the read current load circuit 13 passes a predetermined current Is through the selected first bit line 4s and passes a predetermined current Ir through the reference first bit line 4r.
At this time, the current Is flows from the read current load circuit 13 to the ground wiring 24 via the selected first bit line 4 s and the first MOS transistor 6 -magnetoresistance element 7 of the selected cell 2 s. Similarly, the first MOS transistor 6 of the read current load circuit 13-reference first bit line 4r-selected reference cell 2r (reference cell 2r corresponding to the intersection of the selected word line 3s and the reference first bit line 4r) 6-magnetic resistance A current Ir flows into the ground wiring 24 via the element 7.
(3) Step S03
In response to the read active signal RA, the sense amplifier 15 causes the difference between the voltage of the selected first bit line 4s when the predetermined current Is flows and the voltage of the reference first bit line 4r when the predetermined current Ir flows. Based on this, either “1” or “0” is output.

  With the above read operation, data of the selected cell 2s can be read.

  Data is written to the memory cell 2 as follows.

(1) Step S11
The X selector 8 selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address (2 bits: X0 and X1). The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(2) Step S12
The Y selector 11 selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address (2 bits: Y0 and Y1). Further, the Y-side current termination circuit 14 selects the selected second bit line 5 s from the plurality of second bit lines 5 by the write active signal WA. A pair of the selected first bit line 4s and the selected second bit line 5s is selected.
At this time, the Y-side current termination circuit 14 applies a predetermined voltage Vterm to the selected second bit line 5s. Based on the write active signal WA and the data signal Data, the Y-side current source circuit 12 has a current Iw (0) (in the case of “0”: Y-side current source circuit 12 having a predetermined magnitude corresponding to the data signal Data. Current Iw (1) (in the case of “1”, the direction of flowing out from the Y-side current source circuit 12) is supplied to the selected first bit line 4s−selected cell 2s.
The current Iw (0) or the current Iw (1) is generated by selecting the selected second bit line 5s-the second MOS transistor 16 of the selected cell 2s (-the lead wiring layer 29 of the selected cell 2s) -the first MOS transistor 6 of the selected cell 2s. The path of the first bit line 4s flows in the forward or reverse direction.
(3) Step S13
In the selected cell 2s, when the current Iw (0) (+ X direction) or the current Iw (1) (−X direction) flows on the lead-out wiring layer 29 in contact with the magnetoresistive element 7, the −Y direction or + Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal Data is stored.

  The reference active signal SR is a signal for selecting the reference cell 2r when writing to the reference cell 2r, and corresponds to the write active signal WA in the normal memory cell 2.

  With the above write operation, data can be written to the selected cell 2s.

FIG. 6 is a graph showing a comparison between the magnetic field H ₀ applied to the magnetoresistive element 7 of the selected cell 2 s and the asteroid curve. The magnitudes of the current Iw (0) and the current Iw (1) are set so that the applied magnetic field H ₀ (H ₀ (0) and H ₀ (1)) is outside the asteroid curve. Since no current flows through the unselected memory cell 2 (hereinafter referred to as “non-selected cell 2”), there is no fear of erroneous writing to the non-selected cell 2, and a sufficiently large current can be set.

  The currents Iw (0) and Iw (1) in the write operation do not flow to other memory cells 2 other than the selected cell 2s and the vicinity thereof, and do not affect the other memory cells 2. Therefore, the reliability of the memory cell can be improved.

  Further, the write currents Iw (0) and Iw (1) do not flow in the memory cells 2 other than the selected cell 2s and in the vicinity thereof. Thereby, it is possible to increase the selectivity when the memory cell 2 is selected.

  The X selector 8 of the present embodiment is different from the conventional technique (two write word lines and two read word lines are required, and two output units are also required corresponding thereto), and the selection in the X-axis direction is performed on the word line 3. Do it only. Therefore, the circuit area of the X selector 8, the circuit area of the X-side current source circuit, and the circuit area of one type of word line can be reduced.

  Further, as shown in FIG. 4, in the selected cell 2s, the magnetoresistive element 7 and the lead-out wiring layer 29 are extremely close to each other, so that write currents Iw (0) and Iw (1) passing through the lead-out wiring layer 29 are generated. It becomes possible to make it smaller.

In the present embodiment, it is also possible to arrange a laminated ferri structure in the lead-out wiring layer. This is shown in FIG.
FIG. 73 is a sectional view showing another application example of the magnetic memory cell and the magnetic random access memory according to the first embodiment of the present invention. That is, FIG. 3 is a diagram showing another application example of the structure of the memory cell 2 and showing a cross section taken along line AA ′ in FIG. 2.

  In the drawing wiring layer 29 in this figure, the laminated ferrimagnetic structure 7-1 is disposed on the side (substrate side) opposite to the magnetoresistive element 7. For example, the shape is preferably the same as or larger than that of the magnetoresistive element 7. The position is preferably directly below the magnetoresistive element 7 with the lead wiring layer 29 interposed therebetween. It becomes possible to increase the influence of the magnetic field by the laminated ferrimagnetic structure 7-1 on the magnetoresistive element 7.

  FIG. 74 is a graph showing the characteristics of the laminated ferri structure 7-1. The vertical axis represents spontaneous magnetization (M), and the horizontal axis represents magnetic field (H). As shown in this graph, the structure of the laminated ferrimagnetic structure 7-1 is designed so that the spontaneous magnetization (M) becomes 0 when the absolute value of the magnetic field (H) is equal to or less than the threshold value (Ht). .

  FIG. 75 shows a structure of the laminated ferri structure 7-1. The laminated ferri structure 7-1 has a laminated ferri structure, and as shown in FIG. 75A, the first magnetic layer 7-2, the nonmagnetic spacer layer 7-3, 2 magnetic layer 7-4. The first magnetic layer 7-2 and the second magnetic layer 7-4 are both made of a ferromagnetic material, and are interposed between the first magnetic layer 7-2 and the second magnetic layer 7-4. The nonmagnetic spacer layer 7-3 is made of a nonmagnetic material.

  The film thickness t of the nonmagnetic spacer layer 7-3 of the laminated ferrimagnetic structure 7-1 is determined so that the first magnetic layer 7-2 and the second magnetic layer 7-4 are antiferromagnetically coupled. Therefore, in a state where no magnetic field is applied to the laminated ferrimagnetic structure 7-1, as shown in FIG. 75C, the first magnetic layer 7-2 and the second magnetic layer 7-4 are In this state, the magnetization of the whole laminated ferrimagnetic structure 7-1 is substantially zero. That is, in a state where a magnetic field is not applied to the laminated ferri structure 7-1, the laminated ferri structure 7-1 has substantially no magnetic moment.

The fact that the first magnetic layer 7-2 and the second magnetic layer 7-4 are antiferromagnetically coupled and the laminated ferrimagnetic structure 7-1 does not have a magnetic moment as a whole is that the offset magnetic field of the magnetoresistive element 7. Is preferable in terms of reducing the size.
For example, when the laminated ferri structure 7-1 has a magnetic moment as a whole, a magnetic field in which the magnetic moment is generated is applied to the magnetoresistive element 7. Therefore, even when the write current Iw is not applied to the lead-out wiring layer 29, a magnetic field that generates a magnetic moment is applied to the magnetoresistive element 7. This magnetic field makes the reversal magnetic field (coercive force) in which the spontaneous magnetization of the free layer of the magnetoresistive element 7 is reversed asymmetric, causing the magnetoresistive element 7 to have an offset magnetic field. The presence of the offset magnetic field in the magnetoresistive element 7 is not preferable in that the write current Iw is increased and the operation margin of the memory cell 2 is decreased. The fact that the laminated ferrimagnetic structure 7-1 does not have a magnetic moment effectively prevents the generation of an offset magnetic field in the magnetoresistive element 7.

  FIG. 75B shows a structure of a preferred laminated ferri structure 7-1. In the preferred laminated ferri structure 7-1, the first magnetic layer 7-2 includes the NiFe layer 7-2a and the CoFe layer 7-2b, and the second magnetic layer 7-4 includes the CoFe layer 7-4a. NiFe layer 7-4b. The nonmagnetic spacer layer 7-3 is formed of a Ru layer. A CoFe layer 7-2b is formed on the NiFe layer 7-2a, and a Ru layer 7-3 is formed on the CoFe layer 7-2b. A CoFe layer 7-4a is formed on the Ru layer 7-3, and a NiFe layer 7-4b is formed on the CoFe layer 7-4a.

  Such a structure of the laminated ferri structure 7-1 has an advantage that the characteristics of the laminated ferri structure 7-1 can be easily adjusted, and thus the design is easy. The magnitude of the magnetization of the laminated ferri structure 7-1 can be determined independently by the thicknesses of the NiFe layer 7-2a and the NiFe layer 7-4b. Further, the coupling constant between the first magnetic layer 7-2 and the second magnetic layer 7-4 can be determined independently by the thickness of the Ru layer 7-3. Thus, the characteristics of the laminated ferrimagnetic structure 7-1 can be freely determined by the thicknesses of the NiFe layer 7-2a, the NiFe layer 7-4b, and the Ru layer 7-3.

FIG. 76 is a diagram illustrating the function of a magnetic structure including a magnetoresistive element and a laminated ferrimagnetic structure. Synthetic antiferromagnet structure 7-1 is magnetized by a magnetic field _{H I} generated by the write current Iw. Here, H _I > Ht. This magnetization produces a magnetic field _{H J.} Thereby, the location of the magneto-resistance element 7, the effective magnetic field H becomes the _{H =} H I + _{H J.} That is, greater than the magnetic field _{H I} according to only the write current Iw. Therefore, even when the same current flows in the same memory cell area, the magnetic field during the write operation can be increased. As a result, it is possible to increase the operation margin without increasing the chip area.

  The description of FIGS. 73 to 76 can be similarly applied to other memory cells and memory cell arrays in this specification.

(Second Embodiment)
A second embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

  A configuration of the magnetic memory cell and the magnetic random access memory according to the second embodiment of the present invention will be described. FIG. 7 is a diagram showing a configuration of a second embodiment of a magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. FIG. 7 shows a configuration in which the circuit example of the MRAM shown in FIG. 1 is hierarchized. The MRAM according to the present embodiment includes cell arrays 41-0 to 41-3, a cell array selector 17, a Y-side current source circuit 12, a read current load circuit 13, and a sense amplifier 15.

The cell arrays 41-0 to 41-3 include a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4 (including a reference first bit line 4r), and a plurality of second bit lines 5 (reference second bits). An X selector 8, a Y selector 11 ′, a Y side current termination circuit 14, and a Y side power supply circuit 19. Each configuration is the same as in the first embodiment except that the Y selector 11 ′ can select not only the first bit line 4 but also the reference first bit line 4 r, and the description thereof will be omitted. To do.
In FIG. 7, four cell arrays 41 are shown, but the present invention is not limited to this number.

  The cell array selector 17 selects the selected cell array 41-i by the selector transistors 17-1 and 17-2 based on a cell array selection signal MWSi (i = 0 to 3: an integer of the cell array 41) for selecting the cell array 41. select. The selected cell array 41-i, the Y-side current source circuit 12, the read current load circuit 13, and the sense amplifier 15 are connected by a first main bit line 18-1 and a second main bit line 18-2, The same operation as in the first embodiment is performed.

  Since the Y-side current source circuit 12, the read current load circuit 13, and the sense amplifier 15 are the same as those in the first embodiment, their descriptions are omitted.

  Next, the operation of the second embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. However, YSWj (j = 0 to m: m + 1 is the number of first bit lines 4) is a signal for selecting the j-th first bit line 4, WA is a write active signal, and RA is a read active signal. YSWR is a signal for selecting a reference cell during a read operation and a write operation, and YSWRW is a signal for selecting a reference cell 2r during a write operation. SR is a signal for activating the reference cell 2r when writing to the reference cell 2r. The same applies throughout this specification.

In the MRAM shown in FIG. 7, data is read from the memory cell 2 as follows.
(1) Step S21
The cell array selector 17 selects the corresponding selector transistors 17-1 and 17-2 based on the cell array selection signal MWSi for selecting any one of the cell arrays 41-i (where i = 0 to n: n + 1 is the number of cell arrays). Is turned on, and the selected cell array 41-i is selected.
At this time, the selected cell array 41-i, the read current load circuit 13, and the sense amplifier 15 are connected by the first main bit line 18-1 and the second main bit line 18-2.
(2) Step S22
Thereafter, the operations in steps S01 to S03 are performed.
However, in step S02, the Y selector 11 ′ selects the reference first bit line 4r as necessary in addition to the selected first bit line 4s.

  With the above read operation, the data of the desired selected cell 2s in the desired selected cell array 41-i can be read.

  Data is written to the memory cell 2 as follows.

(1) Step S31
The cell array selector 17 turns on the corresponding selector transistors 17-1 and 17-2 and selects the selected cell array 41-i based on the cell array selection signal MWSi for selecting any one of the cell arrays 41-i.
At this time, the selected cell array 41-i and the Y-side current source circuit 12 are connected by the first main bit line 18-1 and the second main bit line 18-2.
(2) Step S32
Thereafter, the operations in steps S11 to S13 are performed. The Y selector 11 ′ selects the reference first bit line 4r as necessary in addition to the selected first bit line 4s.

  Through the above write operation, data can be written to the desired selected cell 2s in the desired selected cell array 41-i.

  When writing to the reference cell 2r, the reference first bit line 4r is selected in the Y selector 11 'and the reference second bit line 5r is selected in the Y-side current termination circuit 14 together with the input of the reference active signal SR.

  According to the present invention, the same effects as those of the first embodiment can be obtained. Further, the MRAM can be made compact by hierarchizing the cell array and sharing some circuits.

(Third embodiment)
A third embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

  First, the configuration of the third embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 8 is a diagram showing a configuration of a third embodiment of a magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. The MRAM according to the present embodiment includes a memory cell array 10, a plurality of write word lines 3W, a plurality of read word lines 3R, a plurality of first bit lines 4, a plurality of second bit lines 5, a write X selector 8-1, and a read. An X selector 8-2, a write Y selector 11-1, a read Y selector 11-2, a Y side power supply circuit 19, a Y side current source circuit 12, a Y side current termination circuit 14 and a current sense amplifier 15a are provided.

In the memory cell array 10, memory cells 20 are arranged in a matrix. Here, the memory cell 20 includes a first MOS transistor 6 and a magnetoresistive element 7. Note that the reference memory cell 20 is referred to as a reference cell 20r. In the reference cell 20r, “0” is written, and usually no write operation is performed.
The first MOS transistor 6 as the first transistor has a gate (first gate) as the write word line 3W, a source (first terminal) as the first bit line 4, and a drain (second terminal) as the magnetoresistive element 7. It is connected to one end side (fourth terminal) and the second bit line 5. Note that the memory cell 20 is different from the memory cell 2 of the first embodiment in that it does not have the second MOS transistor 16.
The first MOS transistor 6 is used for flowing a current in the vicinity of the magnetoresistive element 7 by connecting the first bit line 4 and the second bit line 5 during a write operation.
The magnetoresistive element 7 has one end side (fourth terminal) connected to the drain of the first MOS transistor 6 and the other end side (third terminal) connected to the read word line 3R. It has spontaneous magnetization whose magnetization direction is reversed according to stored data.

The first bit line 4 is provided so as to extend in the Y-axis direction (bit line direction) as the first direction, and is connected to the write Y selector 11-1. The reference first bit line 4 is referred to as a reference first bit line 4r.
The second bit line 5 is paired with the first bit line 4 and extends in the Y-axis direction. One end is connected to the Y-side current termination circuit 14 and the other end is connected to the read Y selector 11-2. ing. The reference second bit line 5 is referred to as a reference second bit line 5r.
The write word line 3W is provided so as to extend in the X-axis direction (word line direction) as a second direction substantially perpendicular to the Y-axis direction, and is connected to the write X selector 8-1.
The read word line 3R is paired with the write word line 3W, is provided to extend in the X-axis direction (word line direction), and is connected to the read X selector 8-2.
Each memory cell 20 corresponds to each of the positions where the plurality of sets of the first bit line and the second bit line intersect with the plurality of sets of the write word line 3W and the read word line 3R. Is provided.

The write X selector 8-1 selects one write word line 3W as the selected write word line 3Ws from the plurality of write word lines 3W during the data write operation.
The read X selector 8-2 selects one read word line 3R as a selected read word line 3Rs from a plurality of read word lines 3R and fixes it to GND (ground) during a data write operation. In the data read operation, one read word line 3R is selected as the selected read word line 3Rs from the plurality of read word lines 3R, and is fixed to a predetermined read voltage Vread (for example, 0.5 V).
The write Y selector 11-1 selects one first bit line 4 from the plurality of first bit lines 4 as the selected first bit line 4s during the write operation.
The read Y selector 11-2 selects one second bit line 5 from the plurality of second bit lines 5 as the selected second bit line 5s during the data read operation.
Here, the memory cell 2 selected by the selected write / read word line 3Ws / 3Rs and the selected first / second bit line 4s / 5s is referred to as a selected cell 2s.

The Y-side current source circuit 12 is a current source that supplies or draws a predetermined current to the selected first bit line 4s during a data write operation. A current selector unit 12b that determines the direction of current and a constant current source 12a that supplies a constant current are provided.
The Y-side current termination circuit 14 selects one second bit line 5 that forms a pair with the selected first bit line 4s as the selected second bit line 5s from the plurality of second bit lines 5 during the data write operation. .
The Y-side power supply circuit 19 supplies a predetermined voltage to the Y-side current termination circuit 14 during a data write operation.
Here, the predetermined current from the Y-side current source circuit 12 flows into the write Y selector 11-1 through the path of the selected first bit line 4s-selected cell 2s-selected second bit line 5s in accordance with the data to be written. Flows in the direction or the direction flowing out from the write Y selector 11-1.

  The current sense amplifier 15a reads data from the selected cell 2s based on the difference between the current flowing through the reference second bit line 5r connected to the reference cell 20r and the current flowing through the selected second bit line 5s connected to the selected cell 2s. Output the data.

FIG. 9 is a view of the memory cell array of the MRAM shown in FIG. 8 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, 2 × 2 memory cells 20 in the memory cell array 1 are shown as representatives.
In the first MOS transistor 6 of the memory cell 20, the source 6 a (first terminal) is connected to the first bit line 4 via the contact wiring 28. The gate 6b (first gate terminal) uses the write word line 3-1 branched from the write word line 3W in the Y-axis direction. The drain 6 c (second terminal) is connected to the second bit line 5 through the contact wiring 27, the lead-out wiring layer 29, and the contact wiring 37.

  The magnetoresistive element 7 is provided on the lead wiring layer 29. The direction of spontaneous magnetization is reversed by the current flowing through the lead wiring layer 29. Here, since the current flowing through the lead wiring layer 29 flows in the X-axis direction, the direction of the magnetic field felt by the magnetoresistive element 7 is the Y-axis direction. Therefore, it is provided in a shape that facilitates magnetization in the Y-axis direction. For example, an ellipse having a long axis parallel to the Y-axis direction or a shape similar to an ellipse. One end (fourth terminal) of the magnetoresistive element 7 is connected to the lead-out wiring layer 29, and the other end (third terminal) is connected to the read word line 3R.

FIG. 10 shows the structure of the memory cell 20 and is a diagram showing a BB ′ cross section in FIG.
The first MOS transistor 6 is formed on the surface portion of the semiconductor substrate. A source 6a as a first diffusion layer provided in the semiconductor substrate is connected to the first bit line 4 via a contact wiring 28 extending in the Z-axis direction. The drain 6c as the second diffusion layer is connected to one end of the lead-out wiring layer 29 via a contact wiring 27 extending in the Z-axis direction. The gate 6b as the first gate uses a write word line 3-1 branched from the write word line 3W. However, the drain 6c is provided inside the memory cell 20 relative to the source 6a. The other end of the lead wiring layer 29 is connected to a contact wiring 37 extending from the second bit line 5 in the Z-axis direction. The lead wiring layer is provided in parallel with the substrate.
The magnetoresistive element 7 is connected to the lead wiring layer 29 on one end side. The other end is connected to the read word line 3R via the contact wiring 26.

  Next, the operation of the magnetic memory cell and magnetic random access memory according to the third embodiment of the present invention will be described.

Reading data from the memory cell 2 is performed as follows.
(1) Step S41
The read X selector 8-2 selects the selected read word line 3Rs from the plurality of read word lines 3R in response to the input of the row address.
(2) Step S42
The read Y selector 11-2 selects the selected second bit line 5s from the plurality of second bit lines 5 in response to the input of the column address. Accordingly, the path of the read X selector 8-2-selected read word line 3Rs-selected cell 20s (the magnetoresistive element 7) -selected second bit line 5s-read Y selector 11-2-current sense amplifier 15a includes: Due to the voltage difference between the read X selector 8-2 and the current sense amplifier 15a, a current Is reflecting the data of the selected cell 20s flows. On the other hand, the data “0” of the reference cell 20r is in the path of the read X selector 8-2-selected read word line 3Rs−reference cell 20r (the magnetoresistive element 7) −reference second bit line 5r−current sense amplifier 15a. The current Ir reflecting the current flows.
(3) Step S43
Based on the difference between the current Is and the current Ir, the current sense amplifier 15a determines that the read data is “0” if they are almost the same, and “1” if they are different (example: smaller), and the result Is output.

  With the above read operation, data of the selected cell 2s can be read.

  Data is written to the memory cell 2 as follows.

(1) Step S51
The write X selector 8-1 selects the selected write word line 3Ws from the plurality of write word lines 3W in response to the input of the row address. The first MOS transistor 6 of each memory cell 2 is turned on.
(2) Step S52
The write Y selector 11-1 selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. Further, the Y-side current termination circuit 14 selects the selected second bit line 5 s from the plurality of second bit lines 5 by the write active signal WA. A pair of the selected first bit line 4s and the selected second bit line 5s is selected. The read word line 3R is fixed to GND.
At this time, the Y-side power supply circuit 19 applies a predetermined voltage Vterm to the selected second bit line 5s. Based on the write active signal WA and the data signal Data, the Y-side current source circuit 12 has a current Iw (0) (in the case of “0”: Y-side current source circuit 12 having a predetermined magnitude corresponding to the data signal Data. Current Iw (1) (in the case of “1”, the direction of flowing out from the Y-side current source circuit 12) is supplied to the selected first bit line 4s−selected cell 2s.
The current Iw (0) or the current Iw (1) is obtained by selecting the path of the selected second bit line 5s (-the lead wiring layer 29 of the selected cell 2s) -the first MOS transistor 6 of the selected cell 2s and the selected first bit line 4s. Flow in forward or reverse direction.
(3) Step S53
In the selected cell 2s, when the current Iw (0) (+ X direction) or the current Iw (1) (−X direction) flows on the lead-out wiring layer 29 in contact with the magnetoresistive element 7, the −Y direction or + Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal Data is stored.

  With the above write operation, data can be written to the selected cell 2s.

According to this embodiment, the same effects as those of the first embodiment and the second embodiment can be obtained.
Further, since the second MOS transistor of the memory cell is not used, the MRAM can be made compact by the circuit area.

(Fourth embodiment)
A fourth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

  The configuration of the magnetic memory cell and the magnetic random access memory according to the fourth embodiment of the present invention will be described. FIG. 11 is a diagram showing a configuration of a fourth embodiment of a magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. FIG. 11 shows a configuration in which the circuit example of the MRAM shown in FIG. 8 is hierarchized. The MRAM according to the present embodiment includes cell arrays 51-0 to 51-3, a cell array selector 17, a Y-side current source circuit 12, and a current sense amplifier 15a.

The cell arrays 51-0 to 51-3 include a memory cell array 10, a plurality of write word lines 3W, a plurality of read word lines 3R, a plurality of first bit lines 4 (including a reference first bit line 4r), and a plurality of second cells. A bit line 5 (including a reference second bit line 5r), a write X selector 8-1, a read X selector 8-2, a Y selector 11 '', a Y side current termination circuit 14, and a Y side power supply circuit 19 are provided. In each configuration, except that the Y selector 11 ″ combines the write Y selector 11-1 and the read Y selector 11-2, and the reference first bit line 4r and the reference second bit line 5r can be selected. Since it is the same as that of the third embodiment, its description is omitted.
In FIG. 11, four cell arrays 51 are shown, but the present invention is not limited to this number.

  The cell array selector 17 selects the selected cell array 51-i by the selector transistors 17-1 and 17-2 based on a cell array selection signal MWSi (i = 0 to 3: an integer of the cell array 51) for selecting the cell array 51. select. The selected cell array 51-i, the Y-side current source circuit 12, and the current sense amplifier 15a are connected by the first main bit line 18-1 and the second main bit line 18-2, and are the same as in the third embodiment. The same operation is performed.

  Since the Y-side current source circuit 12 and the sense amplifier 15a are the same as those in the third embodiment, description thereof is omitted.

  Next, the operation of the magnetic memory cell and magnetic random access memory according to the fourth embodiment of the present invention will be described. However, YSWj (j = 0 to m: m + 1 is the number of first bit lines 4) is a signal for selecting the j-th first bit line 4, WA is a write active signal, and RA is a read active signal. YSWR is a signal for selecting a reference cell during a read operation and a write operation, and YSWRW is a signal for selecting a reference cell during a write operation. SR is a signal for activating the reference cell 2r when writing to the reference cell 2r. The same applies throughout this specification.

In the MRAM shown in FIG. 11, data is read from the memory cell 2 as follows.
(1) Step S61
The cell array selector 17 selects the corresponding selector transistors 17-1 and 17-2 based on the cell array selection signal MWSi for selecting any one of the cell arrays 51-i (i = 0 to n: n + 1 is the number of cell arrays). Is turned on, and the selected cell array 51-i is selected.
At this time, the selected cell array 51-i and the current sense amplifier 15 are connected by the first main bit line 18-1 and the second main bit line 18-2.
(2) Step S62
Thereafter, the operations of Steps S41 to S43 are performed.
However, the read Y selector 11-2 in steps S41 to S43 is replaced with a Y selector 11 ''. In step S42, the Y selector 11 '' selects the reference second bit line 5r.

  With the above read operation, the data of the desired selected cell 2s in the desired selected cell array 51-i can be read.

  Data is written to the memory cell 2 as follows.

(1) Step S71
The cell array selector 17 turns on the corresponding selector transistors 17-1 and 17-2 to select the selected cell array 51-i based on the cell array selection signal MWSi for selecting any one of the cell arrays 51-i.
At this time, the selected cell array 51-i and the Y-side current source circuit 12 are connected by the first main bit line 18-1 and the second main bit line 18-2.
(2) Step S72
Thereafter, the operations in steps S51 to S53 are performed.
However, the write Y selector 11-1 in steps S51 to S53 is replaced with a Y selector 11 ''. In step S52, the Y selector 11 '' selects the reference first bit line 4r.

  With the above write operation, data can be written to the desired selected cell 2s in the desired selected cell array 51-i.

  When writing to the reference cell 2r, the reference first bit line 4r is selected by the Y selector 11 ″ and the reference second bit line 5r is selected by the Y-side current termination circuit 14 together with the input of the reference active signal SR. .

According to this embodiment, the same effect as that of the second embodiment can be obtained.
Further, since the second MOS transistor of the memory cell is not used, the MRAM can be made compact by the circuit area.

(Fifth embodiment)
A fifth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

First, the configuration of the fifth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 1 is a diagram showing a configuration of a fifth embodiment of a magnetic random access memory (MRAM) including magnetic memory cells of the present invention. The MRAM according to the present embodiment includes a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4, a plurality of second bit lines 5, an X selector 8, a Y selector 11, a Y-side current source circuit 12, Y A side power supply circuit 19, a read current load circuit 13, a Y side current termination circuit 14, and a sense amplifier 15 are provided.
Since the configuration of FIG. 1 is the same as that of the first embodiment, description thereof is omitted.

FIG. 12 is a view of the memory cell array of the MRAM shown in FIG. 1 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, 2 × 2 memory cells 2a in the memory cell array 1 (here, shown as memory cells 2a because the structure is different from the case of FIG. 2) are shown as representatives.
The memory cell 2a of the present embodiment has a first bit line 4 and a second bit line 5 sandwiched between the branched word line 3-1 (gate 6b) and word line 3-2 (gate 16b). Is different from FIG. 2 of the first embodiment.
However, the second embodiment is the same as the first embodiment except that the arrangement of the first MOS transistor 6 and the second MOS transistor 16 is changed and the arrangement of the first bit line 4 and the second bit line 5 is changed accordingly. Therefore, the description is omitted.

  With such an arrangement, the margin of the shape of the lead-out wiring layer 29 is increased. Thereby, the shape of the lead wiring layer 29 can be made long and wide, and the magnetoresistive element 7 formed thereon can be enlarged.

FIG. 13 shows the structure of the memory cell 2a, and shows a CC ′ cross section in FIG.
The source 6a of the first MOS transistor 6 is connected to the first bit line 4 via a contact wiring 28 extending in the Z-axis direction. The drain 6c is connected to one end of the lead-out wiring layer 29 through a contact wiring 27 extending in the Z-axis direction. The gate 6b uses the word line 3-1 branched from the word line 3. However, the source 6a is provided inside the memory cell 2a with respect to the drain 6c.
Similarly, the source 16a of the second MOS transistor 16 is connected to the second bit line 5 via a contact wiring 38 extending in the Z-axis direction. The drain 16c is connected to the other end of the lead-out wiring layer 29 via a contact wiring 37 extending in the Z-axis direction. The gate 16b uses the word line 3-2 branched from the word line 3. However, the source 16a is provided inside the memory cell 2a with respect to the drain 16c.
The lead wiring layer 29 is provided so as to cover the first bit line 4 and the second bit line 5 passing through the memory cell 2a.
The magnetoresistive element 7 is connected to the lead wiring layer 29 on one end side. The other end side is connected to a ground (GND) line 24 via a contact wiring 26.

  Next, since the operation of the fifth embodiment of the magnetic memory cell and magnetic random access memory of the present invention is the same as that of the first embodiment, description thereof will be omitted.

  The first bit line 4 and the second bit line 5 in the present embodiment are closer than both bit lines in the first embodiment. However, both the bit lines of the present embodiment are farther from the magnetoresistive element 7 than the lead wiring layer 29 in the memory cell 2a. Therefore, the magnetic field reaching the magnetoresistive element 7 is small even if the same current as that of the lead-out wiring layer 29 flows through both bit lines. Moreover, in the case of the memory cell 2 a of the present invention, the magnetic fields from the first bit line 4 and the second bit line 5 are applied in a direction orthogonal to the anisotropy of the magnetoresistive element 7. These are shown in FIG.

FIG. 14 is a graph showing the magnetic field that may be applied to the selected cell (FIG. 14A) and the non-selected cell (FIG. 14B). A magnetic field in the X-axis direction is applied to the non-selected cell in FIG. 14B by the magnetic field H _X1 from the first bit line 4 and the second bit line 5. However, since the size is sufficiently small, there is no influence. If the selected cell in FIG. 14 (a), and has a magnetic field _{H X1} from the first bit line 4 and the second bit line 5, by lead wiring layer 29 and the synthetic magnetic field _{H 1} of the magnetic field _{H Y1.} That is, as compared with the case of the first embodiment in FIG. 6, it is slightly shifted from the Hy axis due to the influence of the magnetic field from the first bit line 4 and the second bit line 5 which are closer. However, looking at the relationship with the asteroid curve, it can be seen that the spontaneous magnetization can be reversed with a smaller magnetic field. In other words, in the selected cell 2a, it can be seen that the magnetic field H _X1 from both bit lines works in a direction that assists magnetization reversal.

Also in this embodiment, the same effect as that of the first embodiment can be obtained.
In addition, since the shape of the lead wiring layer 29 and the margin of the magnetoresistive element 7 are increased and the design rule can be relaxed, the yield can be improved.

  The magnetoresistive element 7 can be enlarged, and the magnetic field in the selected cell can be reduced with lower write currents Iw (0) and Iw (1) due to the magnetic field effect from the first bit line 4 and the second bit line 5. It becomes possible to reverse the spontaneous magnetization of the resistance element.

(Sixth embodiment)
A sixth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

First, the configuration of the sixth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 8 is a diagram showing a configuration of a sixth embodiment of a magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. The MRAM according to the present embodiment includes a memory cell array 10, a plurality of write word lines 3W, a plurality of read word lines 3R, a plurality of first bit lines 4, a plurality of second bit lines 5, a write X selector 8-1, and a read. An X selector 8-2, a write Y selector 11-1, a read Y selector 11-2, a Y side power supply circuit 19, a Y side current source circuit 12, a Y side current termination circuit 14, and a current sense amplifier 15a are provided.
Since the configuration of FIG. 8 is the same as that of the third embodiment, the description thereof is omitted.

FIG. 15 is a view of the memory cell array of the MRAM shown in FIG. 8 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, a 2 × 2 memory cell 20a in the memory cell array 1 (in this case, the structure is different from the case of FIG. 9 and is displayed as a memory cell 20a) is shown as a representative. Also, the read word line 3R shown in FIG. 9 is provided on the magnetoresistive element 7 as in FIG. 9, but is omitted in this figure from the viewpoint of easy viewing.
The memory cell 20a of the present embodiment is different from that of the third embodiment in that the first bit line 4 is provided inside the memory cell 20a with respect to the branched write word line 3-1 (gate 6b). This is different from FIG.
However, since the arrangement of the first MOS transistor 6 and the accompanying change in the arrangement of the first bit line 4 are the same as in the third embodiment, the description thereof is omitted.

  With such an arrangement, the margin of the shape of the lead-out wiring layer 29 is increased. Thereby, the shape of the lead wiring layer 29 can be made long and wide, and the magnetoresistive element 7 formed thereon can be enlarged.

FIG. 16 shows the structure of the memory cell 20a, and shows a DD ′ section in FIG.
The source 6a of the first MOS transistor 6 is connected to the first bit line 4 via a contact wiring 28 extending in the Z-axis direction. The drain 6c is connected to one end of the lead-out wiring layer 29 through a contact wiring 27 extending in the Z-axis direction. The gate 6b uses a write word line 3-1 branched from the write word line 3W. However, the source 6a is provided inside the memory cell 20a rather than the drain 6c.
The lead wiring layer 29 is provided so as to cover the first bit line 4 passing through the memory cell 20a.
The magnetoresistive element 7 is connected to the lead wiring layer 29 on one end side. The other end is connected to the read word line 3R via the contact wiring 26.

  Next, the operation of the sixth embodiment of the magnetic memory cell and magnetic random access memory according to the present invention is the same as the operation of the third embodiment, and a description thereof will be omitted.

  According to this embodiment, the same effects as those of the third and fifth embodiments can be obtained.

(Seventh embodiment)
A seventh embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

First, the configuration of the seventh embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 1 is a diagram showing a configuration of a seventh embodiment of a magnetic random access memory (MRAM) including a magnetic memory cell of the present invention. The MRAM according to the present embodiment includes a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4, a plurality of second bit lines 5, an X selector 8, a Y selector 11, a Y-side current source circuit 12, Y A side power supply circuit 19, a read current load circuit 13, a Y side current termination circuit 14, and a sense amplifier 15 are provided.
Since the configuration of FIG. 1 is the same as that of the first embodiment, description thereof is omitted.

FIG. 17 is a view of the memory cell array of the MRAM shown in FIG. 1 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, a 2 × 2 memory cell 2b in the memory cell array 1 (here, shown as a memory cell 2b because the structure is different from that in FIG. 2) is shown as a representative.
The magnetoresistive element 7 is provided on the lead wiring layer 29. The direction of spontaneous magnetization is reversed by the current flowing through the lead wiring layer 29. Since the current flowing through the lead wiring layer 29 flows in the X-axis direction, the direction of the magnetic field felt by the magnetoresistive element 7 is the Y-axis direction. In the present embodiment, the magnetization anisotropy of the magnetoresistive element 7 is inclined by a predetermined angle θ with respect to the Y axis. In the example of FIG. 17, the shape of the magnetoresistive element 7 is made anisotropic, and the magnetoresistive element 7 is inclined 45 ° with respect to the Y axis (θ = 45 °). Thereby, the write current can be set small, and the current consumption can be reduced. This is illustrated in FIG.

FIG. 18 is a graph showing a magnetic field generated by a write current and an asteroid curve indicating a magnetic field necessary for the magnetoresistive element 7 to be magnetized. In the case of the memory cell 2b of FIG. 17, the magnetic field due to the write current is applied in a direction shifted by 45 ° from the anisotropy of the magnetic material of the magnetoresistive element 7. From the comparison of the asteroid curve in FIG. 18 and the magnetic field H ₀ generated by the write current, it can be seen that the magnetic field H ₀ can be made smaller than in the case of FIG. That is, the write current can be set small, and the current consumption can be reduced.
Even if the predetermined angle for tilting the magnetization anisotropy of the magnetoresistive element 7 with respect to the Y axis is slightly tilted with respect to the Y axis, it is effective. More preferably, it is 10 ° -80 °. More preferably, it is 30 to 60 degrees. The same effect can be obtained by tilting to the opposite side of the Y axis in the same manner.

  The other configuration in FIG. 17 is the same as that of the first embodiment, and thus the description thereof is omitted.

  Next, since the operation of the seventh embodiment of the magnetic memory cell and magnetic random access memory of the present invention is the same as that of the first embodiment, the description thereof is omitted.

According to the present embodiment, the same effect as that of the first embodiment can be obtained.
In addition, by tilting the anisotropy of the magnetic material of the magnetoresistive element 7, the write current can be set small, and the current consumption can be reduced, so that the transistor size of the memory cell 2b can be reduced. Therefore, the chip size can be reduced and the cost can be reduced.

In the above embodiment, the magnetoresistive element 7 is inclined. In addition, by making the magnetoresistive element 7 asymmetric with respect to the direction of the easy axis of magnetization, the same effect as in the above embodiment can be obtained. This is shown in FIG.
FIG. 77 is a diagram showing a configuration showing another application example of the seventh embodiment of the magnetic memory cell and magnetic random access memory of the present invention. In this figure, only the magnetoresistive element 7 portion of the lead wiring layer 29 is shown. Compared to the case of FIG. 17, in this case, the magnetoresistive element 7 is asymmetrical in the easy axis direction (direction Hx in the figure).

  FIG. 78 is a graph showing the asteroid characteristics in the case of FIG. The vertical axis represents the magnetic field (Hy) in the Y direction, and the horizontal axis represents the magnetic field (Hx) in the X direction. As described above, the asteroid characteristic of the magnetic material of the asymmetrical magnetoresistive element 7 is asymmetric with respect to two adjacent quadrants (example: first quadrant and second quadrant). In this case, when the second quadrant and the fourth quadrant are used for the write operation, the write current Iw can be reduced due to asymmetry as compared with the case where the first quadrant and the third quadrant are used or in the normal case. . As a result, the operation margin can be increased without increasing the chip area.

  The description of FIGS. 77 to 78 can be similarly applied to other memory cells and memory cell arrays in this specification.

(Eighth embodiment)
An eighth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

First, the configuration of the eighth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 8 is a diagram showing a configuration of an eighth embodiment of a magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. The MRAM according to the present embodiment includes a memory cell array 10, a plurality of write word lines 3W, a plurality of read word lines 3R, a plurality of first bit lines 4, a plurality of second bit lines 5, a write X selector 8-1, and a read. An X selector 8-2, a write Y selector 11-1, a read Y selector 11-2, a Y side current source circuit 12, a Y side power supply circuit 19, a Y side current termination circuit 14, and a current sense amplifier 15a are provided.
Since the configuration of FIG. 8 is the same as that of the third embodiment, the description thereof is omitted.

FIG. 19 is a view of the memory cell array of the MRAM shown in FIG. 8 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, a 2 × 2 memory cell 20b in the memory cell array 10 (here, shown as a memory cell 20b because the structure is different from that in FIG. 9) is shown as a representative. Also, the read word line 3R shown in FIG. 9 is provided on the magnetoresistive element 7 as in FIG. 9, but is omitted in this figure from the viewpoint of easy viewing.
Since the magnetoresistive element 7 is the same as that of the seventh embodiment, the description thereof is omitted.
Further, since the other configuration in FIG. 19 is the same as that of the third embodiment, the description thereof is omitted.

  Next, since the operation of the eighth embodiment of the magnetic memory cell and magnetic random access memory of the present invention is the same as that of the third embodiment, the description thereof is omitted.

  According to the present embodiment, the same effects as those of the third and seventh embodiments can be obtained.

(Ninth embodiment)
A ninth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

  First, the configuration of the ninth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 20 is a diagram showing a configuration of a ninth embodiment of a magnetic random access memory (MRAM) including a magnetic memory cell according to the present invention. The MRAM of this embodiment includes a memory cell array 1, a plurality of word lines 3 (a set of two word lines 3a and 3b), a plurality of first bit lines 4, a plurality of second bit lines 5, A selector 8, a Y selector 11, a Y-side current source circuit 12, a Y-side power supply circuit 19, a read current load circuit 13, a Y-side current termination circuit 14, and a sense amplifier 15 are provided.

In the memory cell array 1, two memory cells 2c-1 and 2c-2 are paired and arranged in a matrix. Here, each of the two memory cells 2c-1 and 2c-2 includes a first MOS transistor 6, a second MOS transistor 16, and a magnetoresistive element 7. The reference memory cell 2 is referred to as reference cells 2r-1 and 2r-2.
In the memory cell 2c-1, the gates of the first MOS transistor 6 and the second MOS transistor 16 are connected to the word line 3a. In the memory cell 2c-2, the gates of the first MOS transistor 6 and the second MOS transistor 16 are connected to the word line 3b.
The memory cell 2c-1 and the memory cell 2c-2 are connected to the first bit line 4 through a common wiring (described later) by connecting the sources of the first MOS transistors 6 respectively. In addition, the memory cell 2c-1 and the memory cell 2c-2 are connected to the second bit line 5 through a common wiring (described later) by connecting the sources of the second MOS transistors 16.
As in the configuration described above, the memory cell 2c-1 and the memory cell 2c-2 share the sources of the first MOS transistor 6 and the second MOS transistor 16, thereby making the circuit of the memory cell 2 (2c-1 and 2c-2). The area is reduced.

However, the word line 3a and the word line 3b are the same as the word line 3 of the first embodiment except that they are structurally combined. In addition, the memory cell 2c-1 and the memory cell 2c-2 are the first MOS transistor 6 and the second MOS transistor 16 of the first embodiment except that the sources of the first MOS transistor 6 and the second MOS transistor 16 are shared. It is the same. Therefore, those descriptions are omitted.
Furthermore, since the other configuration of FIG. 20 is the same as that of the first embodiment, the description thereof is omitted.

FIG. 21 is a view of the memory cell array of the MRAM shown in FIG. 20 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, 4 × 4 (2 sets × 2 sets) of memory cells 2c (2c-1 and 2c-2) in the memory cell array 1 are shown as representatives.
In the first MOS transistor 6 of the memory cell 2 c-1, the source 6 a (first terminal) is connected to the first bit line 4 via the contact wiring 28. The gate 6b (first gate terminal) uses the word line 3a. The drain 6c (second terminal) is connected to the drain 16c (sixth terminal) of the second MOS transistor 16 through the contact wiring 27, the lead-out wiring layer 29, and the contact wiring 37. In the second MOS transistor 16, the gate 16b (second gate terminal) uses the word line 3a. The source 16 a (fifth terminal) is connected to the second bit line 5 through the contact wiring 38.
On the other hand, in the first MOS transistor 6 of the memory cell 2 c-2, the source 6 a (first terminal) is connected to the first bit line 4 through the contact wiring 28. The gate 6b (first gate terminal) uses the word line 3b. The drain 6c (second terminal) is connected to the drain 16c (sixth terminal) of the second MOS transistor 16 through the contact wiring 27, the lead-out wiring layer 29, and the contact wiring 37. In the second MOS transistor 16, the gate 16b (second gate terminal) uses the word line 3b. The source 16 a (fifth terminal) is connected to the second bit line 5 through the contact wiring 38.

Here, the diffusion layer (sources (6a and 16a) and drains (6c and 16c) of each MOS transistor) is at a predetermined angle φ (in FIG. 21) with respect to the first bit line 4 and the second bit line 5. , Φ = 45 °). With such a layout, it is possible to increase the density at which the diffusion layers are arranged, and to reduce the size of the memory cell 2c. In the present embodiment, the wirings (28 and 38) for connecting the first bit line 4 and the second bit line 5 and the memory cells 2c are shared. This common wiring can also reduce the size of the memory cell 2c.
The predetermined angle φ is preferably 30 ° to 60 ° from the viewpoint of making the memory cell 2c compact. More preferably, the angle is 40 ° to 50 °. It may be tilted to either side with respect to both bit lines (4 and 5).

In this layout, the first bit line 4 and the second bit line 5 are arranged below the magnetoresistive element 7. Therefore, the magnetic field from both bit lines affects the magnetoresistive element 7. This is shown in FIG.
FIG. 22 is a graph showing a magnetic field that may be applied to the selected cell. FIG. 22B shows the magnetic field H _X1 from the first bit line 4 and the second bit line 5 that may be applied to the selected cell 2c. The magnitude of the magnetic field H _X1 is sufficiently small and does not affect the spontaneous magnetization of the magnetoresistive element 7. However, due to the magnetic field, as shown in FIG. 22A, the selected cell 2 c has a magnetic field H _X1 from the first bit line 4 and the second bit line 5 and a magnetic field H _Y1 from the extraction wiring layer 29. synthetic magnetic field H ₁ becomes can take. In this case, as shown in FIG. 22C, when the direction of the magnetoresistive element 7 is shifted by 45 ° from the Y axis as in the seventh embodiment, the magnetic field element H _X1 is shifted in advance by an angle Δ. Design. If the direction of the magnetic anisotropy of the magnetoresistive element 7 is slightly shifted (Δ), the operation margin is not reduced, and the magnitude of the magnetic field for writing can be increased (H ₁ ). The magnetic field from the current can only work in a good direction.

  Since other configurations are the same as those of the seventh embodiment, the description thereof is omitted.

  Next, with regard to the operation of the ninth embodiment of the magnetic memory cell and magnetic random access memory of the present invention, the wiring (28 and 28) connecting the first bit line 4 and the second bit line 5 to each memory cell 2c. 38), the diffusion layers are φ-inclined, and the first bit line 4 and the second bit line 5 pass under the lead-out wiring layer 29. Description is omitted.

According to this embodiment, the same effect as that of the seventh embodiment can be obtained.
Further, the size of the memory cell 2c can be reduced by increasing the density at which the diffusion layers of the transistors are arranged and by making the wirings connecting the bit lines and the memory cells 2c common. Therefore, the chip size can be reduced and the cost can be reduced.

(Tenth embodiment)
A tenth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  First, the configuration of the tenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 23 is a diagram showing a configuration of a tenth embodiment of a magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. The MRAM of the present embodiment includes a memory cell array 10, a plurality of write word lines (a set of two write word lines 3aW and a write word line 3bW), and a plurality of read word lines (two read word lines 3aR and a read). A set of word lines 3bR), a plurality of first bit lines 4, a plurality of second bit lines 5, a write X selector 8-1, a read X selector 8-2, a write Y selector 11-1, and a read Y selector 11- 2, Y-side current source circuit 12, Y-side power supply circuit 19, Y-side current termination circuit 14 and current sense amplifier 15a.

In the memory cell array 10, two memory cells 20c-1 and 20c-2 are paired and arranged in a matrix. Here, each of the two memory cells 20c-1 and 20c-2 includes a first MOS transistor 6, a second MOS transistor 16, and a magnetoresistive element 7. The reference memory cell 20 is referred to as reference cells 20r-1 and 20r-2.
In the memory cell 20c-1, the gate of the first MOS transistor 6 is connected to the write word line 3aW. In the memory cell 20c-2, the gate of the first MOS transistor 6 is connected to the write word line 3bW.
In the memory cell 20c-1 and the memory cell 20c-2, the source of each first MOS transistor 6 is connected to the first bit line 4 by a common wiring (described later). Similarly, the drain of each first MOS transistor 6 is connected to the second bit line 5 by a common wiring (described later).
As described above, the memory cell 20c-1 and the memory cell 20c-2 reduce the circuit area of the memory cell 20 (20c-1 and 20c-2) by sharing the source and drain of the first MOS transistor 6. is doing.

However, the write word line 3aW and the write word line 3bW are the same as the write word line 3W of the third embodiment except that they are structurally combined. The read word line 3aR and the read word line 3bR are the same as the read word line 3R of the third embodiment except that they are structurally combined.
The memory cell 20c-1 and the memory cell 20c-2 are the same as the first MOS transistor 6 of the third embodiment except that the source and drain of the first MOS transistor 6 are shared. Therefore, those descriptions are omitted.
Furthermore, since the other configuration of FIG. 23 is the same as that of the third embodiment, the description thereof is omitted.

  FIG. 24 is a view of the memory cell array of the MRAM shown in FIG. 23 as viewed from above the substrate on which the memory cell array is manufactured (positive direction of the Z axis). In this figure, 4 × 4 (2 sets × 2 sets) of memory cells 2c (2c-1 and 2c-2) in the memory cell array 1 are shown as representatives. Further, the read word line 3aR and the read word line 3bR shown in FIG. 9 are provided on the magnetoresistive element 7 similarly to FIG. 9, but are omitted in this figure from the viewpoint of easy viewing.

In the first MOS transistor 6 of the memory cell 20 c-1, the source 6 a (first terminal) is connected to the first bit line 4 via the contact wiring 28. The gate 6b (first gate terminal) uses the write word line 3aW. The drain 6 c (second terminal) is connected to the second bit line 5 through the contact wiring 27, the lead-out wiring layer 29, and the contact wiring 37.
On the other hand, in the first MOS transistor 6 of the memory cell 02c-2, the source 6a (first terminal) is connected to the first bit line 4 via the contact wiring 28. The gate 6b (first gate terminal) uses the write word line 3bW. The drain 6 c (second terminal) is connected to the second bit line 5 through the contact wiring 27, the lead-out wiring layer 29, and the contact wiring 37.
The other configuration in FIG. 24 is the same as that in FIG. 21 of the ninth embodiment, and a description thereof will be omitted.

  Next, regarding the operation of the magnetic memory cell and the magnetic random access memory according to the tenth embodiment of the present invention, the wiring (28 and 28) connecting the first bit line 4 and the second bit line 5 to each memory cell 20c. 37) in common, the diffusion layers are inclined by φ, and the first bit line 4 and the second bit line 5 pass under the lead-out wiring layer 29, and the operation is the same as in the eighth embodiment. Therefore, the description is omitted.

According to the present embodiment, the same effect as that of the eighth embodiment can be obtained.
Further, the size of the memory cell 20c can be reduced by increasing the density at which the diffusion layers of the transistors are arranged and by sharing the wiring connecting the bit lines and the memory cells 20c. Therefore, the chip size can be reduced and the cost can be reduced.

(Eleventh embodiment)
An eleventh embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

First, the configuration of the eleventh embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 1 is a diagram showing a configuration of an eleventh embodiment of a magnetic random access memory (MRAM) including magnetic memory cells of the present invention. The MRAM according to the present embodiment includes a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4, a plurality of second bit lines 5, an X selector 8, a Y selector 11, a Y-side current source circuit 12, Y A side power supply circuit 19, a read current load circuit 13, a Y side current termination circuit 14, and a sense amplifier 15 are provided.
Since the configuration of FIG. 1 is the same as that of the first embodiment, description thereof is omitted.

FIG. 25 is a view of the memory cell array of the MRAM shown in FIG. 1 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, a 2 × 2 memory cell 2d in the memory cell array 1 (here, the structure is different from the case of FIG. 2 and is displayed as a memory cell 2d) is shown as a representative.
In the memory cell array 1 of the present embodiment, the ground wiring 24 is extended in the X-axis direction between two adjacent word lines 3. The ground wiring 24 is provided at a position below the lead wiring layer 29 (on the semiconductor substrate side) in the memory cells 2d arranged in the X-axis direction. Thereby, the magnetoresistive element 7 is provided on the ground wiring 24. One end is connected to the ground wiring 24 and the other end is connected to the lead wiring layer 29.
Further, the lead wiring layer 29 is inclined at a predetermined angle ψ (45 ° in FIG. 25) with respect to the magnetoresistive element 7 formed on the ground wiring 24 with the direction of magnetic anisotropy parallel to the Y-axis direction. ing. As a result, the write current can be set small as in the seventh embodiment, and the effect of reducing current consumption can be obtained.

  It should be noted that even if the predetermined angle ψ depending on the direction of magnetization anisotropy of the lead wiring layer 29 and the magnetoresistive element 7 is slightly inclined as shown in the seventh embodiment, there is an effect. However, from the relationship of wiring, it is more preferably 30 ° to 60 °. More preferably, the angle is 40 ° to 50 °.

  The other configuration of the memory cell array 1 and the other configuration of FIG. 25 are the same as those in the first embodiment, and thus description thereof is omitted.

  With this arrangement, the thickness of the lead wiring layer 29 can be easily increased. Thereby, even when the current for writing is large and it is desired to increase the thickness of the lead-out wiring layer 29 in order to increase the reliability, it is possible to easily change the thickness to an appropriate thickness.

FIG. 26 shows the structure of the memory cell 2d, and shows a cross section taken along line EE ′ in FIG.
The magnetoresistive element 7 is provided on the ground wiring 24 extending in parallel with the word line 3, and the lead wiring layer 29 is provided thereon. Although not shown in the drawing, both ends of the lead wiring layer 29 are connected to the drain 6c of the first MOS transistor 6 through a contact wiring 27 that extends in the Z-axis direction, and the second MOS transistor through a contact wiring 37 that extends in the Z-axis direction. 16 drains 16c.
The other configuration of the memory cell 2d is the same as that of the first embodiment, and the description thereof is omitted.

  Next, since the operation of the eleventh embodiment of the magnetic memory cell and magnetic random access memory of the present invention is the same as that of the first embodiment, the description thereof is omitted.

Also in this embodiment, the same effects as those in the first and seventh embodiments can be obtained.
Further, the margin of the shape (thickness) of the lead wiring layer 29 is increased, and the shape of the lead wiring layer 29 corresponding to the magnitude of the write current can be formed. Thereby, the reliability of the memory cell 2 can be improved.

(Twelfth embodiment)
A twelfth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

First, the configuration of the twelfth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 8 is a diagram showing a configuration of a twelfth embodiment of a magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. The MRAM according to the present embodiment includes a memory cell array 10, a plurality of write word lines 3W, a plurality of read word lines 3R, a plurality of first bit lines 4, a plurality of second bit lines 5, a write X selector 8-1, and a read. An X selector 8-2, a write Y selector 11-1, a read Y selector 11-2, a Y side current source circuit 12, a Y side power supply circuit 19, a Y side current termination circuit 14, and a current sense amplifier 15a are provided.
Since the configuration of FIG. 8 is the same as that of the third embodiment, the description thereof is omitted.

27 is a view of the memory cell array of the MRAM shown in FIG. 8 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, a 2 × 2 memory cell 20d in the memory cell array 10 (in this case, the memory cell 20d is displayed because it has a different structure from that in FIG. 9) is shown as a representative.
In the memory cell array 10 of the present embodiment, the read word line 3R extends between the two adjacent write word lines 3W in the X-axis direction at a position that does not overlap the memory cell 20d. The read word line 3R has a read word line 3R-1 branched for each memory cell 20d. The read word line 3R-1 is provided so as to enter a position below the lead wiring layer 29 (semiconductor substrate side) in the memory cells 20d arranged in the X-axis direction. Thereby, the magnetoresistive element 7 is provided on the read word line 3R-1. One end is connected to the read word line 3R-1 and the other end is connected to the lead-out wiring layer 29.

  The other configuration of the memory cell array 10 and the other configuration of FIG. 27 are the same as those of the third embodiment, and thus description thereof is omitted.

  With this arrangement, the thickness of the lead wiring layer 29 can be easily increased. Thereby, even when the current for writing is large and it is desired to increase the thickness of the lead-out wiring layer 29 in order to increase the reliability, it is possible to easily change the thickness to an appropriate thickness.

FIG. 28 shows the structure of the memory cell 20d and is a view showing the FF ′ cross section in FIG.
The magnetoresistive element 7 is provided on the read word line 3R-1 branched from the read word line 3R extending in parallel with the write word line 3W, and the lead-out wiring layer 29 is provided thereon. One end of the lead wiring layer 29 is connected to the drain 6c of the first MOS transistor 6 through a contact wiring 27 extending in the Z-axis direction, and the other is connected to the second bit line 5 through a contact wiring 37 extending in the Z-axis direction. is doing.
Since the configuration of the other memory cell 20d is the same as that of the third embodiment, description thereof is omitted.

  Next, the operation of the twelfth embodiment of the magnetic memory cell and magnetic random access memory of the present invention is the same as that of the third embodiment, so that the description thereof is omitted.

Also in this embodiment, the same effect as in the third embodiment can be obtained.
Further, the margin of the shape (thickness) of the lead wiring layer 29 is increased, and the shape of the lead wiring layer 29 corresponding to the magnitude of the write current can be formed. As a result, the reliability of the memory cell 20 can be improved.

(Thirteenth embodiment)
A thirteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

  The configuration of the thirteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 29 is a diagram showing a configuration of a thirteenth embodiment of a magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. FIG. 29 shows a configuration in which the circuit example of the MRAM shown in FIG. The MRAM according to the present embodiment includes cell arrays 41a-0 to 41a-3 (shown as 41a because the cell array 41 in FIG. 7 in the second embodiment similar to the present embodiment is partially changed). A selector 44, a Y-side current source circuit 42, a read current load circuit 13 and a sense amplifier 15 are provided.

The cell arrays 41a-0 to 41a-3 include a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4 (including a reference first bit line 4r), and a plurality of second bit lines 5 (reference second bits). A line 5r), an X selector 8, a Y selector 11 ', and a Y-side current termination circuit 14. Each configuration is the same as in the first embodiment except that the Y selector 11 ′ can select not only the first bit line 4 but also the reference first bit line 4 r, and the description thereof will be omitted. To do.
In FIG. 29, four cell arrays 41a are shown, but the present invention is not limited to this number.

  The cell array selector 44 uses the selector transistors 44-1 and 44-2 to select the selected cell array 41a-i based on a cell array selection signal MWSi (i = 0 to 3: an integer of the cell array 41a) for selecting the cell array 41a. select. The selected cell array 41a-i is connected to the Y-side current source circuit 42, the read current load circuit 13, and the sense amplifier 15 by the first main bit line 18-1 and the second main bit line 18-2, and the data Write and read operations.

  The Y-side current source circuit 42 is a current source that supplies and draws a predetermined current between the selected first bit line 4s and the selected second bit line 5s of the selected cell array 41a-i during a data write operation. is there. For example, during the write operation of data “1”, a current is supplied to the first main bit line 18-1—cell array selector 44—selected cell array 41a-i, and Y selector 11′—selected first bit line 4s—selected cell 2s. Current is passed through the path of the selected second bit line 5s-Y side current source termination circuit 14, the cell array selector 44, and the second main bit line 18-2 (the second main bit line 18-2 is fixed to the ground). During the write operation of data “0”, the current is supplied to the second main bit line 18-2-cell array selector 44-selected cell array 41a-i in the reverse direction, and the Y-side current source termination circuit 14-selected second bit line is supplied. 5s-selected cell 2s-selected first bit line 4s-Y selector 11'-cell array selector 44-first main bit line 18-1 (first main bit line 18-1 is fixed to ground) to supply current To do. However, 42a generates a constant current, and 42b selects a current supply direction.

The read current load circuit 13 supplies a predetermined current to the selected first bit line 4s of the selected cell array 41a-i during the data read operation. At the same time, a predetermined current is supplied to the reference first bit line 4r of the selected cell array 41a-i. That is, during the data read operation, a current is passed through the first main bit line 18-1−cell array selector 44−Y selector 11′−selected cell 2s. At the same time, current flows through the second main bit line 18-2-cell array selector 44-Y side current termination circuit 14-reference cell 2r.
The sense amplifier 15 reads the selected cell 2s based on the difference between the voltage of the second main bit line 18-2 connected to the reference cell 2r and the voltage of the first main bit line 18-1 connected to the selected cell 2s. Output data.

  Next, the operation of the thirteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

In the MRAM of FIG. 29, data is read from the memory cell 2 as follows.
(1) Step S81
The cell array selector 44 turns on the corresponding selector transistors 44-1 and 44-2 based on the cell array selection signal MWSi for selecting any one of the cell arrays 41a-i to select the selected cell array 41a-i.
At this time, the selected cell array 41a-i, the read current load circuit 13, and the sense amplifier 15 are connected by the first main bit line 18-1 and the second main bit line 18-2.
(2) Step S82
The X selector 8 of the selected cell array 41a-i selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(3) Step S83
The Y selector 11 ′ of the selected cell array 41 a-i selects the selected first bit line 4 s from the plurality of first bit lines 4 in response to column address input. At the same time, the Y-side current termination circuit 14 selects the reference second bit line 5r. Then, in response to the read active signal, the read current load circuit 13 causes the first main bit line 18-1-cell array selector 44-Y selector 11'-selected first bit line 4s-selected cell 2s first MOS transistor 6-magnetic resistance. The current Is is supplied to the ground wiring 24 via the element 7. At the same time, the second main bit line 18-2-cell array selector 44-Y side current termination circuit 14-reference second bit line 5r-selected reference cell 2r (corresponding to the intersection of the selected word line 3s and the reference first bit line 4r) Current Ir flows into the ground wiring 24 via the second MOS transistor 16-the magnetoresistive element 7 of the reference cell 2r).
(4) Step S84
Based on the read active signal, the sense amplifier 15 sets either “1” or “0” based on the potential difference between the potential of the first main bit line 18-1 and the potential of the second main bit line 18-2. Output.

  With the above read operation, the data of the desired selected cell 2s in the desired selected cell array 41a-i can be read.

  Data is written to the memory cell 2 as follows.

(1) Step S91
The cell array selector 44 turns on the corresponding selector transistors 44-1 and 44-2 based on the cell array selection signal MWSi for selecting any one of the cell arrays 41a-i to select the selected cell array 41a-i.
At this time, the selected cell array 41a-i and the Y-side current source circuit 42 are connected by the first main bit line 18-1 and the second main bit line 18-2.
(2) Step S92
The X selector 8 of the selected cell array 41a-i selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(3) Step S93
The Y selector 11 ′ of the selected cell array 41 a-i selects the selected first bit line 4 s from the plurality of first bit lines 4 in response to column address input. Further, the Y-side current termination circuit 14 selects the selected second bit line 5s from the plurality of second bit lines 5 by the write active signal. A pair of the selected first bit line 4s and the selected second bit line 5s is selected.
(A) When “1” is written Second main bit line 18-2 is fixed to the ground. That is, the selected second bit line 5 s is fixed to the ground via the Y-side current termination circuit 14. The Y-side current source circuit 42 has a current Iw (1) having a predetermined magnitude corresponding to the data signal based on the write active signal and the data signal (“1”) (direction flowing out from the Y-side current source circuit 42). The first main bit line 18-1—cell array selector 44—Y selector 11′—selected first bit line 4s—selected cell 2s—selected second bit line 5s—Y-side current termination circuit 14—second main bit line 18-2 Flow through the grounding path.
(B) When “0” is written First main bit line 18-1 is fixed to ground. That is, the selected first bit line 4s is fixed to the ground via the Y selector 11 ′. The Y-side current source circuit 42 has a current Iw (0) having a predetermined magnitude corresponding to the data signal based on the write active signal and the data signal (“0”) (direction flowing out from the Y-side current source circuit 42). The second main bit line 18-2-cell array selector 44-Y side current termination circuit 14-selected second bit line 5s-selected cell 2s-selected first bit line 4s-Y selector 11'-first main bit line 18-1-flow through grounding path.
(4) Step S94
In the selected cell 2s, when the current Iw (0) (−X direction) or the current Iw (1) (+ X direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the + Y direction or −Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal is stored.

  Through the above write operation, data can be written to the desired selected cell 2s in the desired selected cell array 41a-i.

According to the present invention, the MRAM can be made compact by layering the cell array and sharing some circuits.
In addition, the constant current source 42a of the Y-side current source circuit 12 only needs to correspond to a single direction (in this embodiment, the flowing-out direction), and the design flexibility can be improved.

(Fourteenth embodiment)
A fourteenth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  A configuration of a fourteenth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described. FIG. 30 is a diagram showing a configuration of a fourteenth embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention. FIG. 30 shows a configuration in which the circuit example of the MRAM shown in FIG. The MRAM in this embodiment includes cell arrays 51a-0 to 51a-3 (displayed as 51a because the cell array 51 in FIG. 11 in the fourth embodiment similar to the present embodiment is partially changed). A selector 44, a Y-side current source circuit 42, and a current sense amplifier 15a are provided.

  The cell arrays 51a-0 to 51a-3 include a memory cell array 10, a plurality of write word lines 3W, a plurality of read word lines 3R, a plurality of first bit lines 4 (including a reference first bit line 4r), and a plurality of second cells. A bit line 5 (including a reference second bit line 5r), a write X selector 8-1, a read X selector 8-2, a Y selector 11 ', and a Y-side current termination circuit 14 are provided.

  However, the memory cell 20 of the memory cell array 10 does not have the first MOS transistor 6, the second MOS transistor 16 (the gate (first gate) is the write word line 3W, and the source (first terminal) is the second bit line 5). In addition, the third embodiment is the same as the third embodiment except that the drain (second terminal) is connected to one end side (fourth terminal) of the magnetoresistive element 7 and the first bit line 4). . The reference cell 20r is the same as that in the third embodiment.

The first bit line 4 is provided so as to extend in the Y-axis direction (bit line direction), and is connected to the Y selector 11 ′. The reference first bit line 4 is referred to as a reference first bit line 4r.
The second bit line 5 is paired with the first bit line 4 and is provided extending in the Y-axis direction. One end of the second bit line 5 is connected to the Y-side current termination circuit 14. The reference second bit line 5 is referred to as a reference second bit line 5r.
The write word line 3 and the read word line 3R are the same as those in the third embodiment.
Each memory cell 20 corresponds to each of the positions where the plurality of sets of the first bit line and the second bit line intersect with the plurality of sets of the write word line 3W and the read word line 3R. Is provided.

The write X selector 8-1 and the read X selector 8-2 are the same as those in the third embodiment.
The Y selector 11 ′ selects one first bit line 4 from the plurality of first bit lines 4 as the selected first bit line 4 s during the write operation and the read operation. Further, the reference first bit line 4r is selected during the write operation of the reference cell 20r.
The Y-side current termination circuit 14 selects one second bit line 5 that forms a pair with the selected first bit line 4s as the selected second bit line 5s from the plurality of second bit lines 5 during the data write operation. . Further, the reference second bit line 5r is selected during the read operation and the write operation of the reference cell 20r.
Here, the memory cell 2 selected by the selected write / read word line 3Ws / 3Rs and the selected first / second bit line 4s / 5s is referred to as a selected cell 2s.
In FIG. 30, four cell arrays 51a are shown, but the present invention is not limited to this number.

  The cell array selector 44 uses the selector transistors 44-1 and 44-2 to select the selected cell array 51a-i based on a cell array selection signal MWSi (i = 0 to 3: an integer of the cell array 41a) for selecting the cell array 51a. select. The selected cell array 51a-i is connected to the Y-side current source circuit 42 and the current sense amplifier 15a by the first main bit line 18-1 and the second main bit line 18-2, and performs data write / read operations. I do.

During the data write operation, the Y-side current source circuit 42 moves between the selected first bit line 4s and the selected second bit line 5s of the selected cell array 51a-i (i = 0 to n: n + 1 is the number of cell arrays). A current source for supplying and drawing a predetermined current. For example, during the write operation of data “1”, current is supplied to the first main bit line 18-1—cell array selector 44—selected cell array 51a-i, and Y selector 11′—selected first bit line 4s—selected cell 2s. Current is passed through the path of the selected second bit line 5s-Y side current source termination circuit 14, the cell array selector 44, and the second main bit line 18-2 (the second main bit line 18-2 is fixed to the ground). During the write operation of data “0”, the current is supplied to the second main bit line 18-2-cell array selector 44—selected cell array 51a-i in the reverse direction, and the Y-side current source termination circuit 14—selected second bit line. 5s-selected cell 2s-selected first bit line 4s-Y selector 11'-cell array selector 44-first main bit line 18-1 (first main bit line 18-1 is fixed to ground) to supply current To do. However, 42a generates a constant current, and 42b selects a current supply direction.
The current sense amplifier 15a includes a current flowing through the reference second bit line 5r (second main bit line 18-2) connected to the reference cell 20r and a selected first bit line 4s (first main bit line 18) connected to the selected cell 2s. Based on the current flowing through -1) and the difference, data is read from the selected cell 2s and the data is output.

  Next, the operation of the fourteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

In the MRAM of FIG. 30, data is read from the memory cell 2 as follows.
(1) Step S101
The cell array selector 44 turns on the corresponding selector transistors 44-1 and 44-2 based on the cell array selection signal MWSi for selecting any one of the cell arrays 51a-i to select the selected cell array 51a-i.
At this time, the selected cell array 51a-i and the current sense amplifier 15 are connected by the first main bit line 18-1 and the second main bit line 18-2.
(2) Step S102
The read X selector 8-2 of the selected cell array 51a-i selects the selected read word line 3Rs from the plurality of read word lines 3W in response to the input of the row address.
(3) Step S103
The Y selector 11 ′ of the selected cell array 51a-i selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. At the same time, the Y-side current termination circuit 14 selects the reference second bit line 5r. Thus, the read X selector 8-2-selected read word line 3Rs-selected cell 20s (the magnetoresistive element 7) -selected second bit line 5s-Y selector 11'-first main bit line 18-1-current sense. A current Is reflecting the data of the selected cell 20s flows through the path of the amplifier 15a due to a voltage difference between the read X selector 8-2 and the current sense amplifier 15a. On the other hand, the path of the read X selector 8-2-selected read word line 3Rs-reference cell 20r (the magnetoresistive element 7) -reference second bit line 5r-second main bit line 18-2-current sense amplifier 15a The current Ir reflecting the data “0” of the reference cell 20r flows.
(4) Step S104
Based on the difference between the current Is and the current Ir, the current sense amplifier 15a determines that the read data is “0” if they are almost the same, and “1” if they are different (example: smaller), and the result Is output.

  With the above read operation, the data of the desired selected cell 2s in the desired selected cell array 51a-i can be read.

  Data is written to the memory cell 2 as follows.

(1) Step S111
The cell array selector 44 turns on the corresponding selector transistors 44-1 and 44-2 based on the cell array selection signal MWSi for selecting any one of the cell arrays 51a-i to select the selected cell array 51a-i.
At this time, the selected cell array 51a-i and the Y-side current source circuit 42 are connected by the first main bit line 18-1 and the second main bit line 18-2.
(2) Step S112
The write X selector 8-1 of the selected cell array 51a-i selects the selected write word line 3Ws from the plurality of write word lines 3W in response to the input of the row address. The second MOS transistor 16 of each memory cell 20 is turned on.
(3) Step S113
The Y selector 11 ′ of the selected cell array 51a-i selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. Further, the Y-side current termination circuit 14 selects the selected second bit line 5s from the plurality of second bit lines 5 by the write active signal. A pair of the selected first bit line 4s and the selected second bit line 5s is selected.
(A) When “1” is written Second main bit line 18-2 is fixed to the ground. That is, the selected second bit line 5 s is fixed to the ground via the Y-side current termination circuit 14. The Y-side current source circuit 42 has a current Iw (1) having a predetermined magnitude corresponding to the data signal based on the write active signal and the data signal (“1”) (direction flowing out from the Y-side current source circuit 42). The first main bit line 18-1—cell array selector 44—Y selector 11′—selected first bit line 4s—selected cell 2s—selected second bit line 5s—Y-side current termination circuit 14—second main bit line 18-2 Flow through the grounding path.
(B) When “0” is written First main bit line 18-1 is fixed to ground. That is, the selected first bit line 4s is fixed to the ground via the Y selector 11 ′. The Y-side current source circuit 42 has a current Iw (0) having a predetermined magnitude corresponding to the data signal based on the write active signal and the data signal (“0”) (direction flowing out from the Y-side current source circuit 42). The second main bit line 18-2-cell array selector 44-Y side current termination circuit 14-selected second bit line 5s-selected cell 2s-selected first bit line 4s-Y selector 11'-first main bit line 18-1-flow through grounding path.
(4) Step S114
In the selected cell 2s, when the current Iw (0) (−X direction) or the current Iw (1) (+ X direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the + Y direction or −Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal is stored.

  With the above write operation, data can be written to the desired selected cell 2s in the desired selected cell array 51a-i.

According to the present invention, the MRAM can be made compact by layering the cell array and sharing some circuits.
In addition, the constant current source 42a of the Y-side current source circuit 12 only needs to correspond to a single direction (in this embodiment, the flowing-out direction), and the design flexibility can be improved.

(Fifteenth embodiment)
A fifteenth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  The configuration of the fifteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 31 is a diagram showing a configuration of a fifteenth embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention. FIG. 31 shows a configuration in which the circuit example of the MRAM shown in FIG. The MRAM of this embodiment includes cell arrays 41c-0 to 41c-3 (displayed as 41c because it is partially changed from the cell array 41a of FIG. 29 in the thirteenth embodiment similar to this embodiment), A selector 44, a Y-side current source circuit 42, a read current load circuit 13 and a sense amplifier 15 are provided.

The cell arrays 41c-0 to 41c-3 include a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4 (including a reference first bit line 4r), and a plurality of second bit lines 5 (reference second bits). Line 5r), X selector 8, Y selector 11 '(however, selection / non-selection of the reference first bit line 4r is also performed), Y-side current termination circuit 14, precharge word line 3p, precharge line 45, A plurality of precharge voltage lines 48, a precharge power supply 46, a precharge selector 47, and precharge transistors 49 (49-1 and 49-2) are provided.
In FIG. 31, four cell arrays 41c are shown, but the present invention is not limited to this number.

In the memory cell array 1, memory cells 2 are arranged in a matrix. Here, the memory cell 2 includes a first MOS transistor 6, a second MOS transistor 16, and a magnetoresistive element 7. The reference memory cell 2 is referred to as a reference cell 2r.
The first MOS transistor 6 and the second MOS transistor 16 are the same as in the thirteenth embodiment.
The magnetoresistive element 7 has one end connected to the drain of each transistor and the other end connected to the precharge voltage line 48. It has spontaneous magnetization whose magnetization direction is reversed according to stored data.
During the read operation, the first MOS transistor 6 is used to connect the magnetoresistive element 7 to the first bit line 4 and to pass a current through the first bit line 4 -the magnetoresistive element 7 -the precharge voltage line 48. During the write operation, the first MOS transistor 6 and the second MOS transistor 16 are used to connect the first bit line 4 and the second bit line 5 and to allow a current to flow in the vicinity of the magnetoresistive element 7.

The precharge power supply 46 applies a predetermined precharge voltage Vpr to the precharge line 45 and the plurality of precharge voltage lines 48. The precharge voltage Vpr is the same voltage as the voltage at the node where the first MOS transistor 6, the second MOS transistor 16, and the magnetoresistive element 7 are connected when a current is passed through the memory cell 2 to write data to the memory cell 2. Is set to be
The precharge selector 47 activates the precharge word line 3p.
The precharge word line 3p is provided so as to extend in the X-axis direction (word line direction) and is connected to the precharge selector 47.
The precharge line 45 is provided so as to extend in the X-axis direction (word line direction) and is connected to a precharge power supply 46. The precharge voltage Vpr is supplied to the first bit line 4 and the second bit line 5 through the precharge transistors 49-1 and 49-2.
The plurality of precharge voltage lines 48 are provided so as to extend in the X-axis direction (word line direction) and are connected to the precharge power supply 46. Each of the plurality of precharge voltage lines 48 is wired for each column of the memory cells 2. Then, the precharge voltage Vpr is supplied to the node opposite to the node between the first MOS transistor 6 and the second MOS transistor 16 in the magnetoresistive element 7 of the memory cell 2.
The precharge transistor 49-1 (precharge unit) has a gate connected to the precharge word line 3p, a source connected to the first bit line 4, and a drain connected to the precharge line 45. The precharge transistor 49-2 (precharge unit) has a gate connected to the precharge word line 3p, a source connected to the second bit line 5, and a drain connected to the precharge line 45.

  Since the other configuration of the cell array 41c is the same as that of the thirteenth embodiment, the description thereof is omitted.

  Since the cell array selector 44, the Y-side current source circuit 42, the read current load circuit 13, and the sense amplifier 15 are the same as those in the thirteenth embodiment, the description thereof is omitted.

  Next, the operation of the fifteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

  In the MRAM of FIG. 31, when the first bit line 4 and the second bit line 5 are not selected, the precharge transistor 49-1 and the precharge transistor 49-2 are activated by the activation of the precharge word line 3p by the precharge selector 47. Is on. Accordingly, the first bit line 4 and the second bit line 5 are precharged to the precharge voltage Vpr from the precharge power supply 46 through the precharge line 45, the precharge transistor 49-1, and the precharge transistor 49-2. ing.

  In the read operation of data from the memory cell 2 and the write operation of data to the memory cell 2 in the MRAM of FIG. 31, the current Is and current Ir at the time of reading are not the ground wiring 24 but the precharge voltage line 48. Since it is the same as in the thirteenth embodiment except that it flows into the precharge power supply 46 via the, the description thereof is omitted.

  According to the present invention, both ends of the magnetoresistive element 7 have the same voltage (precharge voltage Vpr) and no potential difference is lost during the data write operation, so that loss of write current in the memory cell 2 can be prevented. That is, it is possible to improve the accuracy of the write current.

  In addition, by setting the first bit line 4 and the second bit line to the precharge voltage Vpr, the first bit line 4 and the second bit line have different potentials, so that the current is generated by the exchange of charges between the parasitic capacitances. 2 can be prevented from being written.

  Further, the MRAM can be made compact by hierarchizing the cell array and sharing some circuits.

(Sixteenth embodiment)
A sixteenth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  The configuration of the sixteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained. FIG. 32 is a diagram showing a configuration of a sixteenth embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention. FIG. 32 shows a configuration in which the circuit example of the MRAM shown in FIG. The MRAM of this embodiment includes cell arrays 51c-0 to 51c-3 (displayed as 51c because it is partially changed from the cell array 51a of FIG. 30 in the fourteenth embodiment similar to this embodiment), A selector 44, a Y-side current source circuit 42, and a current sense amplifier 15 are provided.

The cell arrays 51c-0 to 51c-3 include a memory cell array 10, a plurality of write word lines 3W, a plurality of read word lines 3R, a plurality of first bit lines 4 (including a reference first bit line 4r), and a plurality of second cells. Bit line 5 (including reference second bit line 5r), write X selector 8-1, read X selector 8-2, Y selector 11 ′ (however, selection / non-selection of reference first bit line 4r is also performed), A Y-side current termination circuit 14, an X-side power supply circuit 46a, a precharge word line 3p, a precharge line 45, a precharge power supply 46, a precharge selector 47, and precharge transistors 49 (49-1 and 49-2) are provided.
In FIG. 32, four cell arrays 51c are shown, but the present invention is not limited to this number.

The precharge power supply 46 applies a predetermined precharge voltage Vpr to the read word line 3R via the precharge line 45 and the read X selector 8-2. The precharge voltage Vpr is the same voltage as the voltage at the node where the first MOS transistor 6 or the second MOS transistor 16 and the magnetoresistive element 7 are connected when a current is passed through the memory cell 20 to write data to the memory cell 20. Is set to be
The X-side power supply circuit 46a applies a predetermined read voltage Vread to the read word line 3R via the read X selector 8-2 during a read operation.
The precharge selector 47, precharge word line 3p, precharge line 45, precharge transistors 49-1 and 49-2 (precharge unit) are the same as those in the fifteenth embodiment, and other configurations of the cell array 51c. Since this is the same as FIG. 30 of the fourteenth embodiment, its description is omitted.

  Since the cell array selector 44, the Y-side current source circuit 42, and the current sense amplifier 15a are the same as those in the fourteenth embodiment, description thereof is omitted.

  Next, the operation of the sixteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

  In the MRAM of FIG. 32, when the first bit line 4 and the second bit line 5 are not selected, the precharge transistor 49-1 and the precharge transistor 49-2 are activated by the activation of the precharge word line 3p by the precharge selector 47. Is on. Accordingly, the first bit line 4 and the second bit line 5 are precharged to the precharge voltage Vpr from the precharge power supply 46 through the precharge line 45, the precharge transistor 49-1, and the precharge transistor 49-2. ing.

  The data read operation from the memory cell 20 and the data write operation to the memory cell 20 in the MRAM of FIG. 32 are the same as those in the fourteenth embodiment, and thus the description thereof is omitted.

According to the present invention, an effect similar to that of the fifteenth embodiment can be obtained.
According to the present invention, the MRAM can be made compact by layering the cell array and sharing some circuits.

(Seventeenth embodiment)
A seventeenth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  A configuration of a seventeenth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described. FIG. 33 is a diagram showing the configuration of a seventeenth embodiment of a magnetic random access memory (MRAM) including magnetic memory cells of the present invention. FIG. 33 shows a configuration in which the circuit example of the MRAM shown in FIG. The MRAM of this embodiment includes cell arrays 41b-0 to 41b-3 (displayed as 41b because it is partially changed from the cell array 41a of FIG. 29 in the thirteenth embodiment similar to this embodiment), A selector 44a, a Y-side current source circuit 42, a read current load circuit 13 and a sense amplifier 15 are provided.

The cell arrays 41b-0 to 41b-3 include a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4 (including a reference first bit line 4r), and a plurality of second bit lines 5 (reference second bits). Line 5r), X selector 8, first Y selector 11'a (however, selection / non-selection of the reference first bit line 4r), second Y selector 11'b (however, the reference first bit line 4r) The Y-side current termination circuit 14 is provided.
In FIG. 33, four cell arrays 41b are shown, but the present invention is not limited to this number.

The first Y selector 11′a performs the same operation as the Y selector 11 of the first embodiment during the write operation. However, in addition, the selection / non-selection of the reference first bit line 4r is also performed.
The second Y selector 11′b performs the same operation as the Y selector 11 of the first embodiment during the read operation. However, the selection / non-selection of the reference first bit line 4r is also performed.

  The other functions of the first Y selector 11 ′ a and the second Y selector 11 ′ b and other configurations are the same as those in the first embodiment, and the description thereof is omitted.

  The cell array selector 44a is based on a cell array selection signal MWSi for selecting the cell array 41a (integer of i = 0-3: number of the cell array 41a), selector write transistor 44a-1a, selector read transistor 44a-1b, selector selector. The selected cell array 41b-i is selected by the read transistor 44a-1c and the selector write transistor 44a-2. The selected cell array 41b-i is connected to the Y-side current source circuit 42 by the first write main bit line 68-1 and the second write main bit line 68-2 and performs a data write operation. Further, the first read main bit line 69-1 and the second read main bit line 69-2 are connected to the read current load circuit 13 and the sense amplifier 15 to perform a data read operation.

The Y-side current source circuit 42 is a current source that supplies and draws a predetermined current between the selected first bit line 4s and the selected second bit line 5s of the selected cell array 41b-i for data writing. .
For example, during the write operation of data “1”, current is supplied to the second write main bit line 68-2-cell array selector 44a (selector write transistor 44a-1a) -selected cell array 41b-i, and the first Y selector 11 ′. a-selected first bit line 4s-selected cell 2s-selected second bit line 5s-Y-side current source termination circuit 14-cell array selector 44a (selector write transistor 44a-2) -first write main bit line 68-1 A current is passed through a path (first write main bit line 68-2 is fixed to ground).
During the write operation of data “0”, the current is supplied to the first write main bit line 68-1-cell array selector 44a (selector write transistor 44a-2) -selected cell array 41a-i in the reverse direction, and the Y-side current Source termination circuit 14-selected second bit line 5s-selected cell 2s-selected first bit line 4s-first Y selector 11'a-cell array selector 44 (selector write transistor 44a-1a) -first write main bit line 68 -1 (the first main bit line 68-1 is fixed to the ground) is supplied with current. However, 42a generates a constant current, and 42b selects a current supply direction.

The read current load circuit 13 supplies a predetermined current to the selected first bit line 4s of the selected cell array 41b-i during the data read operation. At the same time, a predetermined current is supplied to the reference first bit line 4r of the selected cell array 41b-i. That is, during the data read operation, the second read main bit line 69-1-cell array selector 44a (selector read transistor 44a-1b) -second Y selector 11'b-selected first bit line 4s-selected cell 2s. Apply current. At the same time, a current flows through the first read main bit line 69-1-cell array selector 44 (selector read transistor 44a-1c) -second Y selector 11'b-selected first bit line 4s-reference cell 2r.
The sense amplifier 15 determines the voltage of the selected cell 2s based on the difference between the voltage of the second read main bit line 69-2 connected to the reference cell 2r and the voltage of the first read main bit line 69-1 connected to the selected cell 2s. Output the read data.

  Next, the operation of the seventeenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

In the MRAM shown in FIG. 33, data is read from the memory cell 2 as follows.
(1) Step S121
The cell array selector 44a turns on the read transistor for selector 44a-1c and the read transistor for selector 44a-1b based on the cell array selection signal MWSi for selecting any one of the cell arrays 41b-i, and selects the selected cell array 41b-i. select.
At this time, the selected cell array 41b-i, the read current load circuit 13, and the sense amplifier 15 are connected by the first read main bit line 69-1 and the second read main bit line 69-2.
(2) Step S122
The X selector 8 of the selected cell array 41b-i selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(3) Step S123
The second Y selector 11′b of the selected cell array 41b-i selects the selected first bit line 4s from the plurality of first bit lines 4 according to the input of the column address. At the same time, the second Y selector 11′b selects the reference first bit line 4r. Then, in response to the read active signal, the read current load circuit 13 causes the first MOS transistor 6 of the selected cell 2s to pass through the second read main bit line 69-2-second Y selector 11′b-selected first bit line 4s. A current Is is caused to flow into the ground wiring 24 via the magnetoresistive element 7. At the same time, the first read main bit line 69-1-second Y selector 11'b-reference first bit line 4r-selected reference cell 2r (reference cell corresponding to the intersection of the selected word line 3s and the reference first bit line 4r) 2r) through the first MOS transistor 6 and the magnetoresistive element 7, current Ir flows into the ground wiring 24.
(4) Step S124
Depending on the read active signal, the sense amplifier 15 is either “1” or “0” based on the potential difference between the potential of the second read main bit line 69-2 and the potential of the first read main bit line 69-1. Output one.

  With the above read operation, the data of the desired selected cell 2s in the desired selected cell array 41b-i can be read.

  Data is written to the memory cell 2 as follows.

(1) Step S131
The cell array selector 44a turns on the selector write transistor 44a-1a and the selector write transistor 44a-2 to turn on the selected cell array 41b-i based on the cell array selection signal MWSi for selecting any one of the cell arrays 41b-i. select.
At this time, the selected cell array 41b-i and the Y-side current source circuit 42 are connected by the second write main bit line 68-2 and the first write main bit line 68-1.
(2) Step S132
The X selector 8 of the selected cell array 41b-i selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(3) Step S133
The first Y selector 11′a of the selected cell array 41b-i selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. The Y-side current termination circuit 14 selects the selected second bit line 5s from the plurality of second bit lines 5 in accordance with the write active signal. A pair of the selected first bit line 4s and the selected second bit line 5s is selected.
(A) When writing “1” The first write main bit line 68-1 is fixed to the ground. That is, the selected second bit line 5 s is fixed to the ground via the Y-side current termination circuit 14. The Y-side current source circuit 42 has a current Iw (1) having a predetermined magnitude corresponding to the data signal based on the write active signal and the data signal (“1”) (direction flowing out from the Y-side current source circuit 42). The second write main bit line 68-2-cell array selector 44a-first Y selector 11'a-selected first bit line 4s-selected cell 2s-selected second bit line 5s-Y-side current termination circuit 14-cell array selector 44a-first write main bit line 68-1--flow through the ground path.
(B) Writing “0” The second write main bit line 68-2 is fixed to the ground. That is, the selected first bit line 4s is fixed to the ground via the first Y selector 11′a. The Y-side current source circuit 42 has a current Iw (0) having a predetermined magnitude corresponding to the data signal based on the write active signal and the data signal (“0”) (direction flowing out from the Y-side current source circuit 42). First write main bit line 68-1-cell array selector 44a-Y side current termination circuit 14-selected second bit line 5s-selected cell 2s-selected first bit line 4s-first Y selector 11'a-cell array selector 44a-second write main bit line 68-2-flows through a ground path.
(4) Step S134
In the selected cell 2s, when the current Iw (0) (−X direction) or the current Iw (1) (+ X direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the + Y direction or −Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal is stored.

  With the above write operation, data can be written to the desired selected cell 2s in the desired selected cell array 41b-i.

In the cell array selector 44a, the read transistor and the write transistor can be used separately, so that the transistor size can be made different when the write current and the read current are different. Thereby, even when the magnitudes of the write current and the read current are different, the write operation and the read operation can be stably performed.
Further, according to the present invention, the MRAM can be made compact by hierarchizing the cell array and sharing some circuits.

(Eighteenth embodiment)
An eighteenth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

The configuration of the eighteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained. FIG. 34 is a diagram showing a configuration of an eighteenth embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention.
34, compared with FIG. 30 of the fourteenth embodiment, the first Y selector 11′a as the Y selector 11 ′ and the first and second main bit lines 18-1 and 18-2 are exclusively used for writing. As shown, first and second write main bit lines 68-1 and 68-2 are provided and used during a write operation. For read only, the second Y selector 11′b is used as the Y selector 11 ′, and the first and second read main bit lines 69-1 and 69− are used as the first and second main bit lines 18-1 and 18-2. 2 are used during read operation.
Then, the cell array selector 44a selects the selector write transistor 44a-1a and the selector write transistor based on the cell array selection signal MWSi for selecting the cell array 41a (i = 0 to 3, an integer of the cell array 41a). The selected cell array 41-i is selected by 44a-2, and during the read operation, the selected cell array 41-i is selected by the selector read transistor 44a-1b and the selector read transistor 44a-1c.
Other configurations are the same as those in the fourteenth embodiment, and thus the description thereof is omitted.

  Next, with regard to the operation of the eighteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention, a write-only configuration (first Y selector 11′a, first and second write main bit lines during the write operation) 68-1 and 68-2, selector write transistor 44a-1a and selector write transistor 44a-2), and a read-only configuration during the read operation (second Y selector 11′b, first and second read main bits) Except for the lines 69-1 and 69-2, the selector read transistor 44a-1b and the selector read transistor 44a-1c), the description is omitted because it is the same as the fourteenth embodiment.

  According to the present invention, the same effect as in the seventeenth embodiment can be obtained.

(Nineteenth embodiment)
A nineteenth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

The configuration of the nineteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained. FIG. 35 is a diagram showing a configuration of a nineteenth embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention. The MRAM of this embodiment includes cell arrays 41d-0 to 41d-3 (displayed as 41d because it is partially changed from the cell array 41a of FIG. 29 in the thirteenth embodiment similar to this embodiment), A selector 44, a Y-side current source circuit 43, a read current load circuit 13, and a sense amplifier 15 are provided.
In FIG. 35, four cell arrays 41d are shown, but the present invention is not limited to this number.

  The cell arrays 41d-0 to 41d-3 include a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4 (including a reference first bit line 4r), and a plurality of second bit lines 5 (reference second bits). Line 5r), X selector 8, Y selector 11 '' (however, the reference first bit line 4r is also selected / deselected), Y-side current termination circuit 14 '' (however, the reference second bit line 5r) Is also selected / deselected).

  Since the memory cell array 1 is the same as that of the first embodiment, the description thereof is omitted.

The first bit line 4 is provided so as to extend in the Y-axis direction (bit line direction) as the first direction, and one is connected to the Y selector 11 ″ and the other is connected to the Y-side current termination circuit 14 ″. ing.
The second bit line 5 is paired with the first bit line 4 and extends in the Y-axis direction. One of the second bit lines 5 is connected to the Y selector 11 ″ and the other is connected to the Y-side current termination circuit 14 ″. ing.
The word line 3 is provided so as to extend in the X-axis direction (word line direction) as a second direction substantially perpendicular to the Y-axis direction, and is connected to the X selector 8.
Each memory cell 2 is provided corresponding to each of positions where a plurality of sets of the first bit line 4 and the second bit line 5 and a plurality of word lines intersect.

The X selector 8 selects one word line 3 from a plurality of word lines 3 extending in the X-axis direction (word line direction) in both the data read operation and the write operation. Select as line 3s.
The Y selector 11 ″ uses one first bit line from a plurality of first bit lines 4 and a plurality of second bit lines 5 extending in the Y-axis direction (bit line direction) during a data read operation. 4 is selected as the selected first bit line 4s, and one second bit line 5 paired therewith is selected as the selected second bit line 5s. Further, during the write operation, either the selected first bit line 4s or the selected second bit line 5s is selected corresponding to the data to be written (either “0” or “1”).
The Y-side current termination circuit 14 ″ selects the reference first bit line 4s and the reference second bit line 5r during the data read operation. Further, during the write operation, either the selected first bit line 4s or the selected second bit line 5s is selected corresponding to the data to be written (either “1” or “0”).

The Y-side current source circuit 43 supplies a predetermined current to the selected first bit line 4s or the selected second bit line 5s via the second main bit line 18-2 during the data write operation. It is. However, 43a generates a constant current, and 43b turns on / off according to the input of current data.
Here, the predetermined current generated by the Y-side current source circuit 43 is determined by the second main bit line 18-2-cell array selector 44- (of the selected cell array 41a-i) according to the data to be written. -Selected first bit line 4s-Selected cell 2s-Selected second bit line 5s-Y selector 11 "-Cell array selector 44-First main bit line 18-1 or second main bit line 18-2-cell array Selector 44-Y-side current termination circuit 14 "(of selected cell array 41a-i)-selected second bit line 5s-selected cell 2s-selected first bit line 4s-Y selector 11"-cell array selector 44-first It flows through the main bit line 18-1 and returns to the Y-side current source circuit 43.

The read current load circuit 13 supplies a predetermined current to the selected cell 2s during a data read operation. Similarly, a predetermined current is passed through the reference cell 2r during a data read operation.
Here, the basic structure of the reference cell 2r is the same as that of the normal memory cell 2. However, the resistance value is a predetermined value (the voltage drop of the magnetoresistive element 7 having data “1” and the magnetoresistive element 7 having data “0” by the predetermined current flowing through the read current load circuit 13. And has a voltage drop that is intermediate to the voltage drop), and is referenced during the read operation of another memory cell 2.

  Since the cell array selector 44 and the sense amplifier 15 are the same as those in the seventeenth embodiment, description thereof is omitted.

  The operation of the nineteenth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described next. YSWRR is a signal for selecting the reference cell 2r during the read operation. The same applies throughout this specification.

In the MRAM of FIG. 35, data is read from the memory cell 2 as follows.
(1) Step S141
The cell array selector 44 selects the selector transistors 44-1 and 44-2 based on the cell array selection signal MWSi (i = 0 to 3: the number of the cell array 41d) for selecting any one of the cell arrays 41d-i. Turn on and select the selected cell array 41d-i.
At this time, the selected cell array 41d-i, the read current load circuit 13, and the sense amplifier 15 are connected by the first main bit line 18-1 and the second main bit line 18-2.
(2) Step S152
The X selector 8 of the selected cell array 41d-i selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(3) Step S153
The Y selector 11 ″ of the selected cell array 41d-i selects the selected first bit line 4s from the plurality of first bit lines 4 and selects the first bit from the plurality of second bit lines 5 in response to the input of the column address. The selected second bit line 5s paired with the line 4s is selected. At the same time, the Y-side current termination circuit 14 selects the reference first bit line 4r and the reference second bit line 5r. Then, in response to the read active signal, the read current load circuit 13 causes the selected cell 2s to pass through the first main bit line 18-1-Y selector 11 ″ -selected first bit line 4s and selected second bit line 5s. The current Is flows into the ground wiring 24 via the first MOS transistor 6 and the second MOS transistor 16 -the magnetoresistive element 7. At the same time, the second main bit line 18-2-Y side current termination circuit 14 ''-reference first bit line 4r and reference second bit line 5r-selected reference cell 2r (selected word line 3s and reference first bit line 4r). Current Ir flows into the ground wiring 24 via the first MOS transistor 6 and the second MOS transistor 16 of the reference cell 2r) corresponding to the intersection with the magnetoresistive element 7.
(4) Step S154
Based on the read active signal, the sense amplifier 15 sets either “1” or “0” based on the potential difference between the potential of the first main bit line 18-1 and the potential of the second main bit line 18-2. Output.

  With the above read operation, the data of the desired selected cell 2s in the desired selected cell array 41d-i can be read.

  Data is written to the memory cell 2 as follows.

(1) Step S161
The cell array selector 44 turns on the selector transistors 44-1 and 44-2 to select the selected cell array 41d-i based on the cell array selection signal MWSi for selecting any one of the cell arrays 41d-i.
At this time, the selected cell array 41d-i, the Y-side current source circuit 12, and the sense amplifier 15 are connected by the first main bit line 18-1 and the second main bit line 18-2.
(2) Step S162
The X selector 8 of the selected cell array 41d-i selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(3) Step S163
A column address and a data signal are input to the Y selector 11 ″ of the selected cell array 41d-i, and the selected first bit line 4s or the selected second bit line 5s is selected according to the data signal. Further, based on the write active signal, the column address, and the data signal, the Y-side current termination circuit 14 selects the selected second bit line 5s or the selected first bit line 4s according to the data signal. A pair of the selected first bit line 4s and the selected second bit line 5s is selected.
(A) Writing “1” The Y-side current termination circuit 14 selects the selected first bit line 4s. The Y selector 11 ″ selects the selected second bit line 5s that forms a pair with the selected first bit line 4s.
Then, the Y-side current source circuit 43 applies a current Iw (1) having a predetermined magnitude to the Y-side current source circuit 43-second main bit line 18-2-Y-side current termination circuit 14 ''-selection. The current flows through the path of 1 bit line 4s-selected cell 2s-selected second bit line 5s-Y selector 11 ''-first main bit line 18-1-Y side current source circuit 43.
(B) Writing “0” The Y-side current termination circuit 14 selects the selected second bit line 5s. The Y selector 11 ″ selects the selected first bit line 4s that forms a pair with the selected second bit line 5s.
Then, the Y-side current source circuit 43 applies a current Iw (0) having a predetermined magnitude to the Y-side current source circuit 43-second main bit line 18-2-Y-side current termination circuit 14 ''-selection. The current flows through the path of 2 bit line 5s−selected cell 2s−selected first bit line 4s−Y selector 11 ″ −first main bit line 18-1-Y side current source circuit 43.
(4) Step S164
In the selected cell 2s, when the current Iw (0) (−X direction) or the current Iw (1) (+ X direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the + Y direction or −Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal is stored.

  Through the above write operation, data can be written to the desired selected cell 2s in the desired selected cell array 41a-i.

According to the present invention, the main bit line selection circuit of the Y-side current source circuit 43 is omitted, and a simple power supply connection circuit 43b can be obtained.
Further, since the read current Is (and Ir) is read using the two MOS transistors, it is possible to suppress the influence of the variation of the MOS transistors in the memory cell.
Furthermore, the MRAM can be made compact by layering the cell array and sharing some circuits.

(20th embodiment)
A twentieth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  The configuration of the twentieth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained. FIG. 36 is a diagram showing a configuration of a twentieth embodiment of a magnetic random access memory (MRAM) including a magnetic memory cell according to the present invention. The MRAM of this embodiment includes a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4 (including a reference first bit line 4r), and a plurality of second bit lines 5 (reference second bit lines 5r). X selector 8, first Y selector 71, second Y selector 72, a plurality of sense amplifiers 73, a plurality of read current load circuits 74, a plurality of third transistors 77, and a plurality of column selection transistors 75 (75-1 and 75). 75-2), reference selection transistor 76 (76-1 and 76-2), sense line 81 (81-1 and 81-2), read current signal line 82, comparison signal line 83, data bus line 84 (84-). 1 and 84-2), and a column signal line 85 is provided. Here, the sense line 81-1 to the data bus line 84 are also referred to as a data processing unit 90.

  Since the memory cell array 1 (including the memory cell 2) is the same as that of the first embodiment, the description thereof is omitted.

The first bit line 4 is provided so as to extend in the Y-axis direction (bit line direction) as the first direction, and one of the first bit lines 4 is connected to the first Y selector 71. Further, the first Y selector 71 extends to the data bus line 84. Here, the signal is described as BLiT (where i is an integer from 0 to n: the number of the first bit line 4).
The second bit line 5 is paired with the first bit line 4 and is provided extending in the Y-axis direction. One of the second bit lines 5 is connected to the second Y selector 72. Further, the second Y selector 72 extends to the data bus line 84. Here, the signal is referred to as BLiN (where i = 0 to n: the number of the first bit line 4).
The word line 3 is provided so as to extend in the X-axis direction (word line direction) as a second direction substantially perpendicular to the Y-axis direction, and is connected to the X selector 8. Here, the signal is referred to as WLk (where k is an integer from 0 to m: the number of the word line 3).
Each memory cell 2 is provided corresponding to each of positions where a plurality of sets of the first bit line 4 and the second bit line 5 and a plurality of word lines intersect.

The X selector 8 selects one word line 3 as the selected word line 3s from the plurality of word lines 3 in both the data read operation and the write operation.
The first Y selector 71 selects one first bit line 4 from the plurality of first bit lines 4 as a selected first bit line 4s during a data read operation and a write operation.
The second Y selector 72 selects one second bit line 5 from the plurality of second bit lines 5 as the selected second bit line 5s during the data write operation.
The sense amplifier 73 is provided in a region surrounded by the first bit line 4 and the second bit line 5 extending in the Y-axis direction, and the sense line 81-1 and the sense line 81-2 extending in the X-axis direction. Yes. Activated by the SAP signal from the sense lines 81-1 and 81-2, the potential difference between the first bit line 4 and the second bit line 5 is amplified at high speed.

The read current load circuit 74 is provided at a point where the first bit line 4 (or the reference first bit line 4) extending in the Y-axis direction and the read current signal line 82 extending in the X-axis direction intersect. . During a data read operation, the data is activated by an LDA signal from the read current signal line 82, and is supplied to the selected cell 2s (or reference cell 2r) via the selected first bit line 4s (or reference first bit line 4r). Apply current.
Here, the basic structure of the reference cell 2r is the same as that of the normal memory cell 2. However, the resistance value is a predetermined value (the voltage drop of the magnetoresistive element 7 having data “1” and the magnetoresistive element 7 having data “0” by the predetermined current flowing through the read current load circuit 13. And has a voltage drop that is intermediate to the voltage drop), and is referenced during the read operation of another memory cell 2.

The third transistor 77 has a gate connected to the comparison signal line 83, one of the other two terminals connected to the second bit line 5, and the other connected to the reference first bit line 4r. The signal is turned on by the input of the RTG signal from the comparison signal line 83, and the potential of the second bit line 5 is made the same as the potential of the reference first bit line 4r.
The column selection transistors 75-1 and 75-2 have gates connected to the column signal line 85, one of the other two terminals connected to the memory cell array 1 side of the first bit line 4 and the second bit line 5, and the other connected to the other. The first bit line 4 and the second bit line 5 are connected to the data bus line 84 side. Based on the YSWi signal from the column signal line 85 (where i is an integer from 0 to n: the number of the first bit line 4), the voltage (BLiT) of the first bit line 4 and the second bit line 5 The voltage (BLiN) is output to the data bus lines 84-1 and 84-2.
The reference selection transistors 76-1 and 76-2 have a gate to the column signal line 85 and one of the other two terminals to the memory cell array 1 side of the reference first bit line 4 r and the reference second bit line 5 r. The other is connected to the data bus line 84 side of the reference first bit line 4r and the reference second bit line 5r. Based on the RYSW signal from the column signal line 85, the voltage (BLRU) of the reference first bit line 4r and the voltage (BLRL) of the reference second bit line 5r are respectively sent to the data bus lines 84-1 and 84-2. Output.

  The sense lines 81 (81-1 and 81-2) output an SAP signal to the sense amplifier 73. The read current signal line 82 outputs an LDA signal to the read current load circuit 74. The comparison signal line 83 outputs an RTG signal to the third transistor 77. The data bus line 84 (84-1 and 84-2) acquires a voltage as data from the first bit line 4 and the second bit line 5. The column signal line 85 outputs a YSWi signal or a RYSW signal.

  Next, the operation of the twentieth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

FIG. 37 is a diagram showing changes in each signal (voltage) during the read operation of the MRAM in FIG. Here, the fact that each signal is in a “High” and “Low” state is simply referred to as H and L.
Reading data from the memory cell 2 is performed as follows.
A. Read Operation for 1 Selected Cell 2s Here, the memory cell 2 selected by the 0th first bit line 4 and second bit line 5 and the 0th word line is defined as a selected cell 2s.
(1) Step S171
At time tR1, the X selector 8 selects the selected word line 3s in response to the H input of the WL0 signal. At the same time, the first Y selector 71 selects the selected first bit line 4s in response to the H input of the RWTG signal. The selected cell 2s is selected by these operations. Further, the third transistor 77 is turned on by the input of the RTG signal H, and the data processing unit 90 side of the selected second bit line 5s paired with the selected first bit line 4s is connected to the reference first bit line 4r. Same potential.
(2) Step S172
At time tR2, the read current load circuit 74 connected to the selected first bit line 4s supplies a current Is having a predetermined magnitude to the selected first bit line 4s by the input of H of the LDA signal. Similarly, the read current load circuit 74 connected to the reference first bit line 4r supplies a current Ir having a predetermined magnitude to the reference first bit line 4r by the input of H of the LDA signal. The current Is flows into the ground line 24 via the respective magnetoresistive elements 7 in the selected cell 2s and the current Ir flows in the reference cell 2r.
At this time, at time tR3 (to tR5), a voltage reflecting data included in the magnetoresistive element 7 of the selected cell 2s appears as the BL0T signal. In addition, a voltage reflecting preset (fixed) data included in the magnetoresistive element 7 of the reference cell 2r appears as a BLRU signal.
Accordingly, at time tR3, the voltage BLS0T on the selected first bit line 4s side of the sense amplifier 81 between the selected first bit line 4s and the selected second bit line 5s becomes a voltage reflecting the BL0T signal. Similarly, the voltage BLS0N on the selected second bit line 5s side is a voltage reflecting the BLRU signal.
(3) Step S173
At time tR4, the LDA signal becomes L, and the current from each read current load circuit 74 stops. At time tR5, the RWTG signal and the RTG signal become L, and the data processing unit 90 and the memory cell array 1 are separated. At this time, the relative magnitude relationship between the voltage BLS0T and the voltage BLS0N of the sense amplifier 81 is maintained.
(4) Step S174
At time tR6, the sense amplifier 73 is activated by the H input of the SAP signal. Then, the voltage difference between the voltage BLS0T and the voltage BLS0N is amplified and becomes a voltage reflecting the read data (corresponding to the voltage BLS0T of the sense amplifier 81). For example, if the read data is “1”, the voltage BLS0T is amplified as indicated by “H” in the figure, and the voltage BLS0N is reduced as indicated by “L” in the figure. If “1”, the opposite is true.
(5) Step S175
At time tR7, the YSW0 signal is input, and the column selection transistor 75 is turned on. Thereby, the amplified or reduced voltage BLS0T is output to the data bus line 84-1, and the voltage BLS0N is output to the data bus line 84-2.
Then, between time tR7 and time tR8, the output / RIO signal of data bus line 84-1 and the output RIO signal of data bus line 84-2 are taken out.
(6) Step S176
The YSW0 signal becomes L at time tR8, and the SAP signal becomes L at time tR9. Accordingly, the voltage BLS0T and the voltage BLS0N become L at time tR10. At time tR11, the WL0 signal becomes L.

  With the above read operation, data of a desired selected cell 2s can be read.

B. Read Operation of All Memory Cells 2 on Selected Word Line 3s FIG. 38 is a diagram showing changes in signals (voltages) during the read operation of the MRAM in FIG. Referring to FIG. 37 and FIG. 38, the read operation of all the memory cells 2 on the selected word line 3s is performed as follows in step S175.

However, in this case, in FIG. 37, BL0T indicates BLkT (where k = 1 to n: n is the number of bit line pairs (first bit line 4 and second bit line 5)), and BLS0T and BLLS0N indicates BLSkT and BLLSkN (where k = 1 to n). YSW0, RIO, and / RIO are in the timing chart of FIG.
In addition, each sense amplifier 73 reads the data of the memory cells 2 on the selected word line 3s at a time from time tR2 to tR5. At time tR6, the amplified or reduced voltage BLSkT and voltage BLSkN are generated.

(5-1) Step S175-1
Time tR7 = time tR7_10 to time tR7_11,... Time tR7_k0 to time tR7_k1..., Time tR7_n0 to time tR7_n1 = time tR8. Input to 75. As a result, the kth column selection transistor 75 is turned on, and the amplified or reduced voltage BLSkT is output to the data bus line 84-1, and the voltage BLSkN is output to the data bus line 84-2. Then, as the output / RIO signal of the data bus line 84-1 and the output RIO signal of the data bus line 84-2, the data of the kth memory cell 2 is extracted from the time tR7_k0 to the time tR7_k1, and the time tR7_n0. To the time tR7_n1, the data of the nth memory cell 2 is taken out.

  That is, since the data of each memory cell 2 is read in batches to the sense amplifier 73, the data can be read continuously by activating the YSW signal continuously. Thereby, the throughput of reading data is improved.

  With the above read operation, the data of all the memory cells 2 on the desired selected word line 3s can be read at once.

FIG. 39 is a diagram showing changes in signals (voltages) during the write operation of the MRAM in FIG. Data is written to the memory cell 2 as follows.
A. Write Operation for 1 Selected Cell 2s Here, the memory cell 2 selected by the 0th first bit line 4 and second bit line 5 and the 0th word line is defined as a selected cell 2s.
(1) Step S181
At time tW10, the X selector 8 sets the WL0 signal to H and selects the selected word line 3s. At this time, the gate potentials of the first MOS transistor 6 and the second MOS transistor 16 are set higher by a predetermined voltage Vα than the normal power supply voltage. At the same time, the first Y selector 71 sets the RWTG signal to H and selects the selected first bit line 4s. Further, the second Y selector 72 sets the WTG signal to H and selects the selected second bit line 5s. The selected cell 2s is selected by these operations.
(2) Step S182
At time tW20, a DIO signal indicating data is input to data bus line 84-1, and an inverted signal / DIO signal of the DIO signal is input to data bus line 84-2. At the same time, the column selection transistors 75-1 and 75-2 are turned on by the input of H of the YSW0 signal. Thereby, the selected first bit line 4s and the selected second bit line 5s are selected on the data processing unit 90 side, and the DIO signal and the / DIO signal are input to each.
(3) Step S183
At time tW30, the potential of the selected first bit line 4s (voltage BLOT) and the potential of the selected second bit line 5s (voltage BLON) become potentials corresponding to data. Then, according to the difference between the voltage BLOT and the voltage BLON, writing is performed between the selected first bit line 4s and the selected second bit line 5s via the selected cell 2s (the first MOS transistor 6 and the second MOS transistor). Current for use flows. The write current flows according to the DIO signal and the / DIO signal.
(4) Step S184
At time tR40, the YSW0 signal becomes L, and the DIO signal and the / DIO signal are stopped. Thereby, the voltage BLOT and the voltage BLON become L. Thereby, the write operation is completed. At time tR50, the WL0 signal, the RWTG signal, and the WTG signal are set to L.

Data can be written to a desired selected cell 2s by the above write operation.
When it is not necessary to rewrite all the data on the selected word line 3s, this method activates the YSW signal while the selected word line 3s is activated and writes the data from the data bus line 84 without passing through the sense amplifier 73. Is preferable from the viewpoint of throughput and power consumption.

B. Write Operation of All Memory Cells 2 on Selected Word Line 3s FIG. 40 is a diagram showing changes in signals (voltages) during the write operation of the MRAM in FIG. The write operation of all the memory cells 2 on the selected word line 3s is performed as follows.
(1) Step S191
Selected word lines from k = 1 to n continuously for each period from time tW1-1 to time tW2-1, time tW1-k to time tW2-k, time tW1-n to time tW2-n Data (DIO signal and inverted signal / DIO signal / DIO signal) to be written in the kth memory cell 2 on 3s is input to the data bus lines 84-1 and 84-2, and the YSWk signal becomes H. Thereby, for each period, the kth column selection transistors 75-1 and 75-2 are turned on, and the voltage BLSOT and the voltage BLSON corresponding to the kth data are generated at both ends of the kth sense amplifier 73. .
(2) Step S192
At time tW2-n, all the sense amplifiers 73 are activated by the input of H of the SAP signal. Then, the larger one of the voltage BLSOT and the voltage BLSON is amplified, and the smaller one is reduced.
(3) Step S193
At time tW3, the X selector 8 sets the WL0 signal to H and selects the selected word line 3s. At this time, the gate potentials of the first MOS transistor 6 and the second MOS transistor 16 are set higher by a predetermined voltage Vα than the normal power supply voltage. At the same time, the first Y selector 71 sets the RWTG signal to H and selects all the selected first bit lines 4s. Further, the second Y selector 72 sets the WTG signal to H and selects all the selected second bit lines 5s. By these operations, all the memory cells 2 on the selected word line 3s are selected.
At this time, according to the difference between the voltage BLSOT and the voltage BLSON, the first MOS transistor 6 is connected between the first bit line 4s and the second bit line 5s in each of all the memory cells 2 on the selected word line 3s. A write current flows through the second MOS transistor. In this case, the current source of the write current is the sense amplifier 73.
Note that the predetermined voltage Vα is about an increase in the potential of the channel portion of the transistor due to the on-resistance of the transistor when a write current flows.
(4) Step S194
At time tR4, the WL0 signal, the RWTG signal, and the WTG signal are set to L. Thereby, the write operation is completed. At time tR5, the SAP signal and the SAN signal become L. Accordingly, the voltage BLS0T and the voltage BLS0N become L at time tR6.

  Through the above write operation, data can be written in a batch to all the memory cells 2 on the desired selected word line 3s. Thereby, the throughput of data processing is improved.

At the time of writing, the gate potentials of the first MOS transistor 6 and the second MOS transistor 16 are set higher by a predetermined voltage Vα than the normal power supply voltage, so that a larger write current can flow. This makes it possible to write data to the selected cell more reliably.
Normally, when a voltage higher than the power supply voltage is applied to the gate, a burden is applied to the gate oxide film. However, since a write current flows during writing, the on-resistance of the transistor increases the potential of the channel portion of the transistor. Because it is not a problem.

  According to the present invention, similarly to a DRAM, it is possible to perform a data read operation / write operation using a sense amplifier attached to each bit line (between the first bit line 4 and the second bit line 5). It becomes.

(Twenty-first embodiment)
A twenty-first embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  First, the configuration of the twenty-first embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 41 is a diagram showing the configuration of a twenty-first embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention. The MRAM according to the present embodiment includes a memory cell array 1, a plurality of first word lines 3c, a plurality of second word lines 3d, a plurality of first bit lines 4, a plurality of common second bit lines 5 ′, an X selector 8, A Y selector 11, a Y side current source circuit 12, a Y side power supply circuit 19, a read current load circuit 13 and a sense amplifier 15 are provided.

In the memory cell array 1, memory cells 2e are arranged in a matrix. Here, the memory cell 2 e includes a first MOS transistor 6, a second MOS transistor 16, and a magnetoresistive element 7. Note that the reference memory cell 2 is referred to as a reference cell 2er.
The first MOS transistor 6 as the first transistor has a gate (first gate) as the first word line 3c, a source (first terminal) as the first bit line 4, and a drain (second terminal) as the magnetoresistive element 7. Are connected to one end side (fourth terminal) and the drain (sixth terminal) of the second MOS transistor 16.
The second MOS transistor 16 has a gate (second gate) as the second word line 3d, a source (fifth terminal) as the common second bit line 5 ', and a drain (sixth terminal) as one end of the magnetoresistive element 7. (Fourth terminal) and the drain (second terminal) of the first MOS transistor 6 are connected.
During the read operation, the first MOS transistor 6 is used to connect the magnetoresistive element 7 to the first bit line 4 and to pass a current from the magnetoresistive element 7 to the first bit line 4. During the write operation, the first MOS transistor 6 and the second MOS transistor 16 are used to connect the first bit line 4 and the common second bit line 5 ′ to flow current near the magnetoresistive element 7.
The magnetoresistive element 7 has one end side (fourth terminal) connected to each of the transistors and the other end side (third terminal) connected to the ground wiring 24. It has spontaneous magnetization whose magnetization direction is reversed according to stored data.

The first bit line 4 is provided so as to extend in the Y-axis direction (bit line direction) as the first direction, and is connected to the Y selector 11. In FIG. 41, the left side of the common second bit line 5 is also referred to as a first bit line 4L, and the right side is also referred to as a first bit line 4R. The reference first bit line 4 is referred to as a reference first bit line 4r.
The common second bit line 5 forms a pair with the two first bit lines 4 disposed on both sides thereof, is provided extending in the Y-axis direction, and is connected to the Y-side power supply circuit 19. The reference second bit line 5 is referred to as a reference second bit line 5r.
The first word line 3c is provided so as to extend in the X-axis direction (word line direction) as a second direction substantially perpendicular to the Y-axis direction, and is connected to the X selector 8.
The second word line 3d is paired with the first word line 3c, is provided to extend in the X-axis direction (word line direction), and is connected to the X selector 8.
In each memory cell 2e, the set (plurality) of the first bit line 4 and the common second bit line 5 ′ and the set (plurality) of the first word line 3c and the second word line 3d intersect. It is provided corresponding to each position.

The X selector 8 selects one first word line 3c as a selected first word line 3cs from the plurality of first word lines 3c during a data read operation. In the data write operation, one first word line 3c is selected as the selected first word line 3cs from the plurality of first word lines 3c, and one second word is selected from the plurality of second word lines 3d. The line 3d is selected as the selected second word line 3ds.
The Y selector 11 selects one first bit line 4 from the plurality of first bit lines 4 as the selected first bit line 4s in both the data read operation and the data write operation.
However, the selected cell 2es is a memory cell 2e selected by the selected word line 3s, the selected first bit line 4s, and the selected common second bit line 5's.

The Y-side current source circuit 12 is a current source that supplies or draws a predetermined current to the selected first bit line 4s during a data write operation.
The Y-side power supply circuit 19 always supplies a predetermined voltage to the common second bit line 5 ′.
Here, the predetermined current by the Y-side current source circuit 12 corresponds to the selected first bit line 4s-selected cell 2es-selected common second bit line 5's (corresponding to the selected first bit line 4s) according to the data to be written. The common second bit line 5 ′) flows in the direction flowing into the Y selector 11 or flowing out from the Y selector 11.

The read current load circuit 13 supplies a predetermined current to the selected first bit line 4s during a data read operation. Similarly, a predetermined current is supplied to the reference first bit line 4r during a data read operation.
The sense amplifier 15 outputs the data read from the selected cell 2es based on the difference between the voltage of the reference first bit line 4r connected to the reference cell 2er and the voltage of the selected first bit line 4s connected to the selected cell 2es. .

  Here, the basic structure of the reference cell 2r is the same as that of the normal memory cell 2. However, the resistance value is a predetermined value (the voltage drop of the magnetoresistive element 7 having data “1” and the magnetoresistive element 7 having data “0” by the predetermined current flowing through the read current load circuit 13. And has a voltage drop that is intermediate to the voltage drop), and is referenced during the read operation of another memory cell 2.

42 is a view of the memory cell array of the MRAM shown in FIG. 41 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, 2 × 2 memory cells 2e in the memory cell array 1 are shown as representatives.
In the first MOS transistor 6 of the memory cell 2 e, the source 6 a (first terminal) is connected to the first bit line 4 via the contact wiring 28. The gate 6b (first gate terminal) uses the first word line 3c-1 branched from the first word line 3c in the Y-axis direction. The drain 6c (second terminal) is connected to the drain 16c (sixth terminal) of the second MOS transistor 16 through the contact wiring 27, the lead-out wiring layer 29, and the contact wiring 37. The second MOS transistor 16 uses a second word line 3d-2 whose gate 16b (second gate terminal) branches off from the second word line 3d in the Y-axis direction. The source 16 a (fifth terminal) is connected to the common second bit line 5 ′ via the contact wiring 38.
The memory cell 2e is arranged in a region surrounded by the first word line 3c, the second word line 3d, the first bit line 4, and the common second bit line 5 ′.
The magnetoresistive element 7 is provided on the lead wiring layer 29. The direction of spontaneous magnetization is reversed by the current flowing through the lead wiring layer 29. Since the current flowing through the lead wiring layer 29 flows in the X-axis direction, the direction of the magnetic field felt by the magnetoresistive element 7 is the Y-axis direction. In the present embodiment, the magnetization anisotropy of the magnetoresistive element 7 is inclined by a predetermined angle with respect to the Y axis. In the example of FIG. 41, the shape of the magnetoresistive element 7 is anisotropy, and the magnetoresistive element 7 is inclined 45 ° with respect to the Y axis. As a result, the write current can be set small, and the current consumption can be reduced (see the description in FIG. 18).
Even if the predetermined angle for tilting the magnetization anisotropy of the magnetoresistive element 7 with respect to the Y axis is slightly tilted with respect to the Y axis, it is effective. More preferably, it is 10 ° -80 °. More preferably, it is 30 to 60 degrees. The same effect can be obtained by tilting to the opposite side of the Y axis in the same manner.
The ground (GND) wiring 24 is provided above the memory cell array 1 shown in FIG. 41 so as to cover the entire memory cell array.

  Next, the operation of the twenty-first embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

Reading of data from the memory cell 2e is performed as follows.
(1) Step S201
The X selector 8 selects the selected first word line 3cs from the plurality of first word lines 3c in response to the input of the row address. The X-side power supply circuit 9 applies a predetermined voltage V1 to the selected word line 3s. The first MOS transistor 6 of each memory cell 2e is turned on.
(2) Step S202
The Y selector 11 selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. Then, in response to the read active signal RA, the read current load circuit 13 supplies a predetermined current Is to the selected first bit line 4s and a predetermined current Ir to the reference first bit line 4r.
At this time, a predetermined current Is flows from the read current load circuit 13 to the ground line 24 via the selected first bit line 4 s and the first MOS transistor 6 -magnetoresistance element 7 of the selected cell 2 s. Similarly, the first MOS transistor 6- of the read current load circuit 13-reference first bit line 4r-selected reference cell 2r (reference cell 2er corresponding to the intersection of the selected first word line 3cs and the reference first bit line 4r). A predetermined current Ir flows into the ground wiring 24 via the magnetoresistive element 7.
(3) Step S203
Based on the read active signal RA, the sense amplifier 15 outputs either “1” or “0” based on the difference between the voltage of the selected first bit line 4s and the voltage of the reference first bit line 4r.

  With the above read operation, the data of the selected cell 2es can be read.

  Data is written to the memory cell 2 as follows.

(1) Step S211
The X selector 8 selects the selected first word line 3cs from the plurality of first word lines 3c in response to the input of the row address. At the same time, the selected second word line 3ds paired with the selected first word line 3cs is selected from the plurality of second word lines 3d. The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2e connected to the selected first word line 3cs and the selected second word line 3ds are turned on.
(2) Step S212
The Y selector 11 selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. The Y-side power supply circuit 19 includes a plurality of common second bit lines 5 ′ (reference second) including a selected common second bit line 5 ′s (common second bit line 5 ′ paired with the selected first bit line 4s). A predetermined voltage Vterm is fixedly applied to the bit line 5r).
Based on the write active signal and the data signal (“1” or “0”), the Y-side current source circuit 12 causes the selected cell 2 es to have a current Iw (0) (Y side) having a predetermined magnitude corresponding to the data signal. Current Iw (1) (direction flowing out from the Y-side current source circuit 12).
The current Iw (0) or the current Iw (1) is generated by selecting the selected second bit line 5's-the second MOS transistor 16 of the selected cell 2es (-the lead wiring layer 29 of the selected cell 2es) -the first MOS transistor of the selected cell 2es. 6 Flow through the path of the selected first bit line 4s in the forward or reverse direction.
(3) Step S213
In the selected cell 2es, when the current Iw (0) (+ X direction) or the current Iw (1) (−X direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the −Y direction or + Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal Data is stored.

  With the above write operation, data can be written to the selected cell 2es.

  According to the present invention, it is possible to obtain the same effect as in the first embodiment (except that only one X-axis direction word line is sufficient).

  According to the present invention, the second bit line 5 can be shared by the two memory cells 2, and the circuit area can be reduced accordingly. Further, since the Y-side current termination circuit is not necessary, the circuit area can be reduced accordingly. That is, the chip size can be reduced, and the cost can be reduced.

(Twenty-second embodiment)
A twenty-second embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  First, the configuration of the twenty-second embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 43 is a diagram showing a configuration of a twenty-second embodiment of a magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. The MRAM of this embodiment includes a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4, an X selector 8, a Y selector 11, a Y-side power supply circuit 58, a read current load circuit 13, and a sense amplifier 15. It has.

In the memory cell array 1, memory cells 2f are arranged in a matrix. Here, the memory cell 2 f includes a first MOS transistor 6, a magnetoresistive element 7, and a capacitor 19. The reference memory cell 2f is referred to as a reference cell 2fr.
The first MOS transistor 6 as the first transistor has a gate (first gate) as the word line 3, a source (first terminal) as the first bit line 4, and a drain (second terminal) as one end of the magnetoresistive element 7. Side (fourth terminal) and one end of the capacitor 19.
The capacitor 19 has one end connected to the drain of the first MOS transistor 6 and the other end connected to the ground wiring 24.
During the read operation, the first MOS transistor 6 is used to connect the magnetoresistive element 7 to the first bit line 4 and to pass a current from the magnetoresistive element 7 to the first bit line 4. During the write operation, the first MOS transistor 6 is used to connect the first bit line 4 and the capacitor 19 to flow current near the magnetoresistive element 7.
The magnetoresistive element 7 has one end side (fourth terminal) connected to the first MOS transistor 6 and the other end side (third terminal) connected to the ground wiring 24. It has spontaneous magnetization whose magnetization direction is reversed according to stored data.

The first bit line 4 is provided so as to extend in the Y-axis direction (bit line direction) as the first direction, and is connected to the Y selector 11.
The word line 3 is provided so as to extend in the X-axis direction (word line direction) as a second direction substantially perpendicular to the Y-axis direction, and is connected to the X selector 8.
Each memory cell 2f is provided corresponding to each of the positions where the plurality of first bit lines 4 and the plurality of word lines 3 intersect.

The X selector 8 selects one word line 3 from the plurality of word lines 3 as a selected word line 3s during a data read / write operation.
The X-side power supply circuit 9 is a power supply that supplies a predetermined voltage to the selected word line 3s during a data read / write operation.
The Y selector 11 selects one first bit line 4 from the plurality of first bit lines 4 as a selected first bit line 4s during a data read / write operation.
The Y-side power supply circuit 58 supplies a predetermined voltage corresponding to the data to the selected first bit line 4s during the data write operation.

The read current load circuit 13 supplies a predetermined current to the selected first bit line 4s during a data read operation. Similarly, a predetermined current is supplied to the reference first bit line 4r during a data read operation.
Here, the basic structure of the reference cell 2r is the same as that of the normal memory cell 2. However, the resistance value is a predetermined value (the voltage drop of the magnetoresistive element 7 having data “1” and the magnetoresistive element 7 having data “0” by the predetermined current flowing through the read current load circuit 13. And has a voltage drop that is intermediate to the voltage drop), and is referenced during the read operation of another memory cell 2.
The sense amplifier 15 reads the data read from the selected cell 2s based on the difference between the voltage of the reference first bit line 4r connected to the reference memory cell 2r and the voltage of the selected first bit line 4s connected to the selected cell 2s. Is output.

FIG. 44 is a view of the memory cell array of the MRAM shown in FIG. In this figure, 2 × 2 memory cells 2 f in the memory cell array 1 are shown as representatives.
In the first MOS transistor 6 of the memory cell 2 f, the source 6 a (first terminal) is connected to the first bit line 4 via the contact wiring 28. The gate 6b (first gate terminal) uses the word line 3-1 branched from the word line 3 in the Y-axis direction. The drain 6 c (second terminal) is connected to the capacitor 19 and the magnetoresistive element 7 through the contact wiring 27 and the lead-out wiring layer 29.
The ground wiring 24 is paired with each of the plurality of word lines 3 and extends in parallel with the word lines 3 in the X-axis direction. A ground wiring 24-1 branched for each memory cell 2f is included. The ground wiring 24-1 in each memory cell 2f is connected to the magnetoresistive element 7 and the capacitor 19.
The magnetoresistive element 7 is provided on the lead wiring layer 29. The direction of spontaneous magnetization is reversed by the current flowing through the lead wiring layer 29. Since the current flowing through the lead wiring layer 29 flows in the X-axis direction, the direction of the magnetic field felt by the magnetoresistive element 7 is the Y-axis direction. In the present embodiment, the magnetization anisotropy of the magnetoresistive element 7 is inclined by a predetermined angle with respect to the Y axis. In the example of FIG. 43, the shape of the magnetoresistive element 7 is anisotropy, and the magnetoresistive element 7 is inclined 45 ° with respect to the Y axis. As a result, the write current can be set small, and the current consumption can be reduced (see the description in FIG. 18).
Even if the predetermined angle for tilting the magnetization anisotropy of the magnetoresistive element 7 with respect to the Y axis is slightly tilted with respect to the Y axis, it is effective. More preferably, it is 10 ° -80 °. More preferably, it is 30 to 60 degrees. The same effect can be obtained by tilting to the opposite side of the Y axis in the same manner.

FIG. 45 shows the structure of the memory cell 2f and shows a cross section GG ′ in FIG.
The first MOS transistor 6 is formed on the surface portion of the semiconductor substrate. A source 6a as a first diffusion layer provided in the semiconductor substrate is connected to the first bit line 4 via a contact wiring 28 extending in the Z-axis direction. The drain 6c as the second diffusion layer is connected to one lower end of the lead wiring layer 29 through a contact wiring 27 extending upward in the Z-axis direction. The gate 6 b as the first gate uses the word line 3-1 branched from the word line 3. However, the drain 6c is provided inside the memory cell 2a with respect to the source 6a.
The magnetoresistive element 7 is connected to the upper side of the lead wiring layer 29 on one end side. The other end side is connected to the lower side of the ground wiring 24-1 branched from the ground (GND) line 24 through the contact wiring 26.
The capacitor 19 is connected to the upper part of the other end of the lead-out wiring layer 29 through a contact wiring 59 extending downward on one end side, and to the wiring layer 60 provided to cover the upper end of the other end side. The wiring layer 60 is connected to the ground wiring 24-1 at one end by a contact wiring 61 extending below the wiring layer 60.

  Next, the operation of the twenty-second embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described with reference to FIG.

Reading data from the memory cell 2f is performed as follows.
(1) Step S221
The Y selector 11 selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. The selected first bit line 4s is set to a predetermined intermediate potential Vm.
(2) Step S222
The X selector 8 selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. However, the X selector 8 increases the voltage little by little and applies the predetermined voltage V1 to the selected word line 3s over a predetermined time. The predetermined time is selected so that the current flowing into the capacitor 19 when the capacitor 19 of the memory cell 2f is charged with the predetermined intermediate potential Vm is so small that the magnetoresistive element 7 cannot be written. The capacitor 19 is charged after a predetermined time.
(3) Step S223
In response to the read active signal RA, the read current load circuit 13 supplies a predetermined current Is to the selected first bit line 4s and a predetermined current Ir to the reference first bit line 4r.
At this time, the current Is flows from the read current load circuit 13 to the ground wiring 24 via the selected first bit line 4 s and the first MOS transistor 6 -magnetoresistance element 7 of the selected cell 2 fs. Similarly, the first MOS transistor 6 of the read current load circuit 13-reference first bit line 4r-selected reference cell 2r (reference cell 2fr corresponding to the intersection of the selected word line 3s and the reference first bit line 4r) 6-magnetic resistance A current Ir flows into the ground wiring 24 via the element 7.
(4) Step S224
Based on the read active signal RA, the sense amplifier 15 outputs either “1” or “0” based on the difference between the voltage of the selected first bit line 4s and the voltage of the reference first bit line 4r.

  With the above read operation, data of the selected cell 2fs can be read.

  Data is written to the memory cell 2 as follows.

(1) Step S231
The Y selector 11 selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. The selected first bit line 4s is set to a predetermined intermediate potential Vm.
(2) Step S232
The X selector 8 selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. The capacitor 19 is charged with the intermediate potential Vm.
(3) Step S233
The Y-side power supply circuit 58 applies a voltage having a predetermined magnitude corresponding to the data signal to the selected cell 2fs based on the write active signal WA and the data signal (“1” or “0”). For example, in the case of the data signal Data “1”, the voltage is higher than the intermediate potential Vm, and in the case of “0”, the voltage is lower than the intermediate potential Vm. Accordingly, when the voltage is higher than the intermediate potential Vm, the current Iw (1) (the direction of flowing out from the Y-side power supply circuit 58) accompanying the storage of the capacitor 19 is lower than the intermediate potential Vm. , A current Iw (0) (in the direction of being drawn into the Y-side power supply circuit 58) flows along with discharge from the capacitor 19.
(4) Step S234
In the selected cell 2fs, when the current Iw (0) (+ X direction) or the current Iw (1) (−X direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the −Y direction or + Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal is stored.

  With the above write operation, data can be written to the selected cell 2fs.

  According to the present invention, it is possible to obtain the same effect as in the first embodiment (except that only one X-axis direction word line is sufficient).

  The currents Iw (0) and Iw (1) in the write operation do not flow in the memory cell 2 other than the selected cell 2s and in the vicinity thereof, and do not affect the other memory cell 2, so that the memory cell 2 The selectivity at the time of selection and the reliability of the memory cell can be improved.

  Unlike the conventional technique, the X selector 8 of the present embodiment performs selection in the X-axis direction using only the word line 3. Therefore, the circuit area of the X selector 8 and the circuit area of one type of word line can be reduced. In addition, since the Y-side current termination circuit is not used, the circuit area can be reduced. That is, the chip size can be reduced.

  Further, as shown in FIG. 45, in the selected cell 2fs, the magnetoresistive element 7 and the lead wiring layer 29 are very close to each other, and therefore, write currents Iw (0) and Iw (1) passing through the lead wiring layer 29 are generated. It becomes possible to make it smaller.

  Each X selector, each Y selector, each Y side current termination circuit, each Y side current source circuit, each read current load circuit, each sense amplifier, each cell array selector, etc. in each embodiment is shown in each figure. It is not limited to the circuit shown. With respect to these, circuits having other configurations can be used as appropriate within the scope of the technical idea of the present invention.

(Twenty-third embodiment)
A twenty-third embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

  First, the configuration of the twenty-third embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 46 is a diagram showing the configuration of a twenty-third embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention. The MRAM according to the present embodiment includes a memory cell array 10, a plurality of write word lines 3W, a plurality of read word lines 3R, a plurality of bit lines 4, a write X selector 8-1, a read X selector 8-2, and an X-side power supply circuit. 9, a Y selector 11, a Y-side voltage source circuit 12v, a read current load circuit 13, and a sense amplifier 15.

  In the memory cell array 10, memory cells 30 are arranged in a matrix. Here, the memory cell 30 includes a first diode 31, a second diode 32, a third diode 33, and the magnetoresistive element 7. The reference memory cell 30 is referred to as a reference cell 30r. In the reference cell 30r, “0” is written, and usually no write operation is performed.

The second diode 32 includes a first terminal having a first polarity (p pole) and a second terminal having a second polarity (n pole). The third diode 33 includes a third terminal having a first polarity (p pole) and a fourth terminal having a second polarity (n pole). The second terminal and the third terminal are connected to the write word line 3W. The first terminal and the fourth terminal are connected to the bit line 4 and the magnetoresistive element 7. The second diode 32 and the third diode 33 are used to connect the bit line 4 and the write word line 3W to cause a current to flow in the vicinity of the magnetoresistive element 7 during a write operation.
The first diode 31 includes a seventh terminal having a first polarity (p pole) and an eighth terminal having a second polarity (n pole). The first diode 31 has a seventh terminal connected to the magnetoresistive element 7 and an eighth terminal connected to the read word line 3R. The first diode 31 is used to connect the bit line 4 and the read word line 3R and allow a current to flow through the magnetoresistive element 7 in a predetermined direction during a read operation.

Here, the characteristics of each diode will be described. FIG. 47 is a graph illustrating the characteristics of the diode. The vertical axis represents the current flowing through the diode. The horizontal axis is the voltage applied to the diode. Vth indicates a forward threshold voltage, and Vbd indicates a reverse breakdown voltage.
FIG. 47A shows the characteristics of one diode. The absolute value of the threshold voltage Vth (example: 0.7V) is smaller than the absolute value of the breakdown voltage Vbd.
FIG. 47B shows characteristics when the second diode 32 and the third diode 33 are connected in parallel in opposite directions (see the memory cell 30). That is, one end side connects the first terminal and the fourth terminal, and the other end side connects the second terminal and the third terminal. In either case, terminals having different characteristics are connected to each other. In this case, the voltage applied between the one end side and the other end side is forward in any diode. Therefore, in the case of the + direction voltage, it has a threshold voltage Vth + (example: + 0.7V), and in the case of the − direction voltage, it has a threshold voltage Vth− (example: −0.7V). That is, it can be regarded as a switching element that is turned off if the applied voltage Vin is Vth− <Vin <Vth +, and turned on otherwise.

  Referring to FIG. 46, magnetoresistive element 7 includes a fifth terminal as one terminal and a sixth terminal as the other terminal. The fifth terminal is connected to the first terminal, the fourth terminal, and the bit line 4, and the sixth terminal is connected to the read word line 3R. It has spontaneous magnetization whose magnetization direction is reversed according to stored data.

The bit line 4 is provided so as to extend in the Y-axis direction (bit line direction) as the first direction, and is connected to the Y selector 11. The reference bit line 4 is referred to as a reference first bit line 4r.
The write word line 3W is provided so as to extend in the X-axis direction (word line direction) as a second direction substantially perpendicular to the Y-axis direction. The write X selector 8-1 is connected.
The read word line 3R is paired with the write word line 3W and is provided to extend in the X-axis direction (word line direction). The read X selector 8-2 is connected.
Each of the memory cells 20 is provided corresponding to each of the positions where the bit line 4 and a plurality of sets of the write word line 3W and the read word line 3R intersect.

The write X selector 8-1 precharges a plurality of write word lines 3W to an intermediate potential Vhalf (for example, power supply voltage = 2.5V and Vhalf = 1.25V). Then, during the data write operation, one write word line 3W is selected as the selected write word line 3Ws from the plurality of write word lines 3W. At this time, the selected write word line 3Ws is set to a potential of Vh + or Vh− according to the write data (D). For example, Vh + is 1.75V and Vh− is 0.75V.
The read X selector 8-2 precharges the plurality of read word lines 3R to an intermediate potential Vhalf (eg, Vhalf = 1.25V). Then, during the data read operation, one read word line 3R is selected as the selected read word line 3Rs from the plurality of read word lines 3R. At that time, the selected read word line 3Rs is set to a potential of Vh− (example: Vh− = 0.75V).
The Y selector 11 precharges the plurality of bit lines 4 to an intermediate potential Vhalf (example: Vhalf = 1.25 V). Then, during the write operation and the read operation, one bit line 4 is selected as the selected bit line 4s from the plurality of bit lines 4. During the write operation, the selected bit line 4s is set to Vh− or Vh + having a potential opposite to that of the selected write word line 3Ws. During the read operation, the selected bit line 4s is set to a potential of Vh + (example: Vh + = 1.75V).
Here, the memory cell 30 selected by the selected write / read word line 3Ws / 3Rs and the selected bit line 4s is referred to as a selected cell 30s.

The Y-side voltage source circuit 12v is a power source that supplies a predetermined voltage to the Y selector 11 (selected bit line 4s) during a data write operation.
The read current load circuit 13 is a power source that supplies a predetermined voltage to the Y selector 11 (selected bit line 4s) and the reference bit line 4r during a data read operation.
The sense amplifier 15 reads data from the selected cell 30s based on the difference between the current flowing through the reference bit line 4r connected to the reference cell 30r and the current flowing through the selected bit line 4s connected to the selected cell 30s, and outputs the data. To do.
The X-side power supply circuit 9 supplies a predetermined voltage (precharge voltage Vhalf, write / read voltage Vh + or Vh−) to the write X selector 8-1 and the read X selector 8-2.

FIG. 48 is a view of the memory cell array of the MRAM shown in FIG. 46 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, 2 × 2 memory cells 30 in the memory cell array 10 are representatively shown.
The second diode 32 of the memory cell 30 is provided between the lead-out wiring layer 29 and the write word line 3W via the contact wiring 55 and the third diode 33 via the contact wiring 56, respectively. The first diode 31 is provided between the read word line 3 </ b> R and the magnetoresistive element 7 via the contact wiring 54.

The magnetoresistive element 7 is provided on the lead wiring layer 29. The direction of spontaneous magnetization is reversed by the current flowing through the lead wiring layer 29. Here, since the current flowing through the lead wiring layer 29 flows in the Y-axis direction, the direction of the magnetic field felt by the magnetoresistive element 7 is the X-axis direction. Therefore, it is provided in a shape that facilitates magnetization in the X-axis direction. For example, an ellipse having a long axis parallel to the X-axis direction or a shape similar to an ellipse.
The lead wiring layer 29 is connected to the bit line 4 through the contact 53.

FIG. 49 shows the structure of the memory cell 30 and shows a cross section gg ′ in FIG.
The memory cell 30 is provided on an interlayer insulating film 35 provided on the surface of the substrate 10. The bit line 4 is provided on the substrate 10 via an interlayer insulating film 35. The substrate 10 extends in the Y-axis direction in parallel with the surface of the substrate 10. The lead wiring layer 29 is connected to the bit line 4 at one end through a contact wiring 53 extending from the bit line 4 in a direction away from the substrate 10. It is parallel to the surface of the substrate 10. The second diode 32 includes a first terminal having a first polarity (p) and a second terminal having a second polarity (n). It extends from the lead wiring layer 29 in a direction away from the substrate 10 and is provided in the middle of the contact wiring 55. The third diode 33 includes a third terminal having a first polarity (p) and a fourth terminal having a second polarity (n). It is provided in the middle of the contact wiring 56 extending from the lead-out wiring layer 29 in a direction away from the substrate 10. The magnetoresistive element 7 includes a fifth terminal and a sixth terminal. The fifth terminal is connected to the lead wiring layer 29. The first diode 31 includes a seventh terminal having a first polarity (p) and an eighth terminal having a second polarity (n). It is provided in the middle of the contact wiring 54 extending from the sixth terminal of the magnetoresistive element 7 in the direction away from the substrate 10. The write word line 3W is connected to the second terminal of the second diode 32 through the contact wiring 55 and is connected to the third terminal of the third diode 33 through the contact wiring 56. The substrate 10 extends in the X-axis direction in parallel with the surface of the substrate 10. The read word line 3 </ b> R is connected to the seventh terminal of the first diode 31 through the contact wiring 54. The substrate 10 extends in the X-axis direction in parallel with the surface of the substrate 10.
The position of the fifth terminal in the lead-out wiring layer 29 is at a position where the contact wiring 53 and the lead-out wiring layer 29 are connected to each other than a position where each of the contact wiring 55 and the contact wiring 56 is connected to the lead-out wiring layer 29. close.

  With this configuration, data can be written to the magnetoresistive element 7 in contact with the lead-out wiring layer 29 when a current flows through the path of the bit line 4-lead-out wiring layer 29 -second diode 32 or third diode 33. Become.

The memory cell 30 in FIG. 49 does not use an element (example: MOS transistor) on the substrate 10 (example: silicon). Accordingly, the memory cells 30 can be provided by being stacked. This is shown in FIG.
FIG. 50 is a diagram showing a cross-sectional structure when the memory cells 30 are stacked. In this case, two layers are stacked. As described above, the memory cell 30 in this embodiment can be provided in a plurality of layers in the Z-axis direction. Therefore, the effective cell area can be reduced.

  Next, the operation of the twenty-third embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

Reading data from the memory cell 30 is performed as follows. However, the write word line 3W, the read word line 3R, and the bit line 4 are precharged to an intermediate potential Vhalf (for example, power supply voltage = 2.5V, Vhalf = 1.25V).
(1) Step S241
The read X selector 8-2 selects the selected read word line 3Rs from the plurality of read word lines 3R by the input of the row address and the RA (Read Active) signal. Then, the selected read word line 3Rs is set to a potential of Vh− (example: Vh− = 0.75V).
(2) Step S242
The Y selector 11 selects the selected bit line 4s from the plurality of bit lines 4 in response to the column address input. Then, the selected bit line 4s is set to a potential of Vh + (example: Vh + = 1.75V).
As a result, the potential of Vh− by the read X selector 8-2 and the potential of Vh + by the Y selector 11 are applied to the selected cell 30s. This potential difference ((Vh +) − (Vh −) = 1.0 V) is set to be larger than the threshold voltage Vth (example: 0.7 V) of the first diode 31 (see FIG. 47A). ). Therefore, the data of the selected cell 30s is reflected in the path of the read X selector 8-2-selected read word line 3Rs-selected cell 30s (the magnetoresistive element 7) -selected bit line 4s-Y selector 11-sense amplifier 15. A current Is flows. Similarly, the data “0” of the reference cell 30r is reflected in the path of the read X selector 8-2-selected read word line 3Rs-reference cell 30r (the magnetoresistive element 7) -reference bit line 4r-sense amplifier 15. Current Ir flows.
(3) Step S243
Based on the difference between the current Is and the current Ir, the sense amplifier 15 sets the read data to “0” if they are the same within a preset value range, and “1” if they are different (example: smaller). And output the result.

  Through the above read operation, data of the selected cell 30s can be read.

  Data is written to the memory cell 2 as follows. However, the write word line 3W, the read word line 3R, and the bit line 4 are precharged to the intermediate potential Vhalf (for example, power supply voltage = 2.5V, Vhalf = 1.25V).

(1) Step S251
The write X selector 8-1 selects a selected write word line 3Ws from a plurality of write word lines 3W by inputting a row address and a WA (Write Active) signal. Then, the selected write word line 3Ws is set to a potential of Vh + or Vh− according to the write data (D). For example, Vh + is 1.75V and Vh− is 0.75V.
(2) Step S252
The Y selector 11 selects the selected bit line 4s from the plurality of bit lines 4 in response to the column address input. Then, the selected bit line 4s is set to a potential of Vh− or Vh + opposite to the potential of the selected write word line 3Ws.
As a result, the potential Vh + or Vh− by the write X selector 8-1 and the potential Vh− or Vh + by the Y selector 11 are applied to the selected cell 30s. This potential difference ((Vh + or Vh −) − (Vh− or Vh +) = ± 1.0 V) is the threshold voltage Vth + or Vth− (example: when the second diode 32 and the third diode 33 are connected in parallel). It is set to be larger than ± 0.7 V) (see FIG. 47B). Therefore, in the path of write X selector 8-1 -select write word line 3 Ws -selected cell 30 s (near the magnetoresistive element 7) -selected bit line 4 s -Y selector 11, a predetermined magnitude corresponding to the data signal D Current Iw (0) (in the case of “0”: direction toward the Y selector 11) or current Iw (1) (in the direction of “1”, direction toward the write selector 8-1) flows.
(3) Step S253
In the selected cell 30s, when the current Iw (1) (+ Y direction) or the current Iw (0) (−Y direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the + X direction or −X Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal D is stored.

With the above write operation, data can be written to the selected cell 30s.
In this case, it is possible to pass a current only to the selected cell during the write operation and the read operation. Since the current flows only in the selected cell to be written, the problem of multiple selection can be eliminated.

According to the present embodiment, the same effect as that of the first embodiment can be obtained.
Further, since no element on the silicon substrate is used, the memory cell 30 can be stacked. In addition, the effective cell area can be reduced.

(24th Embodiment)
A twenty-fourth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  The configuration of the twenty-fourth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 51 is a diagram showing a configuration of a twenty-fourth embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention. FIG. 51 shows a configuration in which the circuit example of the MRAM shown in FIG. 46 is hierarchized. The MRAM according to the present embodiment includes cell arrays 41d-0 to 41d-3, a cell array selector 17a, a Y-side voltage source circuit 12, a read current load circuit 13, and a sense amplifier 15.

The cell array 41d-i (an integer from 0 to 3) includes a memory cell array 30, a plurality of write word lines 3W, a plurality of read word lines 3R, a plurality of bit lines 4 (including a reference first bit line 4r), and a write An X selector 8-1, a read X selector 8-2, a Y selector 11d, and a reference Y selector 11r are provided. Since each configuration is the same as that of the twenty-third embodiment, its description is omitted. However, the Y selector 11d is the same as the Y selector 11, but does not have a function of selecting the reference bit line 4 in the Y selector 11. The reference Y selector 11r has a function of selecting the reference bit line 4. Here, the precharge voltage Vhalf for each selector is supplied to each selector by a power source (not shown). The read X selector 8-2 is supplied with a Vh− potential from an X-side power supply circuit 9 (not shown) during a read operation.
In FIG. 51, four cell arrays 41d are shown, but the present invention is not limited to this number.

  The cell array selector 17a selects the selected cell array 41d-i by the selector transistors 17a-1 to 17a-3 based on the cell array selection signal MWSi (i = 0 to 3: the number of the cell array 41d) for selecting the cell array 41d. . The selected cell array 41d-i is connected to the Y-side voltage source circuit 12v, the read current load circuit 13, and the sense amplifier 15 by the first main bit line 62, the second main bit line 63, and the third main bit line 64, respectively. The same operation as in the twenty-third embodiment is performed.

  The Y-side current source circuit 12v, the read current load circuit 13 and the sense amplifier 15 are the same as those in the twenty-third embodiment except that they are outside the cell array 41d and are common to the cell arrays 41d-i. Omitted.

  Next, the operation of the twenty-fourth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained. However, WA is a write active signal, RA is a read active signal, and SR is a signal that activates the reference cell 30r when writing to the reference cell 30r. The same applies throughout this specification.

In the MRAM shown in FIG. 51, data is read from the memory cell 30 as follows. However, the write word line 3W, the read word line 3R, and the bit line 4 are precharged to an intermediate potential Vhalf (for example, power supply voltage = 2.5V, Vhalf = 1.25V).
(1) Step S261
The cell array selector 17a selects the corresponding selector transistors 17a-1, 17a- based on the cell array selection signal MWSi for selecting any one of the cell arrays 41d-i (i = 0 to n: n is the number of the selector array). 2 and 17a-3 are turned on, and the selected cell array 41d-i is selected.
At this time, the selected cell array 41d-i, the read current load circuit 13 and the sense amplifier 15 are connected by the first main bit line 62 and the second main bit line 63.
(2) Step S262
The read X selector 8-2 selects the selected read word line 3Rs from the plurality of read word lines 3R by the input of the row address and the RA signal. Then, the selected read word line 3Rs is set to a potential of Vh− (example: Vh− = 0.75V).
(3) Step S263
The Y selector 11d selects the selected bit line 4s from the plurality of bit lines 4 in response to the column address input. Then, the selected bit line 4s is set to a potential of Vh + (example: Vh + = 1.75V). The potential Vh + is applied by the read current load circuit 13 via the first main bit line 62.
The reference Y selector 11r sets the reference bit line 4r to a potential of Vh + (example: Vh + = 1.75V) in response to the input of the RA signal. The potential Vh + is applied by the read current load circuit 13 through the second main bit line 63.
As a result, the potential of Vh− by the read X selector 8-2 and the potential of Vh + by the Y selector 11d are applied to the selected cell 30s. This potential difference ((Vh +) − (Vh −) = 1.0 V) is set to be larger than the threshold voltage Vth (example: 0.7 V) of the first diode 31. Accordingly, in the path of the read X selector 8-2-selected read word line 3Rs-selected cell 30s (the magnetoresistive element 7) -selected bit line 4s-Y selector 11d-cell array selector 17a-sense amplifier 15, the selected cell 30s A current Is reflecting the data flows. Similarly, the path of the read X selector 8-2-selected read word line 3Rs-reference cell 30r (the magnetoresistive element 7) -reference bit line 4r-reference Y selector 11r-cell array selector 17a-sense amplifier 15 has a reference path. A current Ir reflecting data “0” of the cell 30r flows.
(3) Step S264
Based on the difference between the current Is and the current Ir, the sense amplifier 15 sets the read data to “0” if they are the same within a preset value range, and “1” if they are different (example: smaller). And output the result.

  With the above read operation, the data of the desired selected cell 30s in the desired selected cell array 41d-i can be read.

  Data is written to the memory cell 30 as follows. However, the write word line 3W, the read word line 3R, and the bit line 4 are precharged to the intermediate potential Vhalf (for example, power supply voltage = 2.5V, Vhalf = 1.25V).

(1) Step S271
The cell array selector 17a turns on the corresponding selector transistors 17a-1, 17a-2, and 17a-3 based on the cell array selection signal MWSi for selecting any one of the cell arrays 41d-i, and selects the selected cell array 41d-i. Select.
At this time, the selected cell array 41d-i is connected to the Y-side voltage source circuit 12v and the sense amplifier 15 by the first main bit line 62 to the third main bit line 64.
(2) Step S272
The write X selector 8-1 selects the selected write word line 3Ws from the plurality of write word lines 3W based on the input of the row address and the WA signal. Then, the selected write word line 3Ws is set to a potential of Vh + or Vh− according to the write data (D). For example, Vh + is 1.75V and Vh− is 0.75V. The potential of Vh + or Vh− is applied by the Y-side voltage source circuit 12v through the third main bit line 64.
(3) Step S273
The Y selector 11d selects the selected bit line 4s from the plurality of bit lines 4 in response to the column address input. Then, the selected bit line 4s is set to a potential of Vh− or Vh + opposite to the potential of the selected write word line 3Ws. The potential of Vh− or Vh + is applied by the Y-side voltage source circuit 12v through the first main bit line 62.
As a result, the potential of Vh + or Vh− by the write X selector 8-1 and the potential of Vh− or Vh + by the Y selector 11 are applied to the selected cell 30s. This potential difference ((Vh + or Vh −) − (Vh− or Vh +) = ± 1.0 V) is the threshold voltage Vth + or Vth− (example: when the second diode 32 and the third diode 33 are connected in parallel). It is set to be larger than ± 0.7V). Therefore, in the path of write X selector 8-1 -select write word line 3 Ws -select cell 30 s (near the magnetoresistive element 7) -select bit line 4 s -Y selector 11 d -cell array selector 17 a -Y side voltage source circuit 12 v. , Current Iw (0) having a predetermined magnitude corresponding to the data signal D (in the case of “0”: direction toward the Y selector 11d) or current Iw (1) (in the case of “1”, the write selector 8-1 Direction).
(3) Step S274
In the selected cell 30s, when the current Iw (1) (+ Y direction) or the current Iw (0) (−Y direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the + X direction or −X Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal D is stored.

  Through the above write operation, data can be written to the desired selected cell 2s in the desired selected cell array 41d-i.

  When writing to the reference cell 2r, the reference bit line 4r is selected by the reference Y selector 11r together with the input of the reference active signal SR.

  According to this embodiment, the same effect as that of the twenty-third embodiment can be obtained. Further, the MRAM can be made compact by hierarchizing the cell array and sharing some circuits.

(25th embodiment)
A twenty-fifth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  First, the configuration of the twenty-fifth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained. FIG. 52 is a diagram showing the configuration of the twenty-fifth embodiment of a magnetic random access memory (MRAM) including magnetic memory cells of the present invention. The MRAM according to the present embodiment includes a memory cell array 10, a plurality of write word lines 3W, a plurality of read word lines 3R, a plurality of first bit lines 4, a plurality of second bit lines 5, an X selector 8, a Y selector 11, A Y-side voltage source circuit 12v, a read current load circuit 13, a Y-side current termination circuit 14, a Y-side power supply circuit 19 and a sense amplifier 15 are provided.

  In the memory cell array 10, memory cells 20j are arranged in a matrix. Here, the memory cell 20 j includes the first MOS transistor 6, the magnetoresistive element 7, and the first diode 31. The reference memory cell 20j is referred to as a reference cell 20r. In the reference cell 20r, “0” is written, and usually no write operation is performed.

The first MOS transistor 6 as the first transistor has a gate (first gate) as the write word line 3W, a source (first terminal) as the first bit line 4, and a drain (second terminal) as the magnetoresistive element 7. It is connected to one end side (fourth terminal) and the second bit line 5. The first MOS transistor 6 is used to select one of the memory cells 20j during the write operation and the read operation.
The magnetoresistive element 7 has one end side (fourth terminal) connected to the drain of the first MOS transistor 6 and the other end side (third terminal) connected to the fifth terminal of the first diode 31. It has spontaneous magnetization whose magnetization direction is reversed according to stored data.
The first diode 31 includes a fifth terminal having a first polarity (p pole) and a sixth terminal having a second polarity (n pole). The first diode 31 has a fifth terminal connected to the magnetoresistive element 7 and a sixth terminal connected to the read word line 3R. The first diode 31 is used to connect the first bit line 4 and the read word line 3R to flow a current in a predetermined direction through the magnetoresistive element 7 during a read operation. The first diode 31 is as described in the twenty-third embodiment (FIG. 47).

The first bit line 4 is provided so as to extend in the Y-axis direction (bit line direction) as the first direction, and is connected to the Y selector 11. The reference first bit line 4 is referred to as a reference first bit line 4r.
The second bit line 5 is paired with the first bit line 4, is provided extending in the Y-axis direction, and is connected to the Y-side current termination circuit 14. The reference second bit line 5 is referred to as a reference second bit line 5r.
The write word line 3W is provided so as to extend in the X-axis direction (word line direction) as a second direction substantially perpendicular to the Y-axis direction, and is connected to the X selector 8.
The read word line 3R is paired with the write word line 3W, is provided to extend in the X-axis direction (word line direction), and is connected to the X selector 8.
Each of the memory cells 20j has a position where a plurality of sets of the first bit line 4 and the second bit line 5 and a plurality of sets of the write word line 3W and the read word line 3R intersect each other. It is provided corresponding to.

The X selector 8 precharges the plurality of read word lines 3R to an intermediate potential Vhalf (for example, power supply voltage = 2.5V and Vhalf = 1.25V). During the data write operation, one write word line 3W is selected as the selected write word line 3Ws from the plurality of write word lines 3W. In the read operation, one write word line 3W is selected as the selected write word line 3Ws from the plurality of write word lines 3W. At the same time, one read word line 3R is selected as a selected read word line 3Rs from the plurality of read word lines 3R. At that time, the selected read word line 3Rs is set to a potential of Vh− (example: Vh− = 0.75V).
The Y selector 11 precharges the plurality of first bit lines 4 to an intermediate potential Vhalf (example: Vhalf = 1.25 V). Then, during the write operation, one first bit line 4 is selected from the plurality of first bit lines 4 as the selected first bit line 4s. At this time, the selected first bit line 4s is set to a potential of Vh + or Vh− according to the write data (D). For example, Vh + is 1.75V and Vh− is 0.75V. In the read operation, one first bit line 4 is selected from the plurality of first bit lines 4 as the selected first bit line 4s. At this time, the selected bit line 4s is set to a potential of Vh + (example: Vh + = 1.75V).
The Y-side current termination circuit 14 precharges the plurality of second bit lines 5 to the intermediate potential Vhalf (for example, Vhalf = 1.25 V). Then, during the data write operation, one second bit line 5 paired with the selected first bit line 4s is selected as the selected second bit line 5s from the plurality of second bit lines 5. The potential is set to Vh− or Vh + which is opposite to the potential of the selected first bit line 4s.
Here, the memory cell 20j selected by the selected write / read word line 3Ws / 3Rs and the selected first / second bit line 4s / 5s is referred to as a selected cell 20js.

The Y-side voltage source circuit 12v supplies a predetermined voltage to the Y selector 11 (selected first bit line 4s) during a data write operation.
The Y-side power supply circuit 19 supplies a predetermined voltage to the Y-side current termination circuit 14 (selected second bit line 5s) during a data write operation.
The read current load circuit 13 is a power source that supplies a predetermined voltage to the Y selector 11 (selected bit line 4s) and the reference bit line 4r during a data read operation.
The sense amplifier 15 reads data from the selected cell 20js based on the difference between the current flowing through the reference bit line 4r connected to the reference cell 20r and the current flowing through the selected bit line 4s connected to the selected cell 20js, and outputs the data. To do.
The X-side power supply circuit 9 supplies a predetermined voltage (first MOS transistor on, precharge voltage Vhalf, read voltage Vh + or Vh−) to the X selector 8.

53 is a view of the memory cell array of the MRAM shown in FIG. 8 as viewed from above the substrate on which the memory cell array is manufactured (positive direction of the Z axis). In this figure, a 2 × 2 memory cell 20j in the memory cell array 10 is shown as a representative.
In the first MOS transistor 6 of the memory cell 20, the source 6 a (first terminal) is connected to the first bit line 4 via the contact wiring 28. The gate 6b (first gate terminal) uses a write word line 3W-1 branched from the write word line 3W in the Y-axis direction. The drain 6 c (second terminal) is connected to the second bit line 5 through the contact wiring 27, the lead-out wiring layer 29, and the contact wiring 37.

  The magnetoresistive element 7 is provided on the lead wiring layer 29. The direction of spontaneous magnetization is reversed by the current flowing through the lead wiring layer 29. Here, since the current flowing through the lead wiring layer 29 flows in the X-axis direction, the direction of the magnetic field felt by the magnetoresistive element 7 is the Y-axis direction. Therefore, it is provided in a shape that facilitates magnetization in the Y-axis direction. For example, an ellipse having a long axis parallel to the Y-axis direction or a shape similar to an ellipse. One end (fourth terminal) of the magnetoresistive element 7 is connected to the lead-out wiring layer 29, and the other end (third terminal) is connected to the read word line 3R via the contact wiring 54-first diode 31.

  With this configuration, when current flows through the path of the first bit line 4 -first MOS transistor 6 -leading wiring layer 29 -second bit line 5, data is written to the magnetoresistive element 7 in contact with the leading wiring layer 29. Is possible.

FIG. 54 shows a structure of the memory cell 20j, and shows a cross section taken along line HH ′ in FIG.
The first MOS transistor 6 is formed on the surface portion of the semiconductor substrate. A source 6a as a first diffusion layer provided in the semiconductor substrate is connected to the first bit line 4 via a contact wiring 28 extending in the Z-axis direction. The drain 6c as the second diffusion layer is connected to one end of the lead-out wiring layer 29 via a contact wiring 27 extending in the Z-axis direction. The gate 6b as the first gate uses the write word line 3W-1 branched from the write word line 3W. However, the drain 6c is provided inside the memory cell 20j with respect to the source 6a. The other end of the lead wiring layer 29 is connected to a contact wiring 37 extending from the second bit line 5 in the Z-axis direction. The lead wiring layer is provided in parallel with the substrate.
The magnetoresistive element 7 is connected to the lead wiring layer 29 on one end side. The other end side is connected to the contact wiring 54. The contact wiring 54 includes the first diode 31 in the middle and is connected to the read word line 3R.

  Next, the operation of the twenty-fifth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

Reading data from the memory cell 2 is performed as follows. However, the read word line 3R, the first bit line 4 and the second bit line 5 are precharged to an intermediate potential Vhalf (eg, power supply voltage = 2.5V, Vhalf = 1.25V).
(1) Step S281
The X selector 8 selects a selected read word line 3Rs from a plurality of read word lines 3R by inputting a row address and an RA signal. Then, the selected read word line 3Rs is set to a potential of Vh− (example: Vh− = 0.75V). At the same time, the selected write word line 3Ws is selected from the plurality of write word lines 3W. As a result, the first MOS transistor is turned on.
(2) Step S282
The Y selector 11 selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. Then, the selected first bit line 4s is set to a potential of Vh + (example: Vh + = 1.75V).
As a result, the potential of Vh− by the X selector 8 and the potential of Vh + by the Y selector 11 are applied to the selected cell 20js. This potential difference ((Vh +) − (Vh −) = 1.0 V) is set to be larger than the threshold voltage Vth (example: 0.7 V) of the first diode 31. Therefore, the current reflecting the data of the selected cell 20js in the path of the X selector 8-selected read word line 3Rs-selected cell 20js (the magnetoresistive element 7) -selected first bit line 4s-Y selector 11-sense amplifier 15. Is flows. Similarly, the current Ir reflecting the data “0” of the reference cell 30 r is in the path of the X selector 8 -selected read word line 3 Rs-reference cell 20 r (the magnetoresistive element 7) -reference bit line 4 r -sense amplifier 15. Flows.
(3) Step S283
Based on the difference between the current Is and the current Ir, the sense amplifier 15 sets the read data to “0” if they are the same within a preset value range, and “1” if they are different (example: smaller). And output the result.

  With the above read operation, the data of the selected cell 20js can be read.

  Data is written to the memory cell 2 as follows. However, the read word line 3R, the first bit line 4 and the second bit line 5 are precharged to an intermediate potential Vhalf (eg, power supply voltage = 2.5V, Vhalf = 1.25V).

(1) Step S291
The X selector 8 selects the selected write word line 3Ws from the plurality of write word lines 3W in response to the input of the row address. The first MOS transistor 6 of each memory cell 20j is turned on.
(2) Step S292
The Y selector 11 selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. Then, the selected first bit line 4s is set to a potential of Vh + or Vh− according to the write data (D). For example, Vh + is 1.75V and Vh− is 0.75V. Further, the Y-side current termination circuit 14 selects the selected second bit line 5s from the plurality of second bit lines 5 in response to the input of the column address. A pair of the selected first bit line 4s and the selected second bit line 5s is selected. Then, the selected second bit line 5s is set to a potential of Vh− or Vh + opposite to the potential of the selected first bit line 4s.
As a result, the potential of Vh + or Vh− by the Y selector 11 and the potential of Vh− or Vh + by the Y-side current termination circuit 14 are applied to the selected cell 20js. By this potential difference ((Vh + or Vh −) − (Vh− or Vh +) = ± 1.0 V), the Y selector 11−the selected first bit line 4s−the selected cell 20js (in the vicinity of the magnetoresistive element 7) −the selected first In the path of the 2-bit line 5s-Y side current termination circuit 14, a current Iw (0) having a predetermined magnitude corresponding to the data signal D (in the case of “0”: a direction toward the Y selector 11) or a current Iw ( 1) (In the case of “1”, the Y-side current termination circuit 14) flows.
(3) Step S293
In the selected cell 20js, when the current Iw (0) (+ X direction) or the current Iw (1) (−X direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the −Y direction or + Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal D is stored.

  With the above write operation, data can be written to the selected cell 20js.

According to the present embodiment, the same effects as those of the first embodiment and the third embodiment can be obtained.
Further, since the first diode 31 is used, the current selectivity during the read operation can be improved as compared with the case where the first diode 31 is not used. As a result, the reading speed can be increased.

(Twenty-sixth embodiment)
A twenty-sixth embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  The configuration of the twenty-sixth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained. FIG. 55 is a diagram showing the configuration of a twenty-sixth embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention. FIG. 55 shows a configuration in which the circuit example of the MRAM shown in FIG. 52 is hierarchized. The MRAM according to the present embodiment includes cell arrays 41e-0 to 41e-3, a cell array selector 17a, a Y-side current source circuit 12, a read current load circuit 13, and a sense amplifier 15.

The cell array 41e-i (i = 0 to 3) is a memory cell array 10, a plurality of write word lines 3W, a plurality of read word lines 3R, and a plurality of first bit lines 4 (including a reference first bit line 4r). , A plurality of second bit lines 5 (including a reference second bit line 5r), an X selector 8, a Y selector 11d, a reference Y selector 11r, and a Y-side current termination circuit 14. Since each configuration is the same as that of the twenty-sixth embodiment, the description thereof is omitted. However, the Y selector 11d is the same as the Y selector 11, but does not have a function of selecting the reference bit line 4 in the Y selector 11. The reference Y selector 11r has a function of selecting the reference bit line 4. Here, the precharge voltage Vhalf for each selector is supplied to each selector by a power source (not shown). The X selector 8 is supplied with a Vh− potential from an X-side power supply circuit 9 (not shown) during a read operation.
In FIG. 55, four cell arrays 41e are shown, but the present invention is not limited to this number.

  The cell array selector 17a selects the selected cell array 41e-i by the selector transistors 17a-1 to 17a-3 based on the cell array selection signal MWSi (i = 0 to 3: the number of the cell array 51) for selecting the cell array 41e. select. The selected cell array 41e-i is connected to the Y-side voltage source circuit 12v, the read current load circuit 13, and the sense amplifier 15 by the first main bit line 62, the second main bit line 63, and the third main bit line 64, respectively. The same operation as in the twenty-fifth embodiment is performed.

  The Y-side current source circuit 12v, the read current load circuit 13 and the sense amplifier 15 are the same as those in the twenty-fifth embodiment except that they are outside the cell array 41e and are common to the cell arrays 41e-i. Omitted.

  Next, the operation of the twenty-sixth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

In the MRAM in FIG. 55, data is read from the memory cell 20j as follows. However, the read word line 3R, the first bit line 4 and the second bit line 5 are precharged to an intermediate potential Vhalf (eg, power supply voltage = 2.5V, Vhalf = 1.25V).
(1) Step S301
The cell array selector 17a selects the corresponding selector transistors 17a-1, 17a- based on the cell array selection signal MWSi for selecting any one of the cell arrays 41e-i (i = 0 to n: n is the number of the selector array). 2 and 17a-3 are turned on, and the selected cell array 41e-i is selected.
At this time, the selected cell array 41e-i, the read current load circuit 13 and the sense amplifier 15 are connected by the first main bit line 62 and the second main bit line 63.
(2) Step S302
The X selector 8 selects a selected read word line 3Rs from a plurality of read word lines 3R by inputting a row address and an RA signal. Then, the selected read word line 3Rs is set to a potential of Vh− (example: Vh− = 0.75V). At the same time, the selected write word line 3Ws is selected from the plurality of write word lines 3W. As a result, the first MOS transistor is turned on.
(3) Step S303
The Y selector 11d selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. Then, the selected bit line 4s is set to a potential of Vh + (example: Vh + = 1.75V). The potential Vh + is applied by the read current load circuit 13 via the first main bit line 62.
The reference Y selector 11r sets the reference bit line 4r to a potential of Vh + (example: Vh + = 1.75V) in response to the input of the RA signal. The potential Vh + is applied by the read current load circuit 13 through the second main bit line 63.
As a result, the potential of Vh− by the X selector 8 and the potential of Vh + by the Y selector 11d are applied to the selected cell 20js. This potential difference ((Vh +) − (Vh −) = 1.0 V) is set to be larger than the threshold voltage Vth (example: 0.7 V) of the first diode 31. Therefore, in the path of X selector 8 -selected read word line 3Rs -selected cell 20js (of magnetoresistive element 7) -selected first bit line 4s -Y selector 11d -cell array selector 17a -sense amplifier 15, the data of selected cell 20js The current Is reflecting the current flows. Similarly, the path of the X selector 8 -selection read word line 3Rs -reference cell 20r (the magnetoresistive element 7) -reference bit line 4r -reference Y selector 11r -cell array selector 17a -sense amplifier 15 has a path of the reference cell 30r. A current Ir reflecting data “0” flows.
(4) Step S304
Based on the difference between the current Is and the current Ir, the sense amplifier 15 sets the read data to “0” if they are the same within a preset value range, and “1” if they are different (example: smaller). And output the result.

  With the above read operation, the data of the desired selected cell 20js in the desired selected cell array 41e-i can be read.

  Data is written to the memory cell 2 as follows. However, the read word line 3R, the first bit line 4 and the second bit line 5 are precharged to an intermediate potential Vhalf (eg, power supply voltage = 2.5V, Vhalf = 1.25V).

(1) Step S311
The cell array selector 17a turns on the corresponding selector transistors 17a-1, 17a-2, and 17a-3 based on the cell array selection signal MWSi for selecting any one of the cell arrays 41e-i, and selects the selected cell array 41e-i. Select.
At this time, the selected cell array 41e-i is connected to the Y-side voltage source circuit 12v, the read current load circuit 13, and the sense amplifier 15 by the first main bit line 62 to the third main bit line 64.
(2) Step S312
The X selector 8 selects the selected write word line 3Ws from the plurality of write word lines 3W in response to the input of the row address. The first MOS transistor 6 of each memory cell 20j is turned on.
(3) Step S313
The Y selector 11d selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. Then, the selected first bit line 4s is set to a potential of Vh + or Vh− according to the write data (D). For example, Vh + is 1.75V and Vh− is 0.75V. The potential of Vh + or Vh− is applied by the Y-side voltage source circuit 12v through the first main bit line 62.
Further, the Y-side current termination circuit 14 selects the selected second bit line 5s from the plurality of second bit lines 5 in response to the input of the column address. A pair of the selected first bit line 4s and the selected second bit line 5s is selected. Then, the selected second bit line 5s is set to a potential of Vh− or Vh + opposite to the potential of the selected first bit line 4s. The potential of Vh− or Vh + is applied by the Y-side voltage source circuit 12v through the third main bit line 64.
As a result, the potential of Vh + or Vh− by the Y selector 11d and the potential of Vh− or Vh + by the Y-side current termination circuit 14 are applied to the selected cell 20js. By this potential difference ((Vh + or Vh −) − (Vh− or Vh +) = ± 1.0 V), the Y selector 11d−the selected first bit line 4s−the selected cell 20js (in the vicinity of the magnetoresistive element 7) −the selected first In the path of the 2-bit line 5s-Y side current termination circuit 14, a current Iw (0) having a predetermined magnitude corresponding to the data signal D (in the case of “0”: a direction toward the Y selector 11) or a current Iw ( 1) (In the case of “1”, the Y-side current termination circuit 14) flows.
(4) Step S314
In the selected cell 20js, when the current Iw (0) (+ X direction) or the current Iw (1) (−X direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the −Y direction or + Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal D is stored.

  With the above write operation, data can be written to the desired selected cell 20js in the desired selected cell array 41e-i.

  When writing to the reference cell 20r, the reference first bit line 4r is selected in the Y selector 11d and the reference second bit line 5r is selected in the Y-side current termination circuit 14 together with the input of the reference active signal SR.

  According to this embodiment, the same effect as that of the 25th embodiment can be obtained. Further, the MRAM can be made compact by hierarchizing the cell array and sharing some circuits.

(Twenty-seventh embodiment)
A twenty-seventh embodiment of a magnetic memory cell and a magnetic random access memory according to the present invention will be described.

  First, the configuration of the twenty-seventh embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 56 is a diagram showing the configuration of a twenty-seventh embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention. The MRAM according to the present embodiment includes a memory cell array 10, a plurality of word lines 3, a plurality of first bit lines 4, a plurality of second bit lines 5, an X selector 8, a Y selector 11, a Y-side voltage source circuit 12v, and a read A current load circuit 13, a Y-side current termination circuit 14, a Y-side power supply circuit 19 and a sense amplifier 15 are provided.

  In the memory cell array 10, memory cells 20f are arranged in a matrix. Here, the memory cell 20 f includes a first MOS transistor 6, a magnetoresistive element 7, a second diode 32, and a third diode 33. The reference memory cell 20f is referred to as a reference cell 20r. In the reference cell 20r, “0” is written, and usually no write operation is performed.

The first MOS transistor 6 as the first transistor has a gate (first gate) as the write word line 3W, a source (first terminal) as the first bit line 4, and a drain (second terminal) as the magnetoresistive element 7. One end side (fourth terminal) is connected to the second diode 32 and the third diode 33. The first MOS transistor 6 is used to select one of the memory cells 20f during the write operation and the read operation.
The magnetoresistive element 7 has one end (fourth terminal) connected to the drain of the first MOS transistor 6 and the other end (third terminal) connected to a predetermined voltage source 24a (Vhalf) source. It has spontaneous magnetization whose magnetization direction is reversed according to stored data.
The second diode 32 includes a fifth terminal having a first polarity (p pole) and a sixth terminal having a second polarity (n pole). The third diode 33 includes a seventh terminal having a first polarity (p pole) and an eighth terminal having a second polarity (n pole). The sixth terminal and the seventh terminal are connected to the second bit line 5. The fifth terminal and the eighth terminal are connected to the fourth terminal of the magnetoresistive element 7. The second diode 32 and the third diode 33 are used to connect the first bit line 4 and the second bit line 5 to cause a current to flow in the vicinity of the magnetoresistive element 7 during a write operation.

The first bit line 4 is provided so as to extend in the Y-axis direction (bit line direction) as the first direction, and is connected to the Y selector 11. The reference first bit line 4 is referred to as a reference first bit line 4r.
The second bit line 5 is paired with the first bit line 4, is provided extending in the Y-axis direction, and is connected to the Y-side current termination circuit 14. The reference second bit line 5 is referred to as a reference second bit line 5r.
The word line 3 is provided so as to extend in the X-axis direction (word line direction) as a second direction substantially perpendicular to the Y-axis direction, and is connected to the X selector 8.
Each memory cell 20f is provided corresponding to each of the positions where the plurality of sets of the first bit line 4 and the second bit line 5 and the word line 3 intersect.

The X selector 8 selects one word line 3 from the plurality of word lines 3 as the selected word line 3s during the data write operation and the read operation.
The Y selector 11 precharges the plurality of first bit lines 4 to an intermediate potential Vhalf (example: Vhalf = 1.25 V). Then, during the write operation, one first bit line 4 is selected from the plurality of first bit lines 4 as the selected first bit line 4s. At this time, the selected first bit line 4s is set to a potential of Vh + or Vh− according to the write data (D). For example, Vh + is 1.75V and Vh− is 0.75V. In the read operation, one first bit line 4 is selected from the plurality of first bit lines 4 as the selected first bit line 4s. At this time, the selected bit line 4s is set to a potential of Vh + (example: Vh + = 1.75V).
The Y-side current termination circuit 14 precharges the plurality of second bit lines 5 to the intermediate potential Vhalf (for example, Vhalf = 1.25 V). Then, during the data write operation, one second bit line 5 paired with the selected first bit line 4s is selected as the selected second bit line 5s from the plurality of second bit lines 5. The potential is set to Vh− or Vh + which is opposite to the potential of the selected first bit line 4s.
Here, the memory cell 20f selected by the selected write / read word line 3Ws / 3Rs and the selected first / second bit line 4s / 5s is referred to as a selected cell 20fs.

  Since the Y-side voltage source circuit 12v, the Y-side power supply circuit 19, the read current load circuit 13, and the sense amplifier 15 are the same as those in the twenty-fifth embodiment, description thereof is omitted.

57 is a view of the memory cell array of the MRAM shown in FIG. 56 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, 2 × 2 memory cells 20f in the memory cell array 10 are shown as representatives.
In the first MOS transistor 6 of the memory cell 20, the source 6 a (first terminal) is connected to the first bit line 4 via the contact wiring 28. The gate 6b (first gate terminal) uses the word line 3-1 branched from the word line 3 in the Y-axis direction. The drain 6 c (second terminal) is connected to the second bit line 5 via the contact wiring 27 -the lead wiring layer 29 -the contact wiring 55 or the contact wiring 56. In the middle of the contact wiring 55 and the contact wiring 56, a second diode 32 and a third diode 33 are provided, respectively.

  The magnetoresistive element 7 is provided on the lead wiring layer 29. The direction of spontaneous magnetization is reversed by the current flowing through the lead wiring layer 29. Here, since the current flowing through the lead wiring layer 29 flows in the X-axis direction, the direction of the magnetic field felt by the magnetoresistive element 7 is the Y-axis direction. Therefore, it is provided in a shape that facilitates magnetization in the Y-axis direction. For example, an ellipse having a long axis parallel to the Y-axis direction or a shape similar to an ellipse. One end side (fourth terminal) of the magnetoresistive element 7 is connected to the lead-out wiring layer 29, and the other end side (third terminal) is connected to a wiring (not shown) to the voltage source 24a that supplies the potential Vhalf.

  With this configuration, when current flows through the path of the first bit line 4 -first MOS transistor 6 -leading wiring layer 29 -second bit line 5, data is written to the magnetoresistive element 7 in contact with the leading wiring layer 29. Is possible.

FIG. 58 shows the structure of the memory cell 20f, and shows a II ′ cross section in FIG.
The first MOS transistor 6 is formed on the surface portion of the semiconductor substrate. A source 6a as a first diffusion layer provided in the semiconductor substrate is connected to the first bit line 4 via a contact wiring 28 extending in the Z-axis direction. The drain 6c as the second diffusion layer is connected to one end of the lead-out wiring layer 29 via a contact wiring 27 extending in the Z-axis direction. The gate 6 b as the first gate uses the word line 3-1 branched from the word line 3. However, the drain 6c is provided inside the memory cell 20f than the source 6a. The other end of the lead wiring layer 29 is connected to a contact wiring 55 and a contact wiring 56 that extend from the second bit line 5 in the Z-axis direction. The lead wiring layer is provided in parallel with the substrate. In the middle of the contact wiring 55 and the contact wiring 56, a second diode 32 and a third diode 33 are provided, respectively.
The magnetoresistive element 7 is connected to the lead wiring layer 29 on one end side. The other end side is connected to the contact wiring 26. The contact wiring 26 is connected to the wiring to the voltage source 24a.

  Next, the operation of the twenty-seventh embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

Reading data from the memory cell 2 is performed as follows. However, the first bit line 4 and the second bit line 5 are precharged to an intermediate potential Vhalf (example: power supply voltage = 2.5V, Vhalf = 1.25V).
(1) Step S321
The X selector 8 selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. As a result, the first MOS transistor 6 is turned on.
(2) Step S322
The Y selector 11 selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. Then, the selected bit line 4s is set to a potential of Vh + (example: Vh + = 1.75V).
As a result, the potential Vhalf of the voltage source 24a and the potential Vh + of the Y selector 11 are applied to the selected cell 20fs. This potential difference ((Vh +) − (Vhalf) = 0.5 V) is set to be smaller than any threshold voltage Vth of the second diode 32 and the third diode 33. As a result, no current flows through each diode, and the voltage of the selected cell 20fs in the path of the voltage source 24a, the selected cell 20fs (the magnetoresistive element 7), the selected first bit line 4s, the Y selector 11 and the sense amplifier 15 is obtained. A current Is reflecting the data flows. In this case, since the threshold voltage of the second diode 32 and the third diode 33 is set to 0.7 V, no current flows through both diodes.
Similarly, a current Ir reflecting data “0” of the reference cell 30 r flows through the path of the voltage source 24 a, the reference cell 20 r (the magnetoresistive element 7), the reference bit line 4 r, and the sense amplifier 15.
(3) Step S323
Based on the difference between the current Is and the current Ir, the sense amplifier 15 sets the read data to “0” if they are the same within a preset value range, and “1” if they are different (example: smaller). And output the result.

  With the above read operation, the data of the selected cell 20fs can be read.

  Data is written to the memory cell 2 as follows. The first bit line 4 and the second bit line 5 are precharged to an intermediate potential Vhalf (example: power supply voltage = 2.5V, Vhalf = 1.25V).

(1) Step S331
The X selector 8 selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. The first MOS transistor 6 of each memory cell 20f is turned on.
(2) Step S332
The Y selector 11 selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. Then, the selected first bit line 4s is set to a potential of Vh + or Vh− according to the write data (D). For example, Vh + is 1.75V and Vh− is 0.75V. Further, the Y-side current termination circuit 14 selects the selected second bit line 5s from the plurality of second bit lines 5 in response to the input of the column address. A pair of the selected first bit line 4s and the selected second bit line 5s is selected. Then, the selected second bit line 5s is set to a potential of Vh− or Vh + opposite to the potential of the selected first bit line 4s.
As a result, the potential of Vh + or Vh− by the Y selector 11 and the potential of Vh− or Vh + by the Y-side current termination circuit 14 are applied to the selected cell 20fs. This potential difference ((Vh + or Vh −) − (Vh− or Vh +) = ± 1.0 V) is set to be larger than the threshold voltage Vth of the second diode 32 and the third diode 33. As a result, in the path of Y selector 11 -selected first bit line 4 s -selected cell 20 fs (in the vicinity of magnetoresistive element 7) -selected second bit line 5 s -Y side current termination circuit 14, it corresponds to data signal D. A current Iw (0) having a predetermined magnitude (in the case of “0”: a direction toward the Y selector 11) or a current Iw (1) (in the case of “1”, the Y-side current termination circuit 14) flows.
(3) Step S333
In the selected cell 20fs, when the current Iw (0) (+ X direction) or the current Iw (1) (−X direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the −Y direction or + Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal D is stored.

  With the above write operation, data can be written to the selected cell 20fs.

According to the present embodiment, the same effects as those of the first embodiment and the third embodiment can be obtained. The number of elements directly using a semiconductor substrate can be reduced and the elements can be miniaturized.
Further, it is not necessary to divide the word line for reading and writing, and the control becomes easy and the decoder circuit can be simplified. Thereby, the chip size can be reduced.

(Twenty-eighth embodiment)
A twenty-eighth embodiment of the magnetic memory cell and the magnetic random access memory according to the present invention will be described.

  The configuration of the twenty-eighth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained. FIG. 59 is a diagram showing the configuration of the twenty-eighth embodiment of a magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. FIG. 59 shows a configuration in which the circuit example of the MRAM shown in FIG. 56 is hierarchized. The MRAM according to the present embodiment includes cell arrays 41f-0 to 41f-3, a cell array selector 17a, a Y-side current source circuit 12v, a read current load circuit 13, and a sense amplifier 15.

The cell array 41f-i (i = 0 to 3) is a memory cell array 10, a plurality of word lines 3W, a plurality of first bit lines 4 (including a reference first bit line 4r), and a plurality of second bit lines 5 (Including the reference second bit line 5r), an X selector 8, a Y selector 11d, a reference Y selector 11r, and a Y-side current termination circuit 14. Since each configuration is the same as that of the 27th embodiment, its description is omitted. However, the Y selector 11d is the same as the Y selector 11, but does not have a function of selecting the reference bit line 4 in the Y selector 11. The reference Y selector 11r has a function of selecting the reference bit line 4. Here, as the precharge voltage Vhalf for each selector, a power source (not shown) is supplied to each selector.
In FIG. 59, four cell arrays 41f are shown, but the present invention is not limited to this number.

Since the cell array selector 17a is the same as that in the twenty-sixth embodiment, its description is omitted.
The Y-side current source circuit 12v, the read current load circuit 13, and the sense amplifier 15 are the same as those in the twenty-seventh embodiment except that they are outside the cell array 41f and are common to the cell arrays 41f-i. Description is omitted.

  Next, the operation of the twenty-eighth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.

In the MRAM in FIG. 59, data is read from the memory cell 20f as follows. However, the first bit line 4 and the second bit line 5 are precharged to an intermediate potential Vhalf (example: power supply voltage = 2.5V, Vhalf = 1.25V).
(1) Step S341
The cell array selector 17a selects the corresponding selector transistors 17a-1, 17a- based on the cell array selection signal MWSi for selecting one of the cell arrays 41f-i (i = 0 to n: n is the number of the selector array). 2 and 17a-3 are turned on, and the selected cell array 41f-i is selected.
At this time, the selected cell array 41e-i, the read current load circuit 13 and the sense amplifier 15 are connected by the first main bit line 62 and the second main bit line 63.
(2) Step S342
The X selector 8 selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. As a result, the first MOS transistor 6 is turned on.
(3) Step S343
The Y selector 11d selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. Then, the selected bit line 4s is set to a potential of Vh + (example: Vh + = 1.75V). The potential Vh + is applied by the read current load circuit 13 via the first main bit line 62.
The reference Y selector 11r sets the reference bit line 4r to a potential of Vh + (example: Vh + = 1.75V) by inputting a column address and an RA signal. The potential Vh + is applied by the read current load circuit 13 through the second main bit line 63.
Thereby, the potential of Vhalf of the voltage source 24a and the potential of Vh + by the Y selector 11d are applied to the selected cell 20fs. This potential difference ((Vh +) − (Vhalf) = 0.5 V) is set to be smaller than the threshold voltage Vth (0.7 V) of the second diode 32 or the third diode 33. Therefore, in the path of voltage source 24a-selected cell 20fs (magnetoresistance element 7) -selected first bit line 4s-Y selector 11d-cell array selector 17a-sense amplifier 15, current Is reflecting the data of selected cell 20fs is obtained. Flowing. Similarly, the data "0" of the reference cell 30r is reflected in the path of the voltage source 24a-reference cell 20r (the magnetoresistive element 7) -reference bit line 4r-reference Y selector 11r-cell array selector 17a-sense amplifier 15. Current Ir flows.
(4) Step S344
Based on the difference between the current Is and the current Ir, the sense amplifier 15 sets the read data to “0” if they are the same within a preset value range, and “1” if they are different (example: smaller). And output the result.

  With the above read operation, the data of the desired selected cell 20fs in the desired selected cell array 41f-i can be read.

  Data is written to the memory cell 2 as follows. However, the first bit line 4 and the second bit line 5 are precharged to an intermediate potential Vhalf (example: power supply voltage = 2.5V, Vhalf = 1.25V).

(1) Step S351
The cell array selector 17a turns on the corresponding selector transistors 17a-1, 17a-2, and 17a-3 based on the cell array selection signal MWSi for selecting any one of the cell arrays 41f-i, and selects the selected cell array 41f-i. Select.
At this time, the selected cell array 41f-i is connected to the Y-side voltage source circuit 12v, the read current load circuit 13, and the sense amplifier 15 by the first main bit line 62 to the third main bit line 64.
(2) Step S352
The X selector 8 selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. The first MOS transistor 6 of each memory cell 20f is turned on.
(3) Step S353
The Y selector 11d selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. Then, the selected first bit line 4s is set to a potential of Vh + or Vh− according to the write data (D). For example, Vh + is 1.75V and Vh− is 0.75V. The potential of Vh + or Vh− is applied by the Y-side voltage source circuit 12v through the first main bit line 62.
Further, the Y-side current termination circuit 14 selects the selected second bit line 5s from the plurality of second bit lines 5 in response to the input of the column address. A pair of the selected first bit line 4s and the selected second bit line 5s is selected. Then, the selected second bit line 5s is set to a potential of Vh− or Vh + opposite to the potential of the selected first bit line 4s. The potential of Vh− or Vh + is applied by the Y-side voltage source circuit 12v through the third main bit line 64.
As a result, the potential Vh + or Vh− by the Y selector 11d and the potential Vh− or Vh + by the Y-side current termination circuit 14 are applied to the selected cell 20fs. This potential difference ((Vh + or Vh −) − (Vh− or Vh +) = ± 1.0 V) is set to be larger than the threshold voltage Vth of the second diode 32 and the third diode 33. As a result, in the path of Y selector 11d-selected first bit line 4s-selected cell 20fs (in the vicinity of magnetoresistive element 7) -selected second bit line 5s-Y-side current termination circuit 14, it corresponds to data signal D. A current Iw (0) having a predetermined magnitude (in the case of “0”: a direction toward the Y selector 11) or a current Iw (1) (in the case of “1”, the Y-side current termination circuit 14) flows.
(4) Step S354
In the selected cell 20fs, when the current Iw (0) (+ X direction) or the current Iw (1) (−X direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the −Y direction or + Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal D is stored.

  With the above write operation, data can be written to the desired selected cell 20fs in the desired selected cell array 41f-i.

  When writing to the reference cell 20r, the reference first bit line 4r is selected in the Y selector 11d and the reference second bit line 5r is selected in the Y-side current termination circuit 14 together with the input of the reference active signal SR.

According to this embodiment, the same effect as that of the 27th embodiment can be obtained. Further, the MRAM can be made compact by hierarchizing the cell array and sharing some circuits.
(Twenty-ninth embodiment)
A twenty-ninth embodiment of the magnetic memory cell and the magnetic random access memory according to the present invention will be described.

  First, the configuration of the twenty-ninth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained. FIG. 60 is a diagram showing the configuration of a twenty-ninth embodiment of a magnetic random access memory (MRAM) including magnetic memory cells of the present invention. The MRAM according to the present embodiment includes a memory cell array 10, a plurality of word lines 3, a plurality of first bit lines 4, a plurality of second bit lines 5, an X selector 8, a Y selector 11, a Y-side voltage source circuit 12v, and a read A current load circuit 13, a Y-side current termination circuit 14, a Y-side power supply circuit 19 and a sense amplifier 15 are provided.

  In the memory cell array 10, memory cells 20g are arranged in a matrix. Here, the memory cell 20 g includes the first MOS transistor 6, the magnetoresistive element 7, the second diode 32, and the third diode 33. The reference memory cell 20g is referred to as a reference cell 20r. In the reference cell 20r, “0” is written, and usually no write operation is performed.

  The memory cell 20g in the present embodiment differs from the memory cell 20f in the twenty-seventh embodiment in that the second diode 32 and the third diode 33 face each other so that the n-poles are joined to each other. Different. That is, the second diode 32 includes a fifth terminal having the first polarity (p) connected to the second bit line 5 and a sixth terminal having the second polarity (n). The third diode 33 includes a seventh terminal having the first polarity (p) connected to the second terminal and an eighth terminal having the second polarity (n) connected to the sixth terminal.

Here, the characteristics of an element (hereinafter also referred to as “series diode element”) in which the second diode 32 and the third diode 33 are joined to face each other will be described. FIG. 61 is a graph for explaining the characteristics of the series diode element. The vertical axis represents the current flowing through the diode. The horizontal axis is the voltage applied to the diode. Vbd + or Vbd− indicates a breakdown voltage in the reverse direction of each of the second diode 32 and the third diode 33. The series diode element ideally does not pass current. However, if the device is designed to facilitate breakdown, the breakdown voltage (Vbd + or Vbd−) can be exceeded with a relatively low voltage reverse bias. Above the breakdown voltage, current can flow over the PN junction. Accordingly, the series diode element can be regarded as a switching element that is turned off if the applied voltage Vin is Vbd− <Vin <Vbd +, and turned on otherwise.
FIG. 47A shows the characteristics of one diode. The absolute value of the threshold voltage Vth (example: 0.7V) is smaller than the absolute value of the breakdown voltage Vbd.

  Other configurations are the same as those in the twenty-seventh embodiment, and a description thereof will be omitted.

FIG. 62 is a view of the memory cell array of the MRAM shown in FIG. 60 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, a 2 × 2 memory cell 20g in the memory cell array 10 is shown as a representative.
The memory cell 20g in the present embodiment differs from the memory cell 20f in the 27th embodiment in that the second diode 32 and the third diode 33 are provided so as to overlap each other in the middle of the contact wiring 54. . Other configurations are the same as those in the twenty-seventh embodiment, and a description thereof will be omitted.

FIG. 63 shows the structure of the memory cell 20g, and shows a JJ ′ cross section in FIG.
The memory cell 20g in the present embodiment differs from the memory cell 20f in the 27th embodiment in that the second diode 32 and the third diode 33 are provided so as to overlap each other in the middle of the contact wiring 54. . Other configurations are the same as those in the twenty-seventh embodiment, and a description thereof will be omitted.

Next, the operation of the twenty-ninth embodiment of the magnetic memory cell and magnetic random access memory of the present invention is the same as the operation of the twenty-seventh embodiment (steps S321 to S323, steps S331 to S333). The description is omitted.
However, the potential difference ((Vh +) − (Vhalf) = 0.5 V) applied to the selected cell 20gs during the read operation is set to be smaller than the breakdown voltages (Vbd + and Vbd−) of the series diode elements. Thereby, no current flows through each diode.
During the write operation, the potential difference ((Vh + or Vh −) − (Vh− or Vh +) = ± 1.0V) applied to the selected cell 20gs is larger than the breakdown voltage (Vbd + and Vbd−) of the series diode element. Is set. Thereby, current Iw (0) or current Iw (1) having a predetermined magnitude corresponding to the data signal D flows in the vicinity of the magnetoresistive element 7 of the selected cell 20fs.

  According to this embodiment, the same effect as that of the 27th embodiment can be obtained. Since the number of elements that directly use the semiconductor substrate can be reduced, the memory cell can be reduced in size. In addition, since the two diodes of the memory cell are formed in an overlapping manner, the chip size can be further reduced.

(Thirty Embodiment)
A thirtieth embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

  The configuration of the 30th embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained. FIG. 64 is a diagram showing a configuration of a thirtieth embodiment of a magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. FIG. 64 shows a configuration in which the circuit example of the MRAM shown in FIG. 60 is hierarchized. The MRAM according to the present embodiment includes cell arrays 41g-0 to 41g-3, a cell array selector 17a, a Y-side current source circuit 12v, a read current load circuit 13, and a sense amplifier 15.

Since each configuration is the same as that of the twenty-eighth embodiment, the description thereof is omitted.
However, the memory cell 20g in the present embodiment is different from the memory cell in the 28th embodiment in that the second diode 32 and the third diode 33 face each other so that the n-poles are joined to each other. Different from 20f. That is, the second diode 32 includes a fifth terminal having the first polarity (p) connected to the second bit line 5 and a sixth terminal having the second polarity (n). The third diode 33 includes a seventh terminal having the first polarity (p) connected to the second terminal and an eighth terminal having the second polarity (n) connected to the sixth terminal.

Next, the operation of the 30th embodiment of the magnetic memory cell and magnetic random access memory of the present invention is the same as the operation of the 28th embodiment (steps S341 to S344, steps S351 to S354). The description is omitted.
However, the potential difference ((Vh +) − (Vhalf) = 0.5 V) applied to the selected cell 20gs during the read operation is set to be smaller than the breakdown voltages (Vbd + and Vbd−) of the series diode elements. Thereby, no current flows through each diode.
During the write operation, the potential difference ((Vh + or Vh −) − (Vh− or Vh +) = ± 1.0V) applied to the selected cell 20gs is larger than the breakdown voltage (Vbd + and Vbd−) of the series diode element. Is set. Thereby, current Iw (0) or current Iw (1) having a predetermined magnitude corresponding to the data signal D flows in the vicinity of the magnetoresistive element 7 of the selected cell 20fs.

According to the present embodiment, the same effect as in the twenty-eighth embodiment can be obtained.
In addition, since the two diodes of the memory cell are formed in an overlapping manner, the chip size can be further reduced.

(Thirty-first embodiment)
A thirty-first embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

  First, the configuration of the thirty-first embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 65 is a diagram showing the configuration of a thirty-first embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention. The MRAM according to the present embodiment includes a memory cell array 1, a plurality of first word lines 3a, a plurality of second word lines 3b, a plurality of first bit lines 4, a plurality of second bit lines 5, an X selector 8, and a Y selector. 11, a Y-side current source circuit 12, a Y-side power supply circuit 19, a read current load circuit 13, a Y-side current termination circuit 14, and a sense amplifier 15.

  In the memory cell array 1, memory cells 2 are arranged in a matrix. Here, the memory cell 2h includes a first MOS transistor 6-1, a second MOS transistor 16-1, a third MOS transistor 6-2, a fourth MOS transistor 16-2, and a magnetoresistive element 7. The reference memory cell 2 is referred to as a reference cell 2r.

  In the first embodiment, the set of the first MOS transistor 6-1, the second MOS transistor 16-1, and the bit line 3 fulfill the function of selecting a memory cell for the magnetoresistive element 7. In the present invention, two functions ((first MOS transistor 6-1, second MOS transistor 16-1, and first bit line 3a) and (third MOS transistor 6-2, fourth MOS transistor 16-2, and second function) The second embodiment is different from the first embodiment in that it is performed by a 2-bit line 3b)). In this case, since the number of MOS transistors through which current flows is doubled, it is possible to increase the current flowing during the read operation and the write operation. Thereby, the reliability of the cell array can be improved.

The first MOS transistor 6-1 has a gate (first gate) as the first word line 3a, a source (first terminal) as the first bit line 4, and a drain (second terminal) as one end side of the magnetoresistive element 7. (Fourth terminal) and the drain (sixth terminal) of the second MOS transistor 16-1.
The second MOS transistor 16-1 has a gate (second gate) as the first word line 3a, a source (fifth terminal) as the second bit line 5, and a drain (sixth terminal) as one end of the magnetoresistive element 7. (Fourth terminal) and the drain (second terminal) of the first MOS transistor 6 are connected.
The third MOS transistor 6-2 has a gate (third gate) as the second word line 3b, a source (seventh terminal) as the first bit line 4, and a drain (eighth terminal) as one end of the magnetoresistive element 7. (Fourth terminal) and the drain (second terminal) of the first MOS transistor 6-1.
The fourth MOS transistor 16-2 has a gate (fourth gate) as the second word line 3b, a source (ninth terminal) as the second bit line 5, and a drain (tenth terminal) as one end of the magnetoresistive element 7. (Fourth terminal) and the drain (sixth terminal) of the second MOS transistor 16-2.
During the read operation, the first MOS transistor 6-1 and the third MOS transistor 6-2 connect the magnetoresistive element 7 to the first bit line 4 and cause a current to flow through the magnetoresistive element 7-first bit line 4. Used. During the write operation, the first MOS transistor 6-1, the second MOS transistor 16-1, the third MOS transistor 6-2, and the fourth MOS transistor 16-2 connect the first bit line 4 and the second bit line 5 to each other. It is used to flow current near the magnetoresistive element 7.

The first word line 3 a is provided so as to extend in the X-axis direction (word line direction) as a second direction substantially perpendicular to the Y-axis direction, and is connected to the X selector 8.
The second word line 3b is provided so as to extend in the X-axis direction (word line direction) and is connected to the X selector 8. The first word line 3 a and the second word line 3 b are branched when one word line 3 leaves the X selector 8. Therefore, both are always at the same potential and are simultaneously selected by the X selector 8.

  Since other configurations are the same as those in the first embodiment, the description thereof is omitted.

FIG. 66 is a view of the memory cell array of the MRAM shown in FIG. 65 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, 2 × 2 memory cells 2 in the memory cell array 1 are shown as representatives.
In the first MOS transistor 6-1 of the memory cell 2h, the source 6-1a (first terminal) is connected to the first bit line 4 via the contact wiring 28-1. The gate 6-1b (first gate terminal) uses the first word line 3a. The drain 6-1 c (second terminal) is connected to the contact wiring 27. Similarly, in the third MOS transistor 6-2, the source 6-2a (seventh terminal) is connected to the first bit line 4 via the contact wiring 28-2. The gate 6-2b (third gate terminal) uses the second word line 3b. The drain 6-2c (eighth terminal) is connected to the contact wiring 27.
At this time, the drain 6-1c (second terminal) and the drain 6-2c (eighth terminal) are formed of a common diffusion layer 6d. The source 6-1a (first terminal) and the source 6-2a (seventh terminal) of the adjacent memory cell 2h are formed by another common diffusion layer 6d.

In the second MOS transistor 16-1, the source 16-1a (fifth terminal) is connected to the second bit line 5 via the contact wiring 38-1. The gate 16-1b (second gate terminal) uses the first word line 3a. The drain 16-1 c (sixth terminal) is connected to the contact wiring 37. Similarly, in the fourth MOS transistor 16-2, the source 16-2a (the ninth terminal) is connected to the second bit line 5 through the contact wiring 38-2. The gate 16-2b (fourth gate terminal) uses the second word line 3b. The drain 16-2c (tenth terminal) is connected to the contact wiring 37.
At this time, the drain 16-1c (sixth terminal) and the drain 16-2c (tenth terminal) are formed of a common diffusion layer 6e. Further, the source 16-1a (fifth terminal) and the source 16-2a (ninth terminal) of the adjacent memory cell 2h are formed of another common diffusion layer 6e.
The contact wiring 27 and the contact wiring 37 are connected via a lead wiring layer 29.

  The magnetoresistive element 7 is provided on the lead wiring layer 29. The direction of spontaneous magnetization is reversed by the current flowing through the lead wiring layer 29. Here, since the current flowing through the lead wiring layer 29 flows in the X-axis direction, the direction of the magnetic field felt by the magnetoresistive element 7 is the Y-axis direction. Therefore, it is provided in a shape that facilitates magnetization in the Y-axis direction. For example, an ellipse having a long axis parallel to the Y-axis direction or a shape similar to an ellipse. One end (fourth terminal) of the magnetoresistive element 7 is connected to the lead wiring layer 29, and the other end (third terminal) is connected to the ground wiring 24 (not shown in FIG. 66). The ground wiring 24 on the other end side (third terminal) does not need to be separated for each memory cell 2h, and thus is integrally formed as shown in FIG.

  In this way, adjacent MOS transistors share the source or drain and the contact wiring. Accordingly, an isolation region between the transistors is not necessary, so that the memory cell can be efficiently arranged in a small area. That is, the number of MOS transistors in the memory cell can be increased without increasing the chip area. This makes it possible to increase the current flowing through the memory cell.

  FIG. 67 shows the structure of the memory cell 2h, and shows the KK ′ cross section in FIG. Since the first MOS transistor and the second MOS transistor are the same as those in the first embodiment (FIG. 4) except that they are separated from each other, the description thereof is omitted.

FIG. 68 is a diagram showing another configuration of the memory cell 2h of the memory cell array of the MRAM shown in FIG. In this figure, 2 × 2 memory cells 2 in the memory cell array 1 are shown as representatives.
In this configuration, the magnetoresistive element 7 is disposed directly on the diffusion layer. Thereby, the lead wiring layer 29 and the contact wirings 27 and 37 can be omitted. Others are the same as in FIG.

  FIG. 69 shows a structure of another configuration of the memory cell 2h, and is a diagram showing a cross-section LL 'in FIG. As compared with FIG. 67, the lead-out wiring layer 29 and the contact wirings 27 and 37 are omitted, and the magnetoresistive element 7 is directly disposed on the diffusion layer.

  Thus, by arranging the magnetoresistive element 7 below each bit line, an area for contact wiring from the MOS transistor to the lead-out wiring layer 29 becomes unnecessary. Therefore, the memory cells can be efficiently arranged in a small area. Also, the memory cells can be arranged low in the height direction.

  Next, regarding the operation of the 31st embodiment of the magnetic memory cell and magnetic random access memory of the present invention, the first MOS transistor 6-1 and the second MOS transistor 16-1 in the first embodiment are respectively ( Except for the first MOS transistor 6-1, the second MOS transistor 16-1, the third MOS transistor 6-2, and the fourth MOS transistor 16-2, the configuration is the same as that of the first embodiment, and thus the description thereof is omitted. .

According to the present invention, the same effect as that of the first embodiment can be obtained.
Further, an area for contact wiring from the MOS transistor to the lead-out wiring layer 29 is not necessary. Therefore, the memory cell can be efficiently arranged in a small area. Since no isolation region between the transistors is necessary, the memory cell can be efficiently arranged in a small area. That is, the number of MOS transistors in the memory cell can be increased without increasing the chip area. This makes it possible to increase the current flowing through the memory cell.

(Thirty-second embodiment)
A thirty-second embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

  The configuration of the thirty-second embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 79 is a diagram showing the configuration of a thirty-second embodiment of a magnetic random access memory (MRAM) including magnetic memory cells according to the present invention. The MRAM according to the present embodiment includes a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4, a plurality of second bit lines 5, a plurality of reference bit lines 35, an X selector 8, and a Y selector 11-1. A read Y selector 11-2, a Y side current source circuit 12, a Y side power supply circuit 19, a read current load circuit 13, a Y side current termination circuit 14 and a sense amplifier 15a.

In the memory cell array 1, memory cells 2 are arranged in a matrix. Here, the memory cell 2 includes a first MOS transistor 6, a second MOS transistor 16, and a magnetoresistive element 7. The reference memory cell 2 is referred to as a reference cell 2r.
The first MOS transistor 6 as the first transistor has a gate (first gate) as the word line 3, a source (first terminal) as the first bit line 4, and a drain (second terminal) as one end of the magnetoresistive element 7. Side (fourth terminal) and the drain (sixth terminal) of the second MOS transistor 16.
The second MOS transistor 16 has a gate (second gate) as the word line 3, a source (fifth terminal) as the second bit line 5, and a drain (sixth terminal) as one end side (fourth terminal) of the magnetoresistive element 7. And the drain (second terminal) of the first MOS transistor 6.
During the read operation, the first MOS transistor 6 is used to connect the magnetoresistive element 7 to the first bit line 4 and to pass a current through the reference bit line 35 -the magnetoresistive element 7 -the first bit line 4. During the write operation, the first MOS transistor 6 and the second MOS transistor 16 are used to connect the first bit line 4 and the second bit line 5 and to allow a current to flow in the vicinity of the magnetoresistive element 7.
The magnetoresistive element 7 has one end (fourth terminal) connected to each of the transistors and the other end (third terminal) connected to the reference bit line 35. It has spontaneous magnetization whose magnetization direction is reversed according to stored data.

The first bit line 4 is provided so as to extend in the Y-axis direction (bit line direction) as the first direction, and has one end connected to the Y selector 11-1 and the other end connected to the Y-side current termination circuit 14. Yes. The reference first bit line 4 is referred to as a reference first bit line 4r.
The second bit line 5 is paired with the first bit line 4, is provided extending in the Y-axis direction, and is connected to the Y-side current termination circuit 14. The reference second bit line 5 is referred to as a reference second bit line 5r.
The read bit line 35 is paired with the first bit line 4 and the second bit line 5, and is provided extending in the Y-axis direction. One end is provided to the read Y selector 11-2 and the other end is provided to the Y side current termination. It is connected to the circuit 14. The reference read bit line 35 is referred to as a reference read bit line 35r.
The word line 3 is provided so as to extend in the X-axis direction (word line direction) as a second direction substantially perpendicular to the Y-axis direction, and is connected to the X selector 8.
Each memory cell 2 is provided corresponding to each of the positions where a plurality of sets of the first bit line, the second bit line, and the read bit line intersect with a plurality of word lines.

The X selector 8 selects one word line 3 as the selected word line 3s from the plurality of word lines 3 in both the data read operation and the write operation.
The Y selector 11-1 selects one first bit line 4 from the plurality of first bit lines 4 as the selected first bit line 4s during the write operation.
The read Y selector 11-2 selects one read bit line 35 as a selected read bit line 35s from the plurality of read bit lines 35 during a data read operation.
Here, the memory cell 2 selected by the selected word line 3s and the selected first bit line 4s is referred to as a selected cell 2s.

The Y-side current source circuit 12 is a current source that supplies or draws a predetermined current to the selected first bit line 4s during a data write operation.
The Y-side current termination circuit 14 selects one second bit line 5 that forms a pair with the selected first bit line 4s as the selected second bit line 5s from the plurality of second bit lines 5 during the data write operation. . Further, the selective read bit line 35 is precharged to a predetermined voltage during the data read operation. A Y-side current termination circuit 14b for controlling the first bit line 4 and the second bit line and a Y-side current termination circuit 14a for controlling the read bit line 35 are provided.
The Y-side power supply circuit 19 supplies a predetermined voltage to the Y-side current termination circuit 14 during a data write operation and a read operation.
Here, the predetermined current from the Y-side current source circuit 12 flows in the path of the selected first bit line 4s-selected cell 2s-selected second bit line 5s into the Y selector 11-1 in accordance with the data to be written. Or it flows in the direction of flowing out from the Y selector 11-1.

The read current load circuit 13 supplies a predetermined current to the selected read bit line 35s-selected cell 2s-selected first bit line 4s during a data read operation. Similarly, during a data read operation, a predetermined current is passed through the reference read bit line 35r, the reference cell 2r, and the reference first bit line 4r.
The sense amplifier 15 reads data from the selected cell 2s based on the difference between the voltage of the reference read bit line 35r connected to the reference cell 2r and the voltage of the selected read bit line 35s connected to the selected cell 2s. Output.

  Here, the basic structure of the reference cell 2r is the same as that of the normal memory cell 2. However, the resistance value is predetermined (the voltage drop of the magnetoresistive element 7 having data “1” and the voltage drop of the magnetoresistive element 7 having data “0” due to the predetermined current flowing through the read current load circuit 13. And has a voltage drop that is intermediate to the minute) and is referred to during the read operation of the other memory cell 2. Such setting can be made by setting the value of the current passed through the reference cell 2r or changing the film characteristics (film thickness, material) of the magnetoresistive element 7 of the reference cell 2r.

FIG. 80 is a view of the memory cell array of the MRAM shown in FIG. 79 as viewed from above the substrate on which the memory cell array is manufactured (in the positive direction of the Z axis). In this figure, 2 × 2 memory cells 2 in the memory cell array 1 are shown as representatives.
In the first MOS transistor 6 of the memory cell 2, the source 6 a (first terminal) is connected to the first bit line 4 via the contact wiring 28. The gate 6b (first gate terminal) uses the word line 3-1 branched from the word line 3 in the Y-axis direction. The drain 6c (second terminal) is connected to the drain 16c (sixth terminal) of the second MOS transistor 16 through the contact wiring 27, the lead-out wiring layer 29, and the contact wiring 37. The second MOS transistor 16 uses a word line 3-2 in which a gate 16b (second gate terminal) branches from the word line 3 in the Y-axis direction. The source 16 a (fifth terminal) is connected to the second bit line 5 through the contact wiring 38.

  The magnetoresistive element 7 is provided on the lead wiring layer 29. The direction of spontaneous magnetization is reversed by the current flowing through the lead wiring layer 29. Here, since the current flowing through the lead wiring layer 29 flows in the X-axis direction, the direction of the magnetic field felt by the magnetoresistive element 7 is the Y-axis direction. Therefore, it is provided in a shape that facilitates magnetization in the Y-axis direction. For example, an ellipse having a long axis parallel to the Y-axis direction or a shape similar to an ellipse. One end (fourth terminal) of the magnetoresistive element 7 is connected to the lead-out wiring layer 29, and the other end (third terminal) is connected to the read bit line 35.

FIG. 81 shows the structure of the memory cell 2 and shows a cross section taken along line MM ′ in FIG.
The first MOS transistor 6 is formed on the surface portion of the semiconductor substrate. A source 6a as a first diffusion layer provided in the semiconductor substrate is connected to the first bit line 4 via a contact wiring 28 extending in the Z-axis direction. The drain 6c as the second diffusion layer is connected to one end of the lead-out wiring layer 29 via a contact wiring 27 extending in the Z-axis direction. The gate 6 b as the first gate uses the word line 3-1 branched from the word line 3. However, the drain 6c is provided inside the memory cell 2 with respect to the source 6a.
The second MOS transistor 16 is formed on the surface portion of the semiconductor substrate. A source 16a as a third diffusion layer provided in the semiconductor substrate is connected to the second bit line 5 through a contact wiring 38 extending in the Z-axis direction. The drain 16c as the fourth diffusion layer is connected to the other end of the lead-out wiring layer 29 via a contact wiring 37 extending in the Z-axis direction. The gate 16 b as the second gate uses the word line 3-2 branched from the word line 3. However, the drain 16c is provided inside the memory cell 2 with respect to the source 16a.
The magnetoresistive element 7 is connected to the lead wiring layer 29 on one end side. The other end is connected to the read bit line 35 via the contact wiring 26.

The memory cell array according to the present embodiment can have a smaller parasitic capacitance than the memory cell array according to the first embodiment. This will be described with reference to FIGS. 82 and 83. FIG.
FIG. 82 is a diagram illustrating parasitic capacitance in the memory cell 2 according to the first embodiment. When the parasitic capacitance is considered, there is one selected cell, and the non-selected cell is mainly considered. The memory cell in this figure is a non-selected cell (the first MOS transistor 6 and the second MOS transistor are off). In this case, in the diffusion capacitor element (Cdif) including the diffusion layers (6a, 6c, 16a, 16c), the counter electrode is the substrate potential. In the case of the first embodiment, since the substrate potential is the GND potential and the potential does not move, the parasitic capacitance value is substantially fixed. In FIG. 82, there are two Cdif for one transistor. Since the parasitic capacitance element of the magnetoresistive element 7 is Ctmr and one end is at the GND potential, Ctmr is also generally fixed in this case. Here, the effective capacitance value Cc at the cell node N1 is represented by the following series coupling of capacitive elements.
1 / Cc = 1 / C (Ctmr) + 1/2 × C (Cdif) (a)
However, C (Ctmr) and C (Cdif) are capacitance values of Ctmr + Cdif, respectively. Here, since Cdif and Ctmr are fixed, Cc is also substantially fixed.

  FIG. 83 is a diagram showing parasitic capacitance in the memory cell 2 of the present embodiment. In the case of the present embodiment, one terminal of the magnetoresistive element 7 is connected to the read bit line 35 instead of GND. Therefore, C (Ctmr) of the parasitic capacitance element of the magnetoresistive element 7 varies depending on the potential of the read bit line 35. With reference to the above equation (a), if C (Cdif) is constant, Cc becomes maximum when C (Ctmr) is infinite. However, even in that case, Cc does not exceed the conventional 2 × C (Cdif). Actually, since C (Ctmr) is about 2 × C (Cdif), Cc is half that of the first embodiment. That is, the memory cell array according to the present embodiment can reduce the parasitic capacitance as compared with the memory cell array according to the first embodiment.

Next, the operation of the thirty-second embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained.
FIG. 84 is a diagram for explaining the operation of the 32nd embodiment of the magnetic random access memory (MRAM) including the magnetic memory cell of the present invention. That is, FIG. 84 is a circuit diagram illustrating a circuit for writing and reading paths, taking one memory cell 2 as an example. FIG. 85 is a diagram showing a timing chart in the read operation. FIG. 86 shows a timing chart in the write operation.

Referring to FIG. 84, reading of data from memory cell 2 is performed as follows.
First, during the read operation, the first bit line 4 and the second bit line 5 (including the reference first and second bit lines 4r and 5r) are always at the GND potential by the Y-side current termination circuit 14b (FIG. 85). Then, BLU5 and BLL4 are always at GND potential). Further, the plurality of read bit lines 35 (including the reference read bit line 35r), all the precharge potential Vpr are precharged to (in FIG. 85, RBLi35 is turned Vpr with _{t R1).}
(1) Step S361
X selector 8, a row address: the input (2 bits X0 and X1), selects a selected word line 3s of a plurality of word lines 3 (in FIG. 85, WL3 becomes high at _{t R1).} The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(2) Step S362
The Y-side current termination circuit 14a receives the read active signal RA (in FIG. 85, RA becomes high at t _R1 ). Thereby, the connection between the plurality of read bit lines 35 and the precharge potential Vpr is turned off. On the other hand, the column address (2 bits: Y0 and Y1) is input to the read Y selector 11-2. As a result, the selected read bit line 35 s is selected from the plurality of read bit lines 35. Then, by the read active signal RA, the read current load circuit 13 causes the precharge voltage Vpr to be applied to the magnetoresistive elements 7 of the selected cell 2s and the reference cell 2r. Thereby, a predetermined current Is is supplied to the selected read bit line 35s, and a predetermined current Ir is supplied to the reference read bit line 35r. In this case, since the precharge voltage is continuously applied to the selected read bit line 35s, the current Is can be supplied without charging the parasitic capacitance of the bit line.
At this time, the selected first bit line 4s (GND) is connected from the read current load circuit 13 via the selected read bit line 35s (generally precharge voltage) via the magnetoresistive element 7-first MOS transistor 6 of the selected cell 2s. Current Is flows into (potential) (in FIG. 85, RBLi35 becomes Vpr or Vpr−Δ depending on the data of the selected cell 2s during t _R2 to t _R5 ). Similarly, magnetoresistive element 7-first MOS transistor of read current load circuit 13-reference read bit line 35r-selected reference cell 2r (reference cell 2r corresponding to the intersection of selected word line 3s and reference first bit line 4r). 6, the current Ir flows into the reference first bit line 4r.
(3) Step S363
Based on the read active signal RA, the sense amplifier 15 is based on the difference between the voltage of the selected read bit line 35s when the predetermined current Is is passed and the voltage of the reference read bit line 35r when the predetermined current Ir is passed. Then, either “1” or “0” is output (in FIG. 85, when OUT is between t _R3 and t _R6 , a predetermined value is output according to the data of the selected cell 2s).
Thereafter, the X selector 8 releases the selected word line 3, the read active signal RA becomes low (t _{R4 in} FIG. 85), the current Is stops (t _{R5 in} FIG. 85), and the output stops (t in FIG. 85). _R6 ), the read operation is completed (t _{R7 in} FIG. 85).

  With the above read operation, data of the selected cell 2s can be read.

Referring to FIG. 84, data is written to memory cell 2 as follows.
First, during the write operation, all of the plurality of read bit lines 35 (including the reference read bit line 35r) are precharged to the precharge potential Vpr (in FIG. 86, RBLi35 is always at Vpr).

(1) Step S371
X selector 8, a row address: the input (2 bits X0 and X1), selects a selected word line 3s of a plurality of word lines 3 (in FIG. 86, WL3 becomes high at _{t W1).} The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(2) Step S372
A column address (2 bits: Y0 and Y1) is input to the Y selector 11-1. As a result, the selected first bit line 4s is selected from the plurality of first bit lines 4. Y-side current termination circuit 14b is input to the write active signal WA (in FIG 86, WA is high at _{t W1).} As a result, the selected second bit line 5s is selected from the plurality of second bit lines 5. A pair of the selected first bit line 4s and the selected second bit line 5s is selected.
At this time, the Y-side current termination circuit 14b applies a predetermined voltage Vterm to the selected second bit line 5s. Based on the write active signal WA and the data signal Data, the Y-side current source circuit 12 has a current Iw (0) (in the case of “0”: Y-side current source circuit 12 having a predetermined magnitude corresponding to the data signal Data. ) Or current Iw (1) (in the case of “1”, the direction of flowing out from the Y-side current source circuit 12) flows to the selected first bit line 4s−selected cell 2s (in FIG. 86, BLU5 and BLL4 are between t _W2 of _{t R4,} it becomes one of two potential between the GND potential and Vtrem according to the data of the selected cell 2s).
The current Iw (0) or the current Iw (1) is generated by selecting the selected second bit line 5s-the second MOS transistor 16 of the selected cell 2s (-the lead wiring layer 29 of the selected cell 2s) -the first MOS transistor 6 of the selected cell 2s. The path of the first bit line 4s flows in the forward or reverse direction.
(3) Step S373
In the selected cell 2s, when the current Iw (0) (+ X direction) or the current Iw (1) (−X direction) flows on the lead-out wiring layer 29 in contact with the magnetoresistive element 7, the −Y direction or + Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal Data is stored.
Thereafter, the X selector 8 releases the selected word line 3, the write active signal WA becomes low (t _{W3 in} FIG. 86), the current Is stops (t _{W4 in} FIG. 86), and the write operation ends (FIG. 86). Then t _W5 ).

  The reference active signal SR is a signal for selecting the reference cell 2r when writing to the reference cell 2r, and corresponds to the write active signal WA in the normal memory cell 2.

  With the above write operation, data can be written to the selected cell 2s.

  Note that by setting the precharge potential Vpr to the same level as the potential of the lead-out wiring layer 29 of the magnetoresistive element 7 during the write operation, it may be set so that no tunnel current flows in the magnetoresistive element 7 during the write operation. Is possible. That is, at the time of data write operation, both ends of the magnetoresistive element 7 are at the same voltage (precharge voltage Vpr) and the potential difference is eliminated, so that loss of write current in the memory cell 2 can be prevented. That is, it is possible to improve the accuracy of the write current.

According to the present embodiment, the same effects as those of the first embodiment can be obtained.
In addition, since one end of the magnetoresistive element is connected to the read bit line and the potential of the read bit line is set to a predetermined precharge voltage, the influence is further reduced without charging the parasitic capacitance of the bit line. It becomes possible. That is, the parasitic capacitance of the bit line can be effectively reduced, and the operation speed of the element can be improved.

(Thirty-third embodiment)
A thirty-third embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described.

  The configuration of the 33rd embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be described. FIG. 87 is a diagram showing the configuration of a thirty-third embodiment of a magnetic random access memory (MRAM) including magnetic memory cells of the present invention. FIG. 87 shows a configuration in which the circuit example of the MRAM shown in FIG. 79 is hierarchized. The MRAM according to the present embodiment includes cell arrays 41h-0 to 41h-3, a cell array selector 44a, a Y-side current source circuit 42, a Y-side current termination circuit 14a '', a read current load circuit 13, and a sense amplifier 15.

The cell arrays 41h-0 to 41h-3 include a memory cell array 1, a plurality of word lines 3, a plurality of first bit lines 4 (including a reference first bit line 4r), and a plurality of second bit lines 5 (reference second bits). A plurality of read bit lines 35 (including a reference read bit line 35r), an X selector 8 and a Y selector 11-1a (however, selection / non-selection of the reference first bit line 4r), read Y A selector 11-2a, a Y-side current termination circuit 14a ′, and a Y-side current termination circuit 14b ′ are provided. Each configuration is such that the Y selector 11-1a can select not only the first bit line 4 but also the reference first bit line 4r, and the Y-side current termination circuit 14b ′ has an external power source. Since this is the same as in the thirty-second embodiment, its description is omitted.
In FIG. 87, four cell arrays 41 are shown, but the present invention is not limited to this number.

  The cell array selector 44a is based on a cell array selection signal MWSi for selecting the cell array 41h (i = integer of 0-3: number of the cell array 41h), a selector write transistor 44a-1a, a selector read transistor 44a-1b, and a selector The selected cell array 41h-i is selected by the read transistor 44a-1c and the selector write transistor 44a-2. The selected cell array 41h-i is connected to the Y-side current source circuit 42 by the first write main bit line 68-1 and the second write main bit line 68-2 and performs a data write operation. The first read main bit line 69-1 and the second read main bit line 69-2 are connected to the read current load circuit 13, the sense amplifier 15, and the Y-side current termination circuit 14a '', and Read operation is performed.

  The Y-side current termination circuit 14a '' precharges the first read main bit line 69-1 and the second read main bit line 69-2 to the precharge voltage Vpr except when the read active signal RA (described later) is high. Charge.

The Y-side current source circuit 42 is a current source that supplies and draws a predetermined current between the selected first bit line 4s and the selected second bit line 5s of the selected cell array 41h-i for data writing. .
For example, during the write operation of data “1”, current is supplied to the second write main bit line 68-2-cell array selector 44a (selector write transistor 44a-1a) -selected cell array 41h-i, and the Y selector 11-1a. -Selected first bit line 4s-Selected cell 2s-Selected second bit line 5s-Y-side current source termination circuit 14b '-Cell array selector 44a (selector write transistor 44a-2)-First write main bit line 68-1 A current flows through a path (first write main bit line 68-2 is fixed to ground).
During the write operation of data “0”, the current is supplied to the first write main bit line 68-1-cell array selector 44a (selector write transistor 44a-2) -selected cell array 41h-i in the reverse direction, and the Y-side current Source termination circuit 14b'-selected second bit line 5s-selected cell 2s-selected first bit line 4s-Y selector 11-1a-cell array selector 44a (selector write transistor 44a-1a) -first write main bit line 68 -1 (the first main bit line 68-1 is fixed to the ground) is supplied with current. However, 42a generates a constant current, and 42b selects a current supply direction.

The read current load circuit 13 supplies a predetermined current to the selected read bit line 35s of the selected cell array 41h-i during the data read operation. At the same time, a predetermined current is supplied to the reference read bit line 35r of the selected cell array 41h-i. That is, during the data read operation, the current flows through the second read main bit line 69-1-cell array selector 44a (selector read transistor 44a-1c) -read Y selector 11-2a-selected read bit line 35s-selected cell 2s. Shed. At the same time, a current flows through the first read main bit line 69-1-cell array selector 44a (selector read transistor 44a-1b) -selected read bit line 35s-reference cell 2r.
The sense amplifier 15 determines the voltage of the selected cell 2s based on the difference between the voltage of the second read main bit line 69-2 connected to the reference cell 2r and the voltage of the first read main bit line 69-1 connected to the selected cell 2s. Output the read data.

  Next, the operation of the 33rd embodiment of the magnetic memory cell and magnetic random access memory of the present invention will be explained. However, YSWj (j = 0 to m: m + 1 is the number of first bit lines 4) is a signal for selecting the j-th first bit line 4, WA is a write active signal, and RA is a read active signal. YSWR is a signal for selecting a reference cell during a read operation and a write operation, and YSWRW is a signal for selecting a reference cell 2r during a write operation. SR is a signal for activating the reference cell 2r when writing to the reference cell 2r. The same applies throughout this specification.

In the MRAM shown in FIG. 87, data is read from the memory cell 2 as follows. The plurality of read bit lines 35 (including the reference read bit line 35r) are all precharged to the precharge potential Vpr by the Y-side current termination circuit 14a ′ except when the cell array selection signal MWSi is high.
(1) Step S381
The cell array selector 44a turns on the selector read transistor 44a-1c, the selector read transistor 44a-1b, and the selector write transistor 44a-1a based on the cell array selection signal MWSi for selecting any one of the cell arrays 41h-i. The selected cell array 41h-i is selected.
At this time, the selected cell array 41h-i, the read current load circuit 13, the sense amplifier 15, and the Y-side current termination circuit 14a '' have the first read main bit line 69-1 and the second read main bit line 69. -2 to connect.
(2) Step S382
The X selector 8 of the selected cell array 41h-i selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(3) Step S383
The read Y selector 11-2a of the selected cell array 41h-i selects the selected read bit line 35s from the plurality of read bit lines 35 in response to the column address input. The Y selector 11-1a selects the selected first bit line 4s from the plurality of first bit lines 4 and selects the reference first bit line 4r by the input of the column address. At this time, the reference read bit line 35r is selected by the selector read transistor 44a-1b. Then, in response to the read active signal, the read current load circuit 13 causes the magnetoresistive element 7-first MOS of the selected cell 2s to pass through the second read main bit line 69-2-read Y selector 11-2a-selected read bit line 35s. The current Is is supplied to the selected first bit line 4s-Y selector 11-1a-second write main bit line 68-2 (GND potential) via the transistor 6. At the same time, the first read main bit line 69-1—the reference read bit line 35r—the magnetoresistive element 7 of the selected reference cell 2r—the first MOS transistor 6 and the reference first bit line 4r—the Y selector 11-1a— The current Ir is supplied to the second write main bit line 68-2 (GND potential).
(4) Step S384
Depending on the read active signal, the sense amplifier 15 is either “1” or “0” based on the potential difference between the potential of the second read main bit line 69-2 and the potential of the first read main bit line 69-1. Output one.

  With the above read operation, the data of the desired selected cell 2s in the desired selected cell array 41b-i can be read.

  Data is written to the memory cell 2 as follows. During the write operation, the plurality of read bit lines 35 (including the reference read bit line 35r) are all precharged to the precharge potential Vpr by the Y-side current termination circuit 14a '.

(1) Step S391
The cell array selector 44a turns on the selector write transistor 44a-1a and the selector write transistor 44a-2 based on the cell array selection signal MWSi for selecting any one of the cell arrays 41h-i, and selects the selected cell array 41h-i. select.
At this time, the selected cell array 41h-i and the Y-side current source circuit 42 are connected by the second write main bit line 68-2 and the first write main bit line 68-1.
(2) Step S392
The X selector 8 of the selected cell array 41h-i selects the selected word line 3s from the plurality of word lines 3 in response to the input of the row address. The first MOS transistor 6 and the second MOS transistor 16 of each memory cell 2 are turned on.
(3) Step S393
The first Y selector 11′a of the selected cell array 41h-i selects the selected first bit line 4s from the plurality of first bit lines 4 in response to the input of the column address. In addition, the Y-side current termination circuit 14b ′ selects the selected second bit line 5s from the plurality of second bit lines 5 by the write active signal. A pair of the selected first bit line 4s and the selected second bit line 5s is selected.
(A) When writing “1” The first write main bit line 68-1 is fixed to the ground. That is, the selected second bit line 5s is fixed to the ground via the Y-side current termination circuit 14b ′. The Y-side current source circuit 42 has a current Iw (1) having a predetermined magnitude corresponding to the data signal based on the write active signal and the data signal (“1”) (direction flowing out from the Y-side current source circuit 42). The second write main bit line 68-2-cell array selector 44a-Y selector 11-1a-selected first bit line 4s-selected cell 2s-selected second bit line 5s-Y-side current termination circuit 14b'-cell array selector 44a-first write main bit line 68-1--flow through the ground path.
(B) Writing “0” The second write main bit line 68-2 is fixed to the ground. That is, the selected first bit line 4s is fixed to the ground via the Y selector 11-1a. The Y-side current source circuit 42 has a current Iw (0) having a predetermined magnitude corresponding to the data signal based on the write active signal and the data signal (“0”) (direction flowing out from the Y-side current source circuit 42). First write main bit line 68-1-cell array selector 44a-Y-side current termination circuit 14b'-selected second bit line 5s-selected cell 2s-selected first bit line 4s-Y selector 11-1a-cell array selector 44a-second write main bit line 68-2-flows through a ground path.
(4) Step S394
In the selected cell 2s, when the current Iw (0) (−X direction) or the current Iw (1) (+ X direction) flows on the lead wiring layer 29 in contact with the magnetoresistive element 7, the + Y direction or −Y Magnetic field is generated in the direction. The spontaneous magnetic field of the free layer 21 of the magnetoresistive element 7 is reversed by the magnetic field, and the spontaneous magnetization corresponding to the data signal is stored.

  Through the above write operation, data can be written to the desired selected cell 2s in the desired selected cell array 41h-i.

According to the present embodiment, the same effect as in the thirty-second embodiment can be obtained.
In addition, since the read transistor and the write transistor can be used separately in the cell array selector 44a, the transistor size can be made different when the write current and the read current are different. Thereby, even when the magnitudes of the write current and the read current are different, the write operation and the read operation can be stably performed.
Further, according to the present invention, the MRAM can be made compact by hierarchizing the cell array and sharing some circuits.

  FIG. 88 is an application of the memory cell shown in FIG. 20 to the memory cell shown in FIG. Its configuration and operation are the same as those in FIG. 79 except that it shares the diffusion layer of the transistors adjacent in the bit line direction (partly refer to the operation in FIG. 20), and a description thereof will be omitted. In this case as well, the same effects as those of the thirty-second embodiment and the same effects as in the case of FIG.

  FIG. 89 is an application of the memory cell shown in FIG. 41 to the memory cell shown in FIG. The configuration and operation are the same as those in FIG. 79 except that the bit line is divided into two and the two transistors are controlled separately (partly refer to the operation in FIG. 41), and the description thereof is omitted. Also in this case, it is possible to obtain the same effect as that of the thirty-second embodiment and the same effect as in the case of FIG. 41 (the second bit line can be shared by two memory cells 2 and the element can be miniaturized, etc.). it can.

  FIG. 90 is an application of the memory cell shown in FIG. 56 to the memory cell shown in FIG. The configuration and operation are the same as those in FIG. 79 except that the second MOS transistor in FIG. 79 is replaced with two diodes (partly refer to the operation in FIG. 56), and thus description thereof is omitted. Also in this case, the same effect as that of the thirty-second embodiment and the same effect as in the case of FIG. 56 (the number of elements directly using the semiconductor substrate can be reduced and the elements can be reduced in size) can be obtained.

  FIG. 91 is an application of the memory cell shown in FIG. 60 to the memory cell shown in FIG. The configuration and operation are the same as those in FIG. 79 except that the second MOS transistor in FIG. 79 is replaced with two diodes (partly refer to the operation in FIG. 60), and thus the description thereof is omitted. Also in this case, the same effect as that of the thirty-second embodiment and the same effect as in the case of FIG. 60 (the number of elements directly using the semiconductor substrate can be reduced and the elements can be reduced in size) can be obtained.

  FIG. 92 is an application of the memory cell shown in FIG. 65 to the memory cell shown in FIG. The configuration and operation are the same as those in FIG. 79 except that the number of the two transistors in FIG. 79 is increased to two (partly refer to the operation in FIG. 65), and thus description thereof is omitted. Also in this case, the same effect as in the thirty-second embodiment and the same effect as in the case of FIG. 65 (the number of MOS transistors in the memory cell can be increased without increasing the chip area, and the current flowing through the memory cell) Etc.) can be obtained.

  In all the embodiments described above, specific circuits shown as each selector, each current source circuit, each current load circuit, each sense amplifier, and each current termination circuit are examples. Therefore, the present invention is not limited to them, and can be used in other circuit configurations as long as they have similar functions and operations.

  The techniques described in the above embodiments can be used in other embodiments as long as there is no technical contradiction.

  Since the MRAM of the present invention has high selectivity for memory cells in the write operation, malfunctions can be significantly reduced. Thereby, the MRAM can be manufactured with a high yield, and as a result, an inexpensive nonvolatile memory can be manufactured. The present invention is not limited to the above embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention.

It is a figure which shows the structure of 1st, 5th, 7th, 11th embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is the figure which looked at MRAM shown in FIG. 1 from the upper direction (positive direction of a Z-axis). It is a figure which shows a ground wiring. (A) It is a figure which shows the AA 'cross section in FIG. 2 of a memory cell. (B) It is sectional drawing which shows the structure of a magnetoresistive element. It is a figure explaining operation | movement of 1st Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. Is a graph showing a comparison between the magnetic field H ₀ and Asuteroito Bu curve applied to the magneto-resistance element of the selected cell. It is a figure which shows the structure of 2nd Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the structure of 3rd, 6th, 8th, 12th embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is the figure which looked at MRAM shown in Drawing 8 from the upper part (positive direction of a Z-axis). It is a figure which shows the BB 'cross section in FIG. 9 of a memory cell. It is a figure which shows the structure of 4th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. Cell array 41'-1 to 41'-4 It is the figure which looked at MRAM shown in FIG. 1 from the upper direction (positive direction of a Z-axis). It is a figure which shows CC 'cross section in FIG. 12 of a memory cell. (A) (b) It is a graph which shows the magnetic field which may be applied to a selection cell and a non-selection cell. It is the figure which looked at MRAM shown in Drawing 8 from the upper part (positive direction of a Z-axis). It is a figure which shows DD 'cross section in FIG. 15 of a memory cell. It is the figure which looked at MRAM shown in FIG. 1 from the upper direction (positive direction of a Z-axis). It is a graph which shows the magnetic field of a write current, and the asteroid curve of a magnetoresistive element. It is the figure which looked at MRAM shown in Drawing 8 from the upper part (positive direction of a Z-axis). It is a figure which shows the structure of 9th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is the figure which looked at MRAM shown in FIG. 20 from upper direction (positive direction of Z-axis). (A)-(c) It is a graph regarding the magnetic field which may be applied to a selection cell. It is a figure which shows the structure of 10th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is the figure which looked at MRAM shown in FIG. 23 from upper direction (positive direction of Z-axis). It is the figure which looked at MRAM shown in FIG. 1 from the upper direction (positive direction of a Z-axis). It is a figure which shows the EE 'cross section in FIG. 25 of a memory cell. It is the figure which looked at MRAM shown in Drawing 8 from the upper part (positive direction of a Z-axis). It is a figure which shows the FF 'cross section in FIG. 27 of a memory cell. It is a figure which shows the structure of 13th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the structure of 14th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the structure of 15th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the structure of 16th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the structure of 17th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the structure of 18th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the structure of 19th Embodiment of the magnetic random access memory (MRAM) containing the magnetic memory cell of this invention. It is a figure which shows the structure of 20th Embodiment of the magnetic random access memory (MRAM) containing the magnetic memory cell of this invention. FIG. 37 is a diagram showing changes in signals during a read operation of the MRAM in FIG. 36. FIG. 37 is a diagram showing changes in signals during a read operation of the MRAM in FIG. 36. FIG. 37 is a diagram showing changes in signals during the write operation of the MRAM in FIG. 36. FIG. 37 is a diagram showing changes in signals during the write operation of the MRAM in FIG. 36. It is a figure which shows the structure of 21st Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is the figure which looked at MRAM shown in FIG. 41 from upper direction (positive direction of Z-axis). It is a figure which shows the structure of 22nd Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is the figure which looked at MRAM shown in FIG. 43 from upper direction (positive direction of Z-axis). FIG. 44 is a diagram showing a GG ′ cross section of the memory cell in FIG. 43. It is a figure which shows the structure of 23rd Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. (A) (b) It is a graph explaining the characteristic of a diode. It is the figure which looked at MRAM shown in FIG. 46 from upper direction (positive direction of Z-axis). FIG. 49 is a diagram showing a gg ′ cross section of the memory cell in FIG. 48. It is a figure which shows the cross-sectional structure at the time of laminating | stacking a memory cell. It is a figure which shows the structure of 24th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the structure of 25th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is the figure which looked at MRAM shown in Drawing 8 from the upper part (positive direction of a Z-axis). FIG. 54 is a diagram showing a HH ′ cross section of the memory cell in FIG. 53. It is a figure which shows the structure of 26th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the structure of 27th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is the figure which looked at MRAM shown in FIG. 56 from upper direction (positive direction of Z-axis). FIG. 58 is a diagram showing a II ′ cross section of the memory cell in FIG. 57. It is a figure which shows the structure of 28th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the structure of 29th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a graph explaining the characteristic of a diode. FIG. 61 is a view of the MRAM shown in FIG. 60 as viewed from above (the positive direction of the Z axis). FIG. 63 is a diagram showing a JJ ′ cross section of the memory cell in FIG. 62. It is a figure which shows the structure of 29th Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the structure of 31st Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. FIG. 66 is a view of the MRAM shown in FIG. 65 as viewed from above (in the positive direction of the Z axis). FIG. 67 is a diagram showing a KK ′ cross section of the memory cell in FIG. 66. FIG. 66 is a diagram of another configuration of the MRAM shown in FIG. 65 viewed from above (the positive direction of the Z axis). FIG. 69 is a diagram showing a LL ′ cross section in FIG. 68 of another configuration of the memory cell. It is a graph which shows the relationship between the gate length of a transistor, and a threshold voltage. It is a graph which shows the relationship between the current capability of a transistor, and gate length. It is a graph which shows the relationship between the gate length of a transistor, and a threshold voltage. It is sectional drawing which shows the other application example of 1st Embodiment of the magnetic memory cell and magnetic random access memory of this invention. It is a graph which shows the characteristic of a laminated ferri structure. (A)-(c) The structure of a laminated ferri structure is shown. It is a figure which shows the function of the magnetic structure comprised by a magnetoresistive element and a laminated ferri structure. It is a figure which shows the structure which shows the other application example of the 7th Embodiment of the magnetic memory cell and magnetic random access memory of this invention. It is a graph which shows the asteroid characteristic in the case of FIG. The vertical axis represents the magnetic field in the Y direction, and the horizontal axis represents the magnetic field in the X direction. It is a figure which shows the structure of 32nd Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. FIG. 80 is a diagram seen from above (the positive direction of the Z axis) of the MRAM shown in FIG. 79. FIG. 81 is a diagram showing a MM ′ cross section of the memory cell 2 in FIG. 80. It is a figure which shows the parasitic capacitance in the memory cell 2 of 1st Embodiment. It is a figure which shows the parasitic capacitance in the memory cell 2 of this Embodiment. It is a figure explaining operation | movement of 32nd Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. It is a figure which shows the timing chart in read-out operation | movement. It is a figure which shows the timing chart in write-in operation | movement. It is a figure which shows the structure of 33rd Embodiment of the magnetic random access memory containing the magnetic memory cell of this invention. The memory cell shown in FIG. 20 is applied to the memory cell shown in FIG. The memory cell shown in FIG. 41 is applied to the memory cell shown in FIG. The memory cell shown in FIG. 56 is applied to the memory cell shown in FIG. The memory cell shown in FIG. 60 is applied to the memory cell shown in FIG. The memory cell 20 shown in FIG. 65 is applied to the memory cell shown in FIG. (A) (b) It is the figure which showed the principle of the magnetoresistive element contained in a magnetic memory cell. It is a figure which shows the cross section of a memory cell. It is a figure which shows the principle of the writing of the data to a magnetoresistive element. It is a figure which shows the conventional MRAM using a memory cell.

Explanation of symbols

1, 10 memory cell array 2, 2a, 2b, 2c-1 to 2, 2d, 2e, 2f, 2h,
20, 20a, 20b, 20c-1 to 2, 20d,
20f, 20g, 20h, 20j, 30 Memory cells 2r (-1 to 2), 20r (-1 to 2), 30r Reference cells 2s, 20s Selected cells 3, 3a, 3b, 3-1 to 2 Word lines 3c ( -1) First word line 3d (-2) Second word line 3s Selected word line 3p Precharge word line 3W (a, b) Write word line 3R (a, b) Read word line 4 (a, b) 1 bit line 4r reference first bit line 4s selection first bit line 5 second bit line 5r reference second bit line 5s selection second bit line 6 (-1) first MOS transistor 6-2 third MOS transistor 6a source 6b gate 6c Drain 6d, 6e Diffusion layer 7 Magnetoresistive element 7-1 Laminated ferri structure 7-2 First magnetic layer 7-3 Nonmagnetic spacer layer 7-4 2 Magnetic layer 8 X selector 9 X side power supply circuit 10 Substrate 11 (','', d), 11-1 Y selector 11-2 Read Y selector 11'a First Y selector 11'b Second Y selector 11r Reference cell selector 12 Y side current source circuit 12v Y side voltage source circuit 13 Read current load circuit 14 ('') Y side current termination circuit 15 Sense amplifier 16 (-1) 2nd MOS transistor 16-2 4th MOS transistor 16a Source 16b Gate 16c Drain 17 (a) Cell array selector 17-1 to 2 Selector transistor 19 Y side power supply circuit 18-1 First main bit line 18-2 Second main bit line 21 Free layer 22 Tunnel insulating layer 23 Pin layer 23
24 (-1) Ground (GND) wiring 25, 35 Interlayer insulating layer 26, 27, 28 (-1, 2), 37, 38 (-1, 2), 53 (a, b), 54 (a, b) ), 55 (a, b), 56 (a, b), 59, 61 Contact wiring 29 (a, b) Lead wiring layer 31 (a, b) First diode 32 (a, b) Second diode 33 ( a, b) Third diode 35 Read bit line 35s Select read bit line 35r Reference read bit line 41 (')-1-4, 41a-1-4, 41b-1-4, 41c-1-4, 41d- 0-3, 41e-0-3, 41f-0-3, 41g-0-3, 41h-0-3 Cell array 41 (') s, 41as, 41bs, 41cs Selected cell array 42 Y side current source circuit 44, 44a Cell array selector 44- ˜2 Selector transistor 44a-1a Selector write transistor 44a-1b Selector read transistor 44a-1c Selector read transistor 44a-2 Selector write transistor 45 Precharge line 46 Precharge power supply 47 Precharge selector 48 Precharge voltage line 49 (−1-2) Precharge transistors 51b-1-4, 51c-1-4 Cell array 58 Y side power supply circuit 60 Wiring layer 62 First main bit line 63 Second main bit line 64 Third main bit line 68- DESCRIPTION OF SYMBOLS 1 1st write main bit line 68-2 2nd write main bit line 69-1 1st read main bit line 69-2 2nd read main bit line 71 1st Y selector 72 2nd Y selector 73 sense amplifier 74 Read current load circuit 75 (−1 to 2) Column selection transistor 76 (−1 to 2) Reference selection transistor 77 Third transistor 81 (−1 to 2) Sense line 82 Read current signal line 83 Comparison signal line 84 (− 1-2) Data bus line 85 Column signal line 90 Data processing unit 101 Memory cell array 102 Memory cell 103 Write word line 104 Read word line 105 Bit line 106 MOS transistor 107 Magnetoresistive element 108 X selector 109 X side current source circuit 110 X Side current termination circuit 111 Y selector 112 Y side current source circuit 113 Read current load circuit 114 Y side current termination circuit 115 Sense amplifier 121 Free layer 122 Tunnel insulating layer 123 Pin layer 124 Antiferromagnetic layer 126, 127, 1 8 contact wiring 129 lead-out wiring

Claims (74)

A first transistor including a first gate, a first terminal as one terminal other than the first gate, and a second terminal as the other terminal;
A magnetoresistive element having spontaneous magnetization whose magnetization direction is reversed according to stored data, and including a third terminal as one terminal and a fourth terminal as the other terminal;
The first terminal is connected to a first bit line;
The second terminal is connected to a second bit line;
The first gate is connected to a first word line;
The third terminal is connected to a second word line;
The fourth terminal is a memory cell connected to the second terminal. The memory cell of claim 1, wherein
A diode provided between the magnetoresistive element and the second word line, the diode including a seventh terminal having a first polarity and an eighth terminal having a second polarity different from the first polarity;
The seventh terminal is connected to the third terminal;
The eighth terminal is a memory cell connected to a second word line. The memory cell according to claim 1 or 2,
Writing data to the memory cell
The first word line is selected and the first transistor is turned on;
A current flows in a direction based on data through a path including the first transistor between the first bit line and the second bit line, so that a magnetic field generated around the path causes the magnetoresistive element to Memory cells. The memory cell according to any one of claims 1 to 3,
Reading said data from said memory cell,
A memory cell configured to measure a resistance of the magnetoresistive element based on a current flowing through a path including the second bit line, the magnetoresistive element, and the second word line. The memory cell of claim 1, wherein
A second gate provided between the first transistor and the second bit line, including a second terminal, a fifth terminal as one terminal other than the second gate, and a sixth terminal as the other terminal; Further comprising two transistors,
The fifth terminal is connected to the second bit line;
The sixth terminal is connected to the second terminal;
The second gate is connected to the first word line;
The third terminal is a memory cell connected to a ground instead of the second word line. The memory cell of claim 1, wherein
A second gate provided between the first transistor and the second bit line, including a second terminal, a fifth terminal as one terminal other than the second gate, and a sixth terminal as the other terminal; Further comprising two transistors,
The fifth terminal is connected to the second bit line;
The sixth terminal is connected to the second terminal;
The second gate is connected to the first word line;
The third terminal is a memory cell connected to a third bit line instead of the second word line. The memory cell according to claim 5 or 6,
Writing data to the memory cell
When the first word line is selected, the first transistor and the second transistor are turned on,
When a current flows in a direction based on data in a path including the first transistor and the second transistor between the first bit line and the second bit line, the magnetic field generated around the path causes the current to flow. A memory cell for a magnetoresistive element. The memory cell according to any one of claims 5 to 7,
Reading said data from said memory cell,
A memory cell configured to measure a resistance of the magnetoresistive element based on a current flowing through a path including the second bit line, the second transistor, and the magnetoresistive element. The memory cell according to claim 5 or 6,
A third transistor including a third gate, a seventh terminal as one terminal other than the third gate, and an eighth terminal as the other terminal;
A fourth transistor including a fourth gate, a ninth terminal as one terminal other than the fourth gate, and a tenth terminal as the other terminal;
Further comprising
The third gate and the fourth gate branch from the first word line and are connected to a third word line having substantially the same potential as the first word line,
The seventh terminal is connected to the first bit line;
The eighth terminal is connected to the second terminal;
The ninth terminal is connected to the second bit line;
The tenth terminal is a memory cell connected to the sixth terminal. The memory cell of claim 9, wherein
Writing data to each of the plurality of memory cells includes:
The selected word line pair is selected, and the first transistor, the second transistor, the third transistor, and the fourth transistor are turned on,
A current flows in a direction based on data through a path including the first transistor, the second transistor, the third transistor, and the fourth transistor between the selected first bit line and the selected second bit line. A memory cell that performs the magnetoresistive element by a magnetic field generated around the path. The memory cell according to claim 9 or 10,
Reading said data from each of said plurality of memory cells,
A memory cell configured to measure a resistance of the magnetoresistive element based on a current flowing through a path including the selected second bit line, the second transistor, the fourth transistor, and the magnetoresistive element. The memory cell of claim 1, wherein
A second diode provided between the first transistor and the second bit line and including a ninth terminal having a first polarity and a tenth terminal having a second polarity different from the first polarity;
A third diode provided between the first transistor and the second bit line and including an eleventh terminal having the first polarity and a twelfth terminal having the second polarity;
The ninth terminal is connected to the second bit line;
The tenth terminal is connected to the second terminal;
The eleventh terminal is connected to the second terminal;
The twelfth terminal is connected to the second bit line;
The third terminal is a memory cell connected to a predetermined voltage source instead of the second word line. The memory cell of claim 1, wherein
A second diode provided between the first transistor and the second bit line and including a ninth terminal having a first polarity and a tenth terminal having a second polarity different from the first polarity; and the second bit A third diode provided between a line and the second diode and including an eleventh terminal of the first polarity and a twelfth terminal of the second polarity;
The ninth terminal is connected to the second bit line;
The tenth terminal is connected to the twelfth terminal;
The eleventh terminal is connected to the second terminal;
The third terminal is connected to a predetermined voltage source instead of the second word line. A reverse voltage applied to either the second diode or the third diode during the write operation is a breakdown voltage. A memory cell that is above the voltage. The memory cell according to claim 12 or 13,
Writing data to the memory cell
The first word line is selected and the first transistor is turned on;
A voltage difference set based on a threshold voltage of the second diode and the third diode between the first bit line and the second bit line causes a difference between the first bit line and the second bit line. A memory cell that is applied to the magnetoresistive element by a magnetic field generated around the path when a current flows in a direction based on data through a path including the first transistor. The memory cell according to any one of claims 12 to 14,
Reading said data from said memory cell,
A memory cell that is measured by measuring a resistance of the magnetoresistive element based on a current flowing through a path including the second bit line and the magnetoresistive element. A second diode including a first terminal having a first polarity and a second terminal having a second polarity different from the first polarity;
A third diode including a third terminal of the first polarity and a fourth terminal of the second polarity;
A magnetoresistive element having spontaneous magnetization whose magnetization direction is reversed according to stored data, and including a fifth terminal as one terminal and a sixth terminal as the other terminal;
The second terminal and the third terminal are connected to a first word line,
The first terminal, the fourth terminal, and the fifth terminal are connected to a bit line,
The sixth terminal is a memory cell connected to a second word line. The memory cell of claim 16, wherein
A first diode including a seventh terminal having the first polarity and an eighth terminal having the second polarity;
The first diode is provided between the magnetoresistive element and the second word line, and the eighth terminal is connected to the second word line and the seventh terminal is connected to the sixth terminal. . The memory cell according to claim 16 or 17,
Writing data to the memory cell
Due to a voltage difference set based on a threshold voltage of the second diode and the third diode between the first word line and the bit line, the second word between the first word line and the bit line. A memory cell that is applied to the magnetoresistive element by a magnetic field generated around the path when a current flows in a direction based on data through a path including one of two diodes and the third diode. The memory cell according to any one of claims 16 to 18, wherein
Reading said data from said memory cell,
A memory cell that is measured by measuring a resistance of the magnetoresistive element based on a current flowing through a path including the bit line, the magnetoresistive element, and the second word line. A transistor comprising a gate, a first terminal as one terminal other than the gate, and a second terminal as the other terminal;
It has spontaneous magnetization whose magnetization direction is reversed according to stored data, and the third terminal as one terminal is connected to the ground, and the fourth terminal as the other terminal is connected to the second terminal through a wiring. Magnetoresistive element,
A capacitor having a fifth terminal as one terminal connected to the ground and a sixth terminal serving as the other terminal connected to the second terminal via the wiring;
The first terminal is connected to a bit line;
The first gate is a memory cell connected to a word line. The memory cell of claim 20, wherein
Writing data to the memory cell
The word line is selected and the transistor is turned on;
The bit line is selected and the capacitor is charged;
After the capacitor is charged, the memory is performed with respect to the magnetoresistive element by a magnetic field generated based on a current flowing between the capacitor and the bit line by setting the bit line to a predetermined voltage based on data cell. The memory cell according to claim 20 or 21 ,
Reading data into the memory cell is as follows:
The bit line is selected, the capacitor is charged,
The word line is selected and the transistor is turned on at a predetermined speed or less,
For a selected cell selected from the plurality of memory cells by the selected bit line and the selected word line, a predetermined current is applied to the selected cell after the capacitor is charged. A memory cell that is measured by measuring a resistance of the magnetoresistive element when flowing through a path including the resistive element. A plurality of memory cells according to any one of claims 1 to 8, 12 to 22 provided in a matrix,
A plurality of first word lines provided corresponding to each of a plurality of rows included in the matrix;
An X selector that selects a selected first word line from the plurality of first word lines;
In a write operation, the word line corresponding to one memory cell is one of the first word lines. Magnetic random access memory. A plurality of memory cells;
Here, each of the plurality of memory cells includes
A first transistor including a first gate, a first terminal as one terminal other than the first gate, and a second terminal as the other terminal;
A magnetoresistive element having spontaneous magnetization whose magnetization direction is reversed according to stored data, and including a third terminal as one terminal and a fourth terminal as the other terminal;
The first terminal is connected to a first bit line;
The second terminal is connected to a second bit line;
The first gate is connected to a first word line;
The third terminal is connected to a second word line or ground;
The fourth terminal is connected to the second terminal;
A memory selection unit that turns the first transistor on or off;
The memory selection unit selects the first word line and turns on the first transistor of the selected cell during a data write operation to a selected cell selected from the plurality of memory cells, thereby A write current flows in a direction based on data in a path including the first transistor in the vicinity of the selected cell between the first bit line and the second bit line, so that a magnetic field generated around the path A magnetic random access memory for the magnetoresistive element. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A plurality of word line pairs of a first word line and a second word line extending in a second direction substantially perpendicular to the first direction;
A first selector that selects a selected first bit line during a write operation from the plurality of first bit lines;
A second selector for selecting a selected second bit line during the write operation from the plurality of second bit lines;
A third selector that selects a selected second bit line during a read operation from the plurality of second bit lines;
A fourth selector for selecting a selected first word line during the write operation from the plurality of first word lines;
A fifth selector for selecting a selected second word line from the plurality of second word lines;
A plurality of memory cells provided corresponding to each of the positions where the plurality of bit line pairs and the plurality of word line pairs intersect, and
Each of the plurality of memory cells includes
A first gate connected to the first word line; a first terminal as one terminal other than the first gate connected to the first bit line; and the other connected to the second bit line. A first transistor including a second terminal as a terminal;
It has spontaneous magnetization whose magnetization direction is reversed according to stored data, and a third terminal as one terminal is connected to the second word line, and a fourth terminal as the other terminal is connected to the second terminal And a magnetic random access memory. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A plurality of word line pairs of a first word line and a second word line extending in a second direction substantially perpendicular to the first direction;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting at least one of the selected first word line and the selected second word line from the plurality of word line pairs;
A plurality of memory cells provided corresponding to each of the positions at which the plurality of bit line pairs and the plurality of word line pairs intersect,
Each of the plurality of memory cells includes
As a gate connected to the first word line, a first terminal as one terminal other than the first gate connected to the first bit line, and as the other terminal connected to the second bit line A transistor including a second terminal of
Magnetoresistance having spontaneous magnetization whose magnetization direction is reversed in accordance with stored data and including a fourth terminal as one terminal connected to the second bit line and a third terminal as the other terminal Elements,
A magnetic random access memory comprising: a diode including a fifth terminal having a first polarity connected to the third terminal and a sixth terminal having a second polarity different from the first polarity connected to the second word line. . A plurality of memory cell arrays;
An array selector for selecting a selected cell array from the plurality of memory cell arrays;
Each of the plurality of memory cell arrays includes
A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A plurality of word line pairs of first and second word lines extending in a second direction substantially perpendicular to the first direction;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting at least one of the selected first word line and the selected second word line from the plurality of word line pairs;
A plurality of memory cells provided corresponding to respective positions where the plurality of bit line pairs and the plurality of word line pairs intersect;
Each of the plurality of memory cells includes
As a gate connected to the first word line, a first terminal as one terminal other than the first gate connected to the first bit line, and as the other terminal connected to the second bit line A transistor including a second terminal of
Magnetoresistance having spontaneous magnetization whose magnetization direction is reversed in accordance with stored data and including a fourth terminal as one terminal connected to the second bit line and a third terminal as the other terminal Elements,
A diode including a fifth terminal having a first polarity connected to the third terminal and a sixth terminal having a second polarity different from the first polarity connected to the second word line;
The first selector and the second selector are connected to the array selector. Magnetic random access memory. The magnetic random access memory according to claim 26 or 27,
Writing data to each of the plurality of memory cells includes:
The selected first word line is selected and the transistor is turned on;
A current flows in a direction based on data through a path including the transistor between the selected first bit line and the selected second bit line, and a magnetic field generated around the path causes the magnetoresistive element to flow. Magnetic random access memory. The magnetic random access memory according to any one of claims 26 to 28,
Reading said data from each of said plurality of memory cells,
A magnetic random access memory that performs measurement by measuring a resistance of the magnetoresistive element based on a current flowing through a path including the selected second bit line, the magnetoresistive element, and the selected second word line. A first diffusion layer provided in a semiconductor substrate, a second diffusion layer, and a first gate provided on the semiconductor substrate between the first diffusion layer and the second diffusion layer via an insulating layer A first transistor including:
A first bit line connected to the first diffusion layer via a first contact wiring extending from the first diffusion layer in a direction away from the semiconductor substrate;
A third diffusion layer provided in the semiconductor substrate, a fourth diffusion layer, and a second diffusion layer provided on the semiconductor substrate between the third diffusion layer and the fourth diffusion layer via an insulating layer; A second transistor including a gate;
A second bit line connected to the third diffusion layer via a third contact wiring extending from the third diffusion layer in a direction away from the semiconductor substrate;
A word line connected to the first gate and the second gate;
A fourth contact is connected to the second diffusion layer at one end via a second contact wiring extending from the second diffusion layer in a direction away from the semiconductor substrate, and extends from the fourth diffusion layer in a direction away from the semiconductor substrate. A lead wiring layer connected to the fourth diffusion layer at the other end via the wiring;
A magnetic random access memory comprising: a magnetoresistive element provided on the lead-out wiring layer and having one terminal connected to the lead-out wiring layer and the other terminal connected to the ground via a fifth contact wiring. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A plurality of word lines extending in a second direction substantially perpendicular to the first direction;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected word line from the plurality of word lines;
A plurality of memory cells provided corresponding to each of the positions at which the plurality of bit line pairs and the plurality of word lines intersect;
Each of the plurality of memory cells includes
A first gate connected to the word line; a first terminal as one terminal other than the first gate connected to the first bit line; and a second terminal as the other terminal. A transistor,
A second gate connected to the word line; a fifth terminal as one terminal other than the second gate connected to the second bit line; and a second terminal connected to the second terminal. A second transistor including a sixth terminal;
Magnetoresistive having spontaneous magnetization whose magnetization direction is reversed according to stored data, a third terminal as one terminal connected to the ground, and a fourth terminal as the other terminal connected to the second terminal Magnetic random access memory comprising the element. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction, and a plurality of third bit lines;
A plurality of word lines extending in a second direction substantially perpendicular to the first direction;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected third bit line from the plurality of third bit lines;
A fourth selector for selecting a selected word line from the plurality of word lines;
A plurality of memory cells provided corresponding to each of the positions at which the plurality of bit line pairs and the plurality of word lines intersect;
Each of the plurality of memory cells includes
A first gate connected to the word line; a first terminal as one terminal other than the first gate connected to the first bit line; and a second terminal as the other terminal. A transistor,
A second gate connected to the word line; a fifth terminal as one terminal other than the second gate connected to the second bit line; and a second terminal connected to the second terminal. A second transistor including a sixth terminal;
It has spontaneous magnetization whose magnetization direction is reversed according to stored data, and a third terminal as one terminal is connected to the third bit line, and a fourth terminal as the other terminal is connected to the second terminal. And a magnetic random access memory. A plurality of memory cell arrays;
An array selector for selecting a selected cell array from the plurality of memory cell arrays;
Each of the plurality of memory cell arrays includes
A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A plurality of word lines extending in a second direction substantially perpendicular to the first direction;
A plurality of memory cells provided corresponding to each of the positions where the plurality of bit line pairs and the plurality of word lines intersect;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected word line from the plurality of word lines;
Each of the plurality of memory cells includes
A first gate connected to the word line; a first terminal as one terminal other than the first gate connected to the first bit line; and a second terminal as the other terminal. A transistor,
A second gate connected to the word line; a fifth terminal as one terminal other than the second gate connected to the second bit line; and a second terminal connected to the second terminal. A second transistor including a sixth terminal;
Magnetoresistive having spontaneous magnetization whose magnetization direction is reversed in accordance with stored data, a third terminal as one terminal connected to the ground, and a fourth terminal as the other terminal connected to the second terminal Including elements and
At least one of the first selector and the second selector is connected to the array selector Magnetic random access memory. A plurality of memory cell arrays;
An array selector for selecting a selected cell array from the plurality of memory cell arrays;
Each of the plurality of memory cell arrays includes
A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction, and a plurality of third bit lines;
A plurality of word lines extending in a second direction substantially perpendicular to the first direction;
A plurality of memory cells provided corresponding to each of the positions where the plurality of bit line pairs and the plurality of word lines intersect;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected second bit line from the plurality of third bit lines;
A fourth selector for selecting a selected word line from the plurality of word lines;
Each of the plurality of memory cells includes
A first gate connected to the word line; a first terminal as one terminal other than the first gate connected to the first bit line; and a second terminal as the other terminal. A transistor,
A second gate connected to the word line; a fifth terminal as one terminal other than the second gate connected to the second bit line; and a second terminal connected to the second terminal. A second transistor including a sixth terminal;
It has spontaneous magnetization whose magnetization direction is reversed according to stored data, and a third terminal as one terminal is connected to the third bit line and a fourth terminal as the other terminal is connected to the second terminal. A magnetoresistive element, and
At least one of the first selector, the second selector, and the third selector is connected to the array selector. Magnetic random access memory. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A plurality of word lines extending in a second direction substantially perpendicular to the first direction;
A precharge word line extending in the second direction;
A precharge line extending in the second direction and supplying a precharge voltage;
A plurality of precharge voltage lines extending in the second direction and provided corresponding to the plurality of word lines and supplying the precharge voltage;
The first bit line and the second bit line are connected to the precharge word line, the precharge line, the first bit line, and the second bit line, and based on a signal from the precharge word line. And a precharge unit for precharging to the precharge voltage,
A plurality of memory cells provided corresponding to each of the positions where the plurality of bit line pairs and the plurality of word lines intersect;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected word line from the plurality of word lines;
Each of the plurality of memory cells includes
A first gate connected to the word line; a first terminal as one terminal other than the first gate connected to the first bit line; and a second terminal as the other terminal. A transistor,
A second gate connected to the word line; a fifth terminal as one terminal other than the second gate connected to the second bit line; and a second terminal connected to the second terminal. A second transistor including a sixth terminal;
It has spontaneous magnetization whose magnetization direction is reversed according to stored data, and the third terminal as one terminal is connected to the precharge voltage line, and the fourth terminal as the other terminal is connected to the second terminal Magnetoresistive element and
The precharge voltage is set to be the same as a voltage generated at a node where the first transistor, the second transistor, and the magnetoresistive element are connected when a current flows through the memory cell during the write operation. Magnetic random access memory. 36. The magnetic random access memory according to claim 35.
The magnetic random access memory, wherein the first bit line and the second bit line are precharged to the precharge voltage when not selected. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A plurality of word lines extending in a second direction substantially perpendicular to the first direction;
A plurality of memory cells provided corresponding to each of the positions where the plurality of bit line pairs and the plurality of word lines intersect;
A first read selector that selects a selected first bit line from the plurality of first bit lines during a read operation;
A first write selector that selects a selected first bit line from the plurality of first bit lines during a write operation;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected word line from the plurality of word lines;
Each of the plurality of memory cells includes
A first gate connected to the word line; a first terminal as one terminal other than the first gate connected to the first bit line; and a second terminal as the other terminal. A transistor,
A second gate connected to the word line; a fifth terminal as one terminal other than the second gate connected to the second bit line; and a second terminal connected to the second terminal. A second transistor including a sixth terminal;
Magnetoresistive having spontaneous magnetization whose magnetization direction is reversed in accordance with stored data, a third terminal as one terminal connected to the ground, and a fourth terminal as the other terminal connected to the second terminal Magnetic random access memory including an element and. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A plurality of word lines extending in a second direction substantially perpendicular to the first direction;
A plurality of memory cells provided corresponding to each of the positions where the plurality of bit line pairs and the plurality of word lines intersect;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected first word line from the plurality of first word lines;
A plurality of extended first bit lines connected to each of the plurality of first bit lines extending from the first selector; and the plurality of first bits extending from the second selector corresponding to each of the plurality of first bit lines. A plurality of sense amplifiers connected to a plurality of extended second bit lines connected to each of the two bit lines and amplifying a potential difference between the extended first bit line and the extended second bit line;
Each of the plurality of memory cells includes
A first gate connected to the word line; a first terminal as one terminal other than the first gate connected to the first bit line; and a second terminal as the other terminal. A transistor,
A second gate connected to the word line; a fifth terminal as one terminal other than the second gate connected to the second bit line; and a second terminal connected to the second terminal. A second transistor including a sixth terminal;
Magnetoresistive having spontaneous magnetization whose magnetization direction is reversed in accordance with stored data, a third terminal as one terminal connected to the ground, and a fourth terminal as the other terminal connected to the second terminal Magnetic random access memory including an element and. The magnetic random access memory according to any one of claims 31 to 38,
Writing data to each of the plurality of memory cells includes:
When the selected word line is selected, the first transistor and the second transistor are turned on,
A magnetic field generated around the path when a current flows in a direction based on data through a path including the first transistor and the second transistor between the selected first bit line and the selected second bit line. Magnetic random access memory that is performed on the magnetoresistive element by The magnetic random access memory according to any one of claims 31 to 39,
Reading said data from each of said plurality of memory cells,
A magnetic random access memory that performs measurement by measuring a resistance of the magnetoresistive element based on a current flowing through a path including the selected second bit line, the second transistor, and the magnetoresistive element. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A plurality of word lines extending in a second direction substantially perpendicular to the first direction;
A plurality of memory cells provided corresponding to each of the positions where the plurality of bit line pairs and the plurality of word lines intersect;
Select one of the selected first bit lines from the plurality of first bit lines or the selected second bit line from the plurality of second bit lines during a write operation, and select the selected first bit line and the selection during a read operation A first selector for selecting a second bit line;
A second selector for selecting a selected second bit line or a selected first bit line that forms a pair with the selected first bit line or the selected second bit line selected by the first selector during a write operation;
A third selector for selecting a selected word line from the plurality of word lines;
Each of the plurality of memory cells includes
A first gate connected to the word line; a first terminal as one terminal other than the first gate connected to the first bit line; and a second terminal as the other terminal. A transistor,
A second gate connected to the word line; a fifth terminal as one terminal other than the second gate connected to the second bit line; and a second terminal connected to the second terminal. A second transistor including a sixth terminal;
Magnetoresistive having spontaneous magnetization whose magnetization direction is reversed in accordance with stored data, a third terminal as one terminal connected to the ground, and a fourth terminal as the other terminal connected to the second terminal Magnetic random access memory including an element and. The magnetic random access memory according to claim 41.
Writing data to each of the plurality of memory cells includes:
When the selected word line is selected, the first transistor and the second transistor are turned on,
A magnetic field generated around the path when a current flows in a direction based on data through a path including the first transistor and the second transistor between the selected first bit line and the selected second bit line. Magnetic random access memory that is performed on the magnetoresistive element by The magnetic random access memory according to claim 41 or 42,
Reading said data from each of said plurality of memory cells,
Based on a current flowing through a path including the first bit line, the first transistor, the magnetoresistive element, the selected second bit line, the second transistor, and the magnetoresistive element, the resistance of the magnetoresistive element is determined. Magnetic random access memory to be measured. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A plurality of word line pairs of a first word line and a second word line extending in a second direction substantially perpendicular to the first direction;
A plurality of memory cells provided corresponding to each of the positions where the plurality of bit line pairs and the plurality of word line pairs intersect;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines during a write operation;
A third selector that selects a selected first word line from the plurality of first word lines and a selected second word line from the plurality of second word lines during a write operation, and selects the selected first word line during a read operation; Comprising
Each of the plurality of memory cells includes
A first transistor having a gate electrode connected to the first word line, the remaining one terminal connected to the first bit line, and the other terminal connected to the magnetoresistive element;
A second transistor having a gate electrode connected to the second word line, a remaining one terminal connected to the other terminal of the first transistor, and the other terminal connected to the second bit line;
A magnetoresistive element having spontaneous magnetization whose magnetization direction is reversed according to stored data, one terminal connected to the ground, and the other terminal connected to the other terminal of the first transistor;
The magnetic random access memory, wherein the second bit line paired with the first bit line is shared by the two first bit lines adjacent to the second bit line. 45. The magnetic random access memory of claim 44.
Writing data to each of the plurality of memory cells includes:
The selected first word line and the selected second word line are selected, and the first transistor and the second transistor are turned on,
A magnetic field generated around the path when a current flows in a direction based on data through a path including the first transistor and the second transistor between the selected first bit line and the selected second bit line. Magnetic random access memory that is performed on the magnetoresistive element by The magnetic random access memory according to claim 44 or 45,
Reading said data from each of said plurality of memory cells,
A magnetic random access memory configured to measure a resistance of the magnetoresistive element based on a current flowing through a path including the first bit line, the first transistor, and the magnetoresistive element. The magnetic random access memory according to claim 31,
Each of the plurality of word lines is a plurality of word line pairs of a first word line and a second word line;
The third selector selects a selected word line pair from the plurality of word line pairs;
Each of the plurality of memory cells includes
A third gate connected to the second word line, a seventh terminal as one terminal other than the third gate connected to the first bit line, and the other terminal connected to the second terminal A third transistor including an eighth terminal as
A fourth gate connected to the second word line; a ninth terminal as one terminal other than the fourth gate connected to the second bit line; and the other terminal connected to the sixth terminal A fourth transistor including a tenth terminal as
The magnetic random access memory, wherein the first gate and the second gate are connected to the first word line. The magnetic random access memory according to claim 32.
Each of the plurality of word lines is a plurality of word line pairs of a first word line and a second word line;
The fourth selector selects a selected word line pair from the plurality of word line pairs;
Each of the plurality of memory cells includes
A third gate connected to the second word line, a seventh terminal as one terminal other than the third gate connected to the first bit line, and the other terminal connected to the second terminal A third transistor including an eighth terminal as
A fourth gate connected to the second word line; a ninth terminal as one terminal other than the fourth gate connected to the second bit line; and the other terminal connected to the sixth terminal A fourth transistor including a tenth terminal as
The magnetic random access memory, wherein the first gate and the second gate are connected to the first word line. The magnetic random access memory according to claim 47 or 48,
Two memory cells adjacent to each other in the direction of the plurality of bit line pairs have diffusion layers of the first terminal and the fifth terminal of one of the memory cells, respectively, and the seventh terminal of the other memory cell. And a magnetic random access memory in common with the diffusion layer of the ninth terminal. The magnetic random access memory according to any one of claims 47 to 49,
Writing data to each of the plurality of memory cells includes:
The selected word line pair is selected, and the first transistor, the second transistor, the third transistor, and the fourth transistor are turned on,
A current flows in a direction based on data through a path including the first transistor, the second transistor, the third transistor, and the fourth transistor between the selected first bit line and the selected second bit line. A magnetic random access memory that performs the magnetic resistance element with a magnetic field generated around the path. The magnetic random access memory according to any one of claims 47 to 50,
Reading said data from each of said plurality of memory cells,
A magnetic random access memory configured to measure a resistance of the magnetoresistive element based on a current flowing through a path including the selected second bit line, the second transistor, the fourth transistor, and the magnetoresistive element. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A word line extending in a second direction substantially perpendicular to the first direction;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected word line from the plurality of word lines;
A plurality of memory cells provided corresponding to each of the positions at which the plurality of bit line pairs and the plurality of word lines intersect;
Each of the plurality of memory cells includes
A transistor including a gate connected to the word line, a first terminal as one terminal other than the gate connected to the first bit line, and a second terminal as the other terminal;
A fourth terminal as one terminal connected to the second terminal, and a second terminal connected to a voltage source for supplying a predetermined voltage, having spontaneous magnetization whose magnetization direction is reversed in accordance with stored data A magnetoresistive element including a third terminal as a terminal of
A second diode including a fifth terminal having a first polarity connected to the second terminal and a sixth terminal having a second polarity different from the first polarity connected to the second bit line; A magnetic random access memory comprising: a third diode including a seventh terminal having the first polarity connected to a line and an eighth terminal having the second polarity connected to the second terminal. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction, and a plurality of third bit lines;
A word line extending in a second direction substantially perpendicular to the first direction;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected third bit line from the plurality of third bit lines;
A fourth selector for selecting a selected word line from the plurality of word lines;
A plurality of memory cells provided corresponding to each of the positions at which the plurality of bit line pairs and the plurality of word lines intersect;
Each of the plurality of memory cells includes
A transistor including a gate connected to the word line, a first terminal as one terminal other than the gate connected to the first bit line, and a second terminal as the other terminal;
As the fourth terminal as one terminal connected to the second terminal and the other terminal connected to the third bit line, having spontaneous magnetization whose magnetization direction is reversed in accordance with stored data A magnetoresistive element including the third terminal of
A second diode including a fifth terminal having a first polarity connected to the second terminal and a sixth terminal having a second polarity different from the first polarity connected to the second bit line; A magnetic random access memory comprising: a third diode including a seventh terminal having the first polarity connected to a line and an eighth terminal having the second polarity connected to the second terminal. A plurality of memory cell arrays;
An array selector for selecting a selected cell array from the plurality of memory cell arrays;
Each of the plurality of memory cell arrays includes
A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A word line extending in a second direction substantially perpendicular to the first direction;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected word line from the plurality of word lines;
A plurality of memory cells provided corresponding to each of the positions at which the plurality of bit line pairs and the plurality of word lines intersect;
Each of the plurality of memory cells includes
A transistor including a gate connected to the word line, a first terminal as one terminal other than the gate connected to the first bit line, and a second terminal as the other terminal;
The third terminal as one terminal connected to the second terminal and the other connected to the voltage source for supplying a predetermined voltage has spontaneous magnetization whose magnetization direction is reversed according to stored data A magnetoresistive element including a fourth terminal as a terminal of
A second diode including a fifth terminal having a first polarity connected to the second terminal and a sixth terminal having a second polarity different from the first polarity connected to the second bit line; A third diode including a seventh terminal of the first polarity connected to a line and an eighth terminal of the second polarity connected to the second terminal;
The first selector and the second selector are connected to the array selector. Magnetic random access memory. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A word line extending in a second direction substantially perpendicular to the first direction;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected word line from the plurality of word lines;
A plurality of memory cells provided corresponding to each of the positions at which the plurality of bit line pairs and the plurality of word lines intersect;
Each of the plurality of memory cells includes
A transistor including a gate connected to the word line, a first terminal as one terminal other than the gate connected to the first bit line, and a second terminal as the other terminal;
A fourth terminal as one terminal connected to the second terminal, and a second terminal connected to a voltage source for supplying a predetermined voltage, having spontaneous magnetization whose magnetization direction is reversed in accordance with stored data A magnetoresistive element including a third terminal as a terminal of
A second diode including a fifth terminal having a first polarity connected to the second bit line and a sixth terminal having a second polarity different from the first polarity;
A magnetic random access memory comprising: a third diode including a seventh terminal having the first polarity connected to the second terminal and an eighth terminal having the second polarity connected to the sixth terminal. A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction, and a plurality of third bit lines;
A word line extending in a second direction substantially perpendicular to the first direction;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected third bit line from the plurality of third bit lines;
A fourth selector for selecting a selected word line from the plurality of word lines;
A plurality of memory cells provided corresponding to each of the positions at which the plurality of bit line pairs and the plurality of word lines intersect;
Each of the plurality of memory cells includes
A transistor including a gate connected to the word line, a first terminal as one terminal other than the gate connected to the first bit line, and a second terminal as the other terminal;
As the fourth terminal as one terminal connected to the second terminal and the other terminal connected to the third bit line, having spontaneous magnetization whose magnetization direction is reversed in accordance with stored data A magnetoresistive element including the third terminal of
A second diode including a fifth terminal having a first polarity connected to the second bit line and a sixth terminal having a second polarity different from the first polarity;
A magnetic random access memory comprising: a third diode including a seventh terminal having the first polarity connected to the second terminal and an eighth terminal having the second polarity connected to the sixth terminal. A plurality of memory cell arrays;
An array selector for selecting a selected cell array from the plurality of memory cell arrays;
Each of the plurality of memory cell arrays includes
A plurality of bit line pairs of a first bit line and a second bit line extending in a first direction;
A word line extending in a second direction substantially perpendicular to the first direction;
A first selector for selecting a selected first bit line from the plurality of first bit lines;
A second selector for selecting a selected second bit line from the plurality of second bit lines;
A third selector for selecting a selected word line from the plurality of word lines;
A plurality of memory cells provided corresponding to each of the positions at which the plurality of bit line pairs and the plurality of word lines intersect;
Each of the plurality of memory cells includes
A transistor including a gate connected to the word line, a first terminal as one terminal other than the gate connected to the first bit line, and a second terminal as the other terminal;
The third terminal as one terminal connected to the second terminal and the other connected to the voltage source for supplying a predetermined voltage has spontaneous magnetization whose magnetization direction is reversed according to stored data A magnetoresistive element including a fourth terminal as a terminal of
A second diode including a fifth terminal having a first polarity connected to the second bit line and a sixth terminal having a second polarity different from the first polarity;
A third diode including a seventh terminal of the first polarity connected to the second terminal and an eighth terminal of the second polarity connected to the sixth terminal;
The first selector and the second selector are connected to the array selector;
Based on the data, a reverse voltage applied to either the second diode or the third diode during a write operation is greater than or equal to a breakdown voltage. Magnetic random access memory. The magnetic random access memory according to any one of claims 52 to 57,
Writing data to each of the plurality of memory cells includes:
The selected word line is selected and the transistor is turned on;
The selected first bit line and the selected second bit are determined by a voltage difference set based on a threshold voltage of the second diode and the third diode between the selected first bit line and the selected second bit line. A magnetic random access memory, which is performed on the magnetoresistive element by a magnetic field generated around the path when a current flows in a direction based on data through a path including the transistor between the bit line and the bit line. A magnetic random access memory according to any one of claims 52 to 58,
Reading said data from each of said plurality of memory cells,
A magnetic random access memory, which is performed by measuring a resistance of the magnetoresistive element based on a current flowing through a path including the selected second bit line and the magnetoresistive element. A bit line provided on the substrate via an insulating layer and parallel to the surface of the substrate;
A lead-out wiring layer connected to the bit line at one end through a first contact wiring extending from the bit line in a direction away from the substrate and parallel to the surface of the substrate;
A second terminal provided in the middle of a second contact wiring including a first terminal having a first polarity and a second terminal having a second polarity different from the first polarity and extending from the lead-out wiring layer in a direction away from the substrate; A diode,
A third diode provided in the middle of a third contact wiring including a third terminal having the first polarity and a fourth terminal having the second polarity and extending from the lead-out wiring layer in a direction away from the substrate;
A magnetoresistive element having spontaneous magnetization whose magnetization direction is reversed according to stored data, including a fifth terminal and a sixth terminal, wherein the fifth terminal is connected to the lead-out wiring layer;
A first terminal provided in the middle of a fourth contact wiring including a seventh terminal having the first polarity and an eighth terminal having the second polarity and extending from the sixth terminal of the magnetoresistive element in a direction away from the substrate; A diode,
Connected to the second terminal of the second diode via the second contact wiring, and connected to the third terminal of the third diode via the third contact wiring, and parallel to the substrate A first word line;
A second word line connected to the seventh terminal of the first diode via the fourth contact wiring and parallel to the substrate;
The position of the fifth terminal in the lead-out wiring layer is such that the first contact wiring, the lead-out wiring layer, and the second contact wiring and the third contact wiring are connected to the lead-out wiring layer. Magnetic random access memory close to where it connects. A plurality of bit lines extending in a first direction;
A plurality of word line pairs of a first word line and a second word line extending in a second direction substantially perpendicular to the first direction;
A first selector that selects a selected bit line during a write operation and a read operation from the plurality of bit lines;
A second selector that selects a selected first word line from the plurality of first word lines during the write operation, and selects a selected second word line from the plurality of second word lines during a read operation;
A plurality of memory cells provided corresponding to respective positions where the plurality of bit lines and the plurality of word line pairs intersect;
Each of the plurality of memory cells includes
A second diode including a first terminal having a first polarity and a second terminal having a second polarity different from the first polarity;
A third diode including a third terminal of the first polarity and a fourth terminal of the second polarity;
A magnetoresistive element having spontaneous magnetization whose magnetization direction is reversed according to stored data, and including a fifth terminal as one terminal and a sixth terminal as the other terminal;
The second terminal and the third terminal are connected to the first word line,
The first terminal, the fourth terminal, and the fifth terminal are connected to the bit line,
The sixth terminal is connected to the second word line. Magnetic random access memory. A plurality of memory cell arrays;
An array selector for selecting a selected cell array from the plurality of memory cell arrays;
Each of the plurality of memory cell arrays includes
A plurality of bit lines extending in a first direction;
A plurality of word line pairs of a first word line and a second word line extending in a second direction substantially perpendicular to the first direction;
A first selector that selects a selected bit line during a write operation and a read operation from the plurality of bit lines;
A second selector that selects a selected first word line from the plurality of first word lines during the write operation, and selects a selected second word line from the plurality of second word lines during a read operation;
A plurality of memory cells provided corresponding to each of the positions where the plurality of bit lines and the plurality of word line pairs intersect, and
Each of the plurality of memory cells includes
A second diode including a first terminal having a first polarity and a second terminal having a second polarity different from the first polarity;
A third diode including a third terminal of the first polarity and a fourth terminal of the second polarity;
A magnetoresistive element having spontaneous magnetization whose magnetization direction is reversed according to stored data, and including a fifth terminal as one terminal and a sixth terminal as the other terminal;
The second terminal and the third terminal are connected to the first word line,
The first terminal, the fourth terminal, and the fifth terminal are connected to the bit line,
The sixth terminal is connected to the second word line. The first selector is connected to the array selector. Magnetic random access memory. The magnetic random access memory according to claim 61 or 62,
The memory cell is
A first diode including a seventh terminal having the first polarity and an eighth terminal having the second polarity;
The first diode is provided between the magnetoresistive element and the second word line, and the eighth terminal is connected to the second word line and the seventh terminal is connected to the sixth terminal. Access memory. The magnetic random access memory according to claim 63,
The magnetic random access memory, wherein the first diode, the second diode, and the third diode are formed at a position away from a substrate. 65. The magnetic random access memory of claim 64.
The memory cell is stacked in a direction away from the substrate. Magnetic random access memory. The magnetic random access memory according to any one of claims 61 to 65,
Writing data to each of the plurality of memory cells includes:
A voltage difference set based on a threshold voltage of the second diode and the third diode between the selected first word line and the selected bit line causes a difference between the selected first word line and the selected bit line. Magnetic randomness is performed on the magnetoresistive element by a magnetic field generated around the path when a current flows in a direction based on data through a path including one of the second diode and the third diode between Access memory. The magnetic random access memory according to any one of claims 61 to 66,
Reading said data from each of said plurality of memory cells,
A magnetic random access memory that performs measurement by measuring a resistance of the magnetoresistive element based on a current flowing through a path including the selected bit line, the magnetoresistive element, and the selected second word line. A plurality of bit lines extending in a first direction;
A plurality of word lines extending in a second direction substantially perpendicular to the first direction;
A first selector for selecting a selected first bit line from the plurality of bit lines;
A second selector for selecting a selected word line from the plurality of word lines;
A plurality of memory cells provided corresponding to respective positions where the plurality of bit lines and the plurality of word lines intersect with each other;
Each of the plurality of memory cells includes
A transistor including a gate connected to the word line, a first terminal as one terminal other than the gate connected to the bit line, and a second terminal as the other terminal;
A capacitor including a fifth terminal as one terminal connected to ground and a sixth terminal as the other terminal connected to the second terminal;
Magnetoresistive having spontaneous magnetization whose magnetization direction is reversed according to stored data, a third terminal as one terminal connected to the ground, and a fourth terminal as the other terminal connected to the second terminal A magnetic random access memory comprising: The magnetic random access memory of claim 68.
Writing data to the memory cell
The first selector selects a selected bit line from the plurality of bit lines, charges the capacitor with the selected bit line set to a predetermined voltage,
The second selector selects the selected word line from the plurality of word lines and turns on the first transistor;
For a selected cell selected from the plurality of memory cells by the selected bit line and the selected word line, after the capacitor is charged, the selected bit line is set to a predetermined voltage based on the data, and A magnetic random access memory that is performed on the magnetoresistive element by a magnetic field generated based on a current flowing between a capacitor and the selected bit line. The magnetic random access memory according to claim 68 or 69,
Reading data into the memory cell is as follows:
The first selector selects a selected bit line from the plurality of bit lines, charges the capacitor with the selected bit line set to a predetermined voltage,
The second selector selects the selected word line from the plurality of word lines and turns on the first transistor at a predetermined speed or less;
A predetermined current is applied to a selected cell selected from the plurality of memory cells by the selected bit line and the selected word line after the capacitor is charged, and the magnetic field of the selected first bit line and the selected cell is increased. A magnetic random access memory which is performed by measuring a resistance of the magnetoresistive element when flowing through a path including the resistive element. The magnetic random access memory according to any one of claims 24 to 59 and 68 to 70,
The threshold voltage of the transistor on the path through which the write current for writing the data to the magnetoresistive element flows is designed on the assumption that a voltage of 1/2 or less of the power supply voltage is applied between the source and drain of the transistor Magnetic random access memory. The magnetic random access memory of claim 71.
The gate length of the transistor is designed to be smaller than that of a standard transistor, where the standard transistor has a premise that a voltage larger than ½ of the power supply voltage is applied between a source and a drain. Designed with magnetic random access memory. The magnetic random access memory according to any one of claims 24 to 72,
Further comprising a magnetic structure provided on the opposite side of the magnetoresistive element across a layer through which a write current for writing the data to the magnetoresistive element flows.
The magnetic random access memory, wherein the magnetic structure superimposes a magnetic field generated by the magnetization of the write current on a magnetic field generated near the magnetoresistive element by the write current. The magnetic random access memory according to any one of claims 24 to 73,
The shape of the magnetoresistive element is asymmetric with respect to the easy axis of the magnetoresistive element. Magnetic random access memory.

Images