JP3883687B2 - Semiconductor device, memory card and data processing system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a nonvolatile memory element capable of storing at least four-value information (information of two bits) in one memory cell, for example, an electrically rewritable nonvolatile semiconductor memory such as a flash memory. More particularly, the present invention relates to a technology that is effective when applied to a data processing system such as a file memory system using the nonvolatile semiconductor memory device.
[0002]
[Prior art]
2. Description of the Related Art Non-volatile semiconductor memory devices such as flash memories that can store information by injecting electrons into or extracting electrons from floating gates have been provided. The flash memory has a memory cell transistor having a floating gate (floating gate), a control gate, a source and a drain. In this memory cell transistor, the threshold voltage increases when electrons are injected into the floating gate, and the threshold voltage decreases when electrons are extracted from the floating gate. The memory cell transistor stores information corresponding to the level of the threshold voltage with respect to the word line voltage (control gate applied voltage) for reading data. Although not particularly limited, in this specification, a state in which the threshold voltage of the memory cell transistor is low is referred to as an erased state, and a state in which the threshold voltage is high is referred to as a written state.
[0003]
As such a flash memory, there is one that stores information of four or more values in one memory cell transistor. Nikkei Microdevices (November 1994) pages 48 and 49 are examples of documents describing such multilevel memories. Furthermore, there is JP-A-9-297996.
[0004]
[Problems to be solved by the invention]
In a multi-level memory, for example, if one state can be selected from an erase state and first to third write states each having a different threshold voltage with respect to the erase state, one memory is selected. Four-value information can be stored in the cell transistor. If the erase operation is performed before the write operation, quaternary information can be obtained by determining whether all of the first to third write states are unselected or which write state is selected. Can memorize. In the write operation for that purpose, write control information for determining whether or not to select the write operation for individually obtaining the first to third write states is required. In order to hold such write control information, a sense latch circuit and a data latch circuit provided in each bit line can be used.
[0005]
The sense launch circuit comprises, for example, a static latch. One end of each bit line is connected to a pair of input / output terminals of the sense latch, and the drain of the memory cell transistor is connected to each bit line. Further, a data latch circuit is connected to the other end of each bit line. The sense latch circuit senses a state in which a current flows or does not flow between a source and a drain when a read voltage or a verify voltage is applied to the control gate of the memory cell transistor. At this time, one operation unselected bit line of the sense latch circuit is precharged to the reference level. In addition, when writing with a high potential difference between the control gate and the drain, the memory cell is distinguished from write selection and write non-selection by increasing or decreasing the drain voltage for each memory cell. In this case, the sense latch circuit latches data corresponding to write selection / non-selection. This latch data is the write control information.
[0006]
Such write control information is generated via a data conversion circuit for every two bits of write data supplied from the outside, and a bit line pair sharing the sense latch circuit with the sense latch circuit of the bit line selected for writing. Are latched by each data latch circuit. When a write operation is performed in units of word lines, write control information is latched in advance in the sense latch circuit and the data latch circuit for all bit lines sharing the word line.
[0007]
In the write operation, first, the presence / absence of the first write state is determined according to the write control information latched in the sense latch circuit, and then, according to the write control information internally transferred from one data latch circuit to the sense latch circuit. The presence / absence of the second write state is determined, and the presence / absence of the third write state is determined in accordance with the write control information internally transferred from the other data latch circuit to the sense latch circuit. In this way, quaternary information specified by 2-bit data can be stored in one memory cell. In the write operation to the first to third write states, a verify operation is performed to check whether the threshold voltage assigned to each write state has been reached.
[0008]
At this time, some of the memory cells are overwritten with respect to the first to third write states, and in this case, the threshold voltages in the previous and next write states can be distinguished. For example, the threshold voltage of the memory cell that should be in the first write state may be so high that it cannot be distinguished from the threshold voltage in the second write state. In such a case, in order to restart the write operation from the beginning, the erase operation is performed on the memory cell to be written, and then the write operation is performed again.
[0009]
However, once the write operation to the first to third write states is performed, the write control information first latched in the sense latch circuit is overwritten by another write control information internally transferred from the data latch circuit and lost. It has been done. For this reason, in order to perform a rewrite operation caused by overwriting, the same write data must be received from the outside again. For this purpose, the control circuit for controlling the access to the flash memory must keep the write data in the work memory for a while after the write operation to the flash memory. It has been clarified by the present inventor that the load increases and causes a reduction in flash memory access or data processing efficiency.
[0010]
Further, when the write operation itself is finally defective, such as a rewrite operation failure caused by overwriting, the write data at that time is stored in another storage area of the flash memory or in another flash memory. It is assumed that At this time, similarly to the above, the flash memory related to the write failure no longer holds the write data at that time. Therefore, even in this case, the control circuit for controlling access to the flash memory must keep the write data in the work memory for a while after the write operation to the flash memory. Or, the data processing efficiency is reduced.
[0011]
An object of the present invention is to provide a semiconductor device in which write data supplied from the outside to a data latch circuit for writing multi-value information in each memory cell is not lost by a write operation.
[0012]
Another object of the present invention is to provide a semiconductor device that does not need to receive write data from the outside again when a multi-value information write operation to a memory cell is performed again.
[0013]
Still another object of the present invention is to provide a semiconductor device capable of rewriting write data relating to the abnormal end held internally by designating another memory address when the write operation ends abnormally. .
[0014]
Another object of the present invention is to provide a semiconductor device capable of outputting write data relating to the abnormal end to the outside when the write operation ends abnormally.
[0015]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0016]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0017]
[1] The present invention according to the first aspect is a process performed in association with a write operation in a semiconductor device capable of storing multi-value information in one electrically erasable and programmable non-volatile memory cell. When an over-write state of a memory cell is detected by a write detection operation (word disturb detection or erotic detection), the write data required for the write operation is stored internally even when re-erasing and starting the write operation again from the beginning. It is possible to guarantee that it is stored in.
[0018]
That is, a semiconductor device includes a sense latch circuit having a pair of input / output terminals, bit lines provided separately corresponding to the respective input / output terminals of the sense latch circuit, and an electrical connection selectively connected to the bit lines. A plurality of nonvolatile memory cells erasable and writable, a data latch circuit coupled to each bit line, input / output means for allowing the data latch circuit to interface with the outside, and data reading from the memory cell And control means for controlling erasing and writing. The control means holds write data from the outside in the data latch circuit, and thresholds a nonvolatile memory cell selected to be connected to the bit line based on the plurality of bits of write data held in the data latch circuit. Write control information for determining which state has a different voltage is generated for each write operation and is latched by the sense latch circuit.
[0019]
According to the above means, the write data given from the outside is latched in the data latch circuit, and the threshold value of the multi-value corresponding to the latched write data is determined for each of the multi-stage write operations, and the determination result is obtained. Write control information is latched in the sense latch circuit, and a write operation for setting a multi-level threshold voltage in the memory cell is performed stepwise in accordance with the write control information latched in the sense latch circuit. Therefore, even after the write operation is completed, the write data originally supplied from the outside remains in the data latch circuit. Therefore, it is not necessary to receive the write data from the outside again even when the multi-value information write operation to the memory cell is performed again according to the result of the word disturb detection or the elastic detection.
[0020]
The following method can be employed for overwriting detection. That is, the control means further determines whether or not the threshold voltage to be set in the memory cell is a threshold voltage corresponding to the threshold voltage to be overwritten detection for each verify read operation for overwriting detection. When the latch data of the data latch circuit is calculated and determined, the determination result is latched by the sense latch circuit, and the determination result data latched by the sense latch circuit is the corresponding threshold voltage Bit line precharge is performed, and overwriting is detected based on whether or not the bit line precharge state is changed by the verify read operation.
[0021]
When the overwriting is detected, the control means can re-execute writing after re-erasing.
[0022]
[2] In the invention according to the second aspect focusing on the more specific means of the arithmetic control according to the first aspect for causing the sense latch circuit to latch write information, the erase states having different threshold voltages, A semiconductor device is assumed in which four-value information can be stored in one memory cell by controlling to a writing state, a second writing state, or a third writing state. At this time, the control means holds the external write data in the data latch circuit, and the 2-bit write data held in the two data latch circuits connected to the pair of bit lines sharing the sense latch circuit A program that determines whether the nonvolatile memory cell selected to be connected to the bit line is in the erased state, the first written state, the second written state, or the third written state in units of Information is calculated and latched by the sense latch circuit for each write operation, and the first to third write states are controlled in accordance with the latched write information.
[0023]
More specifically, the control means sets the first logical value when the sense latch circuit latches the write control information having the output data on the memory cell connection selection bit line side as the first logical value. A memory cell connected to the bit line to be written is operated for writing. The calculation of the write control information by the control means includes the first write data bit latched in the data latch circuit on one memory cell connection selection bit line side sharing the sense latch circuit and the other memory cell connection non-selection bit. A logical sum of the logically inverted data of the first write data bit and the second write data bit with respect to the second write data bit latched in the data latch circuit on the line side, the first write data A bit line pre-determined based on the latch data of the data latch circuit, the logical sum of the bit and the second write data bit, and the logical sum of the first write data bit and the logical inverted data of the second write data bit. This is an operation based on the charge operation and the sense operation by the sense latch circuit. The control means causes the sense latch circuit to latch the logical sum sequentially obtained by the calculation for each write operation, and the memory of the memory cell connection selection bit line in which the latched logical sum becomes the first logical value. Write the cell.
[0024]
A more specific example of the means for overwriting determination according to the above can be as follows. The control means further has a threshold voltage to be set in the memory cell for each verify read operation for overwriting detection caused by the writing operation, corresponding to a threshold voltage to be overwritten detection target. Whether the latch data of the data latch circuit is calculated or not, the determination result is latched by the sense latch circuit, and the determination result data latched by the sense latch circuit is the corresponding threshold voltage. In this case, bit line precharge is performed, and overwriting is detected based on whether or not the bit line precharge state is changed by the verify read operation. The operation for the determination by the control means includes the first write data bit latched in the data latch circuit on one memory cell connection selection bit line side sharing the sense latch circuit and the other memory cell connection non-selection bit. A negative OR of the first write data bit and the second write data bit, the first write data bit, and the second write data bit latched in the data latch on the line side The logical product of the second write data bit with the logically inverted data and the logical product of the first write data bit and the second write data bit are converted into the bit line precharge operation and sense by the latch data of the data latch circuit. The operation is based on the sense operation by the latch circuit. The control means causes the sense latch circuit to latch the negative logical sum and the logical product obtained sequentially by the calculation as the determination result data for each overwrite detection operation, and the sense latch circuit selects the memory cell connection selection bit. When the determination result data in which the output data on the line side is the second logic value is latched, the memory cell connection selection bit line is precharged via the precharge circuit.
[0025]
[3] Even if a write error occurs from the above means, the write data at that time is stored in the semiconductor device. Focusing on this, when the control circuit accepts the supply of the retry write command after the abnormal end of the write operation, the write data already held by the data latch circuit at the address supplied with the command is received. Can be controlled to write. Since the semiconductor device has such a retry function, the memory controller or the control device that controls the access of the semiconductor device changes the write address or sector address of the semiconductor device in which the write operation has ended abnormally and re-executes. Writing can be performed easily.
[0026]
Further, it can be considered that the rewrite target can be changed to another semiconductor device after the abnormal end of the write operation. In this case, the control circuit outputs the write data held by the data latch circuit to the outside via the input / output means when receiving the supply of the recovery read command after the abnormal end of the write operation. is there. With this recovery function, the memory controller of the memory card constituted by a plurality of semiconductor devices or the control device that controls the access of the memory card does not store the write data by itself. Rewriting can be easily performed on a semiconductor device different from the device.
[0027]
[4] In the rewrite operation, after erasing by an erase command, writing can be performed on the same region by a write command. Such a rewriting process can be realized by a single command, that is, a rewriting command. That is, when the rewrite first command is supplied, the control means captures the rewrite address, captures write data into the data latch circuit, and after the rewrite second command is supplied, stores the rewrite address in the area specified by the rewrite address. Erasing is performed, and then the write operation is controlled based on the data held in the data latch circuit. This makes it possible to rewrite all sector data with a single command.
[0028]
It is also possible to realize data rewriting for a part of the sector with a single command. In other words, when the first rewrite command is supplied, the control means takes in the rewrite address, saves the data at the fetched address in the data latch circuit, and writes after specifying the rewrite address within the range of the rewrite address after the save. After the data is fetched into the data latch circuit and the rewrite second command is supplied, the sector area specified by the rewrite address is erased, and then held in the data latch circuit of the sector area specified by the rewrite address. The write operation is controlled based on the stored data.
[0029]
[5] When the semiconductor device is used as a file memory or the like, a management area can be allocated to the sector of the semiconductor device, and the remaining part can be released as a user area. The management area stores, for example, information on the number of rewrites and good / bad sectors, and the semiconductor device can support a command to automatically exclude the management area from being erased when the sector erases by the user. Furthermore, the usability of the file memory is improved. From this point of view, a partial erase command may be supported. That is, the control means fetches the sector address when the partial erase first command is supplied, and then when the partial erase second command is supplied, the data corresponding to a certain area in the area specified by the sector address. The latch saves the data in the fixed area, sets data indicating the erase state in the data latch circuit corresponding to the other area, and erases the area specified by the sector address. The write control is performed according to the data set in the data latch circuit.
[0030]
[6] A memory card can be realized by mounting the semiconductor device on a card substrate together with a memory controller for controlling access to the semiconductor device and an external interface circuit connected to the memory controller.
[0031]
In addition, a data processing system can be configured including the semiconductor device, a memory controller that controls access to the semiconductor device, and a processor that controls the memory controller.
[0032]
Focusing on the retry write command, a data processing system is configured including a control device that outputs a retry write command and a write address to the semiconductor device when the abnormal end of the write operation by the semiconductor device is detected. be able to.
[0033]
Further, focusing on the recovery read command, when the abnormal end of the write operation by the semiconductor device is detected, the recovery read command is output to the semiconductor device related to the abnormal end, and the semiconductor to which the recovery read command is supplied A data processing system can be configured including a control device that takes in the write data output by the apparatus and controls the writing of the taken-in write data to another semiconductor device.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
<Overall configuration of flash memory>
FIG. 1 shows an overall configuration of a flash memory 1 according to the first embodiment of the present invention, in which 2-bit information can be written into one memory cell and the information can be read out. Has been.
[0035]
Reference numeral 3 denotes a memory array having a memory mat, a data latch circuit, and a sense latch circuit. The memory mat 3 has a large number of nonvolatile memory cell transistors that can be electrically erased and written. For example, as illustrated in FIG. 2, the memory cell transistor includes a source S and a drain D formed in a semiconductor substrate or a memory well SUB, a floating gate FG formed in a channel region via a tunnel oxide film, and a floating The control gate CG is configured to overlap the gate via an interlayer insulating film. The control gate CG is connected to the word line 6, the drain D is connected to the bit line 5, and the source S is connected to a source line not shown.
[0036]
The external input / output terminals I / O0 to I / O7 are also used as address input terminals, data input terminals, data output terminals, and command input terminals. The X address signal input from the external input / output terminals I / O 0 to I / O 7 is supplied to the X address buffer 8 via the multiplexer 7. X address decoder 9 decodes the internal complementary address signal output from X address buffer 8 to drive the word line.
[0037]
A sense latch circuit (not shown) is provided on one end side of the bit line 5 and a data latch circuit (not shown) is provided on the other end. The bit line 5 is selected by the Y gate array circuit 13 based on the selection signal output from the Y address decoder 11. The Y address signal inputted from the external input / output terminals I / O0 to I / O7 is preset in the Y address counter 12, and the address signal sequentially incremented from the preset value is given to the Y address decoder 11.
[0038]
The bit line selected by the Y gate array circuit 13 is conducted to the input terminal of the output buffer 15 during the data output operation, and is conducted to the output terminal of the input buffer 17 via the data control circuit 16 during the data input operation. The connection between the output buffer 15 and the input buffer 17 and the input / output terminals I / O 0 to I / O 7 is controlled by the multiplexer 7. Commands supplied from the input / output terminals I / O 0 to I / O 7 are supplied to the mode control circuit 18 via the multiplexer 7 and the input buffer 17. The data control circuit 16 makes it possible to supply the memory array 3 with logical value data in accordance with the control of the mode control circuit 18 in addition to the data supplied from the input / output terminals I / O0 to I / O7.
[0039]
The control signal buffer circuit 19 is supplied with a chip enable signal CEb, an output enable signal OEb, a write enable signal WEb, a serial clock signal SC, a reset signal RESb, and a command enable signal CDEb as access control signals. The mode control circuit 18 controls the signal interface function with the outside according to the state of these signals, and controls the internal operation according to the command code. When a command or data is input to the input / output terminals I / O0 to I / O7, the signal CDEb is asserted. If the command is a command, the signal WEb is further asserted, and if it is data, WEb is negated. If it is an address input, the signal CDEb is negated and the signal WEb is asserted. As a result, the mode control circuit 18 can distinguish commands, data, and addresses that are multiplexed from the external input / output terminals I / O0 to I / O7. The mode control circuit 18 can assert the ready / busy signal R / Bb during the erase or write operation to inform the outside of the state.
[0040]
The internal power supply circuit 20 generates various operating power supplies 21 for writing, erasing verification, reading, and the like, and supplies them to the X address decoder 9 and the memory cell array 3.
[0041]
The mode control circuit 18 controls the flash memory 1 as a whole in accordance with commands. The operation of the flash memory 1 is basically determined by commands.
[0042]
As shown in FIG. 3, for example, commands assigned to the flash memory are read, recovery read, erase, write, additional write, retry write, partial erase, and rewrite commands. In the figure, the command code is expressed in hexadecimal notation. Of commands related to read operations (read, recovery read) and commands related to write operations, commands that do not require supply of write data (retry write) are composed of the first command, and other commands are composed of the first and second commands. Is done. The contents of each command will be described in detail later.
[0043]
The flash memory 1 has a status register 180 for indicating its internal state, and its contents can be read from the input / output terminals I / O0 to I / O7 by asserting the signal OEb. FIG. 4 illustrates the correspondence between the contents of each bit of the status register 180 and the input / output terminals I / O0 to I / O7.
[0044]
FIG. 5 shows the relationship between the data latch circuit and the sense latch circuit included in the memory array 3. An array SLA of sense latch circuits SL is arranged in the center, and on one input / output node side of the sense latch circuit SL, a switch circuit / arithmetic circuit array 30L, a memory mat MML, a switch circuit / arithmetic circuit array 31L, and an upper data latch Similarly, the array DLLA of the circuit DLL is arranged, and the switch circuit / arithmetic circuit array 30R, the memory mat MMR, the switch circuit / arithmetic circuit array 31R, and the array DLRA of the lower data latch circuit DLR are similarly arranged on the other input / output node side. Has been placed. Further, as shown in FIG. 5, if the configuration is understood by focusing on a pair of bit lines, the pair of data input / output nodes SLL and SLR of the sense latch circuit SL in the static latch form are connected to the bit lines G-BLL, Data latch circuits DLL and DLR are provided via the G-BLR. The data latch circuits DLL and DLR can latch write data bits supplied via the Y gate array circuit 13. According to this example, since the flash memory 1 has 8-bit input / output terminals I / O0 to I / O7, write data is input to the data latch circuits DLL and DLR of the four pairs of bit lines by one write data input. Can be set. The mode of the data set is made constant as represented by the correspondence between the data latches DDL and DLR and the input / output terminals I / O4 and I / O0 in FIG. In this description, since the unit of writing is a word line unit, after setting the write data in the data latch circuits DLL and DLR relating to the bit lines of all the memory cells whose selection terminals are coupled to one word line. Then, the write operation by applying the write voltage is performed.
[0045]
In the multi-value information storage technology to be realized by the flash memory 1 shown in FIG. 1, the information storage state of one memory cell is the erase state (“11”), the first write state (“10”), the first One of the two write states (“00”) and the third write state (“01”) is selected. A total of four information storage states are determined by 2-bit data. That is, 2-bit data is stored in one memory cell. The relationship between the quaternary data and the threshold voltage is as shown in the threshold voltage distribution diagram of FIG.
[0046]
In order to obtain the threshold distribution as shown in FIG. 7, three different types of write verify voltages applied to the word line during the write operation are set, and these are sequentially switched to perform the write operation in three steps. In FIG. 7, VWV1, VWV2, and VWV3 are write verify voltages used when obtaining the first write state, the second write state, and the third write state, respectively.
[0047]
FIG. 8 shows an example of the voltage application state of the word line and the bit line in the individual write operations divided into three times. 0V is applied to the bit line selected for writing, and 6V is applied to the non-selected bit line. Although not particularly limited, the word line is set to 17 V, for example. As the write high voltage application time increases, the threshold voltage of the memory cell increases. Three kinds of write threshold voltage control can be performed by time control in such a high voltage state, and further by level control of a high voltage applied to the word line.
[0048]
Whether 0V or 6V is applied to the bit line is determined by the logical value of the write control information latched by the sense latch circuit SL. Although details will be described later, control is performed on the write operation selection memory mat side so that the latch data of the sense latch is selected for writing when the logic value is “1” and is selected when the logic value is “0”. Details of the control will be described later. The switch circuit / arithmetic circuit includes a precharge circuit. When the latch data of the sense latch is “1” and 6V is applied to the bit line, the precharge circuit pre-charges the bit line in advance. Operates to charge. As described above, by performing precharge in the precharge circuit in advance, it is possible to reduce the peak current when 6 V is applied to the bit line.
[0049]
The latch operation of the write control information for the sense latch circuit is controlled for each of the three write operations. This write control is performed by the mode control circuit 18, and at this time, the write control information to be latched by the sense latch circuit SL is calculated using the write data bits held by the data latch circuits DLL and DLR for each write operation. Are generated and the sense latch circuit SL latches them. For example, if the write data latched in the data latch circuits DLL and DLR is “01” as illustrated in FIG. 6, the “01” state is the third write state as illustrated in FIG. It is. If the write operation divided into three times after the erase state employs a write procedure in which the write state is generated in the order of the lower threshold voltage as in the second mode (Case 2) of FIG. 9, the first time The result calculated using the write data (“01”) of the data latch circuits DLL and DLR during the write operation for obtaining the first write state is the logical value “1”, and the second write state is the second time. The result calculated using the write data (“01”) of the data latch circuits DLL and DLR during the write operation for obtaining the logical value “1”, and the write operation for obtaining the third write state for the third time Sometimes the result calculated using the write data (“01”) of the data latch circuits DLL and DLR is a logical value “0”. Such calculation is performed by operating the switch circuit / calculation circuit. Therefore, the write voltage is applied only at the time of the third write, and the third write state (“01”) among the four values is realized in the memory cell.
[0050]
In this manner, when the write operation is performed in three steps, the write data latched in the data latch circuits DLL and DLR first is not destroyed and is maintained as it is. This is because a control sequence is adopted in which the 2-bit write data latched in the data latch circuits DLL and DLR is used for calculation for each write operation and is set in the sense latch circuit SL every time.
[0051]
The order in which the threshold voltage is changed in the write operation is not limited to the second mode (Case 2) in FIG. 9, but may be set from the first mode (Case 1) with a higher threshold voltage or the second mode (Case 1). As in the third mode (Case 3), the threshold voltage change rate obtained by one write operation is made the same for any write state, or the fourth mode (Case 4) or the fifth mode (Case 5). It is also possible to control as follows.
[0052]
During the data read operation, three types of voltages as word line selection levels to be applied to the word lines are set, and the three read operations are performed while sequentially changing the three types of word line selection levels. Binary (1 bit) data read from the memory cell is latched in the sense latch circuit 4. Every time it is latched, an operation is performed to reflect the sense latched contents in the 2-bit information of the data latch circuit. Two bits obtained in the data latch circuits DLL and DLR by the result of the three sense latches are data corresponding to the four-value information held by the memory cell.
[0053]
<Details of memory array>
Next, details of the memory array will be described. FIG. 10 shows an example of a circuit configuration centering on a sense latch circuit and a data latch circuit in the flash memory. As apparent from FIG. 10, the configuration around the left and right bit lines G-BLL and G-BLR of the sense latch circuit SL is a mirror-symmetric structure with the sense latch circuit SL as the center.
[0054]
The memory mats MML and MMR have a plurality of electrically rewritable memory cells MC (typically several are shown). As shown in FIG. 2, one memory cell MC includes a control gate, a floating gate, a source, a drain, and an electrically rewritable transistor (memory cell transistor). The layout structure of the memory cell is not particularly limited, but is a so-called AND type. As exemplified on the memory mat MMR side, in the AND type configuration, a plurality of the memory cell transistors are arranged in parallel via respective diffusion layers (semiconductor regions) that constitute a source and a drain common to them, The diffusion layer constituting the drain is coupled to the bit line G-BLR via the selection transistor M1, and the diffusion layer constituting the source is coupled to the common source line VMMR via the selection transistor M2. Details of the AND type memory cell structure will be described later. SSi is a switch control signal for the selection transistor M2, and SDi is a switch control signal for the selection transistor M1. WL is a word line coupled to the control gate of the memory cell MC. The memory mat MML is similarly configured. In the drawings attached to the present specification, the P channel type MOS transistor is shown as distinguished from the N channel type MOS transistor by attaching an arrow to the base gate.
[0055]
The sense latch circuit SL is composed of a static latch composed of a pair of CMOS inverters, that is, a circuit formed by coupling the input terminal of one CMOS inverter to the output terminal of the other CMOS inverter. SLR and SLL are a pair of input / output nodes of the sense latch circuit SL. SLP and SLN are operating power supplies of the sense latch circuit SL. The series circuit of the MOS transistors M3L and M4L and the direct circuit of the MOS transistors M3R and M4R constitute a column switch circuit that inputs data to the sense latch circuit SL as a complementary signal. MOS transistors M5L and M5R selectively discharge input / output nodes SLL and SLR.
[0056]
The data latch circuit DLR is composed of a static latch composed of a pair of CMOS inverters, that is, a circuit formed by coupling the input terminal of one CMOS inverter to the output terminal of the other CMOS inverter. DLRR and DLRL are a pair of input / output nodes of the data latch circuit DLR. DLPR and DLNR are operation power supplies of the data latch circuit DLR. The series circuit of the MOS transistors M6L and M7L and the direct circuit of the MOS transistors M6R and M7R constitute a column switch circuit that inputs and outputs data in the form of complementary signals to the data latch circuit DLR. MOS transistors M8L and M8R selectively charge input / output nodes DLRL and DLRR to voltage FPC.
[0057]
The data latch circuit DLL is constituted by a static latch composed of a pair of CMOS inverters, that is, a circuit formed by coupling the input terminal of one CMOS inverter to the output terminal of the other CMOS inverter. DLLLR and DLLL are a pair of input / output nodes of the data latch circuit DLL. DLPL and DLNL are operating power supplies for the data latch circuit DLL. The series circuit of the MOS transistors M9L and M10L and the direct circuit of the MOS transistors M9R and M10R constitute a column switch circuit that inputs and outputs data in the form of complementary signals to the data latch circuit DLL. The MOS transistors M11L and M11R selectively charge the input / output nodes DLLL and DLLR to the voltage FPC.
[0058]
The switch circuit / arithmetic circuit 30R includes MOS transistors M20R to M25R. The transistor M20R receives the voltage level of the input / output node SLR of the sense latch circuit SL at the gate, and supplies the voltage FPC to the bit line G-BLR via the MOS transistor M21R when it is at the high level. The supplied voltage level is determined by the conductance control of the MOS transistor M21R according to the voltage level of the control signal PCR. The transistor M22R forms a transfer gate that selectively connects the input / output node SLR and the bit line G-BLR. The MOS transistor M23R is used for all determination. The MOS transistors M24R and M25R are used for precharging and discharging the bit line G-BLR. The switch circuit / arithmetic circuit 30L is similarly configured by MOS transistors M20L to M25L. The gate control signals of the MOS transistors M20L, M22L, M24L, and M25L are different from those of the MOS transistors M20R, M22R, M24R, and M25R.
[0059]
The switch circuit / arithmetic circuit 31R includes MOS transistors M26R to M28R. The transistor M26R receives the voltage level of the input / output node DLRL of the data latch circuit DLR at its gate, and supplies the voltage FPC to the bit line G-BLR via the MOS transistor M27R when it is at the high level. The supplied voltage level is determined by the conductance control of the MOS transistor M27R according to the voltage level of the control signal PCDR. The transistor M28R forms a transfer gate that selectively connects the input / output node DLRL and the bit line G-BLR. The switch circuit / arithmetic circuit 31L is similarly configured by MOS transistors M26L to M28L. The gate control signals of the MOS transistors M27L and M28L are different from those of the MOS transistors M27R and M28R.
[0060]
In the configuration of FIG. 10, basic circuit operations in reading and writing are as follows. For example, in FIG. 10, when reading is performed in the verify operation for the memory cells MC included in the memory mat MMR, the set MOS transistor M5L on the non-selected memory mat MML side is turned on to activate the sense latch SL. Thus, a high level is latched at the input / output node SLR of the sense latch SL. Then, the bit line G-BLR is precharged to 1V by controlling the PCR to 1V + Vth, for example. On the other hand, on the non-selected memory mat MML side, the gate voltage RPCL of the MOS transistor M24L is controlled to 0.5V + Vth to precharge the bit line G-BLL to 0.5V. This 0.5 V is used as a reference level for the sensing operation by the sense latch circuit SL. On the other hand, in the read operation according to the read command, the signal RPCR on the selected memory mat (MMR) side is set to 1V + Vth, and the signal RPCL on the non-selected memory mat (MML) side is set to 0.5V + Vth, so The mat side bit line is precharged to 1V, and the non-selected memory mat side bit line is precharged to 0.5V. Of course, if the selected memory mat is MML and the non-selected memory mat is MMR, the signal RPCR is set to 0.5V + Vth and the signal RPCL is set to 1V + Vth. The precharged 0.5V is used as a reference level as described above. After the word line selection operation, the transfer MOS transistors M221 and M22R are turned on. At this time, the sense latch circuit SL senses whether the level of the bit line G-BLR is higher or lower than 0.5 V, and Read data from the cell MC is latched.
[0061]
In the write operation, after the write control information is latched in the sense latch SL, the gate control signals PCR and PCL of the MOS transistors M21R and M21L are controlled to a high level, thereby the high-level input / output node of the sense latch circuit SL. Is precharged to a high level via the MOS transistor M20R or M20L, and then the MOS transistors M22R and M22L are turned on, and the high-level input / output of the sense latch circuit from the power supply SLP of the sense latch circuit A voltage is applied to the bit line coupled to the node. At this time, a high write voltage is applied to the word line of the write sector of the memory mat selected for writing. As a result, among the memory cells connected to the control gate to which the write voltage is applied on the write selection memory mat side, the memory cells whose bit lines are at a low level such as the ground voltage are targeted for writing.
[0062]
The all determination transistors M23L and M23R are used as follows. MOS transistors M23L and M23R have their gates coupled to the corresponding bit lines and their sources coupled to the ground potential. There are actually a large number of configurations related to the bit lines G-BLL and G-BLR centered on one sense latch circuit SL typically shown in FIG. The drains of the transistor M23L on the left side of FIG. 10 across the sense latch circuit SL are all commonly connected to the terminal ECL, and a current corresponding to the state (level) of the left bit line represented by the bit line G-BLL is applied to the terminal. Flowed to ECL. Similarly, all the drains of the right transistor M23R in FIG. 10 across the sense latch circuit SL are also connected in common to the terminal ECR, and the terminal ECR has the state of the right bit line represented by the bit line G-BLR ( Current corresponding to the level). Although not particularly illustrated, it is detected whether all the bit lines G-BLL (G-BLR) on the left (right) side of the sense latch circuit SL are in the same state based on a change in the terminal ECL (ECR). A current sense type amplifier is provided. This amplifier is used for detecting whether all memory cells to be erase-verified or written-verified have a predetermined threshold voltage, that is, for all determination.
[0063]
The configuration of the memory mats MMR and MML illustrated in FIG. 10 is an AND type. A more detailed example of the AND type memory mat is shown in FIG. Although not shown in particular, the memory cell shown in FIG. 11 has a structure formed by a process using two metal wiring layers, and the memory cell MC and the selection MOS transistors M1 and M2 are arranged in parallel in the vertical diffusion layer. And a control gate made of polysilicon or the like extending in the lateral direction. The memory cell MC of the flash memory is, for example, an N channel type MOS transistor configured on a P type substrate.
[0064]
The memory mat of the flash memory is not limited to the AND type, and other structures such as a NOR type shown in FIG. 12, a DiNOR type shown in FIG. 13, a NAND type shown in FIG. 14, and a HiCR type shown in FIG. It is also possible to do. Regardless of the structure, all the memory cells of the flash memory basically have the same configuration, but when the memory cells are arranged in an array, the characteristics of the individual memory mats appear. The NOR type requires a contact with the bit line (metal wiring layer) for each memory, so it is difficult to reduce the occupied area. However, in the NAND type, DiNOR type, and AND type, the contact with the bit line is provided for each block. Since the arrangement is sufficient, the occupation area can be reduced.
[0065]
<Details of write operation>
FIG. 16 is a flowchart showing an example of the write operation designated by the first command (1FH) and the second command (40H). This write is a write (sector write) using a word line as a unit.
[0066]
First, when the first command (1FH) is fetched (S1), the next input is fetched as a sector address (S2), and the input after the sector address fetching is until the second command (40H) is fetched (S4). Then, it is taken in as write data (S3). The sector address fetched in step S2 is an X address, which selects one word line to which a high write voltage is applied. The repetitive fetching of the write data in step S3 is performed on the data latch circuits DLL and DLR in byte units while gradually incrementing the Y address counter 12 from the initial value. For example, as shown in FIG. 5, the write data is latched in the data latch circuit arrays DLLA and DLRA assigned to the pair of memory mats MML and MMR related to one sense latch circuit array SLA. For example, assuming that the control gates of n memory cells are coupled to one word line, n-bit write data is latched in the data latch circuit arrays DLLA and DLRA, respectively.
[0067]
After the write data is latched, a “01” write process TS1, a “00” write process TS2, a “10” write process TS3, and an elastic / disturb detection process TS4 are performed.
[0068]
For example, as illustrated in FIG. 17, the “01” write process TS1 sets the threshold voltage of the memory cell MC to the third state with respect to the erase state (“11”) which is one of the four values. In the write state (“01”), and VWV3 is used as the write verify voltage. As shown schematically in FIG. 16, the “01” write processing TS1 is a sense latch circuit that writes write control data at an enable level in response to 2-bit “01” data latched by the data latch circuits DLL and DLR. SL is latched (“01” data latch), and a write operation corresponding to “01” data is performed on the memory cell transistor by the latched enable level write control data (“01” data write), and VWV3 for the write operation is performed The processing is roughly divided into processing for performing write verification (write verification VWV3).
[0069]
In the “00” write process TS2, for example, as illustrated in FIG. 18, the threshold voltage of the memory cell MC is set to the second value for the erase state (“11”) which is one of four values. The write state is “00”, and VWV2 is used as the write verify voltage. In the “00” write process TS2, as schematically shown in FIG. 16, the write control data at the enable level is sense latched in response to the 2-bit “00” data latched in the data latch circuits DLL and DLR. The circuit SL is latched (“00” data latch), and a write operation corresponding to “00” data is performed on the memory cell transistor by the latched enable level write control data (“00” data write), and VWV2 corresponding to the write operation. Is roughly classified into a write verify process (write verify VWV2).
[0070]
For example, as illustrated in FIG. 19, the “10” write process TS3 sets the threshold voltage of the memory cell MC to the first with respect to the erased state (“11”) which is one of four values. The write state (“10”) is obtained, and VWV1 is used as the write verify voltage. As shown schematically in FIG. 16, the “10” write process TS3 sense-latches write control data at the enable level in response to 2-bit “10” data latched by the data latch circuits DLL and DLR. The circuit SL is latched (“10” data latch), and a write operation corresponding to the “10” data is performed on the memory cell transistor by the latched enable level write control data (“10” data write), and VWV1 for the write operation Is roughly classified into a write verify process (write verify VWV1). The write verify voltage is VWV3>VWV2> VWV1.
[0071]
In the elastic / disturb detection process TS4, as illustrated in FIG. 20, a disturb detection process ("11" word disturb detection VWDS in FIG. 16) detects whether the threshold voltage of the erased memory cell exceeds VWDS. The threshold voltage of the memory cell transistor subjected to the “10” write process exceeds VWE1 (“10” elastic detection VWE1 in FIG. 16), or the threshold voltage of the memory cell transistor subjected to the “00” write process is VWE2. Is an elastic detection process for detecting whether or not the value exceeds “00” (“00” elastic detection VWE2 in FIG. 16).
[0072]
If the series of processing results up to the elastic / disturb detection processing TS4 is normal, the pass flag is set in the status register 180 (S5), and the series of write processing ends (OK). If the detection result of the elastic / disturb detection process TS4 is an error, it is determined whether the number of errors has reached a specified number (S6). If not, the write sector is erased (S7) and again. Redo from "01" write. The number of redoes is held in a counter means (not shown), and it is determined whether the number of errors has reached a specified value based on the count value of the counter means (S6). When the number of errors reaches a specified value, a fail flag is set in the status register 180 (S8), and a series of write processing ends abnormally (NG).
[0073]
As is apparent from FIG. 16, when re-erasing is performed and writing is repeated again, it is not necessary to retake the write data of the write sector. This is because the write data for one sector once latched in the data latch circuits DLL and DLR in step S3 is not destroyed even if the processes TS1 to TS4 are performed, and remains in the data latch circuits DLL and DLR as they are. .
[0074]
This depends on the latch operation control mode of the write control information described above for the sense latch circuit SL. That is, the write control information to be latched by the sense latch circuit SL is generated by performing an operation using the write data bits held by the data latch circuits DLL and DLR for each write operation, and generating the control information. Latches. For example, if the write data latched in the data latch circuits DLL and DLR is “01” as illustrated in FIG. 6, the “01” state is the third write state as illustrated in FIG. It is. When the write operation divided into three times after the erase state is performed in the second mode (Case 2) of FIG. 9, the data latch circuit DLL, during the write operation for obtaining the first write state for the first time The result calculated using the write data (“01”) of the DLR is a logical value “1”, and the write data (“” of the data latch circuits DLL and DLR at the time of the write operation for obtaining the second write state at the second time. 01 ") is the logical value" 1 ", and the write data (" 01 ") of the data latch circuits DLL and DLR is used in the third write operation to obtain the third write state. The calculated result is a logical value “0”. Such calculation is performed by operating the switch circuit / calculation circuit. Therefore, in the memory cell transistor, a high electric field for writing is applied between the drain and the control gate only at the time of the third writing, and the third writing state (“01”) among the four values is applied to the memory cell. ) Is realized.
[0075]
In this manner, when the write operation is performed in three steps, the write data latched in the data latch circuits DLL and DLR first is not destroyed and is maintained as it is. This is because a control sequence is adopted in which the 2-bit write data latched in the data latch circuits DLL and DLR is used for calculation for each write operation and is set in the sense latch circuit SL every time. Similarly, in the elastic disturbance detection process, a control sequence is adopted in which the result calculated using the 2-bit write data latched in the data latch circuits DLL and DLR is set in the sense latch circuit SL every time. Also at this time, the write data latched in the data latch circuits DLL and DLR first is not destroyed and is maintained as it is.
[0076]
The processing (data latch processing) for causing the sense latch circuit SL to latch the result calculated using the 2-bit write data latched in the data latch circuits DLL and DLR is related to the current processing in TS1 to TS4. The method is different.
[0077]
FIG. 21 logically shows an example of calculation contents of the data latch processing. The calculation contents in FIG. 21 relate to the sense latch data on the operation selection memory mat side (input / output node data of the sense latch circuit SL on the operation selection memory mat side). Although a specific calculation method will be described in detail later, a multi-sense method and a multi-power supply method can be adopted. In the multi-sense method, the bit line precharge voltage is set to three levels of 0 V, 0.5 V, and 1.0 V, and the sense latch circuit SL latches the target data by a plurality of sense operations by the sense latch circuit SL. is there. In the multi-power supply system, the bit line precharge voltage is set to four levels of 0 V, 0.5 V, 1.0 V, and 2.0 V, and the target data is transferred to the sense latch circuit SL by one sensing operation by the sense latch circuit SL. It is an operation to latch.
[0078]
In FIG. 21, A and B are 2-bit write data corresponding to one sense latch circuit SL, A is an upper data bit latched in the data latch circuit DLL, and B is latched in the data latch circuit DLR. Lower data bit. According to FIG. 21, in the case of “01” write data latch processing, the logical sum of inverted data of data bits A and B, in the case of “00” write data latch processing, the logical sum of data bits A and B, “ In the case of 10 "write data latch processing, the logical sum of the inverted data of data bit A and B is obtained. In the case of" 00 "elastic detection data latch processing, negative logical sum of data bits A and B, and" 10 "error. In the tick detection data latch process, the logical product of the inverted data of the data bits A and B is used. In the “11” elastic detection data latch process, the logical product of the data bits A and B is used.
[0079]
When the arithmetic logic of FIG. 21 is adopted, the logical value of the arithmetic result for the logical values of the data bits A and B is as shown in FIG. As described above, the logical value “0” (low level) of the sense latch data means application of a write electric field (write selection).
[0080]
FIG. 23 illustrates a more detailed flowchart of the “01” write process TS1. According to this, the “01” write process TS1 includes the data latch process S10, the “01” write bias application process S11, the write verify process S12, and the all determination process S13. In the data latch process S10, when the 2-bit write data “01” is latched in the corresponding two data latch circuits DLL, DLR, the write enable bit is latched in the sense latch circuit SL, and the other write data In this case, the write disable level is latched by the sense latch circuit SL. In the “01” write bias application process S11, when the write enable level is latched in the sense latch circuit SL, a high electric field is applied between the bit line on the input / output node side of the enable level and the control gate in the write selection memory mat. Is applied. In the process S12, a verify operation is performed with the write verify voltage VWV3. In the process S13, it is determined whether or not the all determination result is an error. If there is an error, the process returns to the process S11. If the all determination result is normal, the “01” writing process is terminated. In the processes TS2 and TS3, the calculation method, the write bias voltage, and the write verify voltage for the data latch process are unique, and the general processing procedure is the same as the flowchart of the process TS1, so the details of these processes are described. The flowchart is not shown.
[0081]
FIG. 24 illustrates a detailed flowchart of the “10” elastic detection process. According to this, the “10” elastic detection process includes a data latch process S20, an elastic verify process S21, and an all determination process S22. The data latch process S20 performs a latch process according to the calculation contents shown in FIGS. The elastic verify process S21 verifies whether the threshold voltage exceeds VWE1 with respect to the memory cell transistor subjected to the “10” write process. In process S22, it is determined whether the all determination result is an error. If YES, the process proceeds to step S6. If the all determination result is normal, the “10” elastic detection process is terminated. The other processes of the elastic / disturb detection process TS4 are specific to the calculation method and verify voltage for the data process with respect to FIG. 24, and the general processing procedure is "10" elastic detection process. The detailed flowchart of these processes is not shown in the figure.
[0082]
<Data latch processing>
An example of an arithmetic processing method of data latch processing represented by steps S10 and S20 is shown in FIGS. In these drawings, the operation selection memory mat is the memory mat (MMR) on the right side of the drawing. Also, in each figure, for the numbers shown corresponding to the signals or nodes shown for each step, numbers with a decimal point mean voltage, numbers without a decimal point are logical values (high level is “1”) ", Low level means" 0 "). The numbers in parentheses corresponding to the data latch circuits DDL and DDR indicate the logical value of the left input / output node outside the parentheses, and the number in parentheses indicates the logical value of the right input / output node.
[0083]
For example, the details of the “01” write data latch processing S10 by the multi-sense method will be described in detail with reference to FIG.
[0084]
It is assumed that data is already latched in the data latch circuits DLL and DLR. The case where the latched data is “01”, “00”, “10”, “11” is illustrated. In Step 2 (Step 2), first, the bit line G-BLL on the non-selected memory mat side is precharged to 0.5 V through the transistor M24L (a), and M26R, M27R according to the latch data of the data latch circuit DLR. Is used to precharge the bit line G-BLR to 0.0V or 1.0V (b).
[0085]
In step 3 (Step 3), the sense latch circuit SL is activated in accordance with the results of (a) and (b) to perform a sense latch operation. As a result, the left and right input / output nodes SL (L) and SL (R) of the sense latch circuit SL are brought into the states shown in FIGS.
[0086]
In Step 4 (Step 4), the voltage of the bit line G-BLL takes the voltage of (e) according to the result of (c), and the other bit line G-BLR is cleared to the logical value “0”.
[0087]
In step 5 (Step 5), the transistor M26L is turned on by the latch data having the logical value “1” of the data latch circuit DLL, and the data latch circuit DLL latches the logical value “1” via the transistors M27L and M26L. The bit line G-BLL to be executed is forced to a low level (g). Further, both input / output nodes SL (L) and SL (R) of the sense latch circuit SL are cleared to a logical value “0”.
[0088]
In step 6 (Step 6), the bit line G-BLR on the selected memory mat side is precharged to 0.5 V (i). When the sense latch circuit SL is sensed in step 7 (Step 7), the input / output node SL (R) or SLR on the selected memory mat side of the sense latch circuit SL latches “01” in the data latch circuits DLL and DLR. Only when this is done, the logical value “0” is latched (j). An example of the operation timing of the write data latch process is shown in FIG.
[0089]
When the latch data of the input / output node on the operation selection memory mat side in the sense latch circuit SL is a logical value “0”, the level of the bit line connected to the input / output node is set to 0V, and the drain is connected to the bit line. A high write electric field is applied between the drain and the control gate of the memory cell transistor to which is connected, and a write operation to the memory cell transistor is performed.
[0090]
As details of the operation of the write bias application process S11 in the write operation, there are FIG. 31 showing the start of the write bias and FIG. 32 showing the end of the write bias. That is, a write blocking voltage is introduced to the bit line of the write non-selected memory mat. The bit line on the write selection memory mat side is set to 0V or 6V according to the latch data of the sense latch circuit SL, and a high voltage such as 17V is applied to the word line to perform writing to the memory cell transistor. After completion of writing, the bit lines G-BLL and G-BLR are discharged. An example of the write operation timing is shown in FIG.
[0091]
After the write bias is applied, the write verify process S12 is performed. For example, as illustrated in FIG. 33, the bit line on the write non-selected memory mat side, such as G-BLL, is written to the reference voltage 0.5V. The bit line on the selected memory mat side, such as G-BLR, is precharged to 1.0V. Thereafter, as illustrated in FIG. 34, a word line selection operation using a verify voltage is performed. By the word line selection operation, the memory cell whose threshold voltage is lower than the verify voltage is turned on, and the high memory cell is turned off. The sense latch circuit SL detects a change in state due to the change in the potential difference of the bit line (FIG. 35), and finally latches the definite data (FIG. 36). An example of the write verify operation timing is shown in FIG.
[0092]
After the sense latch circuit SL latches the definite data, the all determination process S13 is performed. In the all determination process, it is detected whether or not the MOS transistor, for example, the transistor M23L of the bit line on the write operation non-selected memory mat side is turned on. If there is at least one memory cell transistor in which writing is defective, the bit line opposite to the bit line to which the transistor is connected goes to the high level, the transistor M23L is turned on, and a current flows (see FIG. 37). While the current flows, there is a write failure, and a bias is applied to the memory cell transistor again as described above. An example of the operation timing of the all determination is shown in FIG.
[0093]
26 shows details of the “00” write data latch process by the multi-sense method, FIG. 27 shows details of the “10” write data latch process by the multi-sense method, and FIG. 28 shows the multi-sense method. Details of the “00” elastic detection data latch processing by the method are shown, FIG. 29 shows details of the “10” elastic detection data latch processing by the multi-sense method, and FIG. 30 shows “11” by the multi-sense method. “Details of disturb detection data latch processing are shown. The specific contents of these processes are different from the data latch process of FIG. 25 in detail, but are common in that precharge and sense operations are used, and the contents can be easily understood from each figure. Detailed description is omitted.
[0094]
42 to 53 show details such as data latch processing in the case of the multiple power supply system. Similarly to FIGS. 25 to 30, FIGS. 42 to 47 are similar to FIGS. 25 to 30, and the operation selection memory mat is the memory mat on the right side of the figure, and in each figure, the operation selection memory mat is displayed corresponding to the signal or node shown for each step. Numbers with a decimal point mean voltage, and numbers without a decimal point mean logical values (high level is “1”, low level is “0”).
[0095]
With reference to FIG. 42, for example, “01” write data latch processing by the multi-power supply method will be described in detail. It is assumed that data is already latched in the data latch circuits DLL and DLR. The case where the latched data is “01”, “00”, “10”, “11” is illustrated. In Step 1 (Step 1), first, the bit line G-BLL on the non-selected memory mat side is precharged to 1.0 V via the transistor M24L (a), and the bit line G-BLR on the selected memory mat side is turned on to the transistor M24R. (B) is precharged to 2.0V.
[0096]
In step 2 (Step 2), the transistor M26L is turned on by the latch data having the logical value “1” of the data latch circuit DLL, and the data latch circuit DLL latches the logical value “1” via the transistors M27L and M26L. The bit line G-BLL to be executed is forced to a low level (c). Similarly, the bit line corresponding to the data latch circuit DLR that turns on the transistor M26R by the latch data of the logical value “1” of the data latch circuit DLR and latches the logical value “1” via the transistors M27R and M26R. Force G-BLR to low level (d).
[0097]
In step 3 (Steps), the 0.0V bit line G-BLR is precharged to 0.5V (e). When the sense latch circuit SL is sensed in step (Step 4), the input / output node SL (R) or SLR on the selected memory mat side of the sense latch circuit SL is latched "01" in the data latch circuits DLL and DLR. Only when it is, the logic value “0” is latched (f). An example of the operation timing of the “01” write data latch process is shown in FIG. When the latch data of the input / output node on the operation selection memory mat side in the sense latch circuit SL is a logical value “0”, the level of the bit line connected to the input / output node is set to 0V, and the drain is connected to the bit line. A high write electric field is applied between the drain and the control gate of the memory cell transistor to which is connected, and a write operation to the memory cell transistor is performed.
[0098]
FIG. 43 shows details of the “00” write data latch process by the multi-power supply method, and FIG. 49 shows an example of the operation waveform. FIG. 44 shows details of the “10” write data latch processing by the multi-power supply method, and FIG. 50 shows an example of the operation waveform. FIG. 45 shows details of the “00” elastic detection data latch processing by the multi-power supply method, and FIG. 51 shows an example of the operation waveform. FIG. 46 shows details of the “10” elastic detection data latch processing by the multi-power supply method, and FIG. 52 shows an example of the operation waveform. FIG. 47 shows details of the “11” disturb detection data latch processing by the multi-power supply method, and FIG. 53 shows an example of the operation waveform. Although the specific contents of these processes differ from the data latch process of FIG. 42 in detail, they are common in that precharge and sense operations are used, and the contents can be easily understood from each figure. Detailed description is omitted.
[0099]
FIG. 54 collectively shows various voltage conditions for each operation mode of the flash memory described above. 54, the read word line voltage of “11” data is 2.4V, the read word line voltage of “10” data is 3.2V, and the read word line voltage of “00” data is 4.0V. The “10” data write word line voltage is 15.1V, the “00” data write word line voltage is 15.8V, and the “01” data write word line voltage is 17.0V. The “10” data verify word line voltage is 2.8V, the “00” data verify word line voltage is 3.6V, and the “01” data verify word line voltage is 4.5V. The “11” word disturb detection voltage is 2.1V, the “10” word disturb detection voltage is 3.1V, and the “00” word disturb detection voltage is 3.9V.
[0100]
《Retry function and recovery function》
As is apparent from the flowchart of FIG. 16, in the above-described flash memory 1, even when a write abnormality occurs, the write data at that time is stored in the data latch circuits DLL and DLR. When the flash memory 1 receives a retry write command after abnormal termination of the write operation, the flash memory 1 writes the write data already held by the data latch circuits DLL and DLR to the address supplied with the command. Operation can be performed. That is, as illustrated in FIG. 55, when the flash memory 1 inputs a retry write command (10H) (S30), it next inputs a sector address (S31, S32), and the input sector address (word line address). ), The write data already latched in the data latches DLL and DLR is written in the flash memory (S33).
[0101]
In addition, the flash memory 1 takes into account the simplification of the process of rewriting to another flash memory as rewriting after abnormal termination of the writing operation. That is, as illustrated in FIG. 56, the flash memory 1 holds the data latch circuits DLL and DLR when the supply of the recovery read command (01H) is received after the abnormal end of the write operation (S40). The written data can be output to the input / output terminals I / O0 to I / O7 through the output buffer 15 and the multiplexer 7 (S41).
[0102]
FIG. 57 shows a transition state of the internal operation in the flash memory having the retry and recovery functions. When the power is turned on, a deep standby state (Deep standby) is set, and when the reset signal is negated, the standby state (Standby) is set. When the chip is selected from the standby state, the output is disabled (output disable), and the operation according to the command input is enabled. Operations according to command input are broadly classified into read (Read setup), sector erase (Sector Erase setup), write (Program setup), and the like. When an error occurs in erasing or writing, a recovery read command (Recovery Read setup) and a retry write command (Retry Program setup) can be accepted.
[0103]
FIG. 58 shows an example of a memory card using the flash memory 1. The memory card 200 shown in the figure is configured by mounting a local memory 201, a memory controller 202, a buffer memory 203, and an external interface circuit 204 on a card board. Many flash memories 1 are mounted in the local memory 200. The memory controller 202 generates a control signal controller 210 that generates access control signals for the flash memory 1 and the buffer memory 203, an address controller 211 that performs chip selection control for the flash memory 1 and the buffer memory 203, and the flash memory 1 and the buffer memory 203. It has a data I / O controller 212 that performs data, command and address interface control. The external interface circuit 204 has a configuration conforming to, for example, a PC card interface.
[0104]
FIG. 59 shows an example of a data processing system using the flash memory 1. The difference from FIG. 58 is that the memory controller 202 is arranged as one peripheral circuit on the control bus CBUS, the address bus ABUS and the data bus DBUS to which the CPU or the microprocessor 230 is connected, like the ROM 231 and the RAM 232. It is that.
[0105]
When the flash memory 1 has the retry function, the memory controller 210 or the microprocessor 230 that controls access to the flash memory 1 changes the write address or sector address for the flash memory in which the write operation is abnormally terminated. Thus, rewriting can be easily performed.
[0106]
In addition, this recovery function causes the memory controller of a memory card constituted by a plurality of flash memories or a control device that controls access to the memory card to end abnormally even if the write data is not stored by itself. Further, rewriting can be easily performed to a flash rush memory different from the flash memory.
[0107]
FIG. 60 shows a conceptual diagram of the retry and recovery function. For example, as shown in (A), the write data and the sector address are supplied from the buffer memory 203 to the flash memory 1 under the control of the memory controller 202, whereby the flash memory 1 operates to write data to the supplied sector address. To do. When an error occurs in the write operation, the flash memory 1 sets an error flag in the control register 180. As in (B), the error flag is transmitted to the microprocessor 230 or the like via the memory controller 202. As a result, when a recovery read command is output from the memory controller 202 to the flash memory 1 as shown in (C), the flash memory 1 writes data latched in the data latch circuits DLL and DLR as shown in (D). Output data. When the memory controller 202 gives a retry write command and a sector address to the flash memory 1 as shown in (E), the flash memory 1 is already latched by the data latch circuits DLL and DLR as shown in (F). The write data is written to the newly designated sector address.
[0108]
《Rewrite function》
The rewrite operation can be realized by erasing with an erase command and then writing with a write command. According to FIG. 3, after executing the erase command, the write command is executed. The flash memory 1 can realize such rewrite processing with a single command, that is, a rewrite command.
[0109]
FIG. 61 shows an example of processing by a rewrite command. That is, when the first rewrite command is supplied (S60), the sector address to be rewritten is fetched (S61), the data of the fetched sector address is read to the data latch circuits DLL and DLR (S62), and then written. Data is taken into the data latch circuits DLL and DLR (S63), and after the rewrite second command is supplied (S64), the sector specified by the rewrite sector address is erased (S65), and then the data latch circuit The designated sector is written with the data held in the DLL and DLR (S66). The write operation of the designated sector is the same as the operation described with reference to FIG. With this rewrite command, rewriting of all sector data can be realized with a single command.
[0110]
It is also possible to realize data rewriting for a part of the sector with a single command. That is, as illustrated in FIG. 62, when the first rewrite command is supplied (S70), the sector address to be rewritten is fetched (S71), and the data latch circuit receives data from the memory cell of the fetched sector address. The data is saved in the DLL and DLR (S72), and then data from the head Y address YA (0) of the sector to the necessary Y address YA (k) is taken into the data latch circuit (S73), and further necessary Accordingly, the Y address YA (m) satisfying k <m is fetched (S74), and data from the fetched Y address YA (m) to the necessary Y address YA (m + 1) is fetched into the data latch circuit. (S75). When the rewrite second command is supplied (S76), the sector designated by the rewrite address is erased, and then the designated sector write operation is performed based on the latch data of the data latch circuits DLL and DLR (S78). . The write operation of the designated sector is the same as the operation described with reference to FIG.
[0111]
Further, the data rewriting process for a part of the sector can be realized as shown in FIG. That is, when the first rewrite command is supplied (S80), a sector address to be rewritten is fetched (S81), and data is saved in the data latch circuits DLL and DLR from the memory cell of the fetched sector address (S82). . Thereafter, the head Y address YA (m) of the sector is fetched (S83), and data from the head Y address YA (m) to the necessary Y address YA (m + k) is fetched into the data latch circuit (S84). . Further, if necessary, the Y address YA (n) satisfying m + k <n is fetched (S85), and the data from the fetched Y address YA (n) to the necessary Y address YA (n + 1) is stored as data. The data is taken into the latch circuit (S86). The processes in steps S85 and S86 can be repeated as many times as necessary. When the second rewrite command is supplied (S87), the sector designated by the rewrite address is erased (S88), and then the designated sector write operation is performed based on the latch data of the data latch circuits DLL and DLR. (S89). The write operation of the designated sector is the same as the operation described with reference to FIG.
[0112]
<Partial erase function>
When the flash memory 1 is used as a file memory or the like, a management area can be allocated to the sector and the remaining part can be released as a user area. The management area stores, for example, information on the number of rewrites and good / bad sectors, and the flash memory 1 supports a command to automatically exclude the management area from being erased when the user erases in units of sectors. Furthermore, the usability of the file memory is improved. From this point of view, the flash memory 1 supports the partial erase command. That is, in FIG. 64 showing the partial erase function, when the partial erase first command is supplied (S90), the sector address is fetched (S91), and then when the partial erase second command is supplied (S92), the sector address The data latch circuits DLL and DLR corresponding to a certain area (for example, the management area) in the sector designated by (1) are saved to the data latch circuits DLL and DLR corresponding to other areas. Sets data instructing the erased state (S93). As a result, the read data is saved in the data latch circuits DLL and DLR corresponding to the management area of the designated sector, and “11” data corresponding to the erased state is stored in the data latch circuits DLL and DLR corresponding to the other areas of the sector. Is set. Then, after erasing the sector specified by the sector address, a write operation is performed in accordance with the data set in the data latch circuits DLL and DLR (S94). The write operation of the designated sector is the same as the operation described with reference to FIG.
[0113]
65 and 66 show a detailed example of the “designated sector data read” operation in step S93 as a whole, and the processing in FIG. 66 follows the processing in FIG. 65 and 66, “1” means that the potential of the corresponding node is high, and “0” means that the potential of the corresponding node is low. 65 and 66 assume a case where the right memory mat is an operation selection memory mat. FIG. 67 shows the relationship between the word line selection levels VRW1, VRW2, and VRW3 used for reading specified sector data and the threshold voltage distribution.
[0114]
In Step 1 (Step 1) of FIG. 65, the word line level is set to VRW1, the data of the memory cell in the designated sector is read, and is latched by the sense latch circuit SL. In step 2 (Step 2), data at the right node of the sense latch circuit SL is internally transferred to the data latch circuit DLR. In step 3 (Step 3), the word line level is set to VRW2, the data of the memory cell in the designated sector is read, and is latched by the sense latch circuit SL. In step 3.5 (Step 3.5), data “0” is set to the right input / output node of the sense latch circuit SL other than the management area selected by the Y address decoder. In step 4 (Step 4), the data of the left node of the sense latch circuit SL is internally transferred to the data latch circuit DLL. As a result, only a part of the required read data is saved in the data latch circuit DLL.
[0115]
In step 5 (step 5), the word line level is set to VRW3, the data of the memory cell in the designated sector is read, and is latched by the sense latch circuit SL. In step 5.5 (Step 5.5), data “1” is set to the right input / output node of the sense latch circuit SL other than the management area selected by the Y address decoder. In step 6 (step 6), the latch data of the data latch DLR is internally transferred to the bit line G-BLR through the transistor M28R. In Step 7 (Step 7), the right bit line G-BLR corresponding to the sense latch circuit SL in which “1” data is set in the right input / output node SLR is controlled to a low level, and Step 8 (Step 8). Thus, data is transferred from the sense latch circuit SL to the data latch circuit DLR. As a result, the 4-level information of the read data of the designated sector is stored in the data latch circuits DLL and DLR in the management area, and the data latch circuits DLL and DLR corresponding to other areas (memory areas) in the designated sector are erased. Data indicating the state is stored.
[0116]
According to the flash memory, memory card, and data processing system described above, the following operational effects can be obtained.
[0117]
[1] The write data given from the outside is latched in the data latch circuits DLL and DLR, and the threshold value of the multi-value corresponding to the latched write data is determined for each of the write operations in a plurality of stages, and the determination result. Write information is latched by the sense latch circuit SL, and a write operation for setting a multi-value threshold voltage in the memory cell is performed stepwise in accordance with the write information latched in the sense latch SL. Therefore, even after the write operation is completed, the write data originally supplied from the outside remains in the data latch circuits DLL and DLR. Therefore, it is not necessary to receive the write data from the outside again even when the multi-value information write operation to the memory cell MC is performed again according to the result of the word disturb detection or the elastic detection.
[0118]
[2] Even if a write error occurs, the write data at that time is stored in the data latch circuits DLL and DLR in the flash memory, so when the supply of the retry write command is accepted after the abnormal end of the write operation, Write data already held in the data latch circuit can be controlled to be written to an address supplied with the command. Since the flash memory has such a retry function, the memory controller that controls access to the flash memory can easily rewrite the semiconductor device in which the write operation is abnormally changed by changing the write address or the sector address. Can be done.
[0119]
[3] The flash memory outputs the write data held by the data latch circuits DLL and DLR to the outside when receiving supply of the recovery read command after the abnormal end of the write operation. With this recovery function, the memory controller of a memory card composed of a plurality of semiconductor devices or a control device that controls access to the memory card can store the same data in a flash memory different from the flash memory in which the write operation is abnormally terminated. Can be easily rewritten.
[0120]
[4] When the rewrite first command is supplied, the rewrite address is fetched and the write data is taken into the data latch circuit. After the rewrite second command is supplied, the area specified by the rewrite address is erased. Next, the write operation is controlled based on the data held in the data latch circuit. This makes it possible to rewrite all sector data with a single command.
[0121]
[5] By supporting the partial erase command, the management area of the sector can be automatically excluded from the erase target.
[0122]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
[0123]
For example, the information held by one memory cell is not limited to four values and may be more than that. For example, in the case of eight values, the number of data latch circuits connected to the bit line may be further increased. The calculation method of the data latch process is not limited to the above description, and can be changed as appropriate. In addition, the number of memory mats, write voltage conditions, erase voltage conditions, verify voltage conditions, and the like can be changed as appropriate. Further, the erased state and the written state can be defined in the opposite direction to the above description. The semiconductor device according to the present invention is not limited to a memory chip such as a flash memory, and can be widely applied to a semiconductor device for data processing or logic operation such as a microcomputer with built-in flash memory. The present invention can also be applied to an EEPROM.
[0124]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0125]
In other words, since multi-value information is written to each memory cell, the write data supplied to the data latch circuit from the outside is not lost by the write operation. Therefore, even after the write operation is completed, the write data originally supplied from the outside remains in the data latch circuit. Therefore, the multi-value information write operation to the memory cell is performed based on the result of the word disturb detection or the elastic detection. It is not necessary to receive the write data from the outside again when the process is performed again.
[0126]
Further, when the multi-value information write operation to the memory cell is performed again, it is not necessary to receive the write data from the outside again.
[0127]
When the write operation ends abnormally, the write data related to the abnormal end held inside can be rewritten by designating another memory address.
[0128]
When the writing operation ends abnormally, write data related to the abnormal end can be output to the outside.
[Brief description of the drawings]
FIG. 1 is an overall block diagram of a flash memory 1 according to a first embodiment of the present invention, in which 2-bit information can be written into and read from one memory cell. is there.
FIG. 2 is a device explanatory diagram illustrating an example of a memory cell transistor.
FIG. 3 is an explanatory diagram illustrating an example of a command of a flash memory.
FIG. 4 is an explanatory diagram showing an example of correspondence between each bit content of a status register and input / output terminals I / O0 to I / O7.
FIG. 5 is an explanatory diagram illustrating an example of a connection relationship among a data latch circuit, a bit line, and a sense latch circuit included in a memory array;
FIG. 6 is an explanatory diagram showing an example of a correspondence relationship between a data latch circuit and input / output terminals I / O4 and I / O0.
FIG. 7 is an explanatory diagram showing a relationship between four-value data and a threshold voltage in a threshold voltage distribution diagram.
FIG. 8 is an explanatory diagram showing an example of voltage conditions for sector batch erase and write.
FIG. 9 is an explanatory diagram exemplarily illustrating various writing modes in a four-value writing process.
FIG. 10 is a circuit diagram showing an example of a configuration centering on a sense latch circuit and a data latch circuit in a flash memory;
FIG. 11 is an example circuit diagram of an AND type memory mat.
FIG. 12 is a circuit diagram of an example of a NOR type memory mat.
FIG. 13 is an example circuit diagram of a DiNOR type memory mat.
FIG. 14 is a circuit diagram of an example of a NAND type memory mat.
FIG. 15 is a circuit diagram of an example of a HiCR type memory mat.
FIG. 16 is a flowchart illustrating an example of a write operation designated by a first command (1FH) and a second command (40H).
FIG. 17 is a schematic explanatory diagram of a “01” write process TS1.
FIG. 18 is a schematic explanatory diagram of a “00” write process TS2.
FIG. 19 is a schematic explanatory diagram of a “10” write process TS3.
FIG. 20 is a schematic explanatory diagram of an elastic / disturb detection process TS4.
FIG. 21 is an explanatory diagram logically showing an example of calculation contents of data latch processing.
22 is an explanatory diagram showing a logical value of a calculation result for logical values of data bits A and B when the arithmetic logic of FIG. 21 is employed.
FIG. 23 is a flowchart showing a more detailed example of “01” write processing TS1.
FIG. 24 is a flowchart showing a non-detailed value example of “10” elastic detection processing;
FIG. 25 is an explanatory diagram showing an example of a “01” write data latch process by a multi-sense method.
FIG. 26 is an explanatory diagram showing an example of a “00” write data latch process by a multi-sense method.
FIG. 27 is an explanatory diagram showing an example of “10” write data latch processing by a multi-sense method;
FIG. 28 is an explanatory diagram showing an example of a “00” elastic detection data latch process by a multi-sense method.
FIG. 29 is an explanatory diagram showing an example of a “10” elastic detection data latch process by a multi-sense method;
FIG. 30 is an explanatory diagram showing an example of “11” disturb detection data latch processing by the multi-sense method;
FIG. 31 is an explanatory diagram showing details of the first operation of the write bias application processing S11 in the write operation.
FIG. 32 is an explanatory diagram showing details of the final operation of the write bias application processing S11 in the write operation.
FIG. 33 is an explanatory diagram showing details of a bit line precharge operation in the VWV3 verify process;
FIG. 34 is an explanatory diagram showing details of a memory discharge operation in the VWV3 verify process;
FIG. 35 is an explanatory diagram showing details of a precharge operation for a sense latch in the VWV3 verify process.
FIG. 36 is an explanatory diagram showing details of a sense latch operation in the VWV3 verify process.
FIG. 37 is an explanatory diagram showing details of an all determination operation in the VWV3 verify process;
FIG. 38 is a timing chart showing an example of operation timing of the write data latch process.
FIG. 39 is a timing chart showing an example of a write operation timing.
FIG. 40 is a timing chart showing an example of operation timing of write verify.
FIG. 41 is a timing chart showing an example of an all determination operation timing.
FIG. 42 is an explanatory diagram of a “01” write data latch process by a multi-power supply method.
FIG. 43 is an explanatory diagram of a “00” write data latch process by a multi-power supply method.
FIG. 44 is an explanatory diagram of “10” write data latch processing by a multi-power supply method;
FIG. 45 is an explanatory diagram of “00” elastic detection data latch processing by a multi-power supply method;
FIG. 46 is an explanatory diagram of “10” elastic detection data latch processing by a multi-power supply system;
FIG. 47 is an explanatory diagram of “11” disturb detection data latch processing by the multi-power supply method;
FIG. 48 is an operation waveform diagram of “01” write data latch processing by a multi-power supply method;
FIG. 49 is an operation waveform diagram of “00” write data latch processing by the multi-power supply method;
FIG. 50 is an operation waveform diagram of “10” write data latch processing by the multiple power supply method;
FIG. 51 is an operation waveform diagram of “00” elastic detection data latch processing by a multiple power supply method;
FIG. 52 is an operation waveform diagram of “10” elastic detection data latch processing by a multiple power supply method;
FIG. 53 is an operation waveform diagram of “11” disturb detection data latch processing by the multiple power supply method;
FIG. 54 is an operation explanatory diagram collectively showing various voltage conditions for each operation mode of the flash memory.
FIG. 55 is a flowchart illustrating an example of a retry writing function.
FIG. 56 is a flowchart illustrating an example of a recovery function.
FIG. 57 is a state transition diagram of an internal operation in a flash memory having a retry and recovery function.
FIG. 58 is a block diagram showing an example of a memory card using a flash memory.
FIG. 59 is a block diagram illustrating an example of a data processing system using a flash memory.
FIG. 60 is a conceptual explanatory diagram of a retry and recovery function.
FIG. 61 is a flowchart illustrating an example of processing by a rewrite command.
FIG. 62 is a flowchart showing an example of processing by a rewrite command for realizing data rewriting for a part of a sector.
FIG. 63 is a flowchart showing another example of processing by a rewrite command for realizing data rewriting for a part of a sector.
FIG. 64 is a flowchart illustrating an example of a partial erase function.
65 is an explanatory diagram showing details of the first half of the designated sector data read operation of FIG. 64; FIG.
66 is an explanatory diagram showing details of the latter half of the designated sector data read operation of FIG. 64;
67 is an explanatory diagram showing a relationship between a word line selection level used for reading specified sector data and a threshold voltage distribution; FIG.
[Explanation of symbols]
1 Flash memory
3 Memory array
16 Data control circuit
18 Mode control circuit
I / O0 to I / O7 I / O terminals
DLL, DLR data latch circuit
DLLA, DLRA Data latch circuit array
MML, MMR Memory mat
SL sense latch circuit
SLA sense latch circuit array
30L, 30R switch circuit / arithmetic circuit
31L, 31R Switch circuit and arithmetic circuit
MC memory cell
G-BLL, G-BLR bit line
200 memory card
201 Local memory
202 Memory controller
203 Buffer memory
204 Interface circuit
230 Microprocessor

Claims (15)

A semiconductor device capable of storing multi-value information in one nonvolatile memory cell that can be electrically erased and written,
A sense latch circuit having a pair of input / output terminals, a bit line provided corresponding to each input / output terminal of the sense latch circuit, and a plurality of electrically erasable and writable bits selectively connected to the bit line Nonvolatile memory cells, data latch circuits coupled to the respective bit lines, input / output means for allowing the data latch circuits to interface with the outside, and control for controlling data reading, erasing and writing to the memory cells Means,
The control means holds external write data in the data latch circuit, and thresholds a nonvolatile memory cell selected to be connected to the bit line based on a plurality of bits of write data held in the data latch circuit. Write control information for determining which state is different in voltage is generated for each write operation and is latched by the sense latch circuit. The control unit further determines whether the threshold voltage to be set in the memory cell is a threshold voltage corresponding to a threshold voltage to be overwritten detection for each verify read operation for overwriting detection. If the latch data of the latch circuit is operated and determined, the determination result is latched by the sense latch circuit, and the determination result data latched by the sense latch circuit is the corresponding threshold voltage. 2. The semiconductor device according to claim 1, wherein line precharge is performed and overwriting is detected based on whether or not the bit line precharge state is changed by a verify read operation. 3. The semiconductor device according to claim 2, wherein when the overwriting is detected, the control unit re-executes writing after re-erasing. A non-volatile memory cell that can be electrically erased and written is controlled to be in an erase state, a first write state, a second write state, or a third write state with different threshold voltages, so that one memory cell has 4 A semiconductor device capable of storing value information,
Select a sense latch circuit having a pair of input / output terminals, a precharge means provided separately for each input / output terminal of the sense latch circuit, a bit line precharged by each precharge means, and a bit line Non-volatile memory cells electrically connected and electrically erasable and writable, a data latch circuit coupled to each bit line, and an input enabling the data latch circuit and the sense latch circuit to interface with the outside. Output means, and control means for controlling data reading, erasing and writing to the memory cell,
The control means holds external write data in the data latch circuit, and uses 2-bit write data held by two data latch circuits connected to a pair of bit lines sharing the sense latch circuit as a unit. Write control information for determining whether the nonvolatile memory cell selected to be connected to the bit line is in the erased state, the first written state, the second written state, or the third written state A semiconductor device, wherein the first and third write states are controlled in accordance with the latched write control information by calculating and latching the sense latch circuit for each write operation. The control means is connected to the bit line having the first logic value when the sense latch circuit latches the write control information having the output data on the memory cell connection selection bit line side as the first logic value. Write the memory cell
The calculation of the write control information by the control means includes the first write data bit latched in the data latch circuit on one memory cell connection selection bit line side sharing the sense latch and the other memory cell connection non-selection bit line. Logical inversion data of the first write data bit and the second write data bit with respect to the second write data bit latched in the data latch circuit on the side, the first write data bit A bit line precharge based on the latch data of the data latch circuit, and a logical sum of the first write data bit and a logical inversion data of the second write data bit. Operation based on the operation and sense operation by the sense latch circuit,
The control means causes the sense latch circuit to latch the logical sum sequentially obtained by the operation for each write operation, and the memory cell connection selection bit line bit line in which the latched logical sum becomes the first logical value 5. The semiconductor device according to claim 4, wherein the memory cell is subjected to a write operation. The control unit further determines whether the threshold voltage to be set in the memory cell is a threshold voltage corresponding to a threshold voltage to be overwritten detection for each verify read operation for overwriting detection. If the latch data of the latch circuit is operated and determined, the determination result is latched by the sense latch circuit, and the determination result data latched by the sense latch circuit is the corresponding threshold voltage. Line precharge is performed, and overwriting is detected based on whether the bit line precharge state is changed by the verify read operation.
The operation for the determination by the control means includes the first write data bit latched in the data latch circuit on the side of one memory cell connection selection bit line sharing the sense latch and the other memory cell connection non-selection bit line. A negative OR of the first write data bit and the second write data bit, the first write data bit and the second write data bit latched in the data latch circuit on the side The logical product of two write data bits with logically inverted data and the logical product of the first write data bit and the second write data bit are converted into a bit line precharge operation and a sense latch by latch data of a data latch circuit. It is an operation that calculates based on the sense operation by the circuit,
The control means causes the sense latch circuit to latch the negative logical sum and the logical product obtained sequentially by the calculation as the determination result data for each overwrite detection operation, and the sense latch circuit selects the memory cell connection selection bit. The memory cell connection selection bit line is precharged via the precharge circuit when the determination result data having the line side output data as the second logic value is latched. 5. The semiconductor device according to 5. When the control circuit receives supply of a retry write command after abnormal termination of the write operation, the control circuit performs write control of the write data already held by the data latch circuit at the address supplied with the command. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. The control circuit outputs the write data held by the data latch circuit to the outside via the input / output means when receiving the supply of the recovery read command after the abnormal end of the write operation. 8. The semiconductor device according to claim 1, wherein the semiconductor device is characterized in that: When the rewrite first command is supplied, the control means takes in the rewrite address, fetches the write data into the data latch circuit, and after the rewrite second command is supplied, erases the area specified by the rewrite address. 9. The semiconductor device according to claim 1, wherein the writing operation is controlled based on data stored in the data latch circuit. When the first rewrite command is supplied, the control means fetches a rewrite address, saves the data at the fetched address in the data latch circuit, specifies the rewrite address within the range of the rewrite address after saving, and writes the write data. After the second command for rewriting is supplied to the data latch circuit, the area designated by the rewrite address is erased, and then the data held in the data latch circuit in the area designated by the rewrite address is stored. 9. The semiconductor device according to claim 1, wherein the write operation is controlled on the basis of the write operation. When the partial erase first command is supplied, the control means takes in the sector address, and when the partial erase second command is supplied, the control means stores the data latch corresponding to a certain area in the area specified by the sector address. Saves the data in the fixed area, sets data indicating an erase state in the data latch circuit corresponding to the other area, and further erases the area specified by the sector address, and then 11. The semiconductor device according to claim 1, wherein write control is performed in accordance with data set in the data latch circuit. A semiconductor device according to any one of claims 1 to 11, a memory controller for controlling access to the semiconductor device, and an external interface circuit connected to the memory controller are mounted on a card board. A memory card characterized by 12. A data processing system comprising: the semiconductor device according to claim 1; a memory controller that controls access to the semiconductor device; and a processor that controls the memory controller. 8. A semiconductor device according to claim 7, and a control device for outputting a retry write command and a write address to the semiconductor device when an abnormal end of a write operation by the semiconductor device is detected. A data processing system. A plurality of semiconductor devices according to claim 8, and further, when the abnormal end of the write operation by the semiconductor device is detected, a recovery read command is output to the semiconductor device related to the abnormal end, and the recovery read command What is claimed is: 1. A data processing system comprising: a controller that takes in write data output from a supplied semiconductor device and controls writing of the taken write data into another semiconductor device.

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