JP3882916B2 - Charge pump circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charge pump circuit mounted on a semiconductor integrated circuit.
[0002]
[Prior art]
A nonvolatile semiconductor memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash memory supplies a high voltage to a word line when data is written to a memory cell. Generally, these semiconductor memories have a charge pump circuit in order to generate a high voltage. A semiconductor memory mounted on a portable device using a battery is required to have low power consumption, and it is necessary to reduce power consumption of a charge pump circuit.
[0003]
In an example of a charge pump circuit capable of reducing power consumption, a boosted voltage is generated by applying a clock having a predetermined frequency to a capacitive element connected to a boost node in the charge pump, and after the boosted voltage rises to a target voltage, The frequency is lowered (for example, see Patent Document 1).
[Patent Document 1]
JP-A-6-62562
[0004]
[Problems to be solved by the invention]
In the above-described example of the charge pump circuit, it is necessary to select one of two clocks according to the boosted voltage, and thus a circuit that generates a plurality of clocks having different frequencies is required. In order to avoid malfunction of the charge pump, it is necessary to prevent a hazard or the like from occurring when the clock frequency is switched. For this reason, a circuit for preventing the occurrence of a hazard or the like must be specially provided.
[0005]
An object of the present invention is to provide a charge pump circuit capable of reducing power consumption. Another object of the present invention is to provide a charge pump circuit capable of generating a predetermined boosted voltage without changing the clock frequency.
[0006]
[Means for Solving the Problems]
According to another aspect of the charge pump circuit of the present invention, the first clock generation circuit generates a plurality of first clocks having the same phase. The charge pump has a plurality of first capacitive elements each receiving a first clock at one end and connected to the first node at the other end, and uses a charge / discharge of the first capacitive element to generate a first boost at the output node. Generate voltage. The first clock generation circuit has a plurality of first clock output circuits corresponding to the first clocks. The first clock output circuit outputs each first clock with the first driving capability when the first boosted voltage is lower than the target voltage, and is weaker than the first driving capability when the first boosted voltage is higher than the target voltage. Each first clock is output with the driving ability.
[0007]
The first clock output circuit constantly outputs each first clock while changing the driving capability in accordance with the first boosted voltage. Thereby, the voltage at one end of the first capacitor element always changes simultaneously. For this reason, the first capacitive element is charged and discharged simultaneously. As a result, in the first capacitor element, one charge / discharge does not affect the other. Therefore, most of the charge charged / discharged in the first capacitor element can contribute to the generation of the first boosted voltage. Since the generation efficiency of the first boosted voltage is improved, for example, the capacity of the first capacitor element can be reduced. As a result, the power consumption of the charge pump circuit can be reduced.
[0008]
Since the first boosted voltage is adjusted by changing the driving capability of the first clock output circuit, a circuit for changing the frequency of the clock for charging and discharging the first capacitive element is not necessary.
Also, Each first clock output circuit has a first weak output circuit, a first strong output circuit, and a first synthesis node. The first weak output circuit always outputs the first weak clock with the second driving capability. The first strong output circuit outputs the first strong clock with the first driving capability when the first boosted voltage is lower than the target voltage. The first synthesis node is connected to the output of the first weak output circuit and the output of the first strong output circuit, and synthesizes the first weak clock and the first strong clock as each first clock.
[0009]
Each first clock output circuit always operates the first weak output circuit, and changes the driving capability depending on the operation / non-operation of the first strong output circuit. That is, the first clock output circuit can easily change the driving capability while always outputting each first clock.
According to another aspect of the charge pump circuit of the present invention, the flag circuit has a flag corresponding to each of the first strong output circuits. The flag circuit sequentially sets the flag when the first boosted voltage is lower than the target voltage, and sequentially resets the flag when the first boosted voltage is higher than the target voltage. Each first strong output circuit operates when the corresponding flag is set, and stops when the corresponding flag is reset.
[0010]
By providing the flag circuit, the number of first strong output circuits to be operated can be controlled with a simple circuit.
According to another aspect of the charge pump circuit of the present invention, the first voltage dividing circuit divides the first boosted voltage to generate the first divided voltage. The voltage comparison circuit compares the first divided voltage with the first reference voltage. The first clock output circuit outputs each first clock with the first driving capability when the voltage comparison circuit determines that the first divided voltage is lower than the first reference voltage, and the first divided voltage is When it is determined that the voltage is higher than one reference voltage, each first clock is output with the second driving capability.
[0011]
The magnitude relationship between the first boosted voltage and the target voltage is recognized by comparing the first divided voltage with the first reference voltage. Since it is not necessary to use the boosted voltage as the first reference voltage, the first reference voltage can be generated with a simple circuit. Therefore, the first reference voltage can be generated accurately and stably.
According to another aspect of the charge pump circuit of the present invention, the second voltage dividing circuit divides the voltage of the power supply line of the internal circuit formed in the semiconductor integrated circuit together with the charge pump circuit to generate the second divided voltage. The switch control circuit turns on the switch when the second divided voltage is lower than the second reference voltage, and connects the output node to the voltage supply line.
[0012]
Since the switch functions as a so-called regulator, the voltage of the voltage supply line can be stabilized at a constant voltage as compared with the case where the first boosted voltage is directly supplied to the internal circuit.
The magnitude relationship between the voltage of the voltage supply line and the target voltage is recognized by comparing the second divided voltage with the second reference voltage. Since it is not necessary to use the boosted voltage as the second reference voltage, the second reference voltage can be generated with a simple circuit. Therefore, the second reference voltage can be generated accurately and stably.
[0013]
According to another aspect of the charge pump circuit of the present invention, the first clock generation circuit generates a plurality of first clocks having the same phase. The second clock generation circuit generates a plurality of second clocks respectively corresponding to the first clock and having a phase opposite to that of the first clock. The charge pump receives a first clock at one end and a plurality of first capacitance elements whose other ends are connected to the first node, receives a second clock at one end, and is connected to the second node at the other end. A plurality of second capacitive elements and a booster switch connected between the first and second nodes and turned on during the effective period of the first clock. The charge pump generates a first boosted voltage at the first node using charge / discharge of the first capacitor element, and generates a first boosted voltage at the output node using charge / discharge of the first capacitor element and the second capacitor element. A higher second boosted voltage is generated. The first clock generation circuit has a plurality of first clock output circuits corresponding to the first clocks. The first clock output circuit outputs each first clock with the first driving capability when the second boosted voltage is lower than the target voltage, and is weaker than the first driving capability when the second boosted voltage is higher than the target voltage. Each first clock is output with the driving ability. The second clock generation circuit has a plurality of second clock output circuits corresponding to the second clocks. The second clock output circuit outputs each second clock with the first driving capability when the second boosted voltage is lower than the target voltage, and outputs with the second driving capability when the second boosted voltage is higher than the target voltage.
[0014]
The first clock output circuit constantly outputs each first clock while changing the driving capability in accordance with the second boosted voltage. Thereby, the voltage at one end of the first capacitor element always changes simultaneously. For this reason, the first capacitive element is charged and discharged simultaneously. As a result, in the first capacitor element, one charge / discharge does not affect the other. Therefore, most of the charge charged / discharged in the first capacitor element can contribute to the generation of the second boosted voltage. The second clock output circuit always outputs each second clock while changing the driving capability according to the second boosted voltage. Thereby, the voltage at one end of the second capacitor element always changes simultaneously. For this reason, the 2nd capacity element is charged and discharged simultaneously. As a result, in the second capacitor element, one charge / discharge does not affect the other. Therefore, most of the charge charged / discharged in the second capacitor element can contribute to the generation of the second boosted voltage. Since the generation efficiency of the second boosted voltage is improved, for example, the capacitances of the first and second capacitive elements can be reduced. As a result, the power consumption of the charge pump circuit can be reduced.
[0015]
Since the second boosted voltage is adjusted by changing the driving capability of the first and second clock output circuits, a circuit for changing the frequency of the clock for charging and discharging the first and second capacitive elements is not necessary.
Since the second boosted voltage is generated using the first boosted voltage and the charge / discharge of the second capacitor element, a high boosted voltage can be generated. Moreover, the predetermined boosted voltage can be generated with high accuracy by generating the second boosted voltage by a two-stage boosting operation.
[0016]
Also, Each first clock output circuit has a first weak output circuit, a first strong output circuit, and a first synthesis node. The first weak output circuit always outputs the first weak clock with the second driving capability. The first strong output circuit outputs the first strong clock with the first driving capability when the second boosted voltage is lower than the target voltage. The first synthesis node is connected to the output of the first weak output circuit and the output of the first strong output circuit, and synthesizes the first weak clock and the first strong clock as each first clock. Each second clock output circuit has a second weak output circuit, a second strong output circuit, and a second synthesis node. The second weak output circuit always outputs the second weak clock with the second driving capability. The second strong output circuit outputs the second strong clock with the first driving capability when the second boosted voltage is lower than the target voltage. The second synthesis node is connected to the output of the second weak output circuit and the output of the second strong output circuit, and synthesizes the second weak clock and the second strong clock as each second clock.
[0017]
Each first clock output circuit always operates the first weak output circuit, and changes the driving capability depending on the operation / non-operation of the first strong output circuit. That is, the first clock output circuit can easily change the driving capability while always outputting each first clock. Similarly, each second clock output circuit always operates the second weak output circuit, and changes the driving capability depending on the operation / non-operation of the second strong output circuit. That is, the second clock output circuit can easily change its driving capability while always outputting each second clock.
[0018]
According to another aspect of the charge pump circuit of the present invention, the flag circuit has a flag corresponding to each of the pair of first and second strong output circuits. The flag circuit sequentially sets the flag when the second boosted voltage is lower than the target voltage, and sequentially resets the flag when the second boosted voltage is higher than the target voltage. Each first and second strong output circuit operates when the corresponding flag is set, and stops when the corresponding flag is reset.
[0019]
By providing the flag circuit, the number of first and second strong output circuits to be operated can be controlled with a simple circuit.
According to another aspect of the charge pump circuit of the present invention, the first voltage dividing circuit divides the second boosted voltage to generate the first divided voltage. The voltage comparison circuit compares the first divided voltage with the first reference voltage. The first clock output circuit outputs each first clock with the first driving capability when the voltage comparison circuit determines that the first divided voltage is lower than the first reference voltage, and the first divided voltage is When it is determined that the voltage is higher than one reference voltage, each first clock is output with the second driving capability. The second clock output circuit outputs each second clock with the first driving capability when the voltage comparison circuit determines that the first divided voltage is lower than the first reference voltage, and the first divided voltage is When it is determined that the voltage is higher than one reference voltage, each second clock is output with the second driving capability.
[0020]
The magnitude relationship between the second boosted voltage and the target voltage is recognized by comparing the first divided voltage with the first reference voltage. Since it is not necessary to use the boosted voltage as the first reference voltage, the first reference voltage can be generated with a simple circuit. Therefore, the first reference voltage can be generated accurately and stably.
According to another aspect of the charge pump circuit of the present invention, the second voltage dividing circuit divides the voltage of the power supply line of the internal circuit formed in the semiconductor integrated circuit together with the charge pump circuit to generate the second divided voltage. The switch control circuit turns on the switch when the second divided voltage is lower than the second reference voltage, and connects the output node to the voltage supply line.
[0021]
Since the switch functions as a so-called regulator, the voltage of the voltage supply line can be stabilized at a constant voltage as compared with the case where the second boosted voltage is directly supplied to the internal circuit.
The magnitude relationship between the voltage of the voltage supply line and the target voltage is recognized by comparing the second divided voltage with the second reference voltage. Since it is not necessary to use the boosted voltage as the second reference voltage, the second reference voltage can be generated with a simple circuit. Therefore, the second reference voltage can be generated accurately and stably.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same reference numerals are used for the voltage of the voltage line and the voltage of the node, respectively. In the figure, a signal indicated by a thick line is composed of a plurality of bits.
FIG. 1 shows a first embodiment of the charge pump circuit of the present invention. This embodiment corresponds to claims 1 to 5. This charge pump circuit is formed in a flash memory, for example. The boosted voltage generated by the charge pump circuit is used for the program operation of the flash memory.
[0023]
The charge pump circuit 10 includes a first clock generation circuit CPG1, a charge pump CP1, a first voltage dividing circuit DV1, a voltage comparison circuit CMP1, a flag circuit FC1, a voltage comparison circuit CMP2 (switch control circuit), a switch SW, and a second voltage division. It has a circuit DV2.
The first clock generation circuit CPG1 generates two first clocks CK1 [0] and CK1 [1] having the same phase based on a first reference clock CK1B supplied from an oscillator (not shown). . Details of the first clock generation circuit CPG1 will be described with reference to FIG.
[0024]
The charge pump CP1 includes first capacitive elements C00 and C01 and nMOS transistors N00 and N01.
The first capacitive elements C00 and C01 receive the first clocks CK1 [0] and CK1 [1] at one end, respectively, and the other end is connected to the first node VN1. The capacitances of the first capacitive elements C00 and C01 are sufficiently larger than the capacitance (parasitic capacitance) of the capacitive element connected to the first node VN1.
[0025]
The gate and drain of the nMOS transistor N00 are both connected to the power supply line VCC. The source of the nMOS transistor N00 is connected to the first node VN1. Thus, the voltage at the first node VN1 does not become lower than the voltage obtained by subtracting the threshold voltage of the nMOS transistor N00 from the power supply voltage VCC.
The gate and drain of the nMOS transistor N01 are both connected to the first node VN1. The source of the nMOS transistor N01 is connected to the output node VO1 of the charge pump CP1. The threshold voltage of the nMOS transistor N01 is, for example, the same as the threshold voltage of the nMOS transistor N00. Thereby, the voltage (first boosted voltage) of the output node VO1 does not become lower than the voltage obtained by subtracting twice the threshold voltage of the nMOS transistor N00 from the power supply voltage VCC.
[0026]
When the first clock CK1 changes from a high level (power supply voltage VCC) to a low level (ground voltage VSS), the first node VN1 is stepped down by capacitive coupling. However, a current is replenished from the power supply line VCC to the first node VN1 via the nMOS transistor N00. Therefore, the first node VN1 becomes a voltage obtained by subtracting the threshold voltage of the nMOS transistor N00 from the power supply voltage VCC.
[0027]
When the first clock CK1 changes from low level to high level, the first node VN1 is boosted by capacitive coupling. At this time, the nMOS transistor N01 is turned on, and a current flows from the first node VN1 to the output node VO1. A capacitive element (not shown) connected to the output node VO1 is charged, and the first boosted voltage VO1 rises. Since the nMOS transistors N00 and N01 are so-called diode-connected, no current flows from the output node VO1 to the first node VN1. As these operations continue, the first boosted voltage VO1 gradually rises at every rising edge of the first clock CK1.
[0028]
The first voltage dividing circuit DV1 includes capacitive elements CD10 and CD11 connected in series via the node VD1 between the output node VO1 and the ground line VSS. The first voltage dividing circuit DV1 divides the first boosted voltage VO1 by the capacitance ratio of the capacitive elements CD10 and CD11, and generates the first divided voltage VD1 at the node VD1.
The voltage comparison circuit CMP1 is composed of a differential amplifier. The voltage comparison circuit CMP1 compares the first divided voltage VD1 with the reference voltage VREF (first reference voltage), and outputs the comparison result to the flag circuit FC1 as a comparison result signal RES1. When the voltage comparison circuit CMP1 determines that the first divided voltage VD1 is lower than the reference voltage VREF, the voltage comparison circuit CMP1 fixes the comparison result signal RES1 at a high level (power supply voltage VCC). When the voltage comparison circuit CMP1 determines that the first divided voltage VD1 is higher than the reference voltage VREF, the voltage comparison circuit CMP1 fixes the comparison result signal RES1 to a low level (ground voltage VSS). The magnitude relationship between the first boosted voltage VO1 and the target voltage is recognized by comparing the first divided voltage VD1 with the reference voltage VREF. For this reason, the boosted voltage need not be used for the reference voltage VREF.
[0029]
The flag circuit FC1 has flags F0 and F1 respectively corresponding to the first strong output circuits S1 of the first clock output circuits CO10 and CO11 described in FIG. The flag circuit FC1 outputs the logical values of the flags F0 and F1 to the first clock generation circuit CPG1 as 2-bit flag signals FLAG [0] and FLAG [1].
The flag circuit FC1 sequentially resets the flags F0 and F1 in a predetermined cycle (Tcyc described in FIG. 3) when the comparison result signal RES1 is at a low level. That is, when the comparison result signal RES1 changes from the high level to the low level, first, the flag signal FLAG [1] changes from the high level to the low level at a predetermined time interval Tcyc, and further, the predetermined time interval Tcyc increases. The flag signal FLAG [0] also changes from high level to low level.
[0030]
The flag circuit FC1 sequentially sets the flags F0 and F1 with a predetermined cycle Tcyc when the comparison result signal RES1 is at a high level. That is, when the comparison result signal RES1 changes from the low level to the high level, the flag signal FLAG [0] first changes from the low level to the high level at a predetermined time interval Tcyc, and further, the predetermined time interval Tcyc increases. The flag signal FLAG [1] also changes from a low level to a high level.
[0031]
The voltage comparison circuit CMP2 is composed of a differential amplifier. The voltage comparison circuit CMP2 compares a second divided voltage VD2 described later with a reference voltage VREF (second reference voltage), and outputs the comparison result to the switch SW as a comparison result signal RES2. When the voltage comparison circuit CMP2 determines that the second divided voltage VD2 is higher than the reference voltage VREF, the voltage comparison circuit CMP2 fixes the comparison result signal RES2 at a high level (power supply voltage VCC). When the voltage comparison circuit CMP2 determines that the second divided voltage VD2 is lower than the reference voltage VREF, the voltage comparison circuit CMP2 fixes the comparison result signal RES2 to a low level (ground voltage VSS). Since the voltage comparison circuit CMP2 receives the common reference voltage VREF as the comparison reference voltage with the voltage comparison circuit CMP1, the scale of the circuit that generates the comparison reference voltage is reduced.
[0032]
The switch SW is composed of a pMOS transistor. The drain and source of the switch SW are connected to the output node VO1 and the voltage supply line VPRG of the memory core CORE (internal circuit), respectively. The gate of the switch SW receives the comparison result signal RES2. The switch SW is turned on when the comparison result signal RES2 is at a low level (when the second divided voltage VD2 is lower than the reference voltage VREF).
[0033]
When the switch SW is turned on, a current flows from the output node VO1 to the voltage supply line VPRG, and the voltage of the voltage supply line VPRG rises until the comparison result signal RES2 changes to a high level. The voltage of the voltage supply line VPRG is supplied as the drain voltage of the memory cell formed in the memory core CORE. Since the switch SW functions as a so-called regulator, the voltage of the voltage supply line VPRG is stabilized at a constant voltage as compared with the case where the first boosted voltage VO1 is directly supplied to the memory core CORE.
[0034]
The second voltage dividing circuit DV2 includes capacitive elements CD20 and CD21 connected in series via the node VD2 between the voltage supply line VPRG and the ground line VSS. The second voltage dividing circuit DV2 divides the voltage of the voltage supply line VPRG by the capacitance ratio of the capacitive elements CD20 and CD21, and generates the second divided voltage VD2 at the node VD2.
FIG. 2 shows details of the first clock generation circuit CPG1 in the first embodiment.
[0035]
The first clock generation circuit CPG1 includes first clock output circuits CO10 and CO11 corresponding to the first clocks CK1 [0] and CK1 [1], respectively.
The first clock output circuit CO10 has a first weak output circuit W1, a first strong output circuit S1, and a first synthesis node ND1.
The first weak output circuit W1 has an output buffer BW composed of an inverter INVW and an inverter of the first transistor size. The inverter INVW outputs an inverted clock of the first reference clock CK1B to the output buffer BW. The output buffer BW inverts the inverted clock of the first reference clock CK1B and outputs it as the first weak clock CK1W. Thereby, the first weak output circuit W1 always outputs the first weak clock CK1W.
[0036]
The first strong output circuit S1 includes an inverter INVS, a NAND circuit NAS, a NOR circuit NRS, a second transistor-sized pMOS transistor PTS and an nMOS transistor NTS that constitute an output buffer. The second transistor size is larger than the first transistor size. The inverter INVS outputs the inverted logic of the flag signal FLAG [0] to the NOR circuit NRS. The NOR circuit NRS is activated when the inversion logic of the flag signal FLAG [0] is at a low level (when the flag signal FLAG [0] is at a high level), and the inversion clock of the first reference clock CK1B is used as an nMOS transistor. Output to NTS gate. The NAND circuit NAS is activated when the flag signal FLAG [0] is at a high level, and outputs an inverted clock of the first reference clock CK1B to the gate of the pMOS transistor PTS.
[0037]
The source of the pMOS transistor PTS and the source of the nMOS transistor NTS are connected to the power supply line VCC and the ground line VSS, respectively. The drain of the pMOS transistor PTS and the drain of the nMOS transistor NTS are both connected to the first synthesis node ND1. When the flag signal FLAG [0] is at a high level, the pMOS transistor PTS and the nMOS transistor NTS are alternately turned on in synchronization with the transition edge of the first reference clock CK1B to generate the first strong clock CK1S. That is, the first strong output circuit S1 has a driving capability (first driving capability) stronger than the driving capability (second driving capability) of the first weak output circuit W1 when the flag signal FLAG [0] is at a high level. The first strong clock CK1S is output.
[0038]
The first synthesis node ND1 is connected to the output of the first weak output circuit W1 and the output of the first strong output circuit S1, and uses the first weak clock CK1W and the first strong clock CK1S as the first clock CK1 [0]. Synthesize. Thereby, the first clock output circuit CO10 uses the first weak clock CK1W as the first clock CK1 [0] when the flag signal FALG [0] is at a low level (when the first boosted voltage VO1 is higher than the target voltage). When the flag signal FLAG [0] is at a high level (when the first boosted voltage VO1 is lower than the target voltage), a clock obtained by synthesizing the first weak clock CK1W and the first strong clock CK1S is the first clock CK1. Output as [0]. Since the first weak output circuit W1 and the first strong output circuit S1 commonly use the first reference clock CK1B, the first weak clock CK1W and the first strong clock CK1S have the same phase. For this reason, as will be described later, no through current is generated in the first clock generation circuit CPG1. As described above, the first clock output circuit CO10 always operates the first weak output circuit W1, and changes the driving capability depending on the operation / non-operation of the first strong output circuit S1.
[0039]
If the driving capability of the first weak output circuit W1 is too weak, the first clock CK1 [0] while the first strong output circuit S1 is stopped (when the flag signal FLAG [0] is low) is the same as floating. It becomes the state of. In this case, when the voltage of the first node VN1 of the charge pump CP1 changes, the voltage of the first composite node ND1 changes to a voltage higher than the power supply voltage VCC or a voltage (negative voltage) lower than the ground voltage VSS due to capacitive coupling. There is. When the first composite node ND1 becomes a voltage higher than the power supply voltage VCC, a forward current flows through a pn junction between the drain and the substrate of the pMOS transistor PTS in the first strong output circuit S1 (a forward bias condition occurs). . When the first composite node ND1 becomes lower than the ground voltage VSS, a forward current flows through the pn junction between the drain and the substrate of the nMOS transistor NTS of the first strong output circuit S1 (a forward bias condition occurs). .
[0040]
In order to prevent this, the first weak output circuit W1 is configured such that the pMOS transistor PTS of the first strong output circuit S1 and the pn junction of the nMOS transistor NTS are at the voltage of the first composite node ND1 while the first strong output circuit S1 is stopped. It is set to the minimum drive capacity that does not turn on due to a change. By setting the first weak output circuit W1 to such a minimum driving capability, the power consumption of the charge pump circuit 10 is reduced.
[0041]
The first clock output circuit CO11 operates in the same manner as the first clock output circuit CO10, receives the first reference clock CK1B and the flag signal FLAG [1], and outputs the first clock CK1 [1]. Since the configuration of the first clock output circuit CO11 is the same as the configuration of the first clock output circuit CO10, detailed description thereof is omitted.
Since the first clock output circuits CO10 and CO11 have the same circuit configuration and use the first reference clock CK1B in common, the first clocks CK1 [0] and CK1 [1] have the same phase.
[0042]
FIG. 3 shows an outline of the operation of the first embodiment.
When the first boosted voltage VO1 becomes higher than the target voltage VT at time T1, the voltage comparison circuit CMP1 changes the comparison result signal RES1 from high level to low level.
At time T2 when a predetermined time interval Tcyc has elapsed from the falling edge of the comparison result signal RES1, the flag circuit FC1 resets the flag F1. For this reason, the flag signal FLAG [1] changes from a high level to a low level. The first strong output circuit S1 of the first clock output circuit CO11 stops in response to the falling edge of the flag signal FLAG [1]. That is, the first clock output circuit CO11 outputs the first weak clock CK1W as the first clock CK1 [1]. As a result, the rising speed of the first boosted voltage VO1 decreases.
[0043]
At time T3 when a predetermined time interval Tcyc has elapsed from the falling edge of the flag signal FLAG [1], the flag circuit FC1 resets the flag F0. For this reason, the flag signal FLAG [0] changes from a high level to a low level. The first strong output circuit S1 of the first clock output circuit CO10 stops in response to the falling edge of the flag signal FLAG [0]. That is, the first clock output circuit CO10 outputs the first weak clock CK1W as the first clock CK1 [0]. As a result, the first boosted voltage VO1 starts to fall.
[0044]
When the first boosted voltage VO1 becomes lower than the target voltage VT at time T4, the voltage comparison circuit CMP1 changes the comparison result signal RES1 from the low level to the high level.
At time T5 when a predetermined time interval Tcyc has elapsed from the rising edge of the comparison result signal RES1, the flag circuit FC1 sets the flag F0. For this reason, the flag signal FLAG [0] changes from a low level to a high level. The first strong output circuit S1 of the first clock output circuit CO10 starts operation in response to the rising edge of the flag signal FLAG [0]. That is, the first clock output circuit CO10 outputs a clock obtained by synthesizing the first weak clock CK1W and the first strong clock CK1S as the first clock CK1 [0]. As a result, the first boosted voltage VO1 changes from falling to rising.
[0045]
At time T6 when a predetermined time interval Tcyc has elapsed from the rising edge of the flag signal FLAG [0], the flag circuit FC1 sets the flag F1. For this reason, the flag signal FLAG [1] changes from a low level to a high level. The first strong output circuit S1 of the first clock output circuit CO11 starts operation in response to the rising edge of the flag signal FLAG [1]. That is, the first clock output circuit CO11 outputs a clock obtained by synthesizing the first weak clock CK1W and the first strong clock CK1S as the first clock CK1 [1]. As a result, the rising speed of the first boosted voltage increases.
[0046]
As described above, in the charge pump circuit 10, the first clock output circuits CO10 and CO11 constantly change the first clocks CK1 [0] and CK1 [1], respectively, while changing the driving capability according to the first boosted voltage VO1. Output. As a result, the voltage at one end of the first capacitive elements C00 and C01 (on the side receiving the first clocks CK1 [0] and CK1 [1]) changes simultaneously. For this reason, the first capacitive elements C00 and C01 are charged and discharged simultaneously. As a result, in the first capacitance elements C00 and C01, one charge / discharge does not affect the other. Therefore, most of the charges charged and discharged in the first capacitive elements C00 and C01 contribute to the generation of the first boosted voltage VO1. In order to improve the generation efficiency of the first boosted voltage VO1, for example, the capacitances of the first capacitive elements C00 and C01 are set small. As a result, the power consumption of the charge pump circuit 10 is reduced.
[0047]
In addition, by using the flag signal FLAG output from the flag circuit FC1, the number of first strong output circuits S1 to be operated is controlled by a simple circuit.
Before the present invention, the inventor determines that at least one of the first clocks CK1 [0] and CK1 [1] is the power supply voltage VCC and the ground when the first boosted voltage VO1 is higher than the target voltage VT. We studied to suppress the generation of the first boosted voltage VO1 by setting the voltage VSS or floating.
[0048]
When only the first clock CK1 [1] is fixed to the power supply voltage VCC or the ground voltage when the first boosted voltage VO1 is higher than the target voltage VT, the first capacitive element C01 that receives the first clock CK1 [1] This is a load for the boosting operation of the first node VN1 by one clock CK1 [0]. For this reason, the current consumption of the first clock CK1 [0] increases. As a result, the effect of reducing power consumption is reduced.
[0049]
When only the first clock CK1 [1] is floated when the first boosted voltage VO1 is higher than the target voltage VT, the voltage of the first node VN1 of the charge pump CP1 changes, so that the first clock CK1 [1] May be higher than the power supply voltage VCC or lower than the ground voltage VSS (negative voltage) due to capacitive coupling. At this time, the pn junction of the output buffer that outputs the first clock CK1 [1] is turned on, and the forward current flows.
[0050]
On the other hand, in the present invention, when the first boosted voltage VO1 is higher than the target voltage VT, the first clock CK1 [1] is output with the second driving capability. There is no load for the boosting operation of the first node VN1 by the clock CK1 [0]. The first weak output circuit W1 of the first clock output circuit CO10 that outputs the first clock CK1 [1] is the pn of the pMOS transistor PTS and the nMOS transistor NTS in the first strong output circuit S1 of the first clock output circuit CO10. Since the minimum driving capability at which the junction is not turned on is set, the first clock CK1 [1] is not affected by the voltage change of the first node VN1 of the charge pump CP1. For this reason, the power consumption of the charge pump circuit 10 is significantly reduced.
[0051]
As described above, in the first embodiment, the following effects can be obtained.
Since the first clock output circuits CO10 and CO11 always output the first clocks CK1 [0] and CK1 [1], respectively, the first capacitive elements C00 and C01 are simultaneously charged and discharged. For this reason, in the first capacitive elements C00 and C01, one charge / discharge does not affect the other. Therefore, most of the charges charged and discharged in the first capacitive elements C00 and C01 can contribute to the generation of the first boosted voltage VO1. Since the generation efficiency of the first boosted voltage VO1 is improved, for example, the capacitance of the first capacitor elements C00 and C01 can be reduced. As a result, the power consumption of the charge pump circuit 10 can be reduced.
[0052]
Since the first boosted voltage VO1 is adjusted by changing the driving capability of the first clock output circuits CO10 and CO11, a circuit for changing the frequency of the clock for charging and discharging the first capacitive elements C00 and C01 is not necessary.
The first clock output circuits CO10 and CO11 always operate the first weak output circuit W1, and change the driving capability depending on the operation / non-operation of the first strong output circuit S1. That is, the first clock output circuits CO10 and CO11 can easily change their driving capabilities while outputting the first clocks CK1 [0] and CK1 [1], respectively.
[0053]
By using the flag signal FLAG output from the flag circuit FC1, the number of first strong output circuits S1 to be operated can be controlled with a simple circuit.
The magnitude relationship between the first boosted voltage VO1 and the target voltage is recognized by comparing the first divided voltage VD1 with the reference voltage VREF. The magnitude relationship between the voltage of the voltage supply line VPRG and the target voltage is recognized by comparing the second divided voltage VD2 with the reference voltage VREF. Since it is not necessary to use the boosted voltage as the reference voltage VREF, the reference voltage VREF can be generated with a simple circuit. Therefore, the reference voltage VREF can be generated accurately and stably.
[0054]
Since the voltage comparison circuit CMP2 receives the reference voltage VREF common to the voltage comparison circuit CMP1 as a comparison reference voltage, the scale of the circuit that generates the comparison reference voltage can be reduced.
By providing the switch SW between the output node VO1 of the charge pump CP1 and the voltage supply line VPRG, the voltage of the voltage supply line VPRG is kept constant compared to the case where the first boosted voltage VO1 is directly supplied to the memory core CORE. The voltage can be stabilized.
[0055]
When the corresponding first strong output circuit S1 is stopped, the first weak output circuit W1 causes the pn junction of the corresponding first strong output circuit S1 and the pn junction of the nMOS transistor NTS to change due to the voltage change of the first composite node ND1. The minimum drive capacity that does not turn on is set. Therefore, it is possible to prevent a forward current from flowing through the pn junctions of the pMOS transistor PTS and the nMOS transistor NTS.
[0056]
FIG. 4 shows a second embodiment of the charge pump circuit of the present invention. This embodiment corresponds to claims 6, 7 and 9. This charge pump circuit is formed in the flash memory, for example, as in the first embodiment. In addition, the same code | symbol is attached | subjected about the element same as the element demonstrated in 1st Embodiment, and detailed description is abbreviate | omitted.
[0057]
The charge pump circuit 20 includes a first clock generation circuit CPG1, a second clock generation circuit CPG2, a charge pump CP2, a first voltage dividing circuit DV3, a voltage comparison circuit CMP1, nMOS transistors NT0, NT1, NT2, a pMOS transistor PT0, and a latch circuit. It has LC, inverters INV0 and INV1, and a NAND circuit NA.
The first clock generation circuit CPG1 receives permission signals EN0 and EN1 instead of the flag signals FALG [0] and FLAG [1] of the first embodiment. The enable signal EN0 changes from the low level to the high level during the program operation of the flash memory. Details of the first clock generation circuit CPG1 will be described with reference to FIG.
[0058]
The second clock generation circuit CPG2 corresponds to the first clock CK1 (CK1 [0], CK1 [1]) based on the second reference clock CK2B supplied from the oscillator (not shown), and the first clock Two second clocks CK2 (CK2 [0], CK2 [1]) having phases opposite to those of CK1 are generated. Details of the second clock generation circuit CPG2 will be described with reference to FIG. The first reference clock CK1B and the second reference clock CK2B have one rising change from the other falling change in order to prevent the valid periods (high level periods) from overlapping each other due to wiring delay or the like. Occurs at predetermined time intervals. For this reason, the first clock CK1 and the second clock CK2 do not overlap each other in the high level period. As a result, malfunction of the charge pump CP2 is prevented.
[0059]
The charge pump CP2 generates the second boosted voltage VO2 at the output node VO2 using the boosting operation by the first clock CK1 and the second clock CK2. Details of the charge pump CP2 will be described with reference to FIG.
The first voltage dividing circuit DV3 includes capacitive elements CD30 and CD31 connected in series via the node VD3 between the output node VO2 and the ground line VSS. The first voltage dividing circuit DV3 divides the second boosted voltage VO2 by the capacitance ratio of the capacitive elements CD30 and CD31, and generates the first divided voltage VD3 at the node VD3.
[0060]
The drain and source of the nMOS transistor NT0 are connected to the output node VO2 and the ground line VSS, respectively. The comparison result signal RES1 output from the voltage comparison circuit CMP1 is applied to the gate of the nMOS transistor NT0. When the comparison result signal RES1 is at a high level (when the first divided voltage VD3 is higher than the reference voltage VREF), the nMOS transistor NT0 is turned on, so that a current flows from the output node VO2 to the ground line VSS. This prevents the second boosted voltage VO2 from rising more than necessary.
[0061]
The source and drain of the pMOS transistor PT0 are connected to the power supply line VCC and the drain of the nMOS transistor NT1, respectively. The gate of the pMOS transistor PT0 receives the enable signal EN0. The source and drain of the nMOS transistor NT1 are connected to the drain of the nMOS transistor NT2 and the drain of the pMOS transistor PT0, respectively. The gate of the nMOS transistor NT1 receives the comparison result signal RES1. The source and drain of the nMOS transistor NT2 are connected to the ground line VSS and the source of the nMOS transistor NT1, respectively. The gate of the nMOS transistor NT2 receives the enable signal EN0. The latch circuit LC includes inverters INVL0 and INVL1 connected in a ring shape. The input of the inverter INVL0 and the output of the inverter INVL1 are connected to the drain of the pMOS transistor PT0 and the drain of the nMOS transistor NT1. For this reason, even when both the pMOS transistor PT0 and the nMOS transistor NT1 are turned off, the latch output signal LO output from the latch circuit LC is fixed to the power supply voltage VCC or the ground voltage VSS.
[0062]
The inverter INV0 outputs the inverted logic of the latch output signal LO to the NAND circuit NA. The NAND circuit NA is activated when the enable signal EN0 is at a high level (during the program operation of the flash memory), and outputs the same logic as the latch output signal LO. The inverter INV1 inverts the output logic of the NAND circuit NA and outputs it as the enable signal EN1 to the first clock generation circuit CPG1 and the second clock generation circuit CPG2.
[0063]
When the enable signal EN0 is at a low level, the pMOS transistor PT0 is turned on and the nMOS transistor NT2 is turned off. When the enable signal EN0 is at a low level, the boosting capability of the charge pump CP2 decreases, and the first divided voltage VD3 becomes lower than the reference voltage VREF. For this reason, the comparison result signal RES1 is fixed to the ground voltage VSS. As a result, the nMOS transistor NT1 is turned off. Therefore, when the enable signal EN0 is at a low level, the input of the latch circuit LC is fixed at a high level.
[0064]
When a program command is supplied to the flash memory and the enable signal EN0 changes from low level to high level, the pMOS transistor PT0 is turned off. The latch output signal LO remains fixed at a low level by the latch circuit LC. For this reason, the enable signal EN1 changes from the low level to the high level in synchronization with the enable signal EN0. That is, the charge pump CP2 starts a boost operation.
[0065]
When the voltage of the second boosted voltage VO2 rises by the boosting operation of the charge pump CP2 and the first divided voltage VD3 becomes higher than the reference voltage VREF, the comparison result signal RES1 is fixed to the power supply voltage VCC. Therefore, the nMOS transistor NT1 is turned on. Accordingly, the latch output signal LO changes from a low level to a high level. As a result, the enable signal EN1 changes from the high level to the low level.
[0066]
FIG. 5 shows details of the first clock generation circuit CPG1 in the second embodiment.
The first clock generation circuit CPG1 includes first clock output circuits CO10 and CO11.
The first clock output circuit CO10 outputs the first weak clock CK1W as the first clock CK1 [0] when the enable signal EN0 is at a low level, and the first weak clock CK1W when the enable signal EN0 is at a high level. A clock obtained by synthesizing the first strong clock CK1S is output as the first clock CK1 [0]. The first clock output circuit CO10 changes the driving capability by constantly operating the first weak output circuit W1 and operating or stopping the first strong output circuit S1 according to the operating state of the flash memory.
[0067]
The first clock output circuit CO11 operates in the same manner as the first clock output circuit CO10, receives the first reference clock CK1B and the enable signal EN1, and outputs the first clock CK1 [1]. The first clock output circuit CO11 changes the driving capability by always operating the first weak output circuit W1 and operating or stopping the first strong output circuit S1 according to the operating state of the flash memory and the second boosted voltage VO2. To do.
[0068]
FIG. 6 shows details of the second clock generation circuit CPG2 in the second embodiment.
The second clock generation circuit CPG2 has the same circuit configuration as the first clock generation circuit CPG1 shown in FIG. That is, the second clock generation circuit CPG2 includes second clock output circuits CO20 and CO21 corresponding to the second clocks CK2 [0] and CK2 [1], respectively.
[0069]
The second clock output circuits CO20 and CO21 have a second weak output circuit W2, a second strong output circuit S2, and a second synthesis node ND2.
The second synthesis node ND2 is connected to the output of the second weak output circuit W2 and the output of the second strong output circuit S2, and synthesizes the second weak clock CK2W and the second strong clock CK2S as the second clock CK2.
[0070]
Since the operation of the second clock generation circuit CPG2 with respect to the second clock CK2 is the same as the operation of the first clock generation circuit CPG1 with respect to the first clock CK1, detailed description thereof is omitted.
FIG. 7 shows details of the charge pump CP2 in the second embodiment.
The charge pump CP2 includes first capacitive elements C10 and C11, second capacitive elements C20 and C21, capacitive elements C14, C24, C30 and C31, nMOS transistors N10 to N12, N20 to 22, N30 to N32 and N40. Yes. For example, the nMOS transistors N10 to N12, N20 to 22, N30 to N32, and N40 have a threshold voltage lower than that of the nMOS transistors constituting the logic circuit.
[0071]
The first capacitive elements C10 and C11 receive the first clocks CK1 [0] and CK1 [1] at one end, respectively, and the other end is connected to the first node P1. The capacitances of the first capacitive elements C10 and C11 are sufficiently larger than the capacitance (parasitic capacitance) of the capacitive element connected to the first node P1.
The capacitive element C14 receives the clock CK2A at one end and is connected to the node G1 at the other end. The capacitance of the capacitive element C14 is sufficiently larger than the capacitance (parasitic capacitance) of the capacitive element connected to the node G1. The clock CK2A changes from a low level to a high level in synchronization with the rising edge of the second clock CK2, and changes from a high level to a low level at a predetermined time interval from the falling edge of the second clock CK2. The clock CK2A is supplied from the oscillator in the same manner as the second reference clock CK2B.
[0072]
The gate, drain, and source of the nMOS transistor N10 are connected to the first node P1, the power supply line VCC, and the node G1, respectively. The gate, drain and source of the nMOS transistor N11 are connected to the node G1, the power supply line VCC, and the first node P1, respectively. The gate, drain, and source of the nMOS transistor N12 are connected to the power supply line VCC, the power supply line VCC, and the first node P1, respectively. As a result, the first node P1 does not become lower than the voltage obtained by subtracting the threshold voltage of the nMOS transistor N12 from the power supply voltage VCC.
[0073]
The second capacitive elements C20 and C21 receive the second clocks CK2 [0] and CK2 [1] at one end, respectively, and the other end is connected to the second node P2. The capacitances of the second capacitive elements C20 and C21 are sufficiently larger than the capacitance (parasitic capacitance) of the capacitive element connected to the second node P2.
The capacitive element C24 receives the clock CK1A at one end and is connected to the node G2 at the other end. The capacitance of the capacitive element C24 is sufficiently larger than the capacitance (parasitic capacitance) of the capacitive element connected to the node G2. The clock CK1A changes from a low level to a high level in synchronization with the rising edge of the first clock CK1, and changes from a high level to a low level at a predetermined time interval from the falling edge of the first clock CK1. The clock CK1A is supplied from an oscillator in the same manner as the first reference clock CK1B.
[0074]
The gate, drain, and source of the nMOS transistor N20 are connected to the second node P2, the first node P1, and the node G2, respectively. The gate, drain and source of the nMOS transistor N21 (boost switch) are connected to the node G2, the first node P1 and the second node P2, respectively. The gate, drain, and source of the nMOS transistor N22 are connected to the power supply line VCC, the power supply line VCC, and the second node P2, respectively. Thereby, the second node P2 does not become lower than the voltage obtained by subtracting the threshold voltage of the nMOS transistor N22 from the power supply voltage VCC.
[0075]
The capacitive element C30 receives the first clock CK1 [0], and the other end is connected to the node P3. The capacitance of the capacitive element C30 is sufficiently larger than the capacitance (parasitic capacitance) of the capacitive element connected to the node P3.
The capacitive element C34 receives the clock CK2A at one end and is connected to the node G3 at the other end. The capacitance of the capacitive element C34 is sufficiently larger than the capacitance (parasitic capacitance) of the capacitive element connected to the node G3.
[0076]
The gate, drain, and source of the nMOS transistor N30 are connected to the node P3, the second node P2, and the node G3, respectively. The gate, drain, and source of the nMOS transistor N31 are connected to the node G3, the second node P2, and the node P3, respectively. The gate, drain, and source of the nMOS transistor N32 are connected to the power supply line VCC, the power supply line VCC, and the node P3, respectively. Thereby, the node P3 does not become lower than the voltage obtained by subtracting the threshold voltage of the nMOS transistor N32 from the power supply voltage VCC.
[0077]
The gate, drain, and source of the nMOS transistor N40 are connected to the node G3, the second node P2, and the output node VO2, respectively.
FIG. 8 shows the operation of the charge pump CP2 in the second embodiment.
First, when the first clocks CK1 [0] and CK1 [1] change from a high level to a low level, the first node P1 is stepped down by the capacitive coupling of the first capacitive elements C10 and C11 (FIG. 8A). )). For this reason, the nMOS transistor N10 is turned off. Similarly, the node P3 is stepped down by the capacitive coupling of the capacitive element C30 (FIG. 8 (b)). For this reason, the nMOS transistor N30 is turned off. Thereafter, when the clock CK1A changes from the high level to the low level, the node G2 is stepped down by the capacitive coupling of the capacitive element C24 (FIG. 8 (c)). For this reason, the nMOS transistor N21 is turned off.
[0078]
Next, when the second clocks CK2 [0] and CK2 [1] change from the low level to the high level, the second node P2 is boosted by the capacitive coupling of the second capacitive elements C20 and C21 (FIG. 8 ( d)). For this reason, the nMOS transistor N20 is turned on, and a current is replenished from the first node P1 to the node G2. When the clock CK2A changes from a low level to a high level in synchronization with the rising edges of the second clocks CK2 [0] and CK2 [1], the node G1 is boosted by capacitive coupling of the capacitive element C14 (FIG. 8 (e)). For this reason, the nMOS transistor N11 is turned on, and a current is replenished from the power supply line VCC to the first node P1. Similarly, the node G3 is boosted by the capacitive coupling of the capacitive element C34 due to the rising change of the clock CK2A (FIG. 8 (f)). For this reason, the nMOS transistor N31 is turned on, and a current is replenished from the second node P2 to the node P3. The nMOS transistor N40 is also turned on by boosting the node G3, and a current is replenished from the second node P2 to the output node VO2. That is, the second boosted voltage VO2 is generated at the output node VO2 (FIG. 8 (g)).
[0079]
Next, when the second clocks CK2 [0] and CK2 [1] change from the high level to the low level, the second node P2 is stepped down by the capacitive coupling of the second capacitive elements C20 and C21 (FIG. 8 ( h)). For this reason, the nMOS transistor N20 is turned off. Thereafter, when the clock CK2A changes from the high level to the low level, the node G1 is stepped down by the capacitive coupling of the capacitive element C14 (FIG. 8 (i)). For this reason, the nMOS transistor N11 is turned off. Similarly, the node G3 is stepped down by the capacitive coupling of the capacitive element C34 due to the falling change of the clock CK2A (FIG. 8 (j)). For this reason, the nMOS transistor N31 is turned off. The second boosted voltage VO2 does not drop because the nMOS transistor N40 is also turned off by stepping down the node G3, and the voltage generated in FIG. 8 (g) is held.
[0080]
Next, when the first clocks CK1 [0] and CK1 [1] change from low level to high level, the first node P1 is boosted by capacitive coupling of the first capacitive elements C10 and C11 (FIG. 8 ( k)). Therefore, the nMOS transistor N10 is turned on, and a current is replenished from the power supply voltage VCC to the node G1. Similarly, the node P3 is boosted by capacitive coupling of the capacitive element C30 (FIG. 8 (l)). For this reason, the nMOS transistor N30 is turned on, and a current is replenished from the second node P2 to the node G3.
[0081]
When the clock CK1A changes from the low level to the high level in synchronization with the rising edge of the first clock CK1, the node G2 is boosted by the capacitive coupling of the capacitive element C24 (FIG. 8 (m)). For this reason, the nMOS transistor N21 is turned on, and a current is replenished from the first node P1 to the second node P2.
When the operation as described above is repeated, the first node P1 is stepped down at every falling edge of the first clocks CK1 [0] and CK1 [1] (FIG. 8 (n)). As the nMOS transistor N11 is turned on by boosting the node G1, a current is replenished from the power supply line VCC to the first node P1. For this reason, the voltage of the first node P1 becomes higher than that before one cycle. At this time, the nMOS transistor N20 is also turned on, so that a current is replenished from the first node P1 to the node G2. For this reason, the voltage of the node G2 is also higher than before one cycle.
[0082]
The node P3 is stepped down at each falling edge of the first clocks CK1 [0] and CK1 [1] (FIG. 8 (o)). When the nMOS transistor N31 is turned on by boosting the node G3, a current is replenished from the second node P2 to the node P3. For this reason, the voltage of the node P3 becomes higher than that before one cycle.
The second node P2 is stepped down at each falling edge of the second clocks CK2 [0] and CK2 [1] (FIG. 8 (p)). When the nMOS transistor N21 is turned on by boosting the node G2, a current is replenished from the first node P1 to the second node P2. For this reason, the voltage of the second node P2 becomes higher than that before one cycle. At this time, the nMOS transistor N30 is also turned on, so that a current is replenished from the second node P2 to the node G3. For this reason, the voltage of the node G3 is also higher than before one cycle.
[0083]
Therefore, by repeating the operations shown in FIGS. 8A to 8M, the second boosted voltage VO2 gradually rises at every rising edge of the second clock CK2 and the second clock CK2A.
As described above, also in the second embodiment, the same effect as in the first embodiment can be obtained. Furthermore, since the second boosted voltage VO2 is generated using the first boosted voltage (the voltage at the first node P1) and the charge / discharge of the second capacitive elements C20 and C21, a high boosted voltage can be generated. By generating the second boosted voltage VO2 by a two-stage boosting operation, a predetermined boosted voltage can be generated with high accuracy.
[0084]
Since the first clock CK1 and the second clock CK2 do not overlap each other in the high level period, malfunction of the charge pump CP2 can be prevented.
FIG. 9 shows a third embodiment of the charge pump circuit of the present invention. This embodiment corresponds to claims 6 to 10. This charge pump circuit is formed in the flash memory, for example, as in the first embodiment. In addition, the same code | symbol is attached | subjected about the element same as the element demonstrated in 1st and 2nd embodiment, and detailed description is abbreviate | omitted.
[0085]
The charge pump circuit 10 includes a first clock generation circuit CPG1a, a second clock generation circuit CPG2a, a charge pump CP2a, a first voltage dividing circuit DV4, a voltage comparison circuit CMP1, a flag circuit FC1a, a voltage comparison circuit CMP2 (switch control circuit), The switch SW and the second voltage dividing circuit DV5 are provided.
The first voltage dividing circuit DV4 includes capacitive elements CD40 and CD41 connected in series via the node VD4 between the output node VO2a and the ground line VSS. The first voltage dividing circuit DV4 divides the second boosted voltage VO2a (voltage of the output node VO2a) by the capacitance ratio of the capacitive elements CD40 and CD41, and generates the first divided voltage VD4 at the node VD4.
[0086]
The flag circuit FC1a is configured by adding flags F2 and F3 to the flag circuit FC1 of the first embodiment. Other configurations are the same as those of the flag circuit FC1 of the first embodiment. The flags F0 to F3 of the flag circuit FC1a are the first strong output circuit S1 of the first clock output circuits CO10 to CO13 described in FIG. 10 and the second strong output circuit of the second clock output circuits CO20 to CO23 described in FIG. Corresponds to each pair of S2. The flag circuit FC1a outputs the logical values of the flags F0 to F3 as the 4-bit flag signal FLAG to the first clock generation circuit CPG1a and the second clock generation circuit CPG2a, respectively.
[0087]
The flag circuit FC1a sequentially resets the flags F0 to F3 at a predetermined cycle Tcyc when the comparison result signal RES1 output from the voltage comparison circuit CMP1 is at a low level. That is, when the comparison result signal RES1 changes from the high level to the low level, the flag signal FLAG sequentially changes from the flag signal FLAG [3] from the high level to the low level at a predetermined time interval Tcyc.
[0088]
The flag circuit FC1a sequentially sets the flags F0 to F3 at a predetermined cycle Tcyc when the comparison result signal RES1 is at a high level. That is, when the comparison result signal RES1 changes from the low level to the high level, the flag signal FLAG sequentially changes from the low level to the high level at a predetermined time interval Tcyc from the flag signal FLAG [0].
The second voltage dividing circuit DV5 includes capacitive elements CD50 and CD51 connected in series via the node VD5 between the voltage supply line VPRG of the memory core CORE and the ground line VSS. The second voltage dividing circuit DV5 divides the voltage of the voltage supply line VPRG by the capacitance ratio of the capacitive elements CD50 and CD51, and generates a second divided voltage VD5 at the node VD5.
[0089]
FIG. 10 shows details of the first clock generation circuit CPG1a in the third embodiment.
The first clock generation circuit CPG1a is configured by adding first clock output circuits CO12 and CO13 to the first clock generation circuit CPG1 of the first embodiment. The first clock output circuits CO10 to CO13 receive the first reference clock CK1B and the flag signals FLAG [0] to FLAG [3], respectively, and output the first clocks CK1 [0] to CK1 [3], respectively. Since the configuration and operation of the first clock output circuits CO12 and CO13 are the same as the configuration and operation of the first clock output circuit CO10, detailed description thereof is omitted.
[0090]
FIG. 11 shows details of the second clock generation circuit CPG2a in the third embodiment.
The second clock generation circuit CPG2a is configured by adding second clock output circuits CO22 and CO23 to the second clock generation circuit CPG2 of the second embodiment. The second clock output circuits CO20 to CO23 receive the second reference clock CK2B and the flag signals FLAG [0] to FLAG [3], respectively, and output the second clocks CK2 [0] to CK2 [3], respectively. Since the configuration and operation of the second clock output circuits CO22 and CO23 are the same as the configuration and operation of the second clock output circuit CO20, detailed description thereof is omitted.
[0091]
FIG. 12 shows details of the charge pump CP2a in the third embodiment. The charge pump CP2a is configured by adding first capacitance elements C12 and C13 and second capacitance elements C22 and C23 to the charge pump CP2 of the second embodiment. Other configurations are the same as those of the charge pump CP2 of the second embodiment.
[0092]
The first capacitive elements C12 and C13 have one end receiving the first clocks CK1 [2] and CK1 [3] and the other end connected to the first node P1. That is, the first capacitive elements C10 to C13 are connected in parallel to the first node P1. The capacitances of the first capacitive elements C12 and C13 are sufficiently larger than the capacitance (parasitic capacitance) of the capacitive element connected to the first node P1. The first capacitive elements C12 and C13 operate in the same manner as the first capacitive elements C10 and C11.
[0093]
One end of each of the second capacitive elements C22 and C23 receives the second clocks CK2 [2] and CK2 [3], and the other end is connected to the second node P2. That is, the second capacitive elements C20 to C23 are connected in parallel to the second node P2. The capacitances of the second capacitive elements C22 and C23 are sufficiently larger than the capacitance (parasitic capacitance) of the capacitive element connected to the second node P2. The second capacitive elements C22 and C23 operate in the same manner as the second capacitive elements C20 and C21.
[0094]
Since the operation of the charge pump CP2a is the same as the operation of the charge pump CP2 of the second embodiment, detailed description thereof is omitted. However, since the number of the first capacitive elements connected to the first node P1 and the number of the second capacitive elements connected to the second node P2 are increased, the second boosted voltage VO2a is the same as that of the second embodiment. Compared to the charge pump CP2, it rises to the target voltage in a short time.
[0095]
As described above, also in the third embodiment, the same effect as in the first and second embodiments can be obtained.
Note that. In the first to third embodiments described above, examples in which the present invention is applied to a flash memory have been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to other semiconductor devices that use a boosted voltage.
[0096]
In the first to third embodiments described above, the example in which the first or second divided voltage is generated using the capacitive element has been described. The present invention is not limited to such an embodiment. For example, the first or second divided voltage may be generated using a resistance element.
The invention described in the above embodiments is organized and disclosed as an appendix.
(Supplementary Note 1) A first clock generation circuit that generates a plurality of first clocks having the same phase, and
Each of the first capacitors receives a first clock at one end, and has a plurality of first capacitors connected to the first node at the other end. A first boosted voltage is applied to an output node by using charge / discharge of the first capacitor. A charge pump for generating,
The first clock generation circuit outputs the first clocks with a first driving capability when the first boosted voltage is lower than a target voltage, and the first clock generation circuit outputs the first clock when the first boosted voltage is higher than the target voltage. A charge pump circuit comprising a plurality of first clock output circuits for outputting each of the first clocks with a second driving capability that is weaker than the driving capability, corresponding to each of the first clocks.
[0097]
(Appendix 2) In the charge pump circuit described in Appendix 1,
Each of the first clock output circuits includes:
A first weak output circuit that constantly outputs a first weak clock with the second driving capability;
A first strong output circuit that outputs a first strong clock when the first boost voltage is lower than the target voltage with the first driving capability;
A first combining node connected to the output of the first weak output circuit and the output of the first strong output circuit and configured to combine the first weak clock and the first strong clock as the first clocks; A charge pump circuit.
[0098]
(Appendix 3) In the charge pump circuit described in Appendix 2,
A flag corresponding to each of the first strong output circuits; the flag is sequentially set when the first boosted voltage is lower than the target voltage; and the flag is set when the first boosted voltage is higher than the target voltage. Equipped with a flag circuit that sequentially resets
Each of the first strong output circuits operates when a corresponding flag is set, and stops when the corresponding flag is reset.
[0099]
(Appendix 4) In the charge pump circuit described in Appendix 2,
Each of the first weak output circuits includes an output buffer having a first transistor size for outputting the first weak clock,
Each of the first strong output circuits includes an output buffer having a second transistor size larger than the first transistor size for outputting the first strong clock.
[0100]
(Appendix 5) In the charge pump circuit described in Appendix 4,
The output buffer of each of the first strong output circuits includes a pMOS transistor and an nMOS transistor each having a drain connected to the first synthesis node,
Each of the first weak output circuits is set to a driving capability in which the pn junction of the output buffer of the corresponding first strong output circuit is not turned on due to the voltage change of the first composite node while the corresponding first strong output circuit is stopped. A charge pump circuit.
[0101]
(Appendix 6) In the charge pump circuit described in Appendix 1,
A first voltage dividing circuit for dividing the first boosted voltage and generating a first divided voltage;
A voltage comparison circuit for comparing the first divided voltage with a first reference voltage;
The first clock output circuit outputs the first clocks with the first driving capability when the voltage comparison circuit determines that the first divided voltage is lower than the first reference voltage, The charge pump circuit according to claim 1, wherein when the first divided voltage is determined to be higher than the first reference voltage, the first clock is output with the second driving capability.
[0102]
(Appendix 7) In the charge pump circuit described in Appendix 1,
A switch connected between the output node and a voltage supply line of an internal circuit formed in the semiconductor integrated circuit together with the charge pump circuit;
A second voltage dividing circuit for dividing the voltage of the voltage supply line to generate a second divided voltage;
And a switch control circuit for turning on the switch when the second divided voltage is lower than a second reference voltage.
[0103]
(Supplementary Note 8) A first clock generation circuit that generates a plurality of first clocks having the same phase, and
A second clock generation circuit for generating a plurality of second clocks respectively corresponding to the first clocks and having phases opposite to the first clocks;
A plurality of first capacitance elements each receiving the first clock at one end and the other end connected to the first node, and a plurality of first capacitors receiving the second clock at one end and the other end connected to the second node A second capacitive element; and a booster switch connected between the first and second nodes and turned on during an effective period of the first clock; and utilizing the charge / discharge of the first capacitive element A charge pump that generates a first boosted voltage at a first node and generates a second boosted voltage higher than the first boosted voltage at an output node by using charge and discharge of the first boosted voltage and the second capacitor element; With
The first clock generation circuit outputs the first clocks with a first driving capability when the second boosted voltage is lower than a target voltage, and the first clock generation circuit outputs the first clock when the second boosted voltage is higher than the target voltage. A plurality of first clock output circuits for outputting each of the first clocks with a second driving capability that is weaker than the driving capability, corresponding to each of the first clocks;
The second clock generation circuit outputs each of the second clocks with the first driving capability when the second boosted voltage is lower than the target voltage, and when the second boosted voltage is higher than the target voltage, A charge pump circuit comprising a plurality of second clock output circuits for outputting each of the second clocks with a second driving capability corresponding to each of the second clocks.
[0104]
(Supplementary note 9) In the charge pump circuit according to supplementary note 8,
Each of the first clock output circuits includes:
A first weak output circuit that constantly outputs a first weak clock with the second driving capability;
A first strong output circuit that outputs a first strong clock when the second boosted voltage is lower than the target voltage with the first driving capability;
A first combining node connected to the output of the first weak output circuit and the output of the first strong output circuit and configured to combine the first weak clock and the first strong clock as the first clocks; ,
Each second clock output circuit includes:
A second weak output circuit that constantly outputs a second weak clock with the second driving capability;
A second strong output circuit that outputs a second strong clock when the second boosted voltage is lower than the target voltage with the first driving capability;
A second combining node connected to the output of the second weak output circuit and the output of the second strong output circuit and configured to combine the second weak clock and the second strong clock as the second clocks; A charge pump circuit.
[0105]
(Supplementary note 10) In the charge pump circuit according to supplementary note 9,
Each of the pair of first and second strong output circuits has a flag corresponding thereto, and when the second boosted voltage is lower than the target voltage, the flag is sequentially set, and the second boosted voltage is set higher than the target voltage. A flag circuit for sequentially resetting the flag when it is high,
Each of the first and second strong output circuits operates when a corresponding flag is set, and stops when the corresponding flag is reset.
[0106]
(Supplementary note 11) In the charge pump circuit according to supplementary note 9,
Each of the first weak output circuits includes an output buffer having a first transistor size for outputting the first weak clock,
Each of the first strong output circuits includes an output buffer having a second transistor size larger than the first transistor size for outputting the first strong clock,
Each of the second weak output circuits includes an output buffer of the first transistor size that outputs the second weak clock,
Each of the second strong output circuits includes an output buffer of the second transistor size for outputting the second strong clock.
[0107]
(Supplementary note 12) In the charge pump circuit according to supplementary note 11,
The output buffer of each of the first strong output circuits includes a pMOS transistor and an nMOS transistor each having a drain connected to the first synthesis node,
The output buffer of each of the second strong output circuits includes a pMOS transistor and an nMOS transistor each having a drain connected to the second synthesis node,
Each of the first weak output circuits is set to a driving capability in which the pn junction of the output buffer of the corresponding first strong output circuit is not turned on due to the voltage change of the first composite node while the corresponding first strong output circuit is stopped. And
Each of the second weak output circuits is set to a driving capability in which the pn junction of the output buffer of the corresponding second strong output circuit is not turned on due to the voltage change of the second combined node while the corresponding second strong output circuit is stopped. A charge pump circuit.
[0108]
(Supplementary note 13) In the charge pump circuit according to supplementary note 8,
A first voltage dividing circuit for dividing the second boosted voltage and generating a first divided voltage;
A voltage comparison circuit for comparing the first divided voltage with a first reference voltage;
The first clock output circuit outputs the first clocks with the first driving capability when the voltage comparison circuit determines that the first divided voltage is lower than the first reference voltage, Outputting each of the first clocks with the second driving capability when it is determined that a first divided voltage is higher than the first reference voltage;
The second clock output circuit outputs the second clocks with the first driving capability when the voltage comparison circuit determines that the first divided voltage is lower than the first reference voltage, The charge pump circuit, wherein the second clock is output with the second driving capability when it is determined that a first divided voltage is higher than the first reference voltage.
[0109]
(Supplementary Note 14) In the charge pump circuit according to Supplementary Note 8,
A switch connected between the output node and a voltage supply line of an internal circuit formed in the semiconductor integrated circuit together with the charge pump circuit;
A second voltage dividing circuit for dividing the voltage of the voltage supply line to generate a second divided voltage;
And a switch control circuit for turning on the switch when the second divided voltage is lower than a second reference voltage.
[0110]
(Supplementary note 15) In the charge pump circuit according to supplementary note 8,
The charge pump circuit according to claim 1, wherein the valid periods of the first and second clocks do not overlap each other.
As mentioned above, although this invention was demonstrated in detail, above-mentioned embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.
[0111]
【The invention's effect】
In the charge pump circuit according to the first aspect, most of the charge charged / discharged in the first capacitor element can contribute to the generation of the first boosted voltage. Since the generation efficiency of the first boosted voltage is improved, for example, the capacity of the first capacitor element can be reduced. As a result, the power consumption of the charge pump circuit can be reduced. In addition, a circuit that changes the frequency of the clock for charging and discharging the first capacitive element is not necessary.
According to another aspect of the charge pump circuit of the present invention, the first clock output circuit can easily change its driving capability while always outputting each first clock.
[0112]
In the charge pump circuit according to the third aspect, the number of the first strong output circuits to be operated can be controlled with a simple circuit by providing the flag circuit.
In the charge pump circuit according to the fourth aspect, the first reference voltage can be generated with a simple circuit. Therefore, the first reference voltage can be generated accurately and stably.
In the charge pump circuit according to the fifth aspect, the voltage of the voltage supply line can be stabilized at a constant voltage as compared with the case where the first boosted voltage is directly supplied to the internal circuit. Further, the second reference voltage can be generated with a simple circuit. Therefore, the second reference voltage can be generated accurately and stably.
[0113]
In the charge pump circuit according to the sixth aspect, most of the charges charged / discharged in the first and second capacitive elements can contribute to the generation of the second boosted voltage. Since the generation efficiency of the second boosted voltage is improved, for example, the capacitances of the first and second capacitive elements can be reduced. As a result, the power consumption of the charge pump circuit can be reduced. Further, a circuit for changing the frequency of the clock for charging and discharging the first and second capacitive elements is not necessary. Furthermore, since the second boosted voltage is generated using the first boosted voltage and the charge / discharge of the second capacitor, a high boosted voltage can be generated. By generating the second boosted voltage by a two-step boosting operation, the predetermined boosted voltage can be generated with high accuracy.
[0114]
According to another aspect of the charge pump circuit of the present invention, the first clock output circuit can easily change its driving capability while always outputting each first clock. Similarly, the second clock output circuit can easily change its driving capability while always outputting each second clock.
In the charge pump circuit according to the eighth aspect, by providing the flag circuit, the number of the first and second strong output circuits to be operated can be controlled with a simple circuit.
[0115]
In the charge pump circuit according to the ninth aspect, the first reference voltage can be generated with a simple circuit. Therefore, the first reference voltage can be generated accurately and stably.
In the charge pump circuit according to the tenth aspect, the voltage of the voltage supply line can be stabilized at a constant voltage as compared with the case where the second boosted voltage is directly supplied to the internal circuit. Further, the second reference voltage can be generated with a simple circuit. Therefore, the second reference voltage can be generated accurately and stably.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a charge pump circuit of the present invention.
FIG. 2 is a block diagram showing details of a first clock generation circuit in the first embodiment.
FIG. 3 is an explanatory diagram showing an outline of operation of the first embodiment.
FIG. 4 is a block diagram showing a second embodiment of the charge pump circuit of the present invention.
FIG. 5 is a block diagram showing details of a first clock generation circuit in the second embodiment.
FIG. 6 is a block diagram showing details of a second clock generation circuit in the second embodiment.
FIG. 7 is a circuit diagram showing details of a charge pump in a second embodiment.
FIG. 8 is a waveform diagram showing the operation of the charge pump in the second embodiment.
FIG. 9 is a block diagram showing a third embodiment of the charge pump circuit of the present invention.
FIG. 10 is a block diagram showing details of a first clock generation circuit in a third embodiment.
FIG. 11 is a block diagram showing details of a second clock generation circuit in the third embodiment.
FIG. 12 is a circuit diagram showing details of a charge pump in a third embodiment.
[Explanation of symbols]
10, 20, 30 Charge pump circuit
CP1, CP2, CP2a Charge pump
CK1, CK1 [0], CK1 [1], CK1 [2], CK1 [3] First clock
CPG1, CPG1a First clock generation circuit
CO10, CO11, CO12, CO13 First clock output circuit
S1 First strong output circuit
CK1S 1st strong clock
W1 First weak output circuit
CK1W 1st weak clock
ND1 first composite node
C00, C01, C10, C11, C12, C13 First capacitor element
VN1, P1 first node
CK2, CK2 [0], CK2 [1], CK2 [2], CK2 [3] Second clock
CPG2, CPG2a Second clock generation circuit
CO20, CO21, CO22, CO23 Second clock output circuit
S2 Second strong output circuit
CK2S Second strong clock
W2 Second weak output circuit
CK2W Second weak clock
ND2 second composite node
C20, C21, C22, C23 Second capacitance element
P2 2nd node
VO1, VO2, VO2a output node
FC1, FC1a flag circuit
F0, F1, F2, F3 flags
DV1, DV3, DV4 First voltage divider
DV2, DV5 Second voltage divider
CMP1, CMP2 voltage comparison circuit
SW switch
VO1 First boost voltage
VO2, VO2a Second boost voltage
VT target voltage
VD1, VD3, VD4 First divided voltage
VD2, VD5 Second divided voltage
VREF reference voltage

Claims (10)

A first clock generation circuit that respectively generates a plurality of first clocks having the same phase;
Each of the first capacitors receives a first clock at one end, and has a plurality of first capacitors connected to the first node at the other end. A first boosted voltage is applied to an output node by using charge / discharge of the first capacitor. A charge pump for generating,
The first clock generation circuit outputs the first clocks with a first driving capability when the first boosted voltage is lower than a target voltage, and the first clock generation circuit outputs the first clock when the first boosted voltage is higher than the target voltage. e Bei a plurality of first clock output circuit for outputting the respective first clock weaker than the driving capability second drive capability corresponding to said first clock,
Each of the first clock output circuits includes:
A first weak output circuit that constantly outputs a first weak clock with the second driving capability;
A first strong output circuit that outputs a first strong clock when the first boost voltage is lower than the target voltage with the first driving capability;
A first combining node connected to the output of the first weak output circuit and the output of the first strong output circuit and configured to combine the first weak clock and the first strong clock as the first clocks; a charge pump circuit, characterized in that is. Each first clock generation circuit synthesizes the first weak clock and the first strong clock when the first boosted voltage is lower than the target voltage and outputs the first clock, and when the first boosted voltage is higher than the target voltage A plurality of first clock generation circuits for outputting the first weak clock as the first clock;
A plurality of first capacitive elements to which the respective first clocks generated by the plurality of first clock generation circuits are input, and the first boosted voltage is obtained by using charge / discharge of the plurality of first capacitive elements. a charge pump circuit, characterized by comprising generating a charge pump, a. The charge pump circuit according to claim 1 , wherein
A flag corresponding to each of the first strong output circuits; the flag is sequentially set when the first boosted voltage is lower than the target voltage; and the flag is set when the first boosted voltage is higher than the target voltage. Equipped with a flag circuit that sequentially resets
Each of the first strong output circuits operates when a corresponding flag is set, and stops when the corresponding flag is reset. The charge pump circuit according to claim 1, wherein
A first voltage dividing circuit for dividing the first boosted voltage and generating a first divided voltage; and a voltage comparing circuit for comparing the first divided voltage with a first reference voltage;
The first clock output circuit outputs the first clocks with the first driving capability when the voltage comparison circuit determines that the first divided voltage is lower than the first reference voltage, The charge pump circuit according to claim 1, wherein when the first divided voltage is determined to be higher than the first reference voltage, the first clock is output with the second driving capability. The charge pump circuit according to claim 1, wherein
A switch connected between the output node and a voltage supply line of an internal circuit formed in the semiconductor integrated circuit together with the charge pump circuit;
A second voltage dividing circuit for dividing the voltage of the voltage supply line to generate a second divided voltage;
And a switch control circuit for turning on the switch when the second divided voltage is lower than a second reference voltage. A first clock generation circuit that respectively generates a plurality of first clocks having the same phase;
A second clock generation circuit for generating a plurality of second clocks respectively corresponding to the first clocks and having phases opposite to the first clocks;
A plurality of first capacitance elements each receiving the first clock at one end and the other end connected to the first node, and a plurality of first capacitors receiving the second clock at one end and the other end connected to the second node A second capacitive element; and a booster switch connected between the first and second nodes and turned on during an effective period of the first clock; and utilizing the charge / discharge of the first capacitive element A charge pump that generates a first boosted voltage at a first node and generates a second boosted voltage higher than the first boosted voltage at an output node by using charge and discharge of the first boosted voltage and the second capacitor element; With
The first clock generation circuit outputs the first clocks with a first driving capability when the second boosted voltage is lower than a target voltage, and the first clock generation circuit outputs the first clock when the second boosted voltage is higher than the target voltage. A plurality of first clock output circuits for outputting each of the first clocks with a second driving capability that is weaker than the driving capability, corresponding to each of the first clocks;
The second clock generation circuit outputs each of the second clocks with the first driving capability when the second boosted voltage is lower than the target voltage, and when the second boosted voltage is higher than the target voltage, A plurality of second clock output circuits that output the second clocks with a second driving capability are provided corresponding to the second clocks, respectively .
Each of the first clock output circuits includes:
A first weak output circuit that constantly outputs a first weak clock with the second driving capability;
A first strong output circuit that outputs a first strong clock when the second boosted voltage is lower than the target voltage with the first driving capability;
A first combining node connected to the output of the first weak output circuit and the output of the first strong output circuit and configured to combine the first weak clock and the first strong clock as the first clocks; ,
Each second clock output circuit includes:
A second weak output circuit that constantly outputs a second weak clock with the second driving capability;
A second strong output circuit that outputs a second strong clock when the second boosted voltage is lower than the target voltage with the first driving capability;
A second combining node connected to the output of the second weak output circuit and the output of the second strong output circuit and configured to combine the second weak clock and the second strong clock as the second clocks; a charge pump circuit, characterized in that is. Each first clock generation circuit synthesizes the first weak clock and the first strong clock when the first boosted voltage is lower than the target voltage and outputs it as a first clock, and when the first boosted voltage is higher than the target voltage A plurality of first clock generation circuits for outputting the first weak clock as the first clock;
  Each of the second clock generation circuits is opposite in phase to the first clock, and when the second boosted voltage is lower than the target voltage, the second weak clock and the second strong clock are combined and output as a second clock, A plurality of second clock generation circuits for outputting the second weak clock as the second clock when the second boosted voltage is higher than the target voltage;
A plurality of first capacitance elements to which the respective first clocks generated by the plurality of first clock generation circuits are input and a plurality of the second clocks to which the respective second clocks generated by the plurality of second clock generation circuits are input The first capacitor is connected between a first node to which outputs of the plurality of first capacitors are connected in common and a second node to which outputs of the plurality of second capacitors are connected in common. A boost switch that is turned on during a valid period of the clock, and generates a first boosted voltage at the first node using charging / discharging of the plurality of first capacitance elements, and the first boosted voltage and the A charge pump circuit comprising: a charge pump that generates a second boosted voltage higher than the first boosted voltage at an output node by using charge / discharge of a second capacitor element. The charge pump circuit according to claim 6 , wherein
Each of the pair of first and second strong output circuits has a flag corresponding thereto, and when the second boosted voltage is lower than the target voltage, the flag is sequentially set, and the second boosted voltage is set higher than the target voltage. A flag circuit for sequentially resetting the flag when it is high,
Each of the first and second strong output circuits operates when a corresponding flag is set, and stops when the corresponding flag is reset. The charge pump circuit according to claim 6, wherein
A first voltage dividing circuit for dividing the second boosted voltage and generating a first divided voltage; and a voltage comparing circuit for comparing the first divided voltage with a first reference voltage;
The first clock output circuit outputs the first clocks with the first driving capability when the voltage comparison circuit determines that the first divided voltage is lower than the first reference voltage, Outputting each of the first clocks with the second driving capability when it is determined that a first divided voltage is higher than the first reference voltage;
The second clock output circuit outputs the second clocks with the first driving capability when the voltage comparison circuit determines that the first divided voltage is lower than the first reference voltage, The charge pump circuit, wherein the second clock is output with the second driving capability when it is determined that a first divided voltage is higher than the first reference voltage. The charge pump circuit according to claim 6, wherein
A switch connected between the output node and a voltage supply line of an internal circuit formed in the semiconductor integrated circuit together with the charge pump circuit;
A second voltage dividing circuit for dividing the voltage of the voltage supply line to generate a second divided voltage;
And a switch control circuit for turning on the switch when the second divided voltage is lower than a second reference voltage.

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