JP3881134B2 - MOS sensor and manufacturing method thereof - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a method for manufacturing a sensor, and more particularly to a method for electrically connecting a photodiode to a MOS gate.
[0002]
[Background Art and Problems to be Solved by the Invention]
In recent years, charge-coupled devices (CCDs) are often used in digital sensors for image extraction. Its use extends to closed circuit TVs, cameras, video recorders and the like. However, the CCD has a problem that the manufacturing cost is high and the miniaturization is not sufficient. Therefore, in order to achieve miniaturization, reduction of energy consumption and manufacturing cost, CMOS photodiodes that can be formed by semiconductor technology have become promising candidates for CCD in the future.
[0003]
Usually, the sensor includes a circuit area and a photosensitive area composed of photodiodes. A photodiode is a photosensitive (photodetection) semiconductor device that converts light energy into an electrical signal through a PN junction. When light does not illuminate the PN junction due to the presence of an internal electric field at the PN junction, electrons in the N-doped region and holes in the P-doped region Cannot diffuse across the PN junction. However, when a sufficiently intense light beam is applied to the junction region, electron-hole pairs are generated in the junction region. These electron-hole pairs move away from each other when they reach a region with an internal electric field. Electrons move toward the N-type region, and holes move toward the P-type region. As a result, a current flows through the PN junction electrode. Ideally, the photodiode should be in an open circuit state with no current flowing when the device is left in the dark.
[0004]
Conventionally, the signal is transmitted from the photosensitive region to the circuit region only through metal wiring connected to the PN photodiode. The junction between the metal wiring and the PN photodiode has a very low potential barrier. If a dark current exists in the PN photodiode, it tends to flow through the junction barrier to the metal wiring, resulting in a noise signal that causes erroneous determination.
[0005]
[Means for Solving the Problems]
An object of the present invention is to provide a method for manufacturing a MOS sensor. That is, the method of manufacturing a MOS sensor according to the present invention includes a step of forming a P-type region extending into a substrate, a step of forming a stacked polysilicon structure on the P-type region, and a step of forming the stacked polysilicon structure as an injection buffer layer And implanting ions into the P-type region to form an N-type region extending at a shallow depth in the substrate, and patterning and etching the stacked polysilicon structure to form an N-type on the P-type region. Forming a stacked polysilicon ring that partially exposes the shape region; and forming a metal wiring that electrically connects the stacked polysilicon ring to the gate of the MOS transistor. .
[0006]
The laminated polysilicon structure is preferably formed by depositing a first polysilicon film on the P-type region and depositing a second polysilicon film on the first polysilicon film. Preferably, the method further includes the step of patterning and etching the first polysilicon film to form at least one window hole exposing the P-type region prior to the deposition of the second polysilicon film. Further, it is preferable that the second polysilicon film is deposited so as to cover the first polysilicon film and to be in contact with the P-type region through the formed window hole.
[0007]
The laminated polysilicon structure serves as an implantation buffer layer that protects the substrate from damage during the ion implantation step. Furthermore, since the photodiode is electrically connected to the MOS gate via the laminated polysilicon ring and the metal wiring, the dark current output from the photodiode when the MOS sensor is activated can be reduced.
[0008]
Both the above description of the present invention and the detailed description of the present invention described below are illustrative, and the present invention is not limited to these and should be construed based on the claims. .
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0010]
FIG. 1A to FIG. 1I are schematic cross-sectional views showing a method for manufacturing a MOS sensor of the present invention.
[0011]
As shown in FIG. 1A, a substrate 100 such as P-type doped silicon is prepared. A twin well process is performed to form P and N wells extending substantially deep in the substrate 100. In the figure, the P-well is indicated by numeral 104, but the N-well is not shown in FIG. 1 (a). A photosensitive unit cell including a photosensitive region and a circuit region will be formed in and on the P-well.
[0012]
A field insulating region 102 such as a field oxide region is formed at the edge of the P well 104 of the substrate 100. The field oxide region 102 can be formed by a thermal oxidation process technique. The field oxide region 102 exposes the first active region 103a and the second active region 103b. A photosensitive region will be formed below the first active region 103a. A transistor will be formed on the second active region 103b. The second active region having a transistor becomes a circuit region.
[0013]
Further, a sacrificial oxide layer 106 is formed on the first active region 103a and the second active region 103b. The sacrificial oxide layer 106 can be formed by using thermal oxidation techniques or vapor deposition techniques.
[0014]
Next, as shown in FIG. 1B, a first polysilicon film 108 is formed on the substrate 100. The first polysilicon film 108 can be formed by chemical vapor deposition (CVD).
[0015]
Next, as shown in FIG. 1C, a photoresist pattern 110 is formed on the first polysilicon film 108. Following the exposure and development of the first photoresist pattern 110, the first polysilicon film 108 is etched to form a plurality of window holes 112 that expose the sacrificial oxide layer 106 on the first active region 103a. Etching can be performed by a dry etching process using the first photoresist pattern 110 as a mask pattern. In the figure, the etched first polysilicon film is indicated by numeral 108a.
[0016]
Next, as shown in FIG. 1D, the sacrificial oxide layer 106 exposed by the window hole 112 is removed by cleaning the bottom of the window hole. This cleaning can be performed by a wet etching technique. In the figure, the remaining sacrificial oxide layer is designated as 106a.
[0017]
Next, as shown in FIG. 1E, after removing the first photoresist pattern 110, a second polysilicon film 114 is deposited on the first polysilicon film 108a. The second polysilicon film 114 is in contact with the substrate through the window hole 112 provided in the first polysilicon film 108a. A stacked polysilicon structure 115 is formed by the first polysilicon film 108 a and the second polysilicon film 114.
[0018]
Next, as shown in FIG. 1F, an N-type region 120 extending in a substantially shallow depth in the P well 104 is formed in the first active region 103a. The N-type region 120 and the P-well region 104 form a PN photodiode. For example, in the N-type region 120, a second photoresist pattern 116 is formed on the second polysilicon film 114 on the first active region 103a, and the second photoresist pattern 116 is used as a mask in the substrate 100. It can be formed by implanting phosphorus ions. In this ion implantation step, the laminated polysilicon structure 115 serves as an implantation buffer layer that protects the substrate 100 from damage caused by ion implantation. The arrows in the figure indicate the direction of ion implantation.
[0019]
Next, as shown in FIG. 1G, after removing the second photoresist pattern 116, the laminated polysilicon structure 115 is patterned and etched to form a laminated polysilicon ring 122 on the first active region 103a. To do. The stacked polysilicon ring 122 including the etched first polysilicon film 108b and the etched second polysilicon film 114a is formed so as to surround the opening 118 that partially exposes the N-type region 120. For example, in the laminated polysilicon ring, a photoresist pattern (not shown) is formed on the laminated polysilicon structure 115, and a predetermined portion of the laminated polysilicon structure is etched away using the photoresist pattern as a mask. Can be formed. After this etching step, the photoresist pattern is removed.
[0020]
Next, as shown in FIG. 1H, a transistor is formed on the second active region 103b. For example, a CMOS transistor can be used as this transistor. This transistor includes a gate 124, a source / drain region 126, and an LDD region 128.
[0021]
Following the formation of the transistor, a metal-interconnecting process is performed as shown in FIG. For example, the interconnect process includes electrically connecting the gate 124 to the stacked polysilicon ring 122 by metal wiring 130, forming a tungsten plug 144 on the source / drain region 126, and on the tungsten plug 144. Forming a light shielding metal member 146.
[0022]
FIG. 2 shows a schematic top view of a MOS sensor according to an embodiment of the invention. As shown in FIG. 2, the transistor Q ₂ is placed on the circuit region 103b including transistors Q ₁ and Q _3. Metal wiring 130 is formed as a connecting medium between the gate 132 of the laminated polysilicon ring 122 and the transistor Q _2.
[0023]
In the present invention, the photodiode is electrically connected to the MOS gate not only through the metal wiring but also through the laminated polysilicon ring and the metal wiring. A diffusion barrier is formed between the stacked polysilicon ring and the substrate for dopant segregation. When the MOS sensor is activated, the diffusion barrier reduces the intensity of dark current flowing from the photodiode to the MOS gate. Thereby, the dark current output from the photodiode can be reduced. This reduction in dark current increases the on / off ratio of the MOS sensor and consequently increases the contrast ratio of the MOS sensor. In other words, it is possible to manufacture a MOS sensor having improved sensitivity according to the present invention.
[0024]
【The invention's effect】
In summary, the MOS sensor manufacturing method of the present invention has the following advantages.
[0025]
1. By using the laminated polysilicon structure as an implantation buffer layer, the substrate can be protected from damage due to the ion implantation step.
[0026]
2. By electrically connecting the photodiode to the MOS gate through the laminated polysilicon ring and the metal wiring, the dark current output from the photodiode when the MOS sensor is activated can be reduced.
[0027]
As described above, the present invention has been described with reference to the preferred embodiments. However, as those skilled in the art can easily understand, appropriate changes and modifications can be made within the scope of the technical idea of the present invention. The scope of patent protection must be determined based on the scope of claims and the equivalent area.
[Brief description of the drawings]
FIGS. 1A to 1I are schematic cross-sectional views illustrating an example of a method for manufacturing a MOS sensor according to the present invention.
FIG. 2 is a schematic top view showing an example of a MOS sensor according to the present invention.
[Explanation of symbols]
100 substrate 102 field insulating region 103a first active region 103b second active region 104 P well region 106 sacrificial oxide layer 106a remaining sacrificial oxide layer 108 first polysilicon film 108a first polysilicon film 110 after etching first Photoresist pattern 112 Window hole 114 Second polysilicon film 115 Stacked polysilicon structure 116 Second photoresist pattern 119 Ion implantation direction 120 N-type region 122 Stacked polysilicon ring 124 Gate 126 Source / drain region 128 LDD region 130 Metal wiring 132 Transistor Q ₂ gate 144 Tungsten plug 146 Light shielding metal member

Claims (7)

Forming a P-type region extending into the substrate; forming a stacked polysilicon structure on the P-type region; and using the stacked polysilicon structure as an implantation buffer layer in the P-type region. Implanting ions to form an N-type region extending at a shallow depth in the substrate; and patterning and etching the stacked polysilicon structure to partially form the N-type region on the P-type region. A method of manufacturing a MOS sensor, comprising: forming a laminated polysilicon ring exposed to the substrate; and forming a metal wiring that electrically connects the laminated polysilicon ring to a gate of a MOS transistor.   The stacked polysilicon structure is formed by depositing a first polysilicon film on the P-type region and depositing a second polysilicon film on the first polysilicon film. The method of manufacturing a MOS sensor according to claim 1.   The method further comprises patterning and etching the first polysilicon film to form at least one window hole exposing the P-type region prior to the deposition of the second polysilicon film. Item 3. A method for manufacturing a MOS sensor according to Item 2.   4. The MOS sensor according to claim 3, wherein the second polysilicon film is deposited so as to cover the first polysilicon film and to be in contact with the P-type region through the window hole. Production method. A P-type region and a method of manufacturing a MOS sensor gate and is electrically connected to a silicon photodiode and a MOS transistor having a N type region on the P-type region, the manufacturing method, the P-type region And depositing a first polysilicon film and patterning and etching the first polysilicon film to form at least one window hole exposing the P-type region prior to the deposition of the second polysilicon film. And depositing the second polysilicon film on the first polysilicon film, and implanting ions into the P-type region using the first and second polysilicon films as implantation buffer layers. , and forming the N-type region extending at a shallow depth in the P-type region, said first and patterning the second polysilicon film and Forming a laminated polysilicon ring on the N-type region so as to surround an opening that partially exposes the N-type region by etching, and the silicon via the laminated polysilicon ring and the metal wiring method of manufacturing a MOS sensor, which comprises the steps of connecting a photodiode electrically to the gate of the MOS transistor. 6. The method of claim 5, wherein the second polysilicon film is deposited to cover the first polysilicon film and to contact the P-type region through the window hole . A MOS transistor having a gate; a metal wiring connected to the gate of the MOS transistor; a stacked polysilicon ring connected to the metal wiring; and a P-type region and a P-type region connected to the stacked polysilicon ring A silicon photodiode having an upper N-type region, wherein the stacked polysilicon ring is formed to surround an opening that partially exposes the N-type region, and includes a first polysilicon film and the first polysilicon. A second polysilicon film formed on the film, wherein the first polysilicon film has at least one window hole, and the second polysilicon film is in contact with the N-type region through the window hole; A MOS sensor characterized by

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