JP3849942B2 - System including ferroelectric memory - Google Patents

Description

  The present invention relates to a system including a nonvolatile semiconductor memory using a ferroelectric, and more particularly, a highly reliable ferroelectric that greatly reduces the probability that a serious failure occurs in a system function due to a malfunction of the memory. The present invention relates to a system including a body memory.

  A memory using a ferroelectric material, for example, a ferroelectric random access memory (FERAM) is a non-volatile memory that stores data in the polarization direction of the ferroelectric material. In a ferroelectric memory, for example, one memory cell is composed of one ferroelectric capacitor and one switching transistor, and the read of stored information is a voltage that aligns the polarization of the ferroelectric capacitor in one direction. Is applied to the capacitor, and at this time, it is determined whether or not the polarization is reversed. An example of such a ferroelectric memory is described in, for example, 1994 IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp. 268-269. 268-269).

  On the other hand, in normal operation, there is a system in which the plate potential of the ferroelectric capacitor is fixed to, for example, a power supply voltage and used as a dynamic random access memory (DRAM). However, when the power is turned off, information on the accumulated potential is converted into information on the polarization direction of the ferroelectric. Thereby, information can be held even after the power is turned off. An example of such a ferroelectric memory is, for example, 1990 SYL symposium digest page 15 to page 16 (1990 Symposium on VLSI Technology, DIGEST OF TECHNICAL PAPERS, pp. 15-16). It is described in.

1994 IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp.268-269 1990 Symposium on VLSI Technology, DIGEST OF TECHNICAL PAPERS, pp.15-16

  In general, it is generally known that in a DRAM, the stored information may be inverted due to a false signal charge generated by radiation and malfunction. Such a stored information inversion phenomenon is considered to occur in the same manner in a method of operating as a normal DRAM even in a ferroelectric memory. In the ferroelectric memory system that detects the polarization direction as described above, the polarization information once disappears because the polarization is aligned in one direction when information is read. For this reason, it is necessary to rewrite the polarization based on the information read out before the end of the information reading operation. If information is erroneously read due to noise or the like, polarization rewriting is also erroneously performed. In the following, such an error, that is, the function of the memory cell itself is not impaired, but an error that occurs when the stored information is erroneously inverted due to radiation or noise will be referred to as a soft error.

Soft errors in ferroelectric memory can cause serious problems compared to DRAM. The reason is as follows.
If a malfunction occurs in information stored in a storage device such as a DRAM and the system stops, at least the system can be restored by restarting. However, information stored in a nonvolatile memory such as a ferroelectric memory is often information that is repeatedly used, such as a system OS (operating system). In particular, in a portable device, if a system OS and application programs that are used repeatedly are stored in a ferroelectric memory, a large-sized non-volatile storage medium such as a hard disk becomes unnecessary, and a compact system is constructed. Can do. Further, since the CPU can access the ferroelectric memory at a higher speed than the hard disk, the startup time of the portable device can be greatly shortened.

  In a system including such a ferroelectric memory, once a soft error occurs in the ferroelectric memory, incorrect information is rewritten, resulting in a serious failure of the system function, for example, causing a system down There is. In such a case, in order to restore the system, it is necessary to rewrite data such as the OS into the ferroelectric memory by connecting to an external non-volatile storage medium such as a hard disk. It is quite inconvenient for the device to stop the function of the system until a non-volatile storage medium such as a hard disk is obtained and connected.

  In a DRAM, there is a method of automatically detecting and correcting a soft error by providing an error correction circuit (ECC circuit) as a method of avoiding the soft error as described above. In a large-scale system such as a large computer, an ECC circuit can be provided on a chip separate from the main body. However, in a small-scale system such as a portable device or a personal computer, an error correction function is provided on the DRAM chip itself to maintain compactness. It is desirable to have The 1987 IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp.22-23, has an error correction function. An example of a DRAM chip is shown.

FIG. 8 shows a conventional example. FIG. 2A shows a basic configuration of a DRAM equipped with an ECC circuit, and FIG. 2B shows a write / read operation flowchart.
As shown in FIG. 2A, the DRAM 80 includes a memory cell array 81 and a peripheral circuit section 84. Data stored in the memory cell array 81 includes two types of information storage bits 82 and parity bits 83 for storing information, and the peripheral circuit unit 84 includes an ECC circuit 85.

  As shown in the flowchart of FIG. 5B, when information is written (step 91), first, parity bit data is generated (step 92), and then information storage bits and parity bits are written to the DRAM 80 (step 93). . When reading information (step 95), first, a plurality of information storage bits and corresponding parity bits are read (step 96). The ECC circuit 85 determines whether or not an error has occurred in any of the bits based on the calculation based on these data, and if an error has occurred, in which bit the error has occurred. After correcting the error (step 97), the data is sent from the DRAM to the CPU (step 98). As a result, it is possible to realize a DRAM that does not malfunction in the CPU.

However, in a conventional DRAM configuration equipped with an ECC circuit, (1) the parity bit must be generated every time writing is performed, and thus the writing speed is reduced. (2) every time data is read, the parity bit is read together with the storage information and the ECC is read out. Since error correction must be performed by performing a check operation, there are problems such as a decrease in reading speed, and (3) an increase in chip size due to the area of the ECC circuit leading to an increase in chip price. .
From the balance between damage to the system and the frequency of occurrence of soft errors when a DRAM causes a soft error, and the degree of the above-mentioned adverse effects when the ECC circuit is mounted, most of the DRAMs currently on the market are equipped with an ECC circuit. It wasn't.

On the other hand, in the ferroelectric memory, for the reasons described above, it is expected that the damage to the system when a soft error occurs is large, and when an ECC circuit is mounted to prevent it. However, there is a problem that the operation speed is lowered and the chip price is increased.
The object of the present invention is to solve the above-mentioned problems, greatly reduce the probability that a system error is caused by a soft error of a ferroelectric memory, and does not cause a decrease in operating speed or an increase in chip price. The object is to provide a system including a ferroelectric memory.

In order to achieve the above object, the system of the present invention provides
(A) In a system having a first mode and a second mode, a first memory block including a plurality of memory cells each having a ferroelectric capacitor and a switching transistor;
A CPU connected to the first memory block, wherein the first memory block stores a first area for storing normal data and error correction information for error correction of the normal data. In the first mode, the CPU accesses the normal data without performing a correction process including an error check using the error correction information, and supplies the normal data to the first memory block. A write operation is prohibited, and a write operation to the first memory block is permitted in the second mode. The system performs an error check on data using the normal data and the error correction information, and the error When error data is detected by the check, a correction process for correcting and writing back the error data is performed. It is (claim 1).

(B) The correction processing is performed by the CPU according to a correction processing program (claim 2).
(C) The system generates a trigger signal based on a predetermined condition and starts the correction process (claim 3).
(D) In the second mode, the memory cell into which correction data is written is the same as the memory cell from which the error data is read out.
(E) The system is a portable device (claim 5).

(F) the plurality of memory cells store data according to a polarization direction of the ferroelectric capacitor;
The data is read from a corresponding memory cell by detecting the polarization direction (claim 6).
(G) The first memory block is used for storing an OS program of the system (claim 7).
(H) The error correction information in the second area is a parity bit of normal data in the first area.

According to the system including the ferroelectric memory of the present invention, there is an effect that the system can be obtained due to the malfunction of the ferroelectric memory. Further, the number of memory chips in the system can be reduced, and there is an effect that a system suitable for a low-cost and compact portable device can be obtained. Furthermore, compared to the case of using an ECC circuit, there is an effect that it is possible to avoid the problem of cost increase due to a decrease in operation speed and an increase in chip area.
Further, when the method of generating the error correction processing start command as in the present invention is adopted, a user-friendly and highly reliable system can be obtained.

Further, when the method of storing the error correction processing program as in the present invention is adopted, the risk of the error correction processing program itself being broken can be avoided, and a highly reliable system can be obtained.
Furthermore, when the method of setting the rewrite prohibition area according to the present invention is adopted, a configuration for making the rewrite prohibition area variable can be easily realized, and a user-friendly system can be obtained.
In addition, when the configuration of the rewrite prohibition area according to the present invention is adopted, rewrite prohibition and permission control becomes easy.
Further, when the control circuit for giving write permission to the rewrite prohibited area according to the present invention is adopted, the malfunction that erroneously writes to the prohibited area can be greatly reduced, and a highly reliable system can be obtained. Further, the control circuit can be easily arranged for each memory mat.

The outline of the embodiment of the present invention is as follows.
First, the system of the present invention has at least a CPU and a ferroelectric memory.
The CPU can access a storage area of a program that performs error correction processing of data.
The storage area (memory cell array) of the ferroelectric memory is divided into a rewritable area and a rewritable area. An OS and application programs are stored in the rewrite prohibition area, and the rewrite permission area is used as a work area. The rewrite prohibited area has an information storage bit area and a parity bit area. The information storage bit area is used for normal information storage, and the parity bit area is used for storing information (parity bit) for recognizing and correcting a soft error when information in the information storage bit occurs. . The rewrite permission area is composed of only information storage bits. A means for normally prohibiting and temporarily permitting writing to the rewrite prohibition area, for example, a control circuit is provided in the peripheral circuit section (see FIG. 1).

In the system of the present invention, the error correction processing of the data in the rewrite prohibited area is performed by the CPU in response to an error correction processing start command (see FIG. 2).
The error correction processing start command is automatically generated by an internal circuit of the system when the system power supply of the present invention is turned on, for example. Alternatively, an error correction processing start command can be generated by the user turning on a switch provided in the system of the present invention (see FIG. 3).
The storage area for the error correction processing program is provided in the ROM section in the CPU. Alternatively, it is provided twice in the rewrite prohibition area in the ferroelectric memory (see FIG. 4).
An address storage section for defining the range of the rewrite prohibition area is provided in the rewrite prohibition area in the peripheral circuit section or the memory cell array (see FIG. 5).
The rewrite prohibition area is configured, for example, in units of two memory mats facing each other across the sense amplifier row (see FIG. 6).

  The control circuit, for example, after giving a write command to one arbitrary address of two memory mats facing each other across the sense amplifier row among the memory mats in the rewrite prohibited area (this write command is not accepted) ), The writing operation to the other memory mat is permitted for a certain period (see FIG. 7).

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is an example showing the basic configuration of the system of the present invention.
The system (100) of this embodiment has at least a CPU (110) and a ferroelectric memory (120). The storage area (memory cell array 121) of the ferroelectric memory (120) is divided into a rewrite prohibition area (122) and a rewrite permission area (123). The rewrite prohibition area (122) is repeatedly used in the system, such as the system OS and application programs, and is used for storing data with almost no rewrite opportunity, and the rewrite permission area (123) is a temporary storage with many rewrite opportunities. Used as an area, that is, a work area. The rewrite prohibition area (122) is provided with a parity bit area together with a normal information storage bit area. The parity bit area has information for restoring the information when the information in the information storage bit area is inverted due to a soft error. For example, a parity bit consisting of 8 memory cells is provided for an information storage bit consisting of 120 memory cells. At this time, one of the eight memory cells of the parity bit is “0” when the number of information “1” is even among the information of 127 memory cells excluding this memory cell, and “0” when the number is odd. 1 'is memorized. This memory cell has information indicating that an error has occurred in any one of the 128 memory cells.

  That is, if the number of “1” information of 127 memory cells does not correspond to the information of the memory cell, an error has occurred. The remaining seven memory cells of the parity bit can take 2 7, that is, 128 states. By making this correspond to information indicating in which of the 128 memory cells an error has occurred, the error can be repaired. In the example described above, it becomes impossible to repair when an error occurs in two or more memory cells. However, according to the system of the present invention as described later, such a case is very rare. The amount of information that can be repaired by one error is sufficient.

In order to repair an error that has occurred in a memory cell, for example, it is necessary to compare an operation result for 120 information storage bits with a result of a parity bit and determine an error location based on the result. This is performed by the CPU (110) based on the program stored in the error correction processing program storage area (111).
If it becomes clear that an error has occurred in the memory cell, the correction data needs to be rewritten to the memory cell. A control circuit (127) for temporarily permitting writing to the rewrite prohibited area (122) is provided in the peripheral circuit portion (126) of the ferroelectric memory.

FIG. 2 is a flowchart of error correction processing in the system (100) of FIG.
First, an error correction processing start command is given to the CPU (110) (step 201). In response to this, the CPU (110) starts the operation according to the error correction processing program (step 202). First, the CPU (110) stores a plurality of information storage bit data (120 memory cell data in the above example) in the ferroelectric memory and the parity bit data (the above-mentioned data). In this example, data of 8 memory cells) is loaded (step 203). Next, the CPU (110) checks whether there is an error in the loaded data according to the procedure instructed by the program (step 204).

If there is an error in the data (step 205: Y), the CPU (100) instructs the control circuit (127) in the ferroelectric memory to temporarily permit writing for data correction. (Step 206). Then, according to the procedure instructed by the program, the error data is corrected and written back to the ferroelectric memory (step 207). The control circuit (127) sets the memory cell again to the rewrite prohibition state after writing the corrected data back to the memory cell (step 208).
After step 208 and when there is no error in the data (step 205: N), it is determined whether or not correction processing has been performed on all data in the rewrite-protected area, and data that has not been corrected yet Is present (step 209: N), the process returns to step 203 again. When there is no data that has not been corrected (step 209: Y), the CPU (110) ends the error correction process (step 210).
The error correction processing is performed on all data in the rewrite prohibited area by the procedure as described above.

  Here, a specific method for determining a parity bit and an embodiment of a 1-bit error correction method will be described. As an example, a case where 8 parity bits are added to 120 information storage bits is shown. First, identification numbers 1 to 128 are assigned to 120 information storage bits and 8 parity bits. However, an identification number of “2 to the power of n” (that is, 1, 2, 4, 8, 16, 32, 64, 128) is assigned to the parity bit. This identification number is merely a virtual one for identifying each bit, and does not indicate a storage address in the ferroelectric memory. For example, eight parity bits may be stored in the continuous address.

Next, data of seven parity bits having an identification number “2 to the power of n” (n is 0 to 6) is determined by the following procedure. That is, when the number of bits whose data is “1” among 63 information storage bits in which the n + 1-th digit is 1 instead of 0 when the identification number is expressed in binary, the identification number The parity bit data of “2 to the power of n” is set to “0”, and is set to “1” when it is an odd number.
The data of the remaining one parity bit (identification number 128, ie, 2 to the 7th power) is determined as follows. That is, of the 120 information storage bits and the 7 parity bits defined above, if the number of bits whose data is “1” is an even number, the parity bit data of the identification number 128 is “0” and an odd number In this case, it is set to “1”.

  Using the parity bit determined as described above, a 1-bit error can be detected and corrected by the following method. That is, data of 120 information storage bits and 8 parity bits are read from the ferroelectric memory, and first, 7 parity bits having an identification number “2 to the nth power” (n is 0 to 6) are obtained. It is checked whether or not the above-mentioned predetermined value (value determined from the information storage bit) is reached. If it is a predetermined value, a binary number of 7 digits is formed with 0 in the (n + 1) th digit and 1 otherwise. The 7-digit binary number formed in this way serves as an error determination number and indicates the identification number (excluding 1 to 127, 128) of the bit in which a 1-bit error has occurred. When the error determination number is 0, there is no error from identification numbers 1 to 127.

  Next, it is checked whether or not the remaining one parity bit of the identification number 128 has the predetermined value. This is a predetermined value. If the error determination number is other than 0, a 2-bit error has occurred. However, the error location at this time is unknown. On the other hand, when the error determination number is 0 but the parity bit of the identification number 128 is not a predetermined value, an error has occurred in the parity bit of the identification number 128 itself. As described above, since it is possible to know the occurrence and error location of a 1-bit error, it is possible to correct information by inverting the bit data at the error location.

According to the embodiment of the configuration of the present invention shown in FIG. 1 and the error correction processing flowchart shown in FIG. 2, the following highly reliable and high performance system can be obtained. That is,
(A) First of all, when a soft error occurs in the storage area of the OS or application program, it is possible to avoid a serious failure in the function of the system. This is because the error location can be repaired and the system function can be restored by giving an error correction processing start command. In addition, since the temporary storage information remains in the work area in a non-volatile manner, even if the system has to be turned on again, there will be no major trouble for the user.

(B) Secondly, the number of chips used in the system can be reduced and a low-cost system can be obtained as compared with the case where the OS and application programs are stored in ROM and the work area is DRAM. Further, since the system can be configured compactly, there is an advantage that a system suitable for a portable device can be obtained. There are similar advantages compared to a system in which the OS and application programs are stored in a hard disk when the system is not used and read from the hard disk to a DRAM or the like when the system is used. Furthermore, since the OS program already exists in the ferroelectric memory that can be accessed from the CPU at a high speed when the system is started, compared with the case where the OS program is temporarily read from the hard disk, which is accessed slowly by the CPU, to the DRAM. Thus, there is an advantage that the startup time can be shortened.

(C) Third, the operating speed of the system does not decrease as in the conventional example shown in FIG. This is because no data check is performed during a normal read operation, and no new parity bit is generated during a normal write operation. This is because the parity bit is provided only for the data in the rewrite prohibited area.
(D) Fourth, since error correction processing is performed using a CPU, an increase in chip area due to mounting of an ECC circuit and an increase in chip price due to the mounting can be avoided.

FIG. 3 is a flowchart showing a procedure for performing error correction processing by a method of generating two types of error correction processing start commands.
In the first embodiment, as shown in the flowchart of FIG. 5A, when the system power supply of the present invention is turned on (step 301), an error correction processing start command is automatically generated by the system internal circuit ( Step 302), whereby the CPU executes an error correction processing program (Step 303) to perform error correction processing.
In the second embodiment, as shown in FIG. 5B, when a user turns on a switch provided in the system of the present invention (step 351), an error correction processing start command is generated (step 352). In this way, the CPU executes an error correction processing program (step 353) to perform error correction processing.

In any embodiment, the error correction processing start command does not need to be frequently generated, and may be given about once a day, for example. It is clear from the following calculation that sufficiently high reliability can be obtained at such a frequency.
A semiconductor memory is usually designed so that the frequency of occurrence of soft errors is 1000 FIT or less. This is the rate at which a soft error occurs at most once every 10 6 hours per chip. Now, assume that the OS program is stored in ferroelectric memory chips of 10 million systems all over the world. At this time, according to the conventional system, on average, 10 systems may fall into a functional failure in one hour. However, it is assumed that the OS program does not work with one error.

On the other hand, when the system of the present invention is operated for 10 hours a day and an error correction processing start command is given once a day, the following occurs.
The worst case in which the OS program is stored in the entire ferroelectric memory chip is calculated. Assume that the storage area is composed of 1000 sets of information storage bits and parity bits. When it is assumed that only a 1-bit error can be repaired in the parity bit, the functional failure occurs in the system of the present invention when two or more soft errors are added to any of the above 1000 groups when the error correction processing start command is given. This is the case where this has occurred.

  If the frequency of soft errors is 1000FIT, a total of 100 errors will occur in 10 million memory chips in 10 hours. Of these, the probability that two or more errors are concentrated in any one of 10 million blocks × 1000 blocks is less than 10 minus the sixth power. This is even less than the frequency of 10 6 days, that is, once every 2740. As described above, according to the system of the present invention, it is possible to extremely reduce the occurrence rate of the functional failure of the system that cannot be repaired due to two or more errors. In the first example shown in FIG. 3A (an example in which an error correction process start command is generated when the power is turned on), an error correction process start command is automatically generated with a frequency of about once a day. There is an effect that a system that is easy to use can be obtained. According to the first and second examples shown in FIGS. 3A and 3B, even if a soft error occurs in the storage area of the OS program and the system functions are stopped, the power is turned on again. If the user turns on a predetermined switch (second example), the function can be recovered with a probability of almost 100%, and a highly reliable system can be obtained.

  Further, according to the system of the present invention, it is not necessary to always equip the system with a non-volatile medium such as a hard disk for storing an OS program or the like when the system is not used, thereby realizing a compact system. Furthermore, the system startup time can be shortened. In both the first and second methods in FIG. 3, even if an error is found in the rewrite-protected area, error correction is performed by the CPU, so that a nonvolatile medium other than the ferroelectric memory (for example, a hard disk) It is not necessary to read the correct OS program from the memory to the ferroelectric memory.

  FIG. 4 is a more specific example of the storage area (111) of the error correction processing program of FIG. FIG. 4A shows an embodiment in which an error correction processing program storage area is provided in a part of the on-chip ROM area in the CPU (110). According to the present embodiment, since a ROM is used, a soft error does not occur in the error correction processing program storage area itself, and error correction processing can be executed without fail, so that a highly reliable system can be obtained. is there. In FIG. 4B, a storage area for the error correction processing program is provided in the rewrite prohibition area (122) of the ferroelectric memory (120). However, in this case, since a soft error may occur in the storage area itself, another identical program is provided for backup purposes. According to the present embodiment, since a system can be constructed using a general-purpose CPU, there is an effect that an inexpensive and highly reliable system can be obtained.

In the above-described embodiment, the range of the rewrite prohibition area is described as being fixed. However, the range of this area may be changed by designation.
FIG. 5 shows an embodiment of the present invention showing a configuration method of an address storage unit for designating the range of the rewrite prohibition area.
In FIG. 5A, an address storage unit for designating the range of the rewrite prohibition area is provided in the peripheral circuit unit. It may be composed of wired logic, fuse, ROM, etc., and the range of the rewrite prohibition area may be fixed, or it may be composed of static RAM (SRAM) with a ferroelectric capacitor so that the range of the rewrite prohibition area can be changed. May be.
FIG. 5B shows an example in which an address storage unit (129) for designating the range of the rewrite prohibition area (122) is provided in the rewrite prohibition area (122) itself. According to the embodiment of FIG. 5B, there is an effect that a configuration in which the rewrite prohibition area is variable can be easily realized.

  FIG. 6 is an embodiment of the present invention showing a more specific example of the memory array configuration in the system of the present invention, and only a part of the components are schematically shown. Each memory cell is composed of one ferroelectric capacitor and one transistor (in FIG. 6, only one memory cell MC is shown as a representative cell). Each memory cell is arranged at the intersection of the word line WL and the bit line BT. For example, 512 memory cells are connected to one word line WL, and 256 memory cells are connected to one bit line pair. , 512 × 256 memory cells constitute one mat.

  The sense amplifier row connected to the bit line pair is arranged to share two mats, for example, the sense amplifier row (1) s is shared by the mat (1) u and the mat (1) d. The rewrite prohibition area and the rewrite permission area are defined in the above two mat units. Defining in mat units has the effect of simplifying the configuration of the control circuit (127) of FIG. A unit of the rewrite prohibition area, that is, a set of information storage bits and parity bits is defined by a size for equally dividing one word line. For example, in FIG. 6, 120 cell information storage bits and 8 cell parity bits form one set, and each word line WL (i) has four sets. With such a configuration, there is an effect that data can be efficiently read out to the CPU during error correction processing.

FIG. 7 is a diagram for explaining an embodiment of the control circuit (127) for giving write permission to the rewrite-prohibited area in FIG. 1, (a) is a specific circuit example of the control circuit (127), b) is a diagram showing an operation flow thereof.
When writing into the memory mat pu, when a write command is given to an arbitrary address of the memory mat pd opposed across the sense amplifier array SA, the other is only for a certain period defined by the delay circuits D1 and D2. The writing to the memory mat pu is permitted. Note that a write command for the first memory mat pd is not accepted.

  In FIG. 7A, the control circuit (127) includes a flip-flop circuit FF, two transistors TR1 and TR2, two delay circuits D1 and D2, two AND circuits G1 and G2, a knot circuit NOT, a multiplexer MPLX, and the like. It is configured. Normally, one node ST1 of the flip-flop circuit FF is at a high level, the high level signal is inverted by the knot circuit NOT, and the AND circuit G2 is closed. For this reason, both the WA from the AND circuit G2 and the Mpu from the multiplexer MPLX are at the low level, and the memory mat pu is in a rewrite prohibited state.

  When a write command (write enable signal WE is at a high level) is applied to the memory mat pd, the addresses A0 to AN input and held in the address buffer are decoded by the address predecoder, and the mat pd selection signal line, mat pu Selection signal line and in-mat selection signal line. The output mat pd selection signal line signal is sent to the delay circuit D1, and is input to the AND circuit G1 after a delay time defined by the delay circuit D1. When the write enable signal WE is at the high level, the transistor TR1 is turned on by the output from the AND circuit G1, and one node ST1 of the flip-flop circuit FF is set to the low level. The low level signal is inverted by the NOT circuit NOT, opens the AND circuit G2, outputs the mat pu selection signal from the address predecoder as WA, and sets the mat pu to the rewrite permission state.

The multiplexer MPLX selects one of the two inputs of the mat pu selection signal line and WA and outputs it as Mpu.
When the write enable signal WE is at a low level, that is, in a read operation, the mat pu selection signal line is output as Mpu, and any word line in the mat pu is activated via the X decoder X-DEC and the X driver X-DRV. Signal.
When the write enable signal WE is at a high level, that is, in a write operation, the mat pu selection signal line is output as Mpu only when the mat is a rewrite permission area. If the mat is a rewrite prohibited area, WA is output as Mpu. The rewrite permission area or the rewrite prohibition area is determined by the information stored in the storage section of the rewrite prohibition mat.

  When one node ST1 of the flip-flop circuit FF becomes low level, the other node ST2 of the flip-flop FF becomes high level, and then the transistor TR2 is turned on after a predetermined delay time specified by the delay circuit D2 elapses. And make ST2 low level. As a result, ST1 returns to high level again.

FIG. 7B is a time chart of signals during a write operation when the mat pu is a rewrite prohibited area.
In FIG. 7A, since the transistor Tr1 is normally off, one node ST1 of the flip-flop FF is at a high level and passes through the knot circuit NOT, so that the output WA of the AND circuit G2 is always at a low level. In the rewrite prohibition area, the write enable signal WE is always at a low level. In the rewrite prohibited area, when the write enable signal WE is at a high level, the output Mpu of the multiplexer MPLX coincides with WA (in this case, WA is at a low level), so that the mat pu is not selected at the time of a write command.

When a write command for an address in the mat pd is generated by the chip selection signal CS (the write enable signal WA is at a high level), the mat pd selection signal is at a high level. As a result, after the delay time by the delay circuit D1, the transistor Tr1 is turned on, and one node ST1 of the flip-flop FF changes to the low level. In this state, since the AND circuit G2 is turned on, the output WA matches the mat pu selection signal line. At this time, when a write command to the mat pu (the write enable signal WE is at a high level) is given, the output Mpu of the multiplexer MPLX becomes a high level in accordance with the mat pu selection signal. As a result, the word line corresponding to the in-mat selection signal from the address predecoder is activated, and the write operation is performed.
In contrast, the rewriting permission for the mat pd may be performed by giving a write command to the mat pu.

  According to the embodiment shown in FIG. 7, there is an effect that a highly reliable system can be obtained. In other words, it is possible to define the rewrite prohibition area from the software side by the program, but according to this embodiment that defines the rewrite prohibition area by the circuit, there is a possibility that the rewrite prohibition area may be erroneously written during normal operation. It is greatly reduced. In addition, since the signals for the two adjacent mat sets are used, there is an advantage that the control circuit (127) can be easily arranged close to each mat set.

It is a basic composition figure of the system of the present invention. It is a flowchart of the error correction process in the system of FIG. It is a figure explaining how to generate the error correction processing start command of the present invention. It is a figure which shows the example of a storage area of the error correction processing program of this invention. It is a figure which shows the structural example of the address memory | storage part of the rewriting prohibition area | region of this invention. FIG. 3 is a diagram illustrating an example of a mat configuration of a ferroelectric memory according to the present invention. FIG. 6 is a control circuit that gives permission to write to a rewrite prohibited area and an operation waveform diagram. It is a system configuration example including a conventional ECC circuit.

Explanation of symbols

80: DRAM (dynamic random access memory)
81: Memory cell array 82: Information storage bit area 83: Parity bit area 84: Peripheral circuit section 85: ECC circuit 100: System of the present invention 110: CPU (central processing unit)
120: Ferroelectric memory 121: Memory cell array 122: Rewrite prohibition area 123: Rewrite prohibition area 124: Information storage bit area 125: Parity bit area 126: Peripheral circuit section 127: Control circuit for giving write permission to the rewrite prohibition area Mat (i) u: Upper mat Mat (i) d: Lower mat
WL (i): Word line
X-DRV: X driver
X-DEC: X decoder
FF: flip-flop circuit
MPLX: Multiplexer
D1, D2: Delay circuit
NOT: Knot circuit
Tr1, Tr2: Transistor
G1, G2: AND circuit
WE: Write enable signal
A0 to AN: Address signal
WA, Mpu: Signal line
CS: Chip selection signal

Claims (8)

In a system having a first mode and a second mode,
A first memory block including a plurality of memory cells each having a ferroelectric capacitor and a switching transistor;
A CPU connected to the first memory block;
The first memory block has a first area for storing normal data and a second area for storing error correction information for error correction of the normal data;
In the first mode, the CPU accesses the normal data without performing a correction process including an error check using the error correction information, and a write operation to the first memory block is prohibited.
In the second mode, a write operation to the first memory block is permitted, and the system performs data error check using the normal data and the error correction information, and error data is detected by the error check. And a correction process for correcting the error data and writing it back. The system of claim 1, wherein
The correction processing is performed by the CPU according to a correction processing program. The system according to claim 1 or 2,
The system generates a trigger signal based on a predetermined condition, and starts the correction process. The system according to any one of claims 1 to 3,
In the second mode, the memory cell to which correction data is written is the same as the memory cell from which the error data is read. The system according to any one of claims 1 to 4,
The system is a portable device. The system according to any one of claims 1 to 5,
The plurality of memory cells store data according to the polarization direction of the ferroelectric capacitor,
The system is characterized in that the data is read from a corresponding memory cell by detecting the polarization direction. The system according to any one of claims 1 to 6,
The system according to claim 1, wherein the first memory block is used for storing an OS program of the system. The system according to any one of claims 1 to 7,
The error correction information in the second area is a parity bit of normal data in the first area.

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