JP3846670B2 - Image reading device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image reading apparatus installed in a scanner, a digital copying machine, a digital color copying machine, a facsimile, a color facsimile, and the like, and more specifically, is output from a photoelectric conversion means (line image sensor) that reads an original image. The present invention relates to a phase adjustment technique of a driving (sampling) clock of a photoelectric conversion unit and an A / D conversion unit in an image reading apparatus having an A / D conversion unit that samples an analog signal and converts it into a digital signal.
[0002]
[Prior art]
Conventionally, photoelectric reading is performed to convert a document image into data in a scanner, a digital copying machine, or the like. As a photoelectric conversion means used for photoelectric reading, a device that detects an analog image signal by scanning a conversion pixel array like a CCD line sensor is adopted.
In order to extract a good analog signal from such a photoelectric conversion means (CCD), it is necessary to provide a drive clock with an appropriate phase. Further, it also affects the drive clock in the analog processing circuit at the next stage that processes the detected image signal when necessary adjustments are made to the phase of the drive clock of the photoelectric conversion means. In addition, since the output delay time of the analog signal from the photoelectric conversion means depends on the drive clock frequency, the output voltage level, and the like, it is necessary to perform actual machine evaluation in order to perform sample hold at an appropriate output position. An A / D converter (ADC) is used to digitize the analog signal after actual machine evaluation, but it is necessary to generate the sampling clock of the analog image signal at an appropriate position in the image signal period.
Conventionally, a timing LSI has been used as means for generating a drive clock to be supplied to such image data processing means. However, as a problem of LSI development, a complete design specification is required at an early stage of LSI development, and the development of LSI takes a long time, which requires a long time for commercialization.
[0003]
[Problems to be solved by the invention]
For this reason, if it is necessary to slightly delay or advance the timing of the drive clock in the second half of product development, a delay line is used at the final stage of the LSI manufacturing process in order not to prolong development. Proposals have been made that can be dealt with by making hardware changes, such as putting in, but this has been very difficult.
The present invention has been made in view of such problems of the prior art, and its object is to sample an analog signal output from a photoelectric conversion means (line image sensor) for reading a document image and convert it into a digital signal A. When it is necessary to change the timing of driving (sampling) clocks of the photoelectric conversion means and the A / D conversion means in the image reading apparatus having the / D conversion means, the phase is delayed or the phase is advanced It is an object of the present invention to provide an image reading apparatus having a driving (sampling) clock phase adjusting means capable of accurately adjusting the frequency without changing hardware.
[0004]
[Means for Solving the Problems]
  The invention of claim 1 is a line image sensor for reading an image, an A / D conversion means for converting an analog image signal output from the line image sensor into digital image data,Said A / D Digital data detection means for detecting digital image data from the conversion means;Drive clock generation means for generating each drive clock for operating the line image sensor and A / D conversion means;An analog image signal output from the line image sensor ODD When EVEN Adjust the gain of each signal 1 The analog signals A / D Analog processing means for outputting to the conversion means;,A line image sensor generated by the drive clock generating means; A / D Phase adjustment means for adjusting clock phase of conversion meansIn an image reading apparatus havingThe analog processing means includes the ODD When EVEN After correcting for the output difference between DC Giving the level difference A / D The digital data detection means outputs to the conversion means and for each drive clock changed by the phase adjustment means. ODD When EVEN The difference between the respective average values is obtained, and the difference is given by the predetermined analog processing means. DC The phase is closest to the level difference.It is characterized by adjusting.
[0007]
  Claim2The invention of claim1In the image reading apparatus described above, the adjustment step of the phase adjustment data has a length that is an integral number of a period of the pixel clock.
[0008]
  Claim3The invention of claim1 or 2In the image reading apparatus described in (1), an adjustment width of the phase adjustment data is set to a length corresponding to one period of the pixel clock.
[0009]
  Claim4The invention of claim1Thru3In the image reading apparatus according to any one of the above, the image reading apparatus includes a shading correction unit at a subsequent stage of the A / D conversion unit, and the digital data detection unit includes a memory for holding detection data in the shading correction unit. It is also used as a memory.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described based on the following examples shown with the accompanying drawings.
First, an outline of a digital color copying machine that can suitably implement the image reading apparatus of the present invention will be described.
FIG. 1 is a diagram showing an outline of the overall configuration of the digital color copying machine of the present embodiment. This digital color copying machine is roughly composed of a color image reading device and a color image recording device. The color image reading apparatus includes an image reading unit (scanner) 2 and an image processing unit 3, while the color image recording apparatus includes an image writing unit 4, a drum unit 8, a developing unit 10, an intermediate transfer unit 9, and a paper feed. Section 11, fixing section 12, copier mechanism section 6, and system control unit 1, rendition section unit 5, image display for performing control operations common to both the reading and recording apparatuses. A unit 7 is provided.
[0011]
The outline of the operation when color copying is performed by the digital color copying machine of this embodiment is as follows. The image reading unit 2 emits reflected light from the document while sub-scanning the document irradiated with illumination light from the light source. An image is read by detection by a 3-line CCD sensor, and image data is sent to the image processing unit 3.
The image processing unit 3 sends image data subjected to image processing such as scanner γ correction, color conversion, main scanning scaling, image separation, processing, area processing, gradation correction processing to the image writing unit 4.
The image writing unit 4 drives an LD (laser diode) by applying a modulation according to the image data. In the drum unit 8, an electrostatic latent image is written by a laser beam from the LD onto a uniformly charged rotating photosensitive drum, and toner is attached by the developing unit 10 to be visualized.
The image formed on the photosensitive drum is retransferred onto the transfer belt of the intermediate transfer unit 9. In the case of full-color copying, four colors (Black: Bk, Cyan: C, Mgenta: M, Yellow: Y) of toner are sequentially stacked on the intermediate transfer belt. In the case of full-color copying, the transfer paper is fed from the paper feeding unit 11 in synchronization with the intermediate transfer belt at the time when the image forming and transferring processes of Bk, C, M, and Y are completed, and the paper is transferred. The toner is transferred from the intermediate transfer belt to the transfer paper at the same time on the transfer paper.
The transfer paper onto which the toner has been transferred is sent to the fixing unit 12 through the conveyance unit, and is thermally fixed by the fixing roller and the pressure roller and is discharged.
[0012]
When performing the above-described copy operation, copy conditions such as a copy mode set by the user's selection are input by the operation unit unit 5. The operation mode to be executed in accordance with the copy conditions such as the set copy mode is notified to the system control unit 1, and the system control unit 1 performs control processing for executing the set copy mode. At this time, the system control unit 1 issues a control instruction to units such as the image reading unit 2, the image processing unit 3, the image writing unit 4, and the image display unit 7.
FIG. 2 is a diagram illustrating an example of an operation panel of the operation unit 5.
As shown in FIG. 2, the operation panel of the operation unit 5 includes a numeric keypad 41, a mode clear / preheat key 42, an interrupt key 43, an image quality adjustment key 44, a program key 45, a print start key 46, a clear / stop key 47, An area processing key 48, a brightness adjustment knob 49, a touch panel key (on the LCD panel 26 in FIG. 3) 50, and an initial setting key 51 are provided.
[0013]
The numeric keypad 41 is used when inputting numerical values such as the number of copies. The mode clear / preheat key 42 is used to cancel the set mode and return to the initial setting, or to set the preheat state by continuously pressing for a predetermined time or longer. The interrupt key 43 is used to interrupt during copying and to copy another document. The image quality adjustment key 44 is used when adjusting the image quality. The program key 45 is used to register or call a frequently used mode. The print start key 46 is a key for starting copying. The clear / stop key 47 is used to clear an input numerical value or to interrupt copying during copying. The area processing key 48 is used when executing an area processing / editing mode on the image display unit (display editor) 7.
The brightness adjustment knob 49 adjusts the brightness of the screen of the LCD panel (see FIG. 3 described later).
The touch panel key 50 sets a key area in the same range as the range of various keys displayed on the LCD panel, and when the touch panel detects a press within the set range, processing of the set key is performed. I do.
The initial setting key 51 is pressed when the user selects each initial setting.
[0014]
Further, in order to display the image read from the image reading unit 2 on the image display unit 7 (FIG. 1), the image reading unit 2 starts reading the original image according to a control instruction from the system control unit 1, and reads the image. The image signal from the unit 2 is subjected to image processing suitable for display on the image display device in the image processing unit 3, and then the image data of the document is output to the image display device such as an LCD panel.
FIG. 3 is a functional block diagram showing a circuit configuration of the image display unit 7.
As shown in FIG. 3, the image display unit 7 is connected to the system control unit 1 via a command line and to the image processing unit 3 via a data line, and includes a FIFO (line buffer) 21, a DRAM (image Data memory) 22, CPU 23, VRAM (video memory) 24, LCDC (LCD controller) 25, LCD (liquid crystal panel) 26, ROM 27, SRAM 28, serial communication driver 29, image data signal buffer (driver / receiver) 30, keyboard 31 Is provided.
[0015]
The image data output from the image processing unit 3 is stored in the image data storage DRAM 22 by the DMA controller built in the CPU 23 via the FIFO 21 of the image display unit 7.
Since an image data control signal is sent to the image display unit 7 together with the image data, it is possible to capture only the effective image area. Valid image data stored in the DRAM 22 is DMA-transferred to the VRAM 24 by the CPU 23. At this time, the CPU 23 can transfer an arbitrary portion of the image data in the DRAM 22 and perform processing such as enlargement / reduction / decimation.
The image data transferred to the VRAM 24 is displayed on the LCD panel 26 under the control of an LCDC (LCD controller) 25.
[0016]
FIG. 4 is a diagram showing an embodiment of the LCD panel of the image display unit 7 shown in FIG.
The image display unit 7 displays an image on the LCD panel 26. In addition, a display editor for performing editing / processing area designation / mode setting in the display screen may also be used. Each setting key in FIG. 4 corresponds to the keyboard 31 in the functional block diagram of FIG. An important part for the image reading apparatus of the present invention is a reading key and a brightness adjustment key. The reading key is a key for starting reading of an original and displaying the entire read image on a display. Is a key for adjusting the brightness of the display.
[0017]
FIG. 5 shows an example of a screen displayed on the LCD panel 26.
As shown in FIG. 5, on the LCD screen, color mode, automatic density, manual density, image quality mode (automatic image separation), automatic paper selection, paper tray, paper automatic scaling, scaling (same size), sorting, There is a mode selection display such as a stack, and further sub-screen selection displays such as create, color processing, double-sided, and variable magnification are also provided.
Further, the LCD panel 26 is used as a touch panel, and a key having the same size as each display unit is set. Some keys can be expanded by pressing the key down.
FIG. 6 shows an example of screen development by pressing the scaling key in FIG.
When the scaling key is pressed, the scaling setting screen is scrolled up from the bottom of the screen. In the scaling setting screen, a key ← for a standard scaling (a scaling mode in which a scaling ratio is set in advance) is set. For example, when a 71% touch panel key is pressed, a scaling factor of 71% is selected. In this screen, a zoom key, a size scaling key, and an independent scaling / enlarged continuous shooting key are set on the left side of the screen to select a scaling mode other than the standard scaling.
[0018]
The touch panel detection circuit and its operation will be described.
FIG. 7 is a diagram illustrating an example of the configuration of the touch panel detection circuit. FIG. 8 shows a setting state of potentials of the X and Y electrodes of the touch panel in the detection circuit of FIG.
As shown in FIG. 7, the touch panel detection circuit includes a touch panel 71, a controller 72, an A / D converter 73, and an operation switching circuit.
The controller 72 sets the detection terminal to the high state, and sets the potentials X1, X2, Yl, and Y2 of each electrode of the touch panel 71 as shown in FIG. Since the Yl and Y2 circuits are pulled up by resistors, Yl becomes + 5v when the touch panel 71 is OFF, and 0v when the touch panel 71 is ON. Therefore, the ON / OFF state is confirmed from the output of the A / D converter 73. When the controller 72 detects the ON state of the touch panel 71, the controller 72 switches to the measurement mode. In the X direction, X1 is + 5v and X2 is 0v, and the potential at the input position is connected to the A / D converter 73 through Yl to calculate coordinates. Also, the coordinates in the Y direction are calculated in the same manner by switching circuits. By such a detection circuit, the pressed position of the touch panel 71 is detected.
[0019]
Regarding the operation unit 5 in which the above-described image display unit and various input keys are integrated on the operation panel (see FIG. 2), the circuit configuration and the outline of the operation will be described below.
FIG. 9 is a functional block diagram illustrating an example of the circuit configuration of the operation unit.
As shown in FIG. 9, the operation unit 5 includes a CPU 53, an address latch 54, an LCDC (LCD controller) 55, an address decoder 56, a system reset 57, a ROM 58, an LED driver 59, a keyboard 60, a touch panel 61, an LCD module 62, and a ROM 63. RAM 64 and optical transceiver 65 are provided.
[0020]
The address signal from the CPU 53 is taken into the address latch 54, and the address signal is given to each memory for access control to the memory. Part of the address signal output from the address latch 54 enters the address decoder 56, where a chip select signal for each IC is generated and used to create a memory map. The address enters the ROM 58 (or RAM) memory or LCDC 55 and is used for address designation.
On the other hand, a data bus from the CPU 53 is connected to the ROM 58 and the LCDC 55 to perform bidirectional data communication. In addition to the address bus and data bus from the CPU 53, the LCDC 55 is connected to an LED driver 59, a keyboard 60, an analog touch panel 61, an LCD module 62, a display data ROM 63, a RAM 64, and the like.
The LCDC 55 creates display data from the data in the ROM 63 and the RAM 64 by a signal from the keyboard or a signal from the touch panel 61, and controls the screen display of the LCD module 62. Further, an optical transceiver 65 as an optical fiber connector is connected to the CPU 53 and performs communication with the outside.
[0021]
Next, an image reading apparatus to which the present invention is applied, which is installed in the above-described digital color copying machine, will be described in more detail below.
FIGS. 10 and 11 are overall block diagrams mainly showing the processing system of the read image signal and the scanner (image reading unit 2) control system of the color image reading apparatus of this embodiment.
The function of each element constituting this processing / control system (hereinafter referred to as a scanner IPU (image processing unit) controller) will be described with reference to FIG.
[0022]
The CPU 101 on the scanner IPU control unit controls the entire scanner IPU control unit by executing a program stored in the ROM 102 and reading / writing data and the like in the RAM 103. The CPU 101 is connected to the system control unit 104 by serial communication, and performs an operation instructed by transmission / reception of commands and data. The system control unit 104 is connected to the operation display unit 105 through serial communication, and can set an instruction such as an operation mode by a key input instruction from the user (the system control unit relates to the system control unit 1 in FIG. 1). See description above).
On the other hand, the CPU 101 is connected to an original detection sensor, an HP sensor, a pressure plate open / close sensor, a cooling fan, and the like constituting the 1 / O 106, and controls operations such as detection and ON / OFF in the 1 / O 106. The scanner motor driver 107 is driven by the PWM output from the CPU 101, generates an excitation pulse sequence, and drives the pulse motor 108 for scanning the original.
[0023]
The document image is illuminated by a halogen lamp 110 driven under a lamp regulator 109, and the reflected light from the document surface is imaged on the light receiving surface of the three-line CCD 111 through a plurality of mirrors and lenses, thereby reading the image on the document surface. It is done.
The 3-line CCD 111 is given a drive clock to each line by the timing circuit 112 on the scanner IPU control unit, and each odd-numbered field (red, green, blue (hereinafter referred to as “R”, “G”, “B” respectively)) Hereinafter, analog image signals of even fields (hereinafter referred to as “EVEN”) are output to the emitter followers 113 to 115.
Analog outputs from the emitter followers 113 to 115 are input to the analog processing circuits 116 to 118, respectively, a subtraction method CDS is executed in the analog processing circuit, line clamping is performed by detecting the optical black portion of the CCD, and ODD and EVEN Each amplifier gain adjustment is performed to correct the output difference. After gain adjustment, the signals are combined by a multiplexer, and finally, after the DC level offset adjustment (detailed in the operation of the phase adjustment mode described later), the R, G, and B signals are converted into RGB A / D converters ( (Hereinafter referred to as [ADC]) 119-121.
[0024]
The R, G, and B analog signals input to the ADCs 119 to 121 are digitized and input to the shading correction circuit 122.
The shading correction circuit 122 has a function of correcting unevenness in the amount of light in the illumination system and variation in CCD pixel output. The shading-corrected image data is input to the inter-line correction memories 123 and 124, and the image data of the number of lines B and G, B and R of the 3-line CCD is delayed in the memory, and the read image signals of B, G and R are delayed. Are aligned to one or more lines and output to the dot correction circuit 125.
The dot correction circuit 125 corrects the misalignment of dots within one line of R, G, and B data in the image data output from the interline correction memories 123 and 124. Next, the reflectance gamma data is corrected by the look-up table method by the scanner γ correction 126 for each color.
[0025]
The corrected image data is input to the RGB filter / color conversion process / magnification process / create process circuit 130 via the automatic document color determination circuit 128, the automatic image separation circuit 129, and the delay memory 127.
The automatic document color determination circuit 128 performs ACS (chromatic / achromatic determination) processing, that is, determination of black and gray. The automatic image separation circuit 129 also performs edge determination (determined by the continuity of white and black pixels), halftone determination (determined by the repetitive pattern of peak / valley peak pixels in the image), and photo determination (character / halftone dot). If there is image data outside), the area of the character and print (halftone dot) part and the photograph part is determined and transmitted to the CPU 101, and the subsequent RGB filter, color conversion, printer gamma correction, YMCK filter, gradation processing Used to switch parameters and coefficients.
[0026]
The R, G, B image data that has passed through the delay memory 127 is input to the RGB filter of the RGB filter, color conversion process, scaling process, and create process circuit 130. The RGB filter performs processing such as R, G, and B MTF correction, smoothing, edge enhancement, and through by switching and setting filter coefficients in accordance with the determination result of the previous region. In the subsequent color conversion processing circuit, YMCK conversion, UCR, UCA processing is executed from the R, G, B data. Further, enlargement / reduction processing is executed on the main scanning image data input to the scaling processing circuit.
After this processing, the image data is branched, and a part of the branched image data is input to the image display unit 132 via the I / F. In this way, the read image can be displayed on the LCD panel (see FIG. 3) surface of the image display unit 132 in the digital color copying machine, and the read result can be monitored.
The create processing circuit performs create editing and color processing. In create editing, italics, mirroring, shadowing, hollowing processing, etc. are executed. In color processing, color conversion, specified color deletion, undercolor processing, and the like are performed.
[0027]
  The write processing circuit 131 such as printer γ correction and YMCK filter sets coefficients used for printer γ conversion and YMCK filter based on the determination of the previous area. Dither processing is performed in the gradation processing included in the writing processing, and video timing allows setting of writing timing, setting of image areas and white areas, and generation of test patterns such as gray scales and color patches. Is processed so that it can be output to an LD (laser diode) and output to the LD. The execution of each of the above function processes is connected to the CPU 101.TheThis is because the setting and operation of each process is performed by an instruction from the system control unit 104 by a program stored in the ROM 102.
[0028]
  Here, the processing system of the read image signal, which is a part deeply related to the present invention, in the scanner IPU control unit of the color image reading apparatus of the above-described embodiment will be described in detail. FIG. 12 is a block diagram of the processing system of the read image signal, and shows a part of the processing system shown in FIGS. In addition, the same code | symbol is attached | subjected to the same component as shown in both figures. Figure10The operation of the processing system will be described focusing on the timing control operation of the drive clock signal related to the processing of the read image signal of this embodiment. The timing circuit 112 outputs an ADCLK signal (ADC sampling clock) to the ADCs (for R, G, B) 119 to 121 and an ICLK signal (image processing system signal clock) to the digital processing system after the shading correction circuit 122. The timing circuit 112 also outputs a drive clock to the 3-line CCD 111, an analog processing system, and the like. With this drive clock, the 3-line CCD 111 outputs an analog signal as a CCD output for each of ODD and EVEN for each of R, G, and B. Similarly, the analog processing circuits 116 to 118 separately process ODD and EVEN, and then synthesize them. Are output as input signals to the ADCs 119 to 121. These signal waveforms and the timing between signals are shown in the timing chart of FIG. This figure is generated based on the scanner image CLK and the CCD sync line that have the same period as the basic clock from the oscillator and the OLSYNC (line synchronization signal) determined according to the CCD line and the quadruple CLK that is four times the basic clock. In addition to ADCLK and ICLK, the CCD output driven by the scanner image CLK and the output timing of the synthesized analog image signal (ADC input signal) in the analog processing circuit for processing the CCD output are shown.
[0029]
Next, the phase adjustment of the drive clock ADCLK signal to the ADCs 119 to 121 output from the timing circuit 112 and the drive clock ICLK signal to the digital processing system after the ADCs 119 to 121 will be described.
A phase adjustment instruction is sent from the CPU 101 to the timing circuit 112 via the address bus / data bus, and is performed by writing adjustment data to the ADCLK and ICLK phase adjustment registers provided in the timing circuit 112 via the bus I / F. A control signal is output by this adjustment data value, and phase adjustment is performed.
The basic clock of the timing circuit 112 is input from an oscillator (not shown). In this example, the basic clock frequency of the oscillator is the same as the scanner image clock frequency, and the PLL circuit generates a quadruple clock (see FIG. 13). Both the quadruple CLK and the basic CLK (scanner image CLK) are used as the phase adjustment circuit. The phase is input and adjusted, and then output to the ADCs 119 to 121 and each digital processing circuit.
[0030]
  The ADCLK and ICLK phase adjustment registers are the following 8-bit registers.
[ADCLK, ICLK phase adjustment register (8 bits)]
D7 D6 D5 D4 D3 D2 D1 D0
− − − − − SEL ADC1 ADC0
  In the 8-bit phase adjustment register, ADCLK and ICLK signal phase adjustment data are written in 2 bits (ADCO and ADC1 bits) of D0 and D1, and ADCLK and ICLK phase adjustment selection data are written in 1 bit (SEL bit) of D2. It has become.
  When the SEL bit is “0”, a mode for adjusting ADCLK and ICLK in the same phase is selected, and when “1”, the mode for adjusting the phase of only ADCLK while ICLK is fixed can be selected.
  These twoAdjustmentThe reason for the mode isOf each adjustment modeThe digital data output timing of the ADCs 119 to 121 to be used and the settling time and hold time of the subsequent digital processing circuit are within the allowable range.modechooseTo be able to. For example, even when a newly developed ADC is adopted and the circuit configuration is changed, the sampling clock and the digital data output timing are changed.
[0031]
In this example, since the ADCLK and ICLK signals are generated using the quadruple clock, the phase adjustment becomes 4 patterns from the signal cycle of the quadruple clock. It goes without saying that the number of resolution bits differs depending on how many times the PLL circuit selects.
14 and 15 show four patterns of ADCLK and ICLK signals that are phase-adjusted by the signal period of the quadruple clock. Each figure is a timing chart when the set value of the register is changed in four stages (x0h to x3h). FIG. 14 shows a case where ADCLK and ICLK are adjusted in the same phase. FIG. Only an example in the case of phase adjustment is shown.
When executing the above, the ADCLK and ICLK signals are set by the initial setting of the software of the CPU 101 executed when the power is turned on. Therefore, when changing the phase adjustment, it is necessary to change the software.
It is also possible to adjust the phase without changing the software. For example, the phase adjustment may be performed by switching the DIP switch on the control board or the SP mode of the operation display unit 105. . In the case of a change from the operation display unit 105, the phase adjustment data input from the operation display unit 105 is transmitted as serial communication data to the CPU 101 of the scanner IPU control unit via the system control unit 104, and the received phase adjustment data is received by the CPU 101. The adjustment operation is performed based on the data.
[0032]
  Next, an embodiment of a method for adjusting the phase of the ADCLK and ICLK signals will be described below. Here, the output change when the adjustment amount is changed is detected, and the optimum adjustment amount is selected based on the detection result. To execute this phase adjustment operation mode, the phase of ADCLK and ICLK signals is changed, the digital image output is detected when changed, the detection result is evaluated, and the phase adjustment data is determined according to the evaluation. Need. In this embodiment, the analog processing circuits 116 to 118, the ADCs 119 to 121, and the shading correction circuit (digital value detection circuit) 122 are made to perform the phase adjustment mode, and the image signal output after being processed by the ADCs 119 to 121 at that time is processed. Detects image signal output after being driven and processed by ADCLK and ICLK signals whose phase has been changed using a digital value detection circuit that is also used as shading correction circuit 122 without providing a new circuit for detection. And try to evaluate it.
[0033]
Hereinafter, the phase adjustment mode of this embodiment will be described in detail.
When an ADC phase adjustment key (not shown) on the SP mode of the operation display unit 105 is pressed, the ADC phase adjustment mode is executed. The CPU 101 notifies the shading correction circuit 122 of the shift to the ADC phase adjustment mode to the register setting unit in the circuit via the bus I / F. As a result, the memory used as the white memory for normal shading correction is read and the average value for each dot (for example, the average of 10 lines) of the image data can be memorized. A detection circuit is used.
Here, a case where ADCLK and ICLK are adjusted in the same phase with the SEL bit of the ADCLK and ICLK phase adjustment registers set to “0” will be described.
[0034]
FIG. 16 shows a flowchart of the ADC phase adjustment mode.
The operation in the ADC phase adjustment mode will be described according to the flow shown in FIG. It should be noted that the step numbers shown in FIG.
This flow is started by pressing the ADC phase adjustment key of the operation display unit 105. First, the shading correction circuit 122 is notified of the transition to the ADC phase adjustment mode, and is set to the phase adjustment mode in which this is operated as a digital value detection circuit. (S1).
Next, since the phase is adjusted based on the data on the white reference plate, the carriage carrying the illumination system is moved from the home position onto the white reference plate and the exposure lamp is turned on (S2).
The exposed white reference plate is imaged on the 3-line CCD 111, and the ADCLK phase adjustment subroutine is executed by the photoelectric conversion output signal (S3).
After the ADCLK phase adjustment subroutine is completed and the exposure lamp is turned off, the home position is returned (S4), and the original shading correction circuit 122 is operated on the circuit that was operating the digital value detection circuit by setting the phase adjustment mode. (S5), the operation of the ADC phase adjustment mode is completed.
[0035]
The ADCLK phase adjustment subroutine in the operation flow of the ADC phase adjustment mode will be described in detail.
FIG. 17 is a chart showing the operation flow of the ADCLK phase adjustment subroutine. The operation of the ADCLK phase adjustment subroutine will be described according to the flow shown in the figure.
In this flow, in step S3 (FIG. 16) of the ADC phase adjustment mode described above, the exposed white reference plate is imaged on the three-line CCD 111, and line-scanned and photoelectrically converted ODD and EVEN image output signals. Start from where you got it.
In the analog processing circuits 116 to 118, after correcting the output difference between the ODD and EVEN image signals by the white reference plate input from the emitter followers 113 to 115, the signal level difference value between the ODD and EVEN is further fixed to a certain value. Amount: Each gain is adjusted so as to be shifted by A (S301).
[0036]
Next, the CPU 101 writes the set value = x0h to the ADCLK and ICLK phase adjustment registers of the timing circuit 112 (S302).
Here, it is confirmed whether or not the line synchronization signal 10 has been counted in order to take an average of outputs for a set time in a set phase (S303), and after confirmation, the digital that operates in the mode set in the previous step S1 (FIG. 16). The CPU 101 reads the averaged data value for each dot from the memory of the value detection circuit 122 (S304).
The difference between the values obtained by averaging the read line unit data by ODD and EVEN is calculated to obtain the difference value: B, and the value set in the previous step S301: A (between ODD and EVEN Difference (signal level difference), that is, (A−B), the absolute value: | A−B | is obtained as a result: C (S305), and the obtained result C is stored in the RAM (1) (S306). ).
[0037]
Next, the CPU 101 writes a setting value = x1h for setting the next shift value in the ADCLK and ICLK phase adjustment registers of the timing circuit 112 (S307), that is, the state of shift 1 (1 pulse delay) (see FIGS. 14 and 15). As in the previous step, the CPU 101 reads the average value data for each dot from the memory of the previous digital value detection circuit 122 after a certain time necessary for averaging (S308) (S309).
The same processing as described above is executed from the read line unit data, C = | A−B | is calculated (S310), and the obtained result is stored in the RAM (2) (S311).
Next, the CPU 101 writes a setting value = x3h for setting the next shift value in the ADCLK and ICLK phase adjustment registers of the timing circuit 112 (S312), that is, the state of shift 4 (advance by one pulse) (see FIGS. 14 and 15). As in the previous step, the CPU 101 reads the average value data for each dot from the memory of the previous digital value detection circuit 122 after a predetermined time required for averaging (S313).
The same processing as described above is executed from the read line unit data, C = | A−B | is calculated (S315), and the obtained result is stored in the RAM (3) (S316).
Result obtained at each shift position and stored in RAMs {circle around (1)} to {circle around (3)}: C = | A−B | is compared to determine the best phase adjustment data (S317), and the determined x0h Any one of .about.x3h is set in the ADCLK and ICLK phase adjustment registers (S318) to complete the ADCLK phase adjustment subroutine.
[0038]
In this example, the quadruple clock is generated by the PLL circuit as the phase adjustment. However, the resolution may be increased by using the 8th and 16th clocks, and the adjustment may be performed with better accuracy. In this case, a good result can be obtained by determining several phases of phase delay and advance pulses from the reference position and comparing the data in the previous calculation to determine the phase.
In the present invention, gain adjustment is performed for ODD and EVEN image data so that the difference between the signal levels of the two is shifted by a certain amount: A. By making a difference between the image signal levels of ODD and EVEN, if sampling is not performed at the correct position, the data at the change point will be captured. Therefore, B (line unit data is averaged by ODD and EVEN. The difference value between the obtained values becomes smaller, and the result C becomes a larger value. That is, if the value of the result C is small, sampling is performed at an appropriate position. For example, the pixel position and the A / D conversion sampling position can be easily visually confirmed with an oscilloscope or the like. It becomes easy to judge.
[0039]
【The invention's effect】
(1) Since the drive clock of the line image sensor and A / D converter (ADC) has been conventionally generated by the timing LSI, it must be changed by hardware such as inserting a delay line when adjusting the timing. However, according to the present invention, a clock generation means capable of adjusting the output timing of the drive clock by phase adjustment data is provided, and the entire apparatus is controlled by a register in the clock generation means. By writing the adjustment data from the CPU via the data bus, the clock is generated without changing the hardware (such as inserting a conventional delay line) in the delayed phase or advanced phase. Gate and sample hold at appropriate output position to drive line image sensor and ADC Theft is possible.
In addition, in order to reduce radiated noise that is performed in accordance with EMI regulations, it is necessary to deal with the CCD drive clock, analog processing execution clock, and ADC clock by smoothing the clock waveform by inserting filters and damping resistors and changing constants. In some cases, a delay occurs at the rise and fall of the clock, resulting in a delay in signal output. For this reason, the insertion of filters and damping resistors and the change of constants have only to be adjusted at a level that does not affect the image data. However, according to the present invention, the phase can be adjusted even if the delay occurs. The adverse effects due to the countermeasures can be prevented, and even under such conditions, the signal output can be sampled with good timing, the radiation noise level can be greatly reduced, and the range of use can be expanded.
[0040]
(2) In addition to the effect of (1) above, digital data obtained by converting the analog image signal photoelectrically converted from the line image sensor by ADC is detected, and phase adjustment data generated based on the detection result is used. By adjusting the timing of the drive clock, the ADC can be driven by sampling and holding at a more appropriate output position.
[0041]
(3) In addition to the effects (1) and (2) above, an analog processing means is provided for adjusting the gain of the analog image signal so as to give an offset to the DC level after correcting the output difference between ODD and EVEN. Therefore, if phase adjustment can be performed at the proper position (gate, sample), the same data value as the level difference given to ODD and EVEN is taken, and if it is not at the proper position (for example, pixel change point), gain adjustment Phase adjustment because it is possible to provide easy-to-process data results when judging changes in output values, such as making it easy to visually check the pixel position and A / D conversion sampling position with an oscilloscope, etc. It is possible to increase the accuracy of.
[0042]
(4) In addition to the effects of (1) to (3) above, the phase adjustment data adjustment step is a 1 / integer of the period of the pixel clock (ADC drive clock) using a PLL multiplier circuit or the like. By eliminating the accumulation and accumulation of the gate delay amount as the length, a more accurate phase adjustment is possible.
[0043]
(5) In addition to the effects (1) to (4) above, the adjustment width of the phase adjustment data extends over one period of the pixel clock (ADC drive clock), so that adjustment for one period can be performed. Therefore, not only the delay direction but also the advance direction can be adjusted, and an optimum operation becomes possible.
[0044]
(6) In addition to the effects (1) to (5) above, the digital data detection means uses the memory holding the detection data also as the memory of the shading correction means. Further, it is possible to suppress an increase in cost when an expensive memory is newly prepared only for phase adjustment.
[Brief description of the drawings]
FIG. 1 is a diagram showing an outline of the overall configuration of a digital color copying machine that can suitably implement an image reading apparatus of the present invention.
FIG. 2 is a diagram showing an example of an operation panel of an operation unit unit of the digital color copying machine shown in FIG.
3 is a functional block diagram showing a circuit configuration of an image display unit of the digital color copying machine shown in FIG. 1. FIG.
4 is a diagram showing an embodiment of the LCD panel of the image display unit shown in FIG. 3;
5 is a diagram showing an example of a screen displayed on the LCD panel shown in FIG. 4. FIG.
6 shows an example of screen expansion by pressing a scaling key on the screen shown in FIG.
FIG. 7 is a diagram illustrating an example of a configuration of a touch panel detection circuit.
8 illustrates a setting state of potentials of X and Y electrodes of the touch panel in the detection circuit of FIG.
9 is a functional block diagram showing an example of a circuit configuration of an operation unit of the digital color copying machine shown in FIG. 1. FIG.
FIG. 10 is an overall block diagram (No. 1) mainly showing a processing system of a read image signal and a scanner control system of a color image reading apparatus to which the present invention is applied.
FIG. 11 is an overall block diagram (No. 2) mainly showing a processing system of a read image signal and a scanner control system of a color image reading apparatus to which the present invention is applied.
FIG. 12 is a block diagram of a processing system of a read image signal in an image reading apparatus to which the present invention is applied.
FIG. 13 is a chart showing each signal waveform and timing between signals in a processing system of a read image signal.
FIG. 14 shows four patterns of ADCLK and ICLK signals (same phase) adjusted in phase by a signal period of a quadruple clock.
FIG. 15 shows four patterns of an ADCLK signal (ICLK signal fixed) whose phase is adjusted by a signal period of a quadruple clock.
FIG. 16 is a chart showing an operation flow in an ADCLK phase adjustment mode.
FIG. 17 is a chart showing an operation flow of an ADCLK phase adjustment subroutine.
[Explanation of symbols]
101 ... CPU, 104 ... System control unit,
105 ... Operation display section 111 ... 3-line CCD,
112 ... Timing circuit, 116-118 ... Analog processing circuit (for R, G, B),
119 to 121 ... ADC (A / D converter) (for R, G, B),
122: Shading correction circuit (digital value detection circuit).

Claims (4)

A line image sensor for reading images;
A / D conversion means for converting an analog image signal output from the line image sensor into digital image data;
And digital data detection means for detecting the digital image data from the A / D conversion means,
Drive clock generation means for generating each drive clock for operating the line image sensor and A / D conversion means;
Analog processing means for outputting the line to each ODD and EVEN signal to the gain adjustment of the analog image signal output from the image sensor, the analog signal summarized them into one for the A / D conversion means,
In the image reading apparatus having a phase adjustment means for adjusting the phase of the clock of the line image sensor generated by the driving clock generation means and the A / D conversion means ,
The analog processing means corrects the output difference between the ODD and EVEN signals, then outputs a predetermined DC level difference to the A / D conversion means, and changes the driving by the phase adjustment means. The digital data detection means obtains the difference between the average values of ODD and EVEN for each clock, and adjusts the phase to the case where the difference is closest to the predetermined DC level difference given by the analog processing means. Image reading device. The image reading apparatus according to claim 1 , wherein the adjustment step of the phase adjustment data has a length of 1 / integer of the period of the pixel clock . The image reading apparatus according to claim 1 or 2, characterized in that the adjustment width of the phase adjustment data length over one period of the pixel clock. 2. The image reading apparatus according to claim 1 , wherein a shading correction unit is provided at a subsequent stage of the A / D conversion unit, and the digital data detection unit also serves as a memory for the shading correction unit. The image reading apparatus according to any one of 1 to 3.

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