JP3835100B2 - Signal modulation device, demodulation device and recording medium - Google Patents

Description

【００３３】
【表５】
上記のように変調されたバイナリ系列は、

となる。
【００３４】
ここで、上記実施形態では、３Ｔの前の反転間隔を制限する例について説明したが、図１０に示した記録信号メモリ２により、記録ブロック単位などの所定ビット数毎にビット送出方向を逆方向にすれば、３Ｔの後の反転間隔を制限することができることは明白である。また、図１に示した状態遷移図において、状態の遷移方向、すなわち図１に示す矢印方向を逆にして、前述した方法を用いて符号化テーブル１１を構成すれば、同様に、３Ｔの後の反転間隔を制限できることは明白である。
【００３５】
符号化テーブル１１の生成例について更に詳細に説明する。前述したように図１に示した状態「２」、「７」を２分割して作成すると、異なる入力データ語Ｄ（ｋ）に対して同一の符号語Ｃ（ｋ）が割り当てられている場合がある。例えば図５に示す符号化テーブルＳ（ｎ）＝０を参照すると、入力データ語Ｄ（ｋ）＝０，１に対して同一の符号語Ｃ（ｋ）＝６４が割り当てられている。
【００３６】
このように、同一の符号語Ｃ（ｋ）が異なる入力データ語Ｄ（ｋ）に割り当てられている場合には、本発明の符号化テーブルは復号装置が復号可能なように、後続の符号語Ｃ（ｋ＋１）がどの符号化テーブルにより符号化されたかを検出することができるように構成されている。すなわち、例えば入力データ語Ｄ（ｋ）＝０に対して次に選択する符号化テーブル情報Ｓ（ｎ＋１）は「４」であり、入力データ語Ｄ（ｋ）＝１に対して次に選択する符号化テーブル情報Ｓ（ｎ＋１）は「５」である。したがって、符号化テーブルＳ（ｎ）＝４と符号化テーブルＳ（ｎ）＝５により生成される符号語が全て異なっていれば、同一の符号語が異なるデータ語に割り当てられていても、元のデータ語に復号することができる。
【００３７】
この第１の実施形態の符号化テーブル１１では、一例として次に選択する符号化テーブル情報Ｓ（ｎ＋１）＝２、３において、また、Ｓ（ｎ＋１）＝４、５において、同一の符号語Ｃ（ｋ）が異なる入力データ語Ｄ（ｋ）に割り当てられている。このため、符号化テーブルＳ（ｎ）＝２、３により生成される符号語Ｃ（ｋ）は同じものが存在せず、また、符号化テーブルＳ（ｎ）＝４、５により生成される符号語Ｃ（ｋ）にも同じものが存在しない。さらに、符号化テーブルＳ（ｎ）＝２、３間、及びＳ（ｎ）＝４、５間における同じ符号語Ｃ（ｋ）は、同じ入力データ語Ｄ（ｋ）により生成されるように配置されている。
【００３８】
＜第２の実施形態＞
上記の第１の実施形態によれば、伝送媒体がＤＳＶ制御を必要としない場合に適用することができる。次に伝送媒体がＤＳＶ制御を必要とする場合に対応することができる第２の実施形態について説明する。まず、符号語Ｃ（ｋ）をＮＲＺＩ変調した場合の極性について説明する。図５〜図９に示す符号化テーブルＳ（ｎ）＝０、１において、入力データ語Ｄ（ｋ）＝０〜１１７に対応する符号語Ｃ（ｋ）は、３Ｔの前の最大反転間隔が８Ｔとなる符号化規則を満たす場合に、符号化テーブルＳ（ｎ）＝３における入力データ語Ｄ（ｋ）＝０〜１１７に対応する符号語Ｃ（ｋ）と入れ替え可能になるように配置されている。さらに、これらの入れ替え可能な符号語Ｃ（ｋ）間においては、次に選択する符号化テーブル情報Ｓ（ｎ＋１）が同一になるように符号語Ｃ（ｋ）が配置されている。また、入れ替え可能な符号語Ｃ（ｋ）間においては、符号語Ｃ（ｋ）の「１」の数の偶奇が異なるように配置がなされ、このため、符号語Ｃ（ｋ）をＮＲＺＩ変調した場合の記録データＳ１の極性がお互いに逆極性となる。
【００３９】
また、符号化テーブルＳ（ｎ）＝５において、入力データ語Ｄ（ｋ）＝０〜３３に対して、入れ替え可能な符号語Ｃ（ｋ）が図５〜図９に示す符号化テーブルにおける符号語以外にもあり、これらの符号語についても同様に、３Ｔの前の最大反転間隔が８Ｔとなる符号化規則を満たす場合に符号語の入れ替えが可能であってＤＳＶ極性が逆となる。図１１〜図１３は第２の符号化テーブルとして、Ｓ（ｎ）＝０、１、５において入れ替え可能な部分（入力データ語Ｄ（ｋ）＝０〜１１７）を示している。なお、図１１〜図１３において１６ビット符号語Ｃ（ｋ）がオール０と記された入力データ語Ｄ（ｋ）に関しては、入れ替え可能な符号語Ｃ（ｋ）が存在しないことを示している。
【００４０】
次に図１４〜図１６を参照して第２の実施形態の変調装置を詳しく説明する。なお、この例ではＤＳＶ（デジタル・サム・バリエーション）の判定を行うための符号語メモリは２つであるが、更に多くの符号語メモリを用いることができる。また、この例では符号語メモリの選択をある時点までのＤＳＶの値に基づいて行っているが、さらに先のＤＳＶの値を演算予測して符号語メモリを選択することもできる。
【００４１】
図１４に示す符号化テーブル１１ａは、第１の実施形態の図５〜図９に示した符号化テーブル１１（第１の符号化テーブル）と図１１〜図１３に示す第２の符号化テーブルを有する。符号語選択肢有無検出回路２１は入力データ語Ｄ（ｋ）と符号化テーブル１１ａからの符号化テーブル情報Ｓ（ｎ）に基づいて、前記のようにＮＲＺＩ極性が逆であって、図１１〜図１３に示すように入れ替え可能な符号語Ｃ（ｋ）が存在するか否かを検出するとともに、入れ替えした場合には符号化規則を維持するか否かを検出して選択肢検出結果を符号化テーブルアドレス演算部２２と絶対値比較回路２５に出力する。符号化テーブルアドレス演算部２２はこの選択肢検出結果と符号化テーブル１１ａからの符号化テーブル情報Ｓ（ｎ）に基づいて、入力データ語Ｄ（ｋ）と符号化テーブル情報Ｓ（ｎ）に対応する符号化テーブルアドレスを計算する。
【００４２】
符号化テーブル１１ａはこのアドレスに基づいて第１、第２のテーブルから２つの符号語候補Ｃ（ｋ）０、Ｃ（ｋ）１を出力する。ここで、符号語の選択肢がない場合には２つの符号語候補Ｃ（ｋ）０、Ｃ（ｋ）１として第１のテーブルから１つの同じ符号語を出力する。符号語候補Ｃ（ｋ）０はＤＳＶ演算メモリ２３−０と符号語メモリ２４−０に印加され、符号語候補Ｃ（ｋ）１はＤＳＶ演算メモリ２３−１と符号語メモリ２４−１に印加される。そして、符号語候補Ｃ（ｋ）０、Ｃ（ｋ）１の各ＣＤＳ（コードワード・デジタル・サム）値が計算され、符号語メモリ２４−０、２４−１にそれぞれ蓄えられた符号語列に対するＤＳＶの加算値がＤＳＶ演算メモリ２３−０、２３−１に保持される。
【００４３】
一方、絶対値比較回路２５は符号語選択肢有無検出回路２１からの選択肢検出結果に基づいて、入力データ語Ｄ（ｋ）に対する符号語があった場合には、その時点までに（すなわち時点ｋ−１までに）ＤＳＶ演算メモリ２３−０、２３−１に保持された各ＤＳＶの加算値の絶対値を比較し、比較結果をメモリ制御／符号出力部２６に送る。メモリ制御／符号出力部２６は、この比較結果に基づいて、ＤＳＶの加算値の絶対値が小さい方の符号語メモリ２４に蓄えられた符号語列を出力符号語列として選択するメモリ制御信号を出力するとともに、選択しなかった方の符号語列のＤＳＶ加算値と符号語メモリ２４の符号語列を、それぞれ選択した方の符号語列のＤＳＶ加算値と符号語メモリ２４の符号語列として入れ替える。
【００４４】
図１５、図１６に示すフローチャートを参照して詳しく説明する。まず、図１５において初期テーブルを選択し（ステップＳ１）、次いで８ビットデータが入力されると（ステップＳ２）、図１１〜図１３に示す第２のテーブルに入れ替え可能な符号語Ｃ（ｋ）が存在するか否かを検出し（ステップＳ３）、有る場合にはステップＳ４以下に進み、他方、無い場合にはステップＳ７に進む。
【００４５】
図１６はステップＳ３における符号語選択肢有無検出処理を詳しく示している。入力データ語Ｄ（ｋ）と符号化テーブル情報Ｓ（ｎ）が入力されると（ステップＳ１０）、図１１〜図１３に示す第２のテーブルに入れ替え可能な符号語Ｃ（ｋ）が存在するか否かを検出し（ステップＳ１１）、有る場合にはステップＳ１２に進み、他方、無い場合には「入れ替え符号語無し」と判断し（ステップＳ１４）、図１５に示すステップＳ７に進む。ステップＳ１２では図１１〜図１３に示す第２のテーブルから符号語Ｃ（ｋ）を選択しても符号化規則を維持できるか否かを検出し、維持できる場合には「入れ替え符号語有り」と判断し（ステップＳ１３）、次いで図１５に示すステップＳ４に進む。他方、維持できない場合にはステップＳ１４に進む。
【００４６】
ステップＳ４以下では、ＤＳＶ演算メモリ２３−０、２３−１を参照して｜ＤＳＶ｜の小さい方の符号語メモリ２４を選択してその符号語列を出力し（ステップＳ４）、次いで選択しなかった方の符号語メモリ２４とＤＳＶ演算メモリ２３の内容を選択した方の符号語メモリ２４とＤＳＶ演算メモリ２３の内容として入れ替える（ステップＳ５）。
【００４７】
次いで図５〜図９に示す第１のテーブルと図１１〜図１３に示す第２のテーブルから２つの符号語候補Ｃ（ｋ）０、Ｃ（ｋ）１を選択し（ステップＳ６）、次いでステップＳ７に進む。ステップＳ７では符号語候補Ｃ（ｋ）０、Ｃ（ｋ）１をそれぞれ符号語メモリ２４−０、２４−１に付加し、次いでは符号語候補Ｃ（ｋ）０、Ｃ（ｋ）１それぞれについてＣＤＳを演算してこれをＤＳＶ演算メモリ２３−０、２３−１に加算し（ステップＳ８）、次いでステップＳ２に戻る。
【００４８】
次に図１７〜図２０を参照して復号装置について説明する。図１７において、不図示の記録媒体から再生されたシリアルビット系列の符号語系列と、図示せぬＰＬＬ回路などにより生成されて符号化ビットに同期するビットクロックが同期語検出部３１とシリアル／パラレル変換器３２に印加される。同期語検出部３１では、記録符号系列に記録単位毎に挿入された同期語とビットクロックに基づいて符号語Ｃ（ｋ）単位のクロックであるワードクロックを生成し、これをシリアル／パラレル変換器３２と、復号テーブル参照アドレス生成部３３と復号テーブル／符号化テーブル演算器／選択器３４に印加する。シリアル／パラレル変換器３２はビットクロックとワードクロックに基づいて、シリアルビット系列の符号語系列をワード単位のビットパラレル構成の符号語Ｃ（ｋ）を生成し、これを復号テーブル参照アドレス生成部３３に出力する。
【００４９】
復号テーブル参照アドレス生成部３３では、符号語Ｃ（ｋ）とワードクロックに基づいて復号テーブル４１（図１９）の参照アドレスを生成し、この第２の実施形態では、符号語Ｃ（ｋ）をそのまま復号テーブル４１の参照アドレスとして用いる。なお、代わりに復号テーブル４１の構成を変えてその容量を少なくし、復号テーブル参照アドレス生成部３３により復号テーブル４１の参照アドレスを演算するようにしてもよい。
【００５０】
図１８は復号テーブル／符号化テーブル演算器／選択器３４を詳しく示し、図１９は図１８の復号テーブル４１の構成を詳しく示している。復号テーブル４１には１６ビットの参照アドレスＣ（ｋ）に対して、２ビットの判定情報Case（ケース）と、各々が共に８ビットの２つのデータ語候補Ｄ（ｋ）０、Ｄ（ｋ）１があらかじめ記憶され、参照アドレスＣ（ｋ）が入力するとデータ語候補Ｄ（ｋ）０、Ｄ（ｋ）１が１ワード遅延部４２を介して選択器４３に印加されるとともに、判定情報Caseが１ワード遅延部４４を介して符号化テーブル演算器４５に印加される。そして、符号化テーブル演算器４５は判定情報Caseに基づいて、選択器４３がデータ語候補Ｄ（ｋ）０、Ｄ（ｋ）１のいずれか１つを選択するための信号を生成する。
【００５１】
符号化テーブル演算器４５の処理を図２０においてＣ言語（一部異なる記述あり）で示す。図２０における
Ｃ（ｋ）∈［Ｃ（ｋ） of （Ｓ（ｎ）＝２）］
は、図５〜図９、図１１〜図１３に示す符号化テーブルにおいて符号語Ｃ（ｋ）が符号化テーブルＳ（ｎ）＝２により符号化されたことを示している。図１９を参照すると、例えば符号語Ｃ（ｋ）が３４、１２８のように入力した場合、前の符号語Ｃ（ｋ）＝３４の場合の判定情報Caseは「２」であるので、次の符号語Ｃ（ｋ）＝１２８が符号化テーブルＳ（ｎ）＝２により符号化されていることがわかり、前の符号語Ｃ（ｋ）＝３４に対して、データ語候補Ｄ（ｋ）０＝２５１、Ｄ（ｋ）１＝２５２の内、データ語Ｄ（ｋ）＝２５２が選択され、これにより復号される。
【００５２】
【発明の効果】
以上説明したように本発明によれば、前後の符号語を直接結合した符号語列をＮＲＺＩ変換した場合の最短符号反転間隔がｄ＋１チャネルビット、最長符号反転間隔がｋ＋１チャネルビット（ｄ、ｋは共に正の整数）に制限される場合、ｄ＋１チャネルビットの最短符号反転間隔が発生する符号語の直前又は直後の符号語の反転間隔がｋ＋１チャネルビットより短くなるように符号化するようにしたので、最短符号反転間隔に対して直後又は直前の符号反転間隔が与える影響を低減することができ、ひいては記録密度を向上させることができる。
【図面の簡単な説明】
【図１】本発明に係る符号器の状態遷移を示す説明図である。
【図２】本発明に係る符号化テーブルの作成過程において用いられる行列を示す説明図である。
【図３】本発明に係る符号化テーブルの作成過程において用いられる行列を示す説明図である。
【図４】本発明に係る符号化テーブルの作成過程を示す説明図である。
【図５】本発明に係る符号化テーブル（その１）を示す説明図である。
【図６】本発明に係る符号化テーブル（その２）を示す説明図である。
【図７】本発明に係る符号化テーブル（その３）を示す説明図である。
【図８】本発明に係る符号化テーブル（その４）を示す説明図である。
【図９】本発明に係る符号化テーブル（その５）を示す説明図である。
【図１０】本発明に係る変調装置の第１の実施形態を示すブロック図である。
【図１１】第２の実施形態の第２の符号化テーブル（その１）を示す説明図である。
【図１２】第２の実施形態の第２の符号化テーブル（その２）を示す説明図である。
【図１３】第２の実施形態の第２の符号化テーブル（その３）を示す説明図である。
【図１４】第２の実施形態の変調装置を示すブロック図である。
【図１５】第２の実施形態の変調処理を説明するためのフローチャートである。
【図１６】図１５の判別ステップの処理を詳しく説明するためのフローチャートである。
【図１７】本発明に係る復調装置の一実施形態を示すブロック図である。
【図１８】図１７の復号テーブル／符号化テーブル演算器／選択器を詳しく示すブロック図である。
【図１９】図１８の復号テーブルを示す説明図である。
【図２０】図１９の符号化テーブル演算器の処理を示す説明図である。
【図２１】ＲＬＬ（２，１０）の符号化器の状態遷移を示す説明図である。
【図２２】従来例における符号間干渉を示す説明図である。
【符号の説明】
１１ 符号化テーブル（符号化手段、第１の符号化テーブル）
１１ａ 符号化テーブル（第１、第２の符号化テーブル）
１２，４２ １ワード遅延部
２１ 符号語選択肢有無検出回路（符号化テーブルアドレス演算部２２と共にテーブル読み出し手段を構成する。）
２２ 符号化テーブルアドレス演算部
２３−０，２３−１ ＤＳＶ演算メモリ（ＤＳＶ演算手段）
２４−０，２４−１ 符号語メモリ
２５ 絶対値比較回路
２６ メモリ制御／符号出力部（絶対値比較回路２５と共に選択手段を構成する。）
４１ 復号テーブル
４３ 選択器（選択手段）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal modulation device, a demodulation device, and a recording medium for recording a digital signal on a recording medium such as an optical disk or a magnetic disk.
[0002]
[Prior art]
As a signal modulation method for recording a digital signal on a disk medium using a light beam, an EFM (Eight to Fourteen Modulation: 8-14 modulation) method used for a CD (Compact Disc) or a DVD (Digital An EFM + (EFM plus: 8-16 modulation) system used for Versatile discs is known. In any case, the shortest code inversion interval is 3T (T is the channel bit period) due to the characteristics of so-called RLL (Run Length Limited) (2, 10) due to the limitation of the recording / reproducing characteristics by the optical transmission system and the recording medium. In addition, the longest code inversion interval is limited to 11T for modulation.
[0003]
FIG. 21 shows the state transition of the RLL (2, 10) encoder in the conventional EFM system and EFM + system, and the numbers “0” to “10” shown in the circles indicate the inside of the encoder. Indicates the state. An arrow indicates a case where transition is possible in the encoder, and numerals “0” and “1” attached to the arrow indicate 1-bit data generated by transition from states “0” to “10”. .
[0004]
[Problems to be solved by the invention]
By the way, it is known that when a digital signal is recorded on a recording medium such as an optical disk at a high density and reproduced, intersymbol interference occurs between adjacent pits / lands (marks / spaces) due to insufficient reproduction band. ing. The magnitude of this intersymbol interference varies particularly depending on the length between adjacent pits / lands (marks / spaces). For example, in the EFM system and the EFM + system, it has a long inversion interval length such as 11T or 10T. When the 3T signal, which is the shortest code inversion interval, appears after the reproduction signal, the influence becomes large.
[0005]
FIG. 22 shows the effect when a recording signal (adjacent signal) having an inversion interval from 3T to 11T exists immediately before the 3T signal which is the shortest code inversion interval in the signal modulation method having RLL (2, 10) characteristics. FIG. Thus, it can be seen that the length of the 3T signal deviates from the original length when the inversion interval of the immediately preceding recording signal is increased. FIG. 22 shows the effect of the inversion interval of the immediately preceding recording signal on the 3T signal, but the effect of the inversion interval of the immediately following recording signal on the 3T signal is the same. In this way, the waveform reproduced with a deviation from the original length causes a reproduction error. When the recording density is increased, this effect is noticeable, which hinders the improvement of the recording density.
[0006]
In view of the above problems, the present invention can reduce the influence of the immediately preceding or immediately preceding code inversion interval on the shortest code inversion interval, and thus improve the recording density, and a signal modulation device and demodulator that can improve recording density. It is another object of the present invention to provide a medium recorded with the modulation method.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, the shortest code inversion interval is d + 1 channel bits and the longest code inversion interval is k + 1 channel bits (d and k are When both are limited to positive integers), encoding is performed such that the inversion interval of the codeword immediately before or after the codeword in which the shortest code inversion interval of d + 1 channel bits occurs is shorter than k + 1 channel bits. It is.
[0008]
That is, according to the present invention, a continuous binary input data string is divided into p bits, and a p-bit input data word is converted into a q-bit code word (p <q: p and q are both positive integers). In addition, the preceding and following codewords are directly combined, and when the combined codeword string is subjected to NRZI conversion, the shortest code inversion interval is d + 1 channel bits, the longest code inversion interval is k + 1 channel bits (d and k are both positive) In a signal modulation device limited to an integer),
Encoding means for encoding an input data word into a code word so that the inversion interval of the code word immediately before or after the code word in which the shortest code inversion interval of the d + 1 channel bits occurs is shorter than the k + 1 channel bits;
There is provided a signal modulation device comprising the above.
[0009]
Further, according to the present invention, a continuous binary input data string is divided every p bits, and a p-bit input data word is converted into a q-bit code word (p <q: p and q are both positive integers). In addition, the preceding and following codewords are directly combined, and when the combined codeword string is subjected to NRZI conversion, the shortest code inversion interval is d + 1 channel bits, the longest code inversion interval is k + 1 channel bits (d and k are both positive) In a signal modulation device limited to an integer),
Information for selecting an encoding table that encodes a code word and the next input data word with an input data word as an address is stored, and the code word and the encoding table selection information indicate that the shortest code inversion interval of the d + 1 channel bits is A plurality of first coding tables configured with a coding rule in which the inversion interval of the codeword immediately before or after the generated codeword is shorter than the k + 1 channel bits;
Information for selecting an encoding table for encoding the code word and the next input data word with the input data word as an address is stored, and the polarity when the code word is NRZI converted is the same input in the first encoding table A plurality of second encoding tables having opposite polarity to the code word for the data word and the same information for selecting the next encoding table;
If the encoding rule is satisfied even if the second encoding table is selected, the first and second code word candidates are read from the first and second encoding tables, respectively, and the second code A table reading means for reading the first and second code word candidates having the same value from the first coding table when the coding table is not satisfied when the coding table is selected;
DSV calculating means for calculating the absolute value of the sum of DSV for each of the first and second codeword candidates read by the table reading means;
Means for selecting, as a code word, the first or second code word candidate having a smaller absolute value of the sum of DSVs calculated by the DSV calculating means;
There is provided a signal modulation device comprising the above.
[0010]
According to the present invention, there is also provided a demodulator that demodulates a codeword modulated by the modulator according to any one of claims 1 to 3 into an original input data word,
Determination information indicating which of the plurality of encoding tables the subsequent code word is encoded by using the code word to be demodulated as an address, and a decoding table that outputs two or more input data word candidates;
Selecting means for selecting one of the two or more input data word candidates as an input data word based on the determination information read from the decoding table;
A demodulation device is provided.
[0011]
According to the present invention, there is also provided a recording medium on which a signal modulated by the signal modulation device according to any one of claims 1 to 3 is recorded.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
<First Embodiment>
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram showing state transition of an encoder according to the present invention, FIGS. 2 and 3 are explanatory diagrams showing matrices used in the process of creating an encoding table according to the present invention, and FIG. 4 is a code according to the present invention. FIG. 5 to FIG. 9 are explanatory diagrams showing an encoding table according to the present invention, and FIG. 10 is a block diagram showing an embodiment of a modulation apparatus according to the present invention.
[0013]
The first embodiment shows a case where the transmission medium does not require DSV control. FIG. 1 shows state transitions for configuring the coding table of the present invention, and numerals “0” to “10” shown in the circles indicate the internal state of the encoder. An arrow indicates a case where transition is possible in the encoder, and numerals “0” and “1” attached to the arrow indicate 1-bit data generated by transition from states “0” to “10”. . Here, as an example, a data word of p = 8 bits is converted into a code word of q = 16 bits, and the preceding and following code words are connected in series without using margin bits, and according to the rules of RLL (2, 10) A case will be described in which the shortest inversion interval = 3T and the longest inversion interval = 11T, and the maximum inversion interval immediately before 3T is 8T.
[0014]
In FIG. 1, when the code word 3T occurs, the state transition is
→ “1” → “2” → “3” → “1” →
(However, the code word bit before the state “1” shown first is “1”.)
This is the case only when transition is made. At this time, the code word is
... 1001 ...
When this is NRZI converted, 3T is generated.
[0015]
Where the codeword is
... 1001 ...
If the longest inversion interval occurs just before
“1” → “2” → “3” → “4” → “5” → “6” → “7” → “1” → “2” → “3” → “1”
This is the case only when transition is made. Therefore, since the code word in this case always includes code word = 1 when transitioning to the state “0”,
... 100000001001 ...
Thus, the longest inversion interval of the code word immediately before 3T is 8T.
[0016]
An adjacency matrix (matrix representing a transitionable state) A in the state transition diagram shown in FIG. 1 is given as an 11th order matrix as shown in FIG. In this adjacency matrix A, columns “0” to “10” are assigned to transition start states “0” to “10” in the state transition diagram shown in FIG. 1, and rows “0” to “10” are assigned to transition end states. “0” to “10” are assigned.
[0017]
A codeword with q = 16 bits can be obtained by raising the adjacency matrix A shown in FIG. 2 to the 16th power, and the matrix A shown in FIG. ¹⁶ Given in. Matrix A shown in FIG. ¹⁶ In FIG. 1, for example, the first row and the first column (= 006) have the transition start state “0” and the transition end state “0” in FIG. 6 represents the number of 16-bit codewords that can be generated. In this case, six types of 16-bit codewords can be configured.
[0018]
This matrix A ¹⁶ By using codewords constructed based on the above, a codeword generated from the row is sequentially combined with a codeword that has ended in a state represented by a certain element (row, column), so that q = It is possible to construct a codeword that satisfies 16 and satisfies d = 2 (3T) and k = 10 (11T), and the code inversion interval immediately before the shortest inversion interval is 3T is limited to the longest = 8T. FIG. 4 is generated using the matrix A shown in FIG. 2, and is q = 16 bits, the encoder state starts from “0” to “10”, and the encoder state ends with “0”. All code words are shown (in decimal). As shown in FIG. 4, it can be seen that the number of codewords matches the number of elements shown in FIG.
[0019]
On the other hand, in FIG. 3 in which the matrix A shown in FIG. 2 is raised to the 16th power, if the sum of the elements of each row is 2 to the pth power, that is, 256 or more in this example, the code for transitioning from each state to a certain state is used as it is. An encoding table can be configured. However, in this example, the sum of elements for each row from the first row to the eleventh row, that is, the number of codewords generated from the states “0” to “10” in FIG.
[0020]
[Table 1]
Line: Sum of elements Corresponding state
1: 165 “0”
2: 238 "1"
3: 343 “2”
4: 494 “3”
5: 474 “4”
6: 444 “5”
7: 400 “6”
8: 338 “7”
9: 250 “8”
10: 195 “9”
11: 115 “10”
[0021]
Therefore, the number of code words is insufficient for the states “0”, “1”, “8”, “9”, “10”, and the coding table cannot be configured as it is.
[0022]
Therefore, after the codewords to be generated are obtained for all the states in FIG. 1, for example, the following known examples “Finite State Modulation Code for Data Storage”, “Finite-State Modulation Codes for Data Storage ", BH Marcus et al., IEEE Journal on selected areas in Communication, vol.10. No.1, January 1992. Select states and then encode by dividing and merging states. A table can be created.
[0023]
In this example, the five states “0”, “1”, “2”, “7”, and “9” in FIG. 1 are divided into 1, 1, 2, 2, and 1, respectively, When the divided state “2” is represented by “21” and “22” and the divided state “7” is represented by “71” and “72”, the number of codewords in each state is
[0024]
[Table 2]
State after division: number of codewords
“0”: 265
“1”: 380
“21”: 271
“22”: 278
“71”: 268
“72”: 274
"9": 311
[0025]
Accordingly, 256 codewords can be generated. The number of codewords for each state after division is determined by how the codewords are allocated, and allocation methods other than this example are possible.
[0026]
Then, six types of encoding tables created by merging the states for states “72” and “9” are shown in FIGS. In this example, the state merging is performed only for the states “72” and “9”, but it is possible to perform more merging and reduce the number of coding tables. As an example of the table, six types are shown. 5-9, the input data is D (k) = 0-255, the coding table type is S (n) = 0, 1, 2, 3, 4, 5, and the output codeword is C ( k), the type of the encoding table to be selected next for the output codeword C (k) is shown as S (n + 1).
[0027]
FIG. 10 is a block diagram showing an embodiment of the modulation apparatus 10 according to the present invention. The modulation apparatus 10 includes the encoding table 11 and the one-word delay unit 12 having the configurations shown in FIGS. In FIG. 10, an input data string Din is added with a synchronization word, an error correction word, or the like by the recording block configuration circuit 1 and converted to a recording block of a predetermined length, and thereafter, an input data word D ( k). The encoding table 11 converts the input data word D (k) into a 16-bit code word C (k) based on the encoding table selection information S (n) at the time of encoding one word before from the one-word delay unit 12. ), And outputs this to the recording signal memory 2, and also outputs to the 1-word delay unit 12 encoding table selection information S (n + 1) to be selected next.
[0028]
The one-word delay unit 12 delays the coding table selection information S (n + 1) and outputs the next input data word D (k) to the coding table 11 as the coding table selection information S (n). To do. Here, the coding table selection information S (n) for the first input data word D (k) can be determined by selecting a synchronization pattern in the recording block configuration circuit 1. The code word C (k) converted by the encoding table 11 is once stored in the recording signal memory 2 and then output as the recording signal S1, but the recording signal memory 2 is unnecessary if it is not necessary to store it. The recording signal S1 is recorded on the recording medium by an NRZI modulator (not shown).
[0029]
An encoding process using the encoding table 11 shown in FIGS. 5 to 9 will be described in detail. Here, the following numerical values are shown in decimal unless otherwise specified. For example, if the initial state is “0”,
[0030]
[Table 3]
D (k) = 0
D (k + 1) = 1
D (k + 2) = 2
D (k + 3) = 3
[0031]
The encoding table S (n), code word C, and next encoding table S (n + 1) for the input data word D are shown below.
[0032]
[Table 4]

[0033]
[Table 5]
The binary sequence modulated as above is

It becomes.
[0034]
Here, in the above embodiment, the example of limiting the inversion interval before 3T has been described. However, the recording signal memory 2 shown in FIG. 10 reverses the bit transmission direction for each predetermined number of bits such as a recording block unit. Obviously, the inversion interval after 3T can be limited. Also, in the state transition diagram shown in FIG. 1, if the coding table 11 is configured using the method described above with the state transition direction, that is, the arrow direction shown in FIG. It is clear that the inversion interval of can be limited.
[0035]
A generation example of the encoding table 11 will be described in more detail. As described above, when the states “2” and “7” shown in FIG. 1 are divided into two and created, the same code word C (k) is assigned to different input data words D (k). There is. For example, referring to the encoding table S (n) = 0 shown in FIG. 5, the same code word C (k) = 64 is assigned to the input data word D (k) = 0,1.
[0036]
In this way, when the same code word C (k) is assigned to different input data words D (k), the encoding table of the present invention is such that the subsequent code word can be decoded by the decoding device. It is configured so that it can be detected by which encoding table C (k + 1) is encoded. That is, for example, the encoding table information S (n + 1) to be selected next for the input data word D (k) = 0 is “4”, and is next selected for the input data word D (k) = 1. The encoding table information S (n + 1) is “5”. Therefore, if the code words generated by the encoding table S (n) = 4 and the encoding table S (n) = 5 are all different, the original code word can be assigned to different data words. Can be decoded into data words.
[0037]
In the encoding table 11 of the first embodiment, as an example, in the encoding table information S (n + 1) = 2, 3 to be selected next, and in S (n + 1) = 4, 5, the same codeword C (K) is assigned to different input data words D (k). For this reason, the code word C (k) generated by the encoding table S (n) = 2, 3 does not exist, and the code generated by the encoding table S (n) = 4, 5 does not exist. The same thing does not exist in the word C (k). Further, the same code word C (k) between the encoding tables S (n) = 2, 3 and S (n) = 4, 5 is arranged to be generated by the same input data word D (k). Has been.
[0038]
<Second Embodiment>
The first embodiment described above can be applied when the transmission medium does not require DSV control. Next, a second embodiment that can cope with a case where the transmission medium requires DSV control will be described. First, the polarity when the codeword C (k) is NRZI modulated will be described. In the coding tables S (n) = 0 and 1 shown in FIGS. 5 to 9, the code word C (k) corresponding to the input data word D (k) = 0 to 117 has a maximum inversion interval before 3T. When the encoding rule of 8T is satisfied, it is arranged so that it can be replaced with the code word C (k) corresponding to the input data word D (k) = 0 to 117 in the encoding table S (n) = 3. ing. Further, between these exchangeable code words C (k), the code words C (k) are arranged so that the next selected coding table information S (n + 1) is the same. In addition, the codewords C (k) are arranged so that the odd / even numbers of the codewords C (k) are “1” different from each other, and therefore the codewords C (k) are NRZI-modulated. In this case, the polarities of the recording data S1 are opposite to each other.
[0039]
Further, in the encoding table S (n) = 5, the exchangeable code word C (k) is the code in the encoding table shown in FIGS. 5 to 9 with respect to the input data word D (k) = 0 to 33. Similarly, for these codewords, if the maximum inversion interval before 3T satisfies the encoding rule of 8T, the codewords can be replaced and the DSV polarity is reversed. FIGS. 11 to 13 show the parts (input data words D (k) = 0 to 117) that can be interchanged as S (n) = 0, 1, and 5 as the second encoding table. In addition, regarding the input data word D (k) in which the 16-bit code word C (k) is written as all 0 in FIGS. 11 to 13, there is no exchangeable code word C (k). .
[0040]
Next, the modulation apparatus according to the second embodiment will be described in detail with reference to FIGS. In this example, there are two codeword memories for performing DSV (digital sum variation) determination, but more codeword memories can be used. In this example, the code word memory is selected based on the DSV value up to a certain point. However, the code word memory can be selected by calculating and predicting the previous DSV value.
[0041]
The encoding table 11a illustrated in FIG. 14 includes the encoding table 11 (first encoding table) illustrated in FIGS. 5 to 9 and the second encoding table illustrated in FIGS. Have Based on the input data word D (k) and the coding table information S (n) from the coding table 11a, the code word option presence / absence detection circuit 21 has the NRZI polarity reversed as described above. As shown in FIG. 13, it is detected whether there is a replaceable codeword C (k), and if it is replaced, it is detected whether the encoding rule is maintained, and the option detection result is encoded table. The data is output to the address calculation unit 22 and the absolute value comparison circuit 25. The encoding table address calculation unit 22 corresponds to the input data word D (k) and the encoding table information S (n) based on this option detection result and the encoding table information S (n) from the encoding table 11a. Calculate the encoding table address.
[0042]
Based on this address, the encoding table 11a outputs two code word candidates C (k) 0 and C (k) 1 from the first and second tables. Here, when there is no codeword option, one codeword is output from the first table as two codeword candidates C (k) 0 and C (k) 1. The codeword candidate C (k) 0 is applied to the DSV operation memory 23-0 and the codeword memory 24-0, and the codeword candidate C (k) 1 is applied to the DSV operation memory 23-1 and the codeword memory 24-1. Is done. Then, the code word strings CD (code word digital sum) values of the code word candidates C (k) 0 and C (k) 1 are calculated and stored in the code word memories 24-0 and 24-1, respectively. DSV addition values for are stored in the DSV calculation memories 23-0 and 23-1.
[0043]
On the other hand, if there is a code word corresponding to the input data word D (k) based on the option detection result from the code word option presence / absence detection circuit 21, the absolute value comparison circuit 25 is up to that point (that is, the time k−). 1) The absolute values of the addition values of the respective DSVs held in the DSV calculation memories 23-0 and 23-1 are compared, and the comparison result is sent to the memory control / code output unit 26. Based on the comparison result, the memory control / code output unit 26 selects a memory control signal for selecting the code word string stored in the code word memory 24 having the smaller absolute value of the DSV addition value as the output code word string. In addition to the output, the DSV addition value of the codeword string not selected and the codeword string of the codeword memory 24 are respectively used as the DSV addition value of the selected codeword string and the codeword string of the codeword memory 24. Replace.
[0044]
This will be described in detail with reference to the flowcharts shown in FIGS. First, an initial table is selected in FIG. 15 (step S1), and then when 8-bit data is input (step S2), a codeword C (k) that can be replaced with the second table shown in FIGS. Is detected (step S3), and if present, the process proceeds to step S4 and thereafter, and if not, the process proceeds to step S7.
[0045]
FIG. 16 shows in detail the code word option presence / absence detection processing in step S3. When the input data word D (k) and the coding table information S (n) are input (step S10), there is a codeword C (k) that can be replaced with the second table shown in FIGS. (Yes in step S11), if there is, the process proceeds to step S12. If not, it is determined that there is no replacement code word (step S14), and the process proceeds to step S7 shown in FIG. In step S12, it is detected whether or not the encoding rule can be maintained even if the code word C (k) is selected from the second table shown in FIGS. (Step S13), and then the process proceeds to step S4 shown in FIG. On the other hand, when it cannot maintain, it progresses to step S14.
[0046]
In step S4 and subsequent steps, the DSV calculation memories 23-0 and 23-1 are referred to, the codeword memory 24 having the smaller | DSV | is selected, and the codeword string is output (step S4), and then not selected. The contents of the codeword memory 24 and the DSV calculation memory 23 are replaced with the contents of the selected codeword memory 24 and the DSV calculation memory 23 (step S5).
[0047]
Next, two code word candidates C (k) 0 and C (k) 1 are selected from the first table shown in FIGS. 5 to 9 and the second table shown in FIGS. 11 to 13 (step S6). Proceed to step S7. In step S7, codeword candidates C (k) 0 and C (k) 1 are added to the codeword memories 24-0 and 24-1, respectively, and then the codeword candidates C (k) 0 and C (k) 1 respectively. The CDS is calculated with respect to and added to the DSV calculation memories 23-0 and 23-1 (step S8), and then the process returns to step S2.
[0048]
Next, the decoding apparatus will be described with reference to FIGS. In FIG. 17, a serial bit sequence code word sequence reproduced from a recording medium (not shown) and a bit clock generated by a PLL circuit (not shown) and synchronized with the encoded bit are synchronized with the sync word detection unit 31 and serial / parallel. Applied to the converter 32. The sync word detection unit 31 generates a word clock which is a clock of a code word C (k) unit based on the sync word inserted in the recording code sequence for each recording unit and a bit clock, and converts the generated word clock into a serial / parallel converter. 32, the decoding table reference address generation unit 33 and the decoding table / encoding table calculator / selector 34. Based on the bit clock and the word clock, the serial / parallel converter 32 generates a code word C (k) having a bit parallel configuration in units of words from the code word sequence of the serial bit series, and generates the decoding table reference address generation unit 33. Output to.
[0049]
The decoding table reference address generation unit 33 generates a reference address of the decoding table 41 (FIG. 19) based on the code word C (k) and the word clock, and in this second embodiment, the code word C (k) is generated. It is used as a reference address for the decoding table 41 as it is. Alternatively, the configuration of the decoding table 41 may be changed to reduce its capacity, and the decoding table reference address generation unit 33 may calculate the reference address of the decoding table 41.
[0050]
18 shows in detail the decoding table / encoding table calculator / selector 34, and FIG. 19 shows the configuration of the decoding table 41 in FIG. 18 in detail. In the decoding table 41, for a 16-bit reference address C (k), 2-bit determination information Case (case) and two data word candidates D (k) 0 and D (k) each having 8 bits each. When 1 is stored in advance and the reference address C (k) is input, the data word candidates D (k) 0 and D (k) 1 are applied to the selector 43 via the 1-word delay unit 42 and the determination information Case Is applied to the coding table calculator 45 via the one-word delay unit 44. Then, the coding table calculator 45 generates a signal for the selector 43 to select one of the data word candidates D (k) 0 and D (k) 1 based on the determination information Case.
[0051]
The processing of the encoding table calculator 45 is shown in C language (some descriptions are different) in FIG. In FIG.
C (k) ε [C (k) of (S (n) = 2)]
Indicates that the code word C (k) is encoded by the encoding table S (n) = 2 in the encoding tables shown in FIGS. 5 to 9 and FIGS. 11 to 13. Referring to FIG. 19, when the code word C (k) is input as 34, 128, for example, the determination information Case when the previous code word C (k) = 34 is “2”. It can be seen that the code word C (k) = 128 is encoded by the encoding table S (n) = 2, and the data word candidate D (k) 0 with respect to the previous code word C (k) = 34. Data word D (k) = 252 is selected from among = 251 and D (k) 1 = 252, and is thus decoded.
[0052]
【The invention's effect】
As described above, according to the present invention, the shortest code inversion interval is d + 1 channel bits and the longest code inversion interval is k + 1 channel bits (d and k are When both are limited to positive integers), encoding is performed such that the inversion interval of the codeword immediately before or after the codeword in which the shortest code inversion interval of d + 1 channel bits occurs is shorter than k + 1 channel bits. The influence of the immediately following or immediately preceding code inversion interval on the shortest code inversion interval can be reduced, and the recording density can be improved.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing state transition of an encoder according to the present invention.
FIG. 2 is an explanatory diagram showing a matrix used in the process of creating a coding table according to the present invention.
FIG. 3 is an explanatory diagram showing a matrix used in the process of creating a coding table according to the present invention.
FIG. 4 is an explanatory diagram showing a process of creating a coding table according to the present invention.
FIG. 5 is an explanatory diagram showing an encoding table (part 1) according to the present invention.
FIG. 6 is an explanatory diagram showing a coding table (part 2) according to the present invention.
FIG. 7 is an explanatory diagram showing an encoding table (part 3) according to the present invention.
FIG. 8 is an explanatory diagram showing a coding table (part 4) according to the present invention.
FIG. 9 is an explanatory diagram showing a coding table (No. 5) according to the present invention.
FIG. 10 is a block diagram showing a first embodiment of a modulation device according to the present invention.
FIG. 11 is an explanatory diagram illustrating a second coding table (part 1) according to the second embodiment;
FIG. 12 is an explanatory diagram illustrating a second coding table (part 2) according to the second embodiment;
FIG. 13 is an explanatory diagram illustrating a second coding table (part 3) according to the second embodiment;
FIG. 14 is a block diagram illustrating a modulation device according to a second embodiment.
FIG. 15 is a flowchart for explaining a modulation process according to the second embodiment;
16 is a flowchart for explaining in detail the processing of the determination step of FIG. 15;
FIG. 17 is a block diagram showing an embodiment of a demodulator according to the present invention.
FIG. 18 is a block diagram showing in detail the decoding table / coding table calculator / selector of FIG. 17;
FIG. 19 is an explanatory diagram showing the decoding table of FIG. 18;
20 is an explanatory diagram showing processing of the coding table computing unit of FIG. 19;
FIG. 21 is an explanatory diagram showing state transition of an encoder of RLL (2, 10).
FIG. 22 is an explanatory diagram showing intersymbol interference in a conventional example.
[Explanation of symbols]
11 Encoding table (encoding means, first encoding table)
11a coding table (first and second coding tables)
12, 42 1-word delay unit
21 Code word option presence / absence detection circuit (configures table reading means together with the encoding table address calculation unit 22)
22 Coding table address calculation unit
23-0, 23-1 DSV calculation memory (DSV calculation means)
24-0, 24-1 codeword memory
25 Absolute value comparison circuit
26 Memory control / sign output unit (constitutes a selection means together with the absolute value comparison circuit 25)
41 Decryption table
43 selector (selection means)

Claims (5)

A continuous binary input data string is divided into p bits, p bit input data words are converted into q bit (p <q: p and q are both positive integers) code words, and the code words before and after are converted. A signal that is directly combined and the shortest code inversion interval is limited to d + 1 channel bits and the longest code inversion interval is limited to k + 1 channel bits (d and k are both positive integers) when the combined codeword strings are subjected to NRZI conversion. In the modulation device,
Encoding means for encoding an input data word into a code word so that the inversion interval of the code word immediately before or after the code word in which the shortest code inversion interval of the d + 1 channel bits occurs is shorter than the k + 1 channel bits;
A signal modulation device comprising: The encoding means has a plurality of encoding tables storing information for selecting a code word and an encoding table for encoding the next input data word with the input data word as an address, and encoding the code word and the encoding table. The table selection information is composed of a coding rule in which the inversion interval of the codeword immediately before or after the codeword in which the shortest code inversion interval of the d + 1 channel bits occurs is shorter than the k + 1 channel bits. The signal modulation device according to claim 1. A continuous binary input data string is divided into p bits, p bit input data words are converted into q bit (p <q: p and q are both positive integers) code words, and the code words before and after are converted. A signal that is directly combined and the shortest code inversion interval is limited to d + 1 channel bits and the longest code inversion interval is limited to k + 1 channel bits (d and k are both positive integers) when the combined codeword strings are subjected to NRZI conversion. In the modulation device,
Information for selecting an encoding table that encodes a code word and the next input data word with an input data word as an address is stored, and the code word and the encoding table selection information indicate that the shortest code inversion interval of the d + 1 channel bits is A plurality of first coding tables configured with a coding rule in which the inversion interval of the codeword immediately before or after the generated codeword is shorter than the k + 1 channel bits;
Information for selecting an encoding table for encoding the code word and the next input data word with the input data word as an address is stored, and the polarity when the code word is NRZI converted is the same input in the first encoding table A plurality of second encoding tables having opposite polarity to the code word for the data word and the same information for selecting the next encoding table;
If the encoding rule is satisfied even if the second encoding table is selected, the first and second code word candidates are read from the first and second encoding tables, respectively, and the second code A table reading means for reading the first and second code word candidates having the same value from the first coding table when the coding table is not satisfied when the coding table is selected;
DSV calculating means for calculating the absolute value of the sum of DSV for each of the first and second codeword candidates read by the table reading means;
Means for selecting, as a code word, the first or second code word candidate having a smaller absolute value of the sum of DSVs calculated by the DSV calculating means;
A signal modulation device comprising: A demodulator that demodulates a codeword modulated by the modulator according to any one of claims 1 to 3 into an original input data word,
Determination information indicating which of the plurality of encoding tables the subsequent code word is encoded by using the code word to be demodulated as an address, and a decoding table that outputs two or more input data word candidates;
Selecting means for selecting one of the two or more input data word candidates as an input data word based on the determination information read from the decoding table;
Demodulator having. A recording medium on which a signal modulated by the signal modulation device according to claim 1 is recorded.

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