JP3813476B2 - Semiconductor device - Google Patents

Description

【００９７】
表１によれば、加速試験前の状態では、再堆積層間絶縁膜が厚い方が分極電荷量が僅かに大きくなっている。しかし、加熱後は、試料間の分極電荷量の差が顕著になる。とくに、再堆積層間絶縁膜３４が０ｎｍの場合、即ち再堆積層間絶縁膜３４を形成しないときには、分極電荷量が加熱後に半分以下に減り、強誘電体キャパシタＱは著しく特性が劣化する。また、再堆積層間絶縁膜３４が３００ｎｍの時は、強誘電体キャパシタＱの劣化は軽度であり、加熱後の分極電荷量は２２．６μＣ/cm²となって、ＦｅＲＡＭを正常に動作させるためには十分な値となっている。
【００９８】
なお、再堆積層間絶縁膜３４の３００ｎｍという膜厚は、空洞３３ｕの露出する部分のばらつきを考慮して決定されるのである。
【００９９】
ところで、再堆積層間絶縁膜３４が厚すぎると、ビアホール３３ａのアスペクト比が増大してビアホール３３ａ内でグルーレイヤ３５ａやタングステン膜３５ｂのカバレッジが悪くなる。即ち、再堆積層間絶縁膜３４の膜厚の上限値は、ビアホール３３ａのアスペクト比から決定される。例えば、ビアホール３３ａのアスペクト比を２．３とする場合に、ビアホール３３ａの直径を０．６μｍ、第４の層間絶縁膜３３の厚さを１．０μｍとすれば、再堆積層間絶縁膜３４の膜厚は約０．４μｍ（４００ｎｍ）必要となる。
【０１００】
以上のような工程によって再堆積層間絶縁膜３４、ビア３５を形成する工程を終えた後に、再堆積層間絶縁膜３４の上に第１のTiN 膜を５０ｎｍ、Al膜を５００ｎｍ、第２のTiN 膜を５０ｎｍの厚さに順次形成し、これらの膜をパターニングすることにより、配線３６を形成する。なお、再堆積層間絶縁膜３４上面にグルーレイヤ３５ａを残す場合には、第１のTiN 膜の形成を省略してグルーレイヤ３５ａの上にアルミニウム膜と第２のTiN 膜を形成することになる。
【０１０１】
次に、第１及び第２のTiN 膜とAl膜、又は、第２のTiN 膜とAl膜とグルーレイヤをフォトリソグラフィ法によりパターニングすることにより、図１６に示すように、二層目のアルミニウム配線３６を再堆積層間絶縁膜３４の上に形成する。
【０１０２】
その後、ＴＥＯＳを用いるプラズマＣＶＤ法により、二層目のアルミニウム配線３６と再堆積層間絶縁膜３４の上に、第１のカバー絶縁膜３７としてSiO₂膜を２００ｎｍの厚さに形成する。さらに、第１のカバー絶縁膜３７の上に、プラズマＣＶＤ法によりSiN よりなる第２のカバー絶縁膜膜３８を５００ｎｍの厚さに形成する。これらの第１及び第２のカバー膜３７，３８により二層目の配線３６が被覆される。
【０１０３】
二層目のアルミニウム配線３６が形成された後のメモリセル領域１における各種導電パターンの平面的な位置関係は図２２のようになる。なお、図２２中で素子分離絶縁膜１１以外の絶縁膜は省略されている。
【０１０４】
以上のような工程により、キャパシタ誘電体膜２４として強誘電体を用いたＦｅＲＡＭの基本的な構造が完成する。
【０１０５】
本実施の形態においては、キャパシタＱと一層目のアルミニウム配線３２ａ，３２ｃ〜３２ｅを覆う第４の層間絶縁膜３３の上面をＣＭＰ法で平坦化している。これにより、キャパシタＱと配線３２ａの上に形成した層間絶縁膜３３のさらに上で平坦に形成される二層目のアルミニウム配線３６のパターン精度を良好にすることができる。
【０１０６】
また、層間絶縁膜３３を研磨した後に、N₂O プラズマアニールを施して層間絶縁膜３３中の水分を除去しているので、その後の工程において加熱されても、強誘電体膜（キャパシタ誘電体膜２４）の還元、劣化が回避される。これにより、良好な特性のＦｅＲＡＭを製造できる。しかも、N₂O プラズマアニールを４５０℃以下で行っているので、一層目のアルミニウム配線を劣化させることもない。
【０１０７】
そのようなN₂O プラズマアニール工程を入れてＦｅＲＡＭを形成した場合と、その工程を省略してＦｅＲＡＭを形成した場合のキャパシタＱの分極電荷量を調べたところ次の表２に示すような結果が得られ、N₂O プラズマアニールがキャパシタの劣化を防止するために有効であることが確かめられた。
【０１０８】
【表２】

【０１０９】
なお、上記の実施の形態では、N₂O を用いたプラズマアニールにより層間絶縁膜３３を脱水処理する場合について説明したが、脱水処理に用いるガスはN₂O に限定されるものではなく、例えばN₂ガス、O₂ガス又はNOガスを用いたプラズマアニールでも同様の効果が得られる。また、プラズマアニールに使用するガスは、N₂O ＋N₂、N₂＋O₂等の混合ガスでもよい。さらに、そのような単体ガス又は混合ガスに、アルゴン(Ar)、ヘリウム(He)、ネオン(Ne)の不活性ガスを混合してプラズマ化してもよい。
【０１１０】
更にまた、上記の実施の形態では層間絶縁膜３３に対し脱水処理を施した後、再堆積層間絶縁膜３４を形成したが、ＣＭＰ研磨後の層間絶縁膜３３の上に再堆積層間絶縁膜３４を形成し、その後脱水処理を施してもよい。
【０１１１】
上記の実施の形態のように再堆積層間絶縁膜３４を薄く形成する場合は再堆積層間絶縁膜３４中に含まれる水分量が極めて少ないが、再堆積層間絶縁膜３４を厚く形成する場合は再堆積層間絶縁膜３４中に含まれる水分によりキャパシタ誘電体膜が還元されてしまうおそれがある。これを防止するために、再堆積層間絶縁膜３４を形成した後、N₂O 又はNOを用いるプラズマアニールによる脱水処理を実施してもよい。但し、この場合、再堆積層間絶縁膜３４をプラズマＣＶＤ法により酸窒化シリコン（SiON）膜又はプラズマＣＶＤ法により窒化シリコン（SiN)膜で形成すると、これらの膜は水分を通しにくいので、第４の層間絶縁膜３３中の水分を十分に除去することができなくなる。このため、再堆積層間絶縁膜３４を形成した後にプラズマアニールを施す場合は、再堆積層間絶縁膜３４をプラズマＴＥＯＳ膜、O₃−ＴＥＯＳ膜、又はプラズマSiO₂膜により形成することが好ましい。
【０１１２】
即ち、再堆積層間絶縁膜３４としては、上述したプラズマＣＶＤ法により形成したＴＥＯＳ膜（Ｐ−ＴＥＯＳ膜）に代えて、熱ＣＶＤ法でオゾン（O₃）とＴＥＯＳとを用いて形成したＴＥＯＳ（O₃−ＴＥＯＳ）膜、プラズマＣＶＤ法により形成したSiO₂（Ｐ−SiO₂）膜、ノンバイアスのＨＤＰ(High Density Plasma) −ＣＶＤにより形成したSiO₂膜、プラズマＣＶＤ法により形成したSiON（Ｐ−SiON）膜及びプラズマＣＶＤ法により形成したSiN ( Ｐ−SiN ）膜などを使用してもよい。但し、O₃−ＴＥＯＳ膜は、水分含有量がＰ−ＴＥＯＳ膜に比べて多いので、本実施形態ではＰ−ＴＥＯＳ膜を用いている。また、SiON膜及びSiN 膜は水分の透過性が低いので、これらの膜を再堆積層間絶縁膜３４として使用する場合は、第４の層間絶縁膜３３を脱水処理した後に、再堆積層間絶縁膜３４を形成することが必要である。
【０１１３】
図２３は、横軸にＰ−ＴＥＯＳ膜に対するプラズマアニール処理時間をとり、縦軸に分極電荷量（Ｑsw）をとって、分極電荷量の脱水処理時間依存性を示す図である。但し、プラズマアニールの条件は、温度が３５０℃、プラズマに印加するパワーが３００Ｗ、N₂O の流量が７００sccm、N₂ガスの流量が２００sccmである。分極電荷量Ｑswの値が大きいほど、分極特性が良好であるといえる。
【０１１４】
図２３からわかるように、プラズマアニールの処理時間を３分以上とすることにより、十分な特性を得ることができる。強誘電体膜の初期状態における分極電荷量は約２８μＣ／ｃｍ² であり、約４分間のプラズマアニールにより初期状態の分極電荷量まで回復させることができる。
【０１１５】
上記した実施形態では、第４の層間絶縁膜３３として、ＴＥＯＳガスを用いるプラズマＣＶＤ法により形成したSiO₂膜（ｐ−ＴＥＯＳ）を用いたが、その他に、熱ＣＶＤ法でO₃とＴＥＯＳとを用いて形成したＴＥＯＳ（O₃−ＴＥＯＳ）膜、プラズマＣＶＤ法により形成したSiO₂（Ｐ−SiO₂）膜などで形成してもよい。 O₃−ＴＥＯＳ膜は、Ｐ−ＴＥＯＳ膜よりも成長速度が遅いが、その膜内に空洞は生じない。
【０１１６】
また、上記した実施形態では、ＦｅＲＡＭ及びその形成工程について説明したが、高誘電体キャパシタを有する揮発性メモリ（ＤＲＡＭ）についても、水分と加熱によって高誘電体材料の絶縁性が劣化したり、高誘電体材料膜と電極との界面が劣化し易くなる。そこで、上記したと同様に、高誘電体キャパシタの上に形成される絶縁膜の上面をＣＭＰ法により平坦化した後に、その表面をN₂O 、NO等のガスを用いてその絶縁膜の脱水処理をしたり、あるいは、そのような脱水処理後、又は脱水処理前に平坦化された面の上にＰ−ＴＥＯＳを用いて再堆積層間絶縁膜を形成してもよい。高誘電体材料として、(BaSr)TiO₃などの高誘電体材料を使用すればよい。
【０１１７】
また、本発明は、強誘電体不揮発性半導体メモリ又は高誘電体半導体メモリとロジックデバイスとを混載したいわゆるシステムＬＳＩの製造に適用することもできる。
【０１１８】
【発明の効果】
以上述べたように本発明によれば、キャパシタとその上を通る配線のさらに上に形成された絶縁膜を研磨して平坦化するようにしたので、その絶縁膜の平坦面の上に配線を精度良く形成することが容易になる。
【０１１９】
また、研磨された絶縁膜に対しN₂O 又はNOを含むプラズマアニールによる脱水処理を施すようにしたので、その絶縁膜の表面に付着している水分、及び絶縁膜中に侵入している水分をより確実に除去することができて、キャパシタを構成する強誘電体材料又は高誘電体材料の還元や、キャパシタ劣化を防止できる。従って、強誘電体材料又は高誘電体材料の誘電特性の劣化を回避でき、良好な特性のＦｅＲＡＭ又はＤＲＡＭを製造することができる。
【図面の簡単な説明】
【図１】図１は、発明の実施の形態の半導体装置の製造方法を示す断面図（その１）である。
【図２】図２は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その２）である。
【図３】図３は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その３）である。
【図４】図４は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その４）である。
【図５】図５は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その５）である。
【図６】図６は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その６）である。
【図７】図７は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その７）である。
【図８】図８は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その８）である。
【図９】図９は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その９）である。
【図１０】図１０は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その１０）である。
【図１１】図１１は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その１１）である。
【図１２】図１２は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その１２）である。
【図１３】図１３は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その１３）である。
【図１４】図１４は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その１４）である。
【図１５】図１５は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その１５）である。
【図１６】図１６は、本発明の実施の形態の半導体装置の製造方法を示す断面図（その１６）である。
【図１７】図１７(a) は図８のＩ−Ｉ線断面図、図１７(b) は図８のII−II線断面図である。
【図１８】図１８(a) は図１１のIII-III 線断面図、図１８(b) は図１３のIV−IV線断面図である。
【図１９】図１９(a) は、図１７(b) の断面を撮影した写真に基づいて描いた断面図であり、図１９(b) は、図１８(a) の断面を撮影した写真に基づいて描いた断面図である。
【図２０】図２０(a) 〜(d) は、図１７(b) に示した空洞が絶縁膜によって十分埋め込まれない工程を示す断面図である。
【図２１】図２１は、本発明の実施形態に係る半導体装置のメモリセルに使用されるキャパシタのリーク電流と累積確率の関係を示す図であって、累積確率を示す縦軸とリーク電流量を示す横軸は対数目盛で示される。
【図２２】図２２は、本発明の実施形態に係る半導体装置のメモリセル領域の導電パターンの配置を示す平面図である。
【図２３】図２３は、本発明の実施形態に係る半導体装置に形成されたキャパシタの分極電荷量の脱水処理時間依存性を示す図である。
【符号の説明】
１０…半導体基板、１１…素子分離絶縁膜、１２ａ，１２ｂ…ウェル領域、１３ａ，１３ｂ，１３ｃ…ゲート電極、１５ａ，１５ｂ…不純物拡散領域、１６…サイドウォール、１７，２６，３１，３３…層間絶縁膜、１８…プラグ、２１…SiON膜、２２…SiO₂膜、２３…下部電極、２４…誘電体膜、２５…上部電極、２７…局所配線、３２ａ…ビット線、３２ｂ〜３２ｇ…配線、３４…再堆積層間絶縁膜、３５ａ…グルーレイヤ、３５ｂ…タングステン膜、３５…プラグ、３６…アルミニウム配線、３７，３８…カバー膜。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more specifically, a nonvolatile semiconductor memory (FeRAM: Ferroelectric Random Access Memory) using a ferroelectric material for a dielectric film of a capacitor, or a high dielectric material for a dielectric film of a capacitor. The present invention relates to a volatile semiconductor memory (DRAM: Dynamic Random Access Memory) used or a semiconductor device represented by a system LSI in which these memory elements and logic elements are mixedly mounted.
[0002]
[Prior art]
In recent years, FeRAM using a ferroelectric material as a dielectric film of a capacitor has attracted attention as a low power consumption nonvolatile semiconductor memory. In recent years, there has been a demand for miniaturization and high integration of semiconductor memories, and a DRAM using a high dielectric material for a dielectric film of a capacitor has been developed to meet the demand.
[0003]
As these FeRAM ferroelectric materials and DRAM high dielectric materials, metal oxides are usually used.
[0004]
Such ferroelectric materials and high-dielectric materials are weak in reducing atmospheres, and in particular, ferroelectric materials have a property that their polarization characteristics are likely to deteriorate.
[0005]
As a method for preventing deterioration of the polarization characteristics of a ferroelectric material, Japanese Patent Laid-Open No. 9-307074 discloses that a lower insulating film of either sputtered silicon oxide or SOG (Spin-On-Glass) is formed on a capacitor. After the formation of ozone and TEOS (tetraethoxysilane; Si (OC ₂ H _Five ) _Four ) To prevent reduction of the dielectric film of the capacitor by forming an upper insulating film of silicon oxide. JP-A-10-275897 discloses that a conductive film for wiring is not formed in a reducing atmosphere using a metal CVD (Chemical Vapor Deposition) apparatus or an MO (Metal Organic) CVD apparatus. It is described that the film is formed by DC sputtering to prevent deterioration of the polarization characteristics of the capacitor below the conductive film for wiring. In this publication, TEOS is used to deposit SiO on a capacitor by plasma CVD. ₂ This SiO film forms ₂ It is described that a wiring is connected to an upper electrode of a capacitor through a hole formed in the film.
[0006]
In Japanese Patent Laid-Open No. 11-238855, a thin conductive pattern (wiring) is connected to the capacitor upper electrode through a hole formed in a thin insulating film covering the capacitor, and further thick on the insulating film covering the conductive pattern. A structure in which an aluminum wiring pattern is formed and the aluminum wiring pattern is further covered with an insulating film is described.
[0007]
[Problems to be solved by the invention]
However, in Japanese Patent Application Laid-Open No. 11-238855, since the aluminum wiring pattern used as the bit line is thick, the unevenness on the surface of the interlayer insulating film formed thereon becomes large.
[0008]
When the unevenness of the interlayer insulating film covering the aluminum wiring pattern becomes large, in the photolithography process for forming the upper wiring on the interlayer insulating film, the focus at the time of exposure tends to be defocused, and the pattern of the upper wiring There arises a problem that accuracy is lowered. In particular, when an interlayer insulating film is formed by a plasma CVD method, uneven steps on the surface of the interlayer insulating film tend to be large.
[0009]
On the other hand, it is conceivable to form an HDP (High Density Plasma) film with small unevenness on the surface, but when the HDP film is formed, hydrogen enters the insulating film and the oxide dielectric of the capacitor There is a risk of reducing the membrane.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to accurately form a capacitor using a ferroelectric material or a high dielectric material and a wiring formed further above the bit line, and to prevent the deterioration of the capacitor and its manufacture. It is to provide a method.
[0011]
[Means for Solving the Problems]
The above-mentioned problem was formed on a semiconductor substrate A first impurity region; a second impurity region; and a gate electrode formed on the semiconductor substrate. A transistor, Said Covering the transistor A first insulating film; Formed on the first insulating film And a dielectric film made of either a ferroelectric material or a high dielectric material, and an upper electrode and a lower electrode sandwiching the dielectric film. A capacitor; Said On the capacitor Formed in Second insulating film And connecting the upper electrode of the capacitor and the first impurity region, formed on the second insulating film. Local wiring, Said Local wiring And a third insulating film formed on the second insulating film, Formed on the third insulating film And connected to the second impurity region through holes formed in the first, second and third insulating films. A first wiring; Said On the first wire Formed by a plasma CVD method using TEOS gas and oxygen gas, and By polishing Flattened top surface Has been dehydrated by plasma annealing A fourth insulating film; Said This is solved by a semiconductor device having the second wiring formed over the fourth insulating film.
[0012]
According to the present invention, a capacitor using a ferroelectric material or a high-dielectric material, a first wiring formed thereon via an insulating film, and a flat top surface formed on the first wiring. And a second wiring formed on the insulating film.
[0013]
Thereby, the pattern of the second wiring formed above the capacitor having the ferroelectric film or the high dielectric film is formed with high accuracy.
[0014]
In addition, the above-described problem is that a capacitor including a dielectric film made of a ferroelectric material or a high dielectric material is formed above a semiconductor substrate, a first insulating film is formed above the capacitor, This is solved by a method for manufacturing a semiconductor device, characterized in that the first insulating film is polished and the upper surface thereof is flattened, and then the first insulating film is dehydrated by plasma annealing.
[0015]
According to the present invention, after forming a capacitor using a ferroelectric material or a high-dielectric material as a dielectric film, a first insulating film is formed thereon, and this first insulating film is formed by, for example, CMP. A step of flattening.
[0016]
In the polishing step, moisture in the polishing agent and moisture in the cleaning liquid not only adhere to the surface of the first insulating film, but also penetrate into the first insulating film. In order to remove the moisture adhering to the surface of the first insulating film and the moisture entering the first insulating film, in the present invention, for example, N ₂ Dehydration is performed from the polished surface of the first insulating film by annealing in a plasma atmosphere of O 2 gas or NO gas.
[0017]
By the way, when an electric furnace is used as a heat treatment for dehydration, since the metal wiring layer is provided below the first insulating film, annealing in the electric furnace is limited to, for example, an aluminum heat-resistant temperature of 450 ° C. or lower. Such simple heat treatment at a low temperature is not sufficient for the effect of dehydration. On the other hand, when plasma annealing is used as in the present invention, it is possible to more reliably remove moisture from the insulating film at a low temperature of 450 ° C. or lower, and the metal wiring layer is formed at such a low temperature. There is no problem of oxidation.
[0018]
Therefore, in such plasma annealing, moisture in the first insulating film can be more reliably removed than in a simple heat treatment. As a result, the reduction of the ferroelectric film or the high dielectric film or the deterioration of the capacitor due to the surface of the first insulating film or moisture therein can be prevented, and a good FeRAM or DRAM can be manufactured.
[0019]
N ₂ According to the plasma annealing of O 2 gas or NO gas, when the first insulating film is formed of a silicon oxide film, at least the surface thereof contains nitrogen.
[0020]
When a cavity (spore, void, or keyhole) is formed in the first insulating film planarized by the CMP method, the cavity may be exposed in a groove shape from the polished surface. is there. When the wiring layer is formed on the polished surface, the conductive material constituting the wiring layer may enter the cavity and short-circuit a plurality of wirings that cross the cavity. For this reason, the second insulating film is formed on the polished surface of the first insulating film, and the cavity exposed in the groove shape on the polished surface of the first insulating film is covered or filled with the second insulating film. It is preferable to do.
[0021]
In order to reliably obtain the above effect, the thickness of the second insulating film is preferably set to 100 nm or more.
[0022]
Further, when the width of the cavity exposed from the polished surface varies and a part of the cavity is not covered with the second insulating film, the metal film formed on the second insulating film has a cavity. There is a risk of forming a slit on the top. If there is a slit in the metal film, hydrogen may enter the first insulating film through the slit to deteriorate the capacitor. Therefore, in order to prevent the formation of slits in the metal film, the thickness of the second insulating film is preferably set to at least 300 nm.
[0023]
Note that a second insulating film may be formed over the first insulating film, and then the above-described plasma annealing may be performed. In this case, deterioration of the insulating characteristics of the first and second insulating films can be avoided, and moisture in the first insulating film and the second insulating film can be removed simultaneously.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0025]
1 to 16 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. The semiconductor device of this embodiment will be described by taking FeRAM as an example.
[0026]
First, steps required until a sectional structure shown in FIG.
[0027]
As shown in FIG. 1, an element isolation insulating film 11 is selectively formed on the surface of a p-type silicon (semiconductor) substrate 10 by a LOCOS (Local Oxidation of Silicon) method. The element isolation insulating film 11 may be formed by STI (Shallow Trench Isolation) in addition to the LOCOS method.
[0028]
After such an element isolation insulating film 11 is formed, p-type impurities and n-type impurities are selectively introduced into predetermined active regions (transistor formation regions) in the memory cell region 1 and the peripheral circuit region 2 of the silicon substrate 10. Thus, the p well 12a and the n well 12b are formed. Although not shown in FIG. 1, a p-well (not shown) is also formed in the peripheral circuit region 2 to form a CMOS.
[0029]
Thereafter, the active region surface of the silicon substrate 10 is thermally oxidized to form a silicon oxide film as the gate insulating film 10a.
[0030]
Next, an amorphous silicon film and a tungsten silicide film are sequentially formed on the entire upper surface of the silicon substrate 10, and the amorphous silicon film and the tungsten silicide film are patterned into a predetermined shape by a photolithography method to obtain gate electrodes 13a to 13c and A wiring 14 is formed. A polysilicon film may be formed in place of the amorphous silicon film constituting the gate electrodes 13a to 13c.
[0031]
In the memory cell region 1, two gate electrodes 13a and 13b are arranged substantially in parallel on one p-well 12a, and these gate electrodes 13a and 13b constitute a part of the word line WL.
[0032]
Next, in the memory cell region 1, n-type impurities are ion-implanted into the p-wells 12a on both sides of the gate electrodes 13a and 13b to form n-type impurity diffusion regions 15a that become the source / drain of the n-channel MOS transistor. . At the same time, an n-type impurity diffusion region may be formed in a p-well (not shown) in the peripheral circuit region 2. Subsequently, in the peripheral circuit region 2, a p-type impurity is ion-implanted into the n-well 12b on both sides of the gate electrode 13c to form a p-type impurity diffusion region 15b that becomes the source / drain of the p-channel MOS transistor. The n-type impurity and the p-type impurity are divided using a resist pattern.
[0033]
Thereafter, after an insulating film is formed on the entire surface of the silicon substrate 10, the insulating film is etched back to leave the side wall insulating film 16 only on both sides of the gate electrodes 13 a to 13 c and the wiring 14. As the insulating film, for example, silicon oxide (SiO2) is formed by a CVD method. ₂ ).
[0034]
Next, a silicon oxynitride (SiON) film is formed as a cover film 3 to a thickness of about 200 nm on the entire surface of the silicon substrate 10 by plasma CVD. Thereafter, silicon oxide (SiO 2) is formed on the cover film 3 by plasma CVD using TEOS gas. ₂ ) To a thickness of about 1.0 μm, First interlayer insulating film (first insulating film) 17 is formed. In addition, SiO formed by plasma CVD method using TEOS ₂ Hereinafter, the film is also referred to as a TEOS film.
[0035]
Subsequently, as the densification treatment of the first interlayer insulating film 17, the first interlayer insulating film 17 is heat-treated at a temperature of 700 ° C. for 30 minutes in a normal-pressure nitrogen atmosphere. Thereafter, the first interlayer insulating film 17 is polished by a chemical mechanical polishing (hereinafter referred to as CMP) method to planarize the upper surface of the first interlayer insulating film 17.
[0036]
Next, steps required until a structure shown in FIG.
[0037]
First, contact holes 17a to 17d having a depth reaching the impurity diffusion regions 15a and 15b and via holes 17e having a depth reaching the wiring 14 are formed in the first interlayer insulating film 17 by photolithography. Thereafter, a Ti (titanium) thin film having a thickness of 20 nm and a TiN (titanium nitride) thin film having a thickness of 50 nm are sequentially formed on the upper surface of the first interlayer insulating film 17 and the inner surfaces of the holes 17a to 17e by sputtering. Further, tungsten (W) is grown on the TiN thin film by the CVD method. As a result, a tungsten film is buried in the contact holes 17a to 17d and the via hole 17e.
[0038]
Thereafter, the tungsten film, the TiN thin film, and the Ti thin film are polished by the CMP method until the upper surface of the first interlayer insulating film 17 is exposed. The tungsten film or the like remaining in the holes 17a to 17e after the polishing is used as plugs 18a to 18e for electrically connecting the later-described wiring to the impurity diffusion regions 15a and 15b and the wiring 14.
[0039]
In one p-well 12a of the memory cell region 1, a first plug 18a on an n-type impurity diffusion region 15a sandwiched between two gate electrodes 13a and 13b is connected to a bit line described later, and the remaining two second second electrodes The plug 18b is connected to a capacitor to be described later.
[0040]
In addition, after forming the contact holes 17a to 17d and the via hole 17e, impurities may be ion-implanted into the impurity diffusion regions 15a and 15b for contact compensation.
[0041]
Next, as shown in FIG. 3, in order to prevent oxidation of the plugs 18a to 18e, silane (SiH _Four ) Is used to form a SiON (insulating film) film 21 with a thickness of 100 nm on the first interlayer insulating film 17 and the plugs 18a to 18e, and plasma using TEOS and oxygen as reaction gases. SiO by CVD ₂ The film 22 is formed to a thickness of 150 nm. The SiON film 21 is formed in order to prevent water from entering the first interlayer insulating film 17.
[0042]
After that, SiON film 21, SiO ₂ In order to densify the films 22, the films are heat-treated at a temperature of 650 ° C. for 30 minutes in a normal-pressure nitrogen atmosphere.
[0043]
The first interlayer insulating film 17 formed by plasma CVD using TEOS gas and SiO 2 ₂ Each of the films 22 is heated at a temperature of 650 to 700 ° C., but a metal film having a low melting point such as aluminum does not exist thereunder, so that no adverse effect is caused by heating at such a temperature.
[0044]
Next, as shown in FIG. 4, SiO (Direct Current) sputtering is used to form SiO. ₂ Ti and Pt (platinum) are sequentially deposited on the film 22 to form a first conductive film 23a having a two-layer structure. In this case, the thickness of the Ti film is about 10 to 30 nm, and the thickness of the Pt film is about 100 to 300 nm. For example, the thickness of the Ti film is 20 nm and the thickness of the Pt film is 175 nm. Note that as the first conductive film 23a, iridium, ruthenium, ruthenium oxide, iridium oxide, ruthenium oxide strontium (SrRuO _Three ) Etc. may be formed.
[0045]
Subsequently, lead zirconate titanate (PZT; Pb (Zr), which is a ferroelectric material, is formed on the first conductive film 23a by RF (Radio Frequency) sputtering. _1-x Ti _x ) O _Three ) Is deposited to a thickness of 100 to 300 nm to form a PZT film 24a. For example, the thickness of the PZT film 24a is 240 nm.
[0046]
Then, as a crystallization process for the PZT film 24a, RTA (Rapid Thermal Annealing) is performed in an oxygen atmosphere at a temperature of 650 to 850 ° C. for 30 to 120 seconds. For example, annealing is performed at a temperature of 750 ° C. for 60 seconds.
[0047]
As a method for forming the ferroelectric material film, there are a spin-on method, a sol-gel method, a MOD (Metal Organi Deposition) method, and an MOCVD method in addition to the sputtering method described above. In addition to PZT, ferroelectric materials include lead lanthanum zirconate titanate (PLZT), SrBi. ₂ (Ta _x Nb _1-x ) ₂ O ₉ (However, 0 <x <1), Bi _Four Ti ₂ O ₁₂ and so on. Furthermore, in the case of forming a DRAM, instead of the above ferroelectric material, (BaSr) TiO _Three A high dielectric material such as (BST) or strontium titanate (STO) may be used.
[0048]
After such a PZT film 24a is formed, a Pt film is formed thereon as a second conductive film 25a to a thickness of 100 to 300 nm by DC sputtering. For example, the thickness of the second conductive film 25a is 200 nm. Note that as the second conductive film 25a, iridium oxide (IrO ₂ ) A film or ruthenium strontium oxide (SRO) may be formed by sputtering.
[0049]
Next, the second conductive film 25a, the PZT film 24a and the first conductive film 23a are sequentially patterned by photolithography to form a capacitor having a predetermined shape as shown in FIG.
[0050]
Here, the second conductive film 25 a becomes the upper electrode 25, the PZT film 24 a becomes the dielectric film 24, and the first conductive film 23 a becomes the lower electrode 23. The upper electrode 25, the dielectric film 24, and the lower electrode 23 constitute a capacitor Q. Capacitors Q are formed around p well 12a by the same number as the MOS transistors formed in one p well 12a.
[0051]
By the way, after the second conductive film 25a is patterned to form the upper electrode 25, recovery annealing is performed to remove damage to the capacitor Q. Specifically, the silicon substrate 10 is placed in an oxygen atmosphere, and the capacitor Q is heated at a temperature of 500 to 700 ° C. for 30 to 120 minutes. For example, recovery annealing is performed by heating at a temperature of 650 ° C. for 60 minutes. Further, after the first conductor film 23a is patterned to form the lower electrode 23, recovery annealing is performed under the same conditions.
[0052]
After the capacitor Q is formed through the above steps, as shown in FIG. 6, a two-layer structure consisting of a TEOS film and an SOG film is formed on the entire surface. Second interlayer insulating film (second insulating film) 26 is formed, and the capacitor Q is covered with the second interlayer insulating film 26. The TEOS film is formed with a thickness of 100 to 300 nm on the entire upper surface of the silicon substrate 10 under the conditions of a growth temperature of 390 ° C. and a power of 400 W by plasma CVD using TEOS gas. The SOG film is formed by applying an SOG solution to a thickness of 80 to 200 nm on the TEOS film and then heating it. In this example, it is assumed that the TEOS film has a thickness of 200 nm and the SOG (Spin-On-Glass) film has a thickness of 100 nm. Here, since the SOG film is a coatable insulating film, the unevenness of the surface becomes small.
[0053]
Note that the SOG film may be removed by etch back. In this case, the thickness of the TEOS film is 500 nm, and the thickness of the SOG film is 100 nm.
[0054]
Then, the second interlayer insulating film 26 is patterned by photolithography to form a contact hole 26a on the upper electrode 25 of the capacitor Q. Thereafter, recovery annealing is performed on the dielectric film 24. Specifically, heating is performed at a temperature of 500 to 650 ° C. for 30 to 120 minutes in an oxygen atmosphere. In this example, heating is performed at a temperature of 550 ° C. for 60 minutes.
[0055]
Next, the second interlayer insulating film 26, SiON film 21, SiO ₂ The film 22 is patterned by photolithography to form a contact hole 26b on the second plug 18b in the memory cell region 1 to expose the second plug 18b. Then, a TiN film having a thickness of 100 nm is formed by sputtering on the second interlayer insulating film 26 and in the contact holes 26a and 26b. Subsequently, the TiN film is patterned by photolithography to electrically connect the second plug 18b on the p-well 12a and the capacitor upper electrode 25 through the contact holes 26a and 26b in the memory cell region 1. A local wiring (local wiring) 27 is formed.
[0056]
Next, steps required until a structure as shown in FIG.
[0057]
First, a TEOS film is formed on the local wiring 27 and the second interlayer insulating film 26 to a thickness of 200 to 400 nm, for example, 300 nm by plasma CVD. This TEOS film is Third interlayer insulating film (third insulating film) Used as 31. Note that the unevenness difference of the upper surface of the third insulating film 31 thereon reflects the unevenness of the upper surface of the second interlayer insulating film 26 therebelow and is not so large as to require polishing.
[0058]
Subsequently, a contact hole is formed on the first plug 18a at the center position of the p-well 12a by patterning the third interlayer insulating film 31 in the memory cell region 1 to the underlying SiON film 21 by photolithography. 31 a is formed, and contact holes 31 c to 31 e are also formed on the plugs 18 c to 18 e in the peripheral circuit region 2.
[0059]
Further, four layers of Ti film, TiN film, Al (aluminum) film and TiN film are sequentially laminated on the third interlayer insulating film 31 and in the contact holes 31c to 31e, and these metal films are patterned. Thus, the bit line 32a is formed in the memory cell region 1, and the wirings 32c to 32e are formed in the peripheral circuit region 2. These bit lines 32a and wirings 32c to 32e are first-layer aluminum wirings.
[0060]
The bit line 32a in the memory cell region 1 is connected to the first plug 18a, and the wirings 32c to 32e in the peripheral circuit region 2 are connected to the plugs 18c to 18e.
[0061]
For example, the lowermost Ti film has a thickness of 20 nm, the lower TiN film has a thickness of 50 nm, the Al film has a thickness of 500 nm, and the upper film has a thickness of each metal film constituting the bit line 32a and the wirings 32c to 32e. The thickness of the TiN film is 100 nm.
[0062]
Next, as shown in FIG. 8, TEOS gas and oxygen (O ₂ ) By plasma CVD using gas, 4th insulating film SiO with a thickness of 2.0 μm ₂ A fourth interlayer insulating film 33 is formed on the third interlayer insulating film 31, the bit line 32a, and the wirings 32c to 32e.
[0063]
The apparatus used for the plasma CVD has a chamber in which a first electrode on which the silicon substrate 10 is placed and a second electrode facing the first electrode is disposed, and applies high-frequency power to the second electrode, and the first electrode Has a single frequency application structure with a constant voltage. The film forming conditions at this time are a growth temperature of 400 ° C. or lower, for example, 390 ° C., and a pressure of 1.2 Pa. The frequency of the high frequency power is 13.56 MHz and the power is 400 W. Note that the flow ratio of oxygen to the TEOS gas is set to about 1, for example. According to these conditions, the ferroelectric material constituting the capacitor Q is hardly deteriorated during the film formation, and the bit line 32a and the wirings 32c to 32e are not adversely affected.
[0064]
Incidentally, since the fourth interlayer insulating film 33 formed by the plasma CVD method using TEOS gas and oxygen gas isotropically grows, the shape of the upper surface of the fourth interlayer insulating film 33 is the bit line below it. It becomes easy to be influenced by the shape of the aluminum wiring of the first layer such as 32a and wirings 32c to 32e. Therefore, when the second layer aluminum wiring is formed on the TEOS film which is the fourth interlayer insulating film 33, the patterning accuracy of the second layer aluminum wiring is lowered or disconnection is likely to occur. There's a problem.
[0065]
Therefore, in order to flatten the upper surface of the TEOS film which is the fourth interlayer insulating film 33, a step of polishing the upper surface by CMP is employed as shown in FIG. The amount of polishing is approximately equivalent to a thickness of about 1.0 μm from the top surface.
[0066]
By the way, when the fourth interlayer insulating film 33 is polished by the CMP method and then the fourth interlayer insulating film 33 is heated as will be described later, it is apparent from experiments that the polarization charge amount of the capacitor Q is reduced by the heating. became.
[0067]
This is because moisture in the slurry used for planarization by the CMP method and moisture in the cleaning liquid used for subsequent cleaning adhere to the surface of the TEOS film as the fourth interlayer insulating film 3. This is because it is absorbed inside and reaches the capacitor Q below, and the moisture deteriorates the capacitor Q by heating.
[0068]
That is, when the capacitor Q is heated at a high temperature after the polishing of the fourth interlayer insulating film 33, the ferroelectric material constituting the capacitor dielectric film 24 is reduced by the moisture in the interlayer insulating film, and the ferroelectricity is increased. This is considered to be due to the loss of the interface between the ferroelectric material and the electrode due to moisture. In particular, when the fourth interlayer insulating film 33 and the third interlayer insulating film 31 are heated in a state where the fourth interlayer insulating film 33 is covered with a metal film to be described later, the fourth interlayer insulating film 33 absorbs the fourth interlayer insulating film 33. The released moisture is less likely to be released to the outside, penetrates into the third interlayer insulating film 31 through the gap between the bit wirings 32a, and reaches the periphery of the capacitor Q. Degradation will progress.
[0069]
Therefore, in order to remove moisture that has entered the fourth interlayer insulating film 33 at the time of polishing or moisture that has adhered to the surface of the fourth interlayer insulating film 33 to prevent deterioration of the capacitor Q, as shown in FIG. The film 33 is dehydrated by plasma annealing.
[0070]
That is, after the fourth interlayer insulating film 33 is planarized by the CMP method, the silicon substrate 10 is placed in a chamber of a plasma generator (not shown), and N in the chamber. ₂ O gas 700sccm, N ₂ Gases are supplied at a flow rate of 200 sccm, these gases are converted into plasma, and the substrate temperature is set to 450 ° C. or lower, for example, 350 ° C., for 3 minutes or more, preferably 4 minutes or more, and the fourth interlayer insulating film 33 is turned into plasma. Expose. As a result, moisture in the fourth interlayer insulating film 33 is released to the outside, and at least the surface of the fourth interlayer insulating film 33 enters nitrogen (N) atoms to form SiON. Is difficult to enter.
[0071]
When trying to nitride a plasma TEOS film with N atoms using a heat treatment that does not use plasma, the N ₂ Since the molecules are inactive, heat treatment at 1000 ° C. or higher is necessary. Also more active ammonia (NH _Three ) Even when molecules are used, heat treatment at 750 ° C. or higher is required, which causes a problem that the lower aluminum wiring layer is melted. In order to effectively nitride the plasma TEOS film, plasma annealing is most effective.
[0072]
Since the plasma annealing is performed at a temperature of 450 ° C. or lower, the first-layer aluminum wirings 32a and 32c to 32e formed from aluminum under the plasma annealing are not adversely affected.
[0073]
In Japanese Patent Laid-Open No. 10-83990 (US Pat. No. 6,017784), after forming a silicon oxide film using TEOS gas, N ₂ Or N ₂ It is described that hydrogen in a silicon oxide film is degassed by O 2 plasma treatment. This plasma treatment is not performed on the polished silicon oxide film, and is not performed on the silicon oxide film covering the ferroelectric capacitor.
[0074]
In contrast, in the embodiment of the present invention, SiO formed using TEOS. ₂ After the surface of the fourth interlayer insulating film 33 made of is polished, the fourth interlayer insulating film 33 is subjected to plasma annealing, and N is removed in order to remove moisture that has entered during the polishing process. ₂ There is no description in the above literature about the effectiveness of O plasma annealing. Further, in the present embodiment, it has been clarified that the characteristics of the ferroelectric or high-dielectric capacitor Q are satisfactorily maintained even after the plasma annealing under the above conditions.
[0075]
After the plasma annealing process as described above is finished, as shown in FIG. Fifth insulating film (hereinafter referred to as “re-deposited interlayer insulating film”) As 34, a TEOS film is formed on the interlayer insulating film 33 to a thickness of 100 nm or more, for example, 200 nm. The redeposited interlayer insulating film 34 is formed to cover the cavity appearing on the polished surface of the fourth interlayer insulating film 33 as described below. The redeposited interlayer insulating film 34 functions as a cap layer, and has an effect of preventing the interlayer insulating film 33 from resorbing moisture. Redeposited interlayer insulation film 34 The optimum film thickness will be described later.
[0076]
Note that the redeposited interlayer insulating film 34 is formed of N. ₂ O Plasma annealing may be performed.
[0077]
By the way, as described above, cavities (also referred to as voids) called keyholes or slits may appear on the polished surface of the fourth interlayer insulating film 33 for the following reason.
[0078]
When a TEOS film is formed by plasma CVD, the TEOS film isotropically grows to a thickness of about 2.0 μm. When the TEOS film reaches a thickness of about 2.0 μm, the bit line in the memory cell region 1 is formed between the first aluminum wirings. Cavities are likely to occur between 32a and between the first-layer aluminum wirings 32c to 32e in the peripheral circuit region 2.
[0079]
Incidentally, as shown in FIG. 17A, since the bit line 32a is lifted by the capacitor Q, the cavity 33u generated between the bit lines 32a is formed at a position higher than the cavity 33u generated in other regions. Will be.
[0080]
Therefore, after the fourth interlayer insulating film 33 made of the TEOS film is polished, as shown in FIG. 17B, the cavities 33u existing in the memory cell region 1 are easily exposed from the polishing surface.
[0081]
17 (a) is a cross-sectional view taken along the line II in FIG. 8, and FIG. 17 (b) is a cross-sectional view taken along the line II-II in FIG. 9. Reference numerals 32f and 32g in FIG. Is shown.
[0082]
As described above, the cavity 33u exposed from above the fourth interlayer insulating film 33 in the memory cell region 1 is exposed in a groove shape between the bit lines 32a. Therefore, the fourth cavity is exposed with the cavity 33u exposed. When the wiring forming metal film is formed directly on the interlayer insulating film 33, the metal film is embedded in the cavity 33u, and even after the wiring is formed by patterning the metal film, the metal film is embedded in the cavity 33u. The metal film remains without being removed. Since the metal film in the cavity 33u serves as a medium for short-circuiting the wirings formed from the same metal film, it is necessary not to form the metal film in the cavity 33u in advance.
[0083]
In the present embodiment, as shown in FIG. 11, after the fourth interlayer insulating film 33 is polished, the redeposited interlayer insulating film 34 covers the polished surface of the fourth interlayer insulating film 33. A metal film is not formed in the cavity 33 u exposed from the polished surface of the fourth interlayer insulating film 34. The cross section taken along the line III-III in FIG. 11 is as shown in FIG.
[0084]
FIG. 19A is a cross-sectional view showing the fourth interlayer insulating film 33 and the underlying structure when there is no redeposited interlayer insulating film 34, and FIG. 19B is the fourth interlayer insulating film 33. It is sectional drawing which shows the state which formed the redeposition interlayer insulation film 34 on the top. 19A and 19B are drawn based on a cross-sectional photograph of the FeRAM memory cell region.
[0085]
After forming the redeposited interlayer insulating film 34 as described above, the process proceeds to a step of forming a second-layer aluminum wiring as shown in FIGS.
[0086]
First, as shown in FIG. 12, the redeposited interlayer insulating film 34 and the fourth interlayer insulating film 33 are patterned by photolithography, and a via hole reaching the first aluminum wiring, for example, the wiring 32d in the peripheral circuit region 2 is formed. 33a is formed. Thereafter, the surface of the underlying wiring 32d is etched through the via hole 33a with a predetermined amount, for example, a depth of 35 nm.
[0087]
Subsequently, as shown in FIG. 13, a 20 nm thick Ti film and a 50 nm thick TiN film are sequentially formed on the inner surface of the via hole 33a and the upper surface of the redeposited interlayer insulating film 34 by sputtering. Let it be layer 35a. FIG. 18B is a sectional view taken along the line IV-IV in FIG.
[0088]
Then tungsten hexafluoride (WF ₆ Gas and Silane (SiH) _Four ) A tungsten seed (not shown) is formed on the glue layer 35a by a CVD method using a gas. In addition, WF ₆ Gas and Silane (SiH _Four ) Hydrogen to gas (H ₂ ) A gas is added to increase the growth temperature to 430 ° C. to form a tungsten film 35b on the glue layer 35a. As a result, as shown in FIG. 14, the via layer 33a is filled with the glue layer 35a and the tungsten film 35b.
[0089]
Thereafter, the tungsten film 35b on the upper surface of the redeposited interlayer insulating film 34 is removed by CMP or etch back, and remains only in the via hole 33a. At this time, the glue layer 35a on the redeposited interlayer insulating film 34 may or may not be removed. FIG. 15 shows a case where the glue layer 35a is removed from the upper surface of the redeposited interlayer insulating film 34 by the CMP method.
[0090]
Thus, a via (plug) 35 for electrically connecting the wiring 32d and the upper layer wiring is formed in the via hole 33a.
[0091]
By the way, the width of the cavity 33u appearing from the polished surface of the fourth interlayer insulating film 33 is not uniform due to variations in polishing by the CMP method. When the exposed width of the cavity 33u varies, the following problem occurs.
[0092]
That is, as shown in FIG. 20A, when the thin redeposited interlayer insulating film 34 is formed on the cavity 33u exposed from the fourth interlayer insulating film 33, the cavity is formed as shown in FIG. In some cases, 33u is not completely covered by the redeposited interlayer insulating film 34, but a part thereof is exposed. In such a state, as shown in FIG. 20 (c), when the above-described glue layer 35a is formed, the glue layer 35a may be stepped on the cavity 33u to form a slit, If the slit exists, hydrogen in the reaction gas used when forming the tungsten film 35b enters the fourth interlayer insulating film 33 therebelow through the slit, as shown in FIG. 20 (d). Hydrogen entering the fourth interlayer insulating film 33 is not preferable because it reduces the capacitor Q and deteriorates the capacitor characteristics.
[0093]
Thus, it has been clarified from experimental results that the redeposited interlayer insulating film 34 needs to have a film thickness of at least 300 nm or more in order to reliably cover the cavity 33u exposed from the fourth interlayer insulating film 33.
[0094]
By the way, in order to prevent the cavity 33u from being filled with the glue layer 35a or the tungsten film 35b, an investigation was made of the required film thickness of the redeposited interlayer insulating film 34. The result shown in FIG. Obtained. The vertical axis in FIG. 21 indicates the frequency of occurrence of leakage between wirings, and the horizontal axis indicates the leakage current value. According to the result of FIG. 21, when the film thickness of the redeposited interlayer insulating film 34 is 50 nm, the frequency of leakage between wirings increases. As the film thickness increases, the frequency of leakage between wirings decreases, and when the film thickness increases, the shorting between wirings occurs substantially. I found that it can be prevented. Therefore, it is desirable that the film thickness of the redeposited interlayer insulating film 34 be at least 100 nm in order to reduce the leakage between wirings due to the exposure of the cavity 33u.
[0095]
On the other hand, a glue layer 35a and a tungsten film 35b are formed on the redeposited interlayer insulating film 34, and this is patterned to form a plug 35, on which a second-layer aluminum wiring described later is formed, After a series of steps such as covering the second-layer aluminum wiring with an insulating film, the relationship between the film thickness of the redeposited interlayer insulating film 34 and the change in the capacitor polarization charge amount by the acceleration test was investigated. The results as shown in Fig. 1 were obtained. The acceleration test was performed by heating the substrate in the atmosphere at a temperature of 200 ° C. for 1 hour.
[0096]
[Table 1]

[0097]
According to Table 1, in the state before the acceleration test, the thicker the redeposited interlayer insulating film, the slightly larger the polarization charge amount. However, after heating, the difference in the amount of polarization charge between samples becomes significant. In particular, when the redeposited interlayer insulating film 34 is 0 nm, that is, when the redeposited interlayer insulating film 34 is not formed, the polarization charge amount is reduced to half or less after heating, and the characteristics of the ferroelectric capacitor Q are remarkably deteriorated. When the redeposited interlayer insulating film 34 is 300 nm, the ferroelectric capacitor Q is slightly deteriorated, and the polarization charge after heating is 22.6 μC / cm. ² Thus, the value is sufficient for normal operation of the FeRAM.
[0098]
The film thickness of 300 nm of the redeposited interlayer insulating film 34 is determined in consideration of the variation of the exposed portion of the cavity 33u.
[0099]
By the way, if the redeposited interlayer insulating film 34 is too thick, the aspect ratio of the via hole 33a is increased and the coverage of the glue layer 35a and the tungsten film 35b is deteriorated in the via hole 33a. That is, the upper limit value of the film thickness of the redeposited interlayer insulating film 34 is determined from the aspect ratio of the via hole 33a. For example, when the aspect ratio of the via hole 33a is 2.3 and the diameter of the via hole 33a is 0.6 μm and the thickness of the fourth interlayer insulating film 33 is 1.0 μm, the redeposited interlayer insulating film 34 The film thickness needs to be about 0.4 μm (400 nm).
[0100]
After completing the steps of forming the redeposited interlayer insulating film 34 and the via 35 by the above-described steps, the first TiN film is 50 nm, the Al film is 500 nm, and the second TiN is formed on the redeposited interlayer insulating film 34. Films are sequentially formed to a thickness of 50 nm, and these films are patterned to form wirings 36. When leaving the glue layer 35a on the upper surface of the redeposited interlayer insulating film 34, the formation of the first TiN film is omitted and the aluminum film and the second TiN film are formed on the glue layer 35a. .
[0101]
Next, by patterning the first and second TiN film and Al film, or the second TiN film, Al film and glue layer by photolithography, a second layer of aluminum is formed as shown in FIG. A wiring 36 is formed on the redeposit interlayer insulating film 34.
[0102]
Thereafter, SiO 2 as a first cover insulating film 37 is formed on the second-layer aluminum wiring 36 and the redeposited interlayer insulating film 34 by plasma CVD using TEOS. ₂ A film is formed to a thickness of 200 nm. Further, a second cover insulating film 38 made of SiN is formed on the first cover insulating film 37 to a thickness of 500 nm by plasma CVD. The first and second cover films 37 and 38 cover the second-layer wiring 36.
[0103]
The planar positional relationship of various conductive patterns in the memory cell region 1 after the formation of the second-layer aluminum wiring 36 is as shown in FIG. In FIG. 22, insulating films other than the element isolation insulating film 11 are omitted.
[0104]
The basic structure of the FeRAM using a ferroelectric material as the capacitor dielectric film 24 is completed through the processes described above.
[0105]
In the present embodiment, the upper surface of the fourth interlayer insulating film 33 covering the capacitor Q and the first-layer aluminum wirings 32a, 32c to 32e is planarized by the CMP method. As a result, the pattern accuracy of the second-layer aluminum wiring 36 formed flat on the interlayer insulating film 33 formed on the capacitor Q and the wiring 32a can be improved.
[0106]
Further, after polishing the interlayer insulating film 33, N ₂ Since moisture in the interlayer insulating film 33 is removed by performing O plasma annealing, reduction and deterioration of the ferroelectric film (capacitor dielectric film 24) can be avoided even when heated in the subsequent process. As a result, a FeRAM having good characteristics can be manufactured. And N ₂ O Since the plasma annealing is performed at 450 ° C. or lower, the first-layer aluminum wiring is not deteriorated.
[0107]
Such N ₂ When the amount of polarization charge of the capacitor Q when the FeRAM is formed by inserting the O plasma annealing step and when the FeRAM is formed by omitting the step, the results shown in the following Table 2 are obtained. ₂ O It was confirmed that plasma annealing was effective to prevent capacitor deterioration.
[0108]
[Table 2]

[0109]
In the above embodiment, N ₂ Although the case where the interlayer insulating film 33 is dehydrated by plasma annealing using O 2 has been described, the gas used for the dehydration process is N ₂ Not limited to O, for example N ₂ Gas, O ₂ Similar effects can be obtained by plasma annealing using gas or NO gas. The gas used for plasma annealing is N ₂ O + N ₂ , N ₂ + O ₂ Or a mixed gas such as Furthermore, an inert gas such as argon (Ar), helium (He), or neon (Ne) may be mixed with such a single gas or a mixed gas to form plasma.
[0110]
Furthermore, in the above embodiment, after the dehydration process is performed on the interlayer insulating film 33, the redeposited interlayer insulating film 34 is formed. However, the redeposited interlayer insulating film 34 is formed on the interlayer insulating film 33 after CMP. After that, dehydration treatment may be performed.
[0111]
When the redeposited interlayer insulating film 34 is formed thin as in the above embodiment, the amount of moisture contained in the redeposited interlayer insulating film 34 is extremely small. The capacitor dielectric film may be reduced by moisture contained in the deposited interlayer insulating film 34. In order to prevent this, after the redeposited interlayer insulating film 34 is formed, N ₂ Dehydration by plasma annealing using O 2 or NO may be performed. However, in this case, if the redeposited interlayer insulating film 34 is formed of a silicon oxynitride (SiON) film by a plasma CVD method or a silicon nitride (SiN) film by a plasma CVD method, these films are difficult to pass moisture. The moisture in the interlayer insulating film 33 cannot be sufficiently removed. Therefore, when plasma annealing is performed after the redeposited interlayer insulating film 34 is formed, the redeposited interlayer insulating film 34 is replaced with a plasma TEOS film, O _Three -TEOS film or plasma SiO ₂ It is preferable to form with a film.
[0112]
That is, as the redeposited interlayer insulating film 34, instead of the TEOS film (P-TEOS film) formed by the plasma CVD method described above, ozone (O _Three ) And TEOS formed using TEOS (O _Three -TEOS) film, SiO formed by plasma CVD method ₂ (P-SiO ₂ ) Film, non-biased HDP (High Density Plasma)-SiO formed by CVD ₂ A film, a SiON (P-SiON) film formed by a plasma CVD method, a SiN (P-SiN) film formed by a plasma CVD method, or the like may be used. However, O _Three Since the -TEOS film has a higher moisture content than the P-TEOS film, the P-TEOS film is used in this embodiment. Further, since the SiON film and the SiN film have low moisture permeability, when these films are used as the redeposited interlayer insulating film 34, after the fourth interlayer insulating film 33 is dehydrated, the redeposited interlayer insulating film is used. 34 need to be formed.
[0113]
FIG. 23 is a diagram showing the dependence of the polarization charge amount on the dehydration time, with the horizontal axis representing the plasma annealing time for the P-TEOS film and the vertical axis representing the polarization charge amount (Qsw). However, the conditions for the plasma annealing are as follows: the temperature is 350 ° C., the power applied to the plasma is 300 W, N ₂ O 2 flow rate is 700sccm, N ₂ The gas flow rate is 200 sccm. It can be said that the larger the value of the polarization charge amount Qsw, the better the polarization characteristics.
[0114]
As can be seen from FIG. 23, sufficient characteristics can be obtained by setting the plasma annealing treatment time to 3 minutes or more. The amount of polarization charge in the initial state of the ferroelectric film is about 28 μC / cm. ² It can be restored to the initial polarization charge amount by plasma annealing for about 4 minutes.
[0115]
In the above-described embodiment, as the fourth interlayer insulating film 33, SiO formed by plasma CVD using TEOS gas is used. ₂ A film (p-TEOS) was used. _Three TEOS (O _Three -TEOS) film, SiO formed by plasma CVD method ₂ (P-SiO ₂ ) A film may be used. O _Three The -TEOS film has a slower growth rate than the P-TEOS film, but no cavity is formed in the film.
[0116]
In the above-described embodiments, the FeRAM and the process for forming the FeRAM have been described. However, in the case of a volatile memory (DRAM) having a high dielectric capacitor, the insulating property of the high dielectric material deteriorates due to moisture and heating. The interface between the dielectric material film and the electrode tends to deteriorate. Therefore, as described above, after planarizing the upper surface of the insulating film formed on the high dielectric capacitor by the CMP method, the surface is made N. ₂ The insulating film is dehydrated using a gas such as O 2 or NO, or a redeposition layer is formed using P-TEOS on the planarized surface after such dehydration or before dehydration. An insulating film may be formed. (BaSr) TiO as a high dielectric material _Three A high dielectric material such as, for example, may be used.
[0117]
The present invention can also be applied to the manufacture of a so-called system LSI in which a ferroelectric nonvolatile semiconductor memory or a high dielectric semiconductor memory and a logic device are mixedly mounted.
[0118]
【The invention's effect】
As described above, according to the present invention, since the insulating film formed further on the capacitor and the wiring passing therethrough is polished and planarized, the wiring is formed on the flat surface of the insulating film. It becomes easy to form with high accuracy.
[0119]
In addition, N is applied to the polished insulating film. ₂ Since the dehydration process by plasma annealing containing O or NO was performed, the moisture adhering to the surface of the insulating film and the moisture penetrating into the insulating film can be more reliably removed, Reduction of the ferroelectric material or high dielectric material constituting the capacitor and deterioration of the capacitor can be prevented. Therefore, deterioration of the dielectric characteristics of the ferroelectric material or the high dielectric material can be avoided, and an FeRAM or DRAM having good characteristics can be manufactured.
[Brief description of the drawings]
FIG. 1 is a sectional view (No. 1) showing a method for manufacturing a semiconductor device according to an embodiment of the invention;
FIG. 2 is a sectional view (No. 2) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 3 is a sectional view (No. 3) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 4 is a sectional view (No. 4) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 5 is a sectional view (No. 5) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 6 is a sectional view (No. 6) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 7 is a sectional view (No. 7) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 8 is a cross-sectional view (No. 8) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 9 is a cross-sectional view (No. 9) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 10 is a cross-sectional view (No. 10) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
11 is a sectional view (No. 11) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention; FIG.
FIG. 12 is a cross-sectional view (No. 12) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 13 is a cross-sectional view (No. 13) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 14 is a cross-sectional view (No. 14) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 15 is a cross-sectional view (No. 15) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 16 is a cross-sectional view (No. 16) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention;
17 (a) is a cross-sectional view taken along the line II of FIG. 8, and FIG. 17 (b) is a cross-sectional view taken along the line II-II of FIG.
18A is a cross-sectional view taken along line III-III in FIG. 11, and FIG. 18B is a cross-sectional view taken along line IV-IV in FIG.
FIG. 19 (a) is a cross-sectional view drawn based on a photograph of the cross section of FIG. 17 (b), and FIG. 19 (b) is a photograph of the cross section of FIG. 18 (a). It is sectional drawing drawn based on this.
20A to 20D are cross-sectional views showing a process in which the cavity shown in FIG. 17B is not sufficiently filled with an insulating film.
FIG. 21 is a diagram showing the relationship between the leakage current of a capacitor used in the memory cell of the semiconductor device according to the embodiment of the present invention and the cumulative probability, where the vertical axis showing the cumulative probability and the amount of leakage current The horizontal axis indicating is shown on a logarithmic scale.
FIG. 22 is a plan view showing a conductive pattern arrangement in the memory cell region of the semiconductor device according to the embodiment of the present invention;
FIG. 23 is a graph showing the dehydration time dependence of the polarization charge amount of the capacitor formed in the semiconductor device according to the embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Element isolation insulating film, 12a, 12b ... Well region, 13a, 13b, 13c ... Gate electrode, 15a, 15b ... Impurity diffusion region, 16 ... Side wall, 17, 26, 31, 33 ... Interlayer Insulating film, 18 ... plug, 21 ... SiON film, 22 ... SiO ₂ Membrane, 23 ... Lower electrode, 24 ... Dielectric film, 25 ... Upper electrode, 27 ... Local wiring, 32a ... Bit line, 32b-32g ... Wiring, 34 ... Redeposited interlayer insulating film, 35a ... Glue layer, 35b ... Tungsten Membrane, 35 ... plug, 36 ... aluminum wiring, 37, 38 ... cover membrane.

Claims (7)

A transistor having a first impurity region and a second impurity region formed in a semiconductor substrate and a gate electrode formed on the semiconductor substrate;
A first insulating film covering the transistor;
A capacitor formed on the first insulating film and having a dielectric film made of either a ferroelectric material or a high dielectric material, and an upper electrode and a lower electrode sandwiching the dielectric film;
A second insulating film formed on the capacitor;
A local wiring formed on the second insulating film and connecting the upper electrode of the capacitor and the first impurity region;
A third insulating film formed on the local wiring and the second insulating film;
A first wiring formed on the third insulating film and connected to the second impurity region through a hole formed in the first, second and third insulating films;
A fourth insulating film formed on the first wiring by a plasma CVD method using a TEOS gas and an oxygen gas , and the upper surface flattened by polishing is dehydrated by plasma annealing ;
A semiconductor device comprising: a second wiring formed on the fourth insulating film. 2. The semiconductor device according to claim 1, wherein a cavity that is partially exposed from the upper surface of the fourth insulating film is formed in the fourth insulating film. The semiconductor device according to claim 2, wherein the cavity exists in a region between the plurality of capacitors. 5. The fifth insulating film according to claim 2, wherein a fifth insulating film that covers the cavity exposed from the upper surface of the fourth insulating film is formed on the fourth insulating film. The semiconductor device described. 5. The semiconductor device according to claim 1, wherein the second wiring is connected to the first wiring through a hole formed in the fourth insulating film. 6. The semiconductor device according to claim 1, wherein the third and fourth insulating films are silicon oxide films. The semiconductor device according to claim 1, wherein an upper surface of the first insulating film is a flattened surface.

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