JP3803503B2 - Magnetic random access memory circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a magnetic random access memory (MRAM) circuit (hereinafter referred to as “MRAM circuit”).
[0002]
[Prior art]
In a magnetic random access memory, a plurality of memory cells are arranged at the intersections of word lines and bit lines. Basically, the memory cell is composed of an insulating layer or a metal layer and two ferromagnetic layers sandwiching it. Digital information is represented by the direction of magnetization of the ferromagnetic layer, and the information is held indefinitely unless it is intentionally rewritten. In order to rewrite the state of the memory cell, a synthetic magnetic field larger than the threshold value is applied to the memory cell by the word current and the bit current to reverse the magnetization of the ferromagnetic layer.
[0003]
As a first technique, a giant magnetoresistive (GMR) is disclosed as a memory cell disclosed in US Pat. No. 5,748,519 and IEEE Transaction On Components Packaging and Manufacturing Technology-Part A Vol. 170 No. 3 pp373-379. FIG. 6 shows a simplified MRAM circuit using elements. This MRAM circuit is generally formed on a semiconductor substrate, and other circuits are mixedly mounted on the same substrate. The MRAM circuit includes a memory array (first array 604 and second array 605), a decoder (row decoder 602 and column decoder 603), and a comparator 606. The row decoder 602 and the column decoder 603 are connected to the address bus 601, respectively. One of the first array 604 and the second array 605 is used as a reference cell at the time of reading.
[0004]
As a second conventional technique, a magnetic tunnel junction (MTJ) element disclosed in US Pat. No. 5,640,343 is used as a memory cell, and one memory cell is formed at the intersection of each word line and sense line. FIG. 7 shows an MRAM circuit having a memory array in which is arranged. This MRAM circuit is composed of row decoders 701 and 702, column decoders 703 and 704, and a matrix circuit having a magnetic tunnel junction element at an intersection connected thereto. The MRAM circuit operates in accordance with the stored information corresponding to the magnitude of the sense current. However, in this disclosure, the voltage detection method and the connection method to the comparator (sense amplifier) are not described.
[0005]
[Problems to be solved by the invention]
In the first prior art, since a separate word line is required for each of the memory cell and the reference cell, the memory cell array and the reference cell array are separated or their distances are separated. Therefore, parasitic elements are easily included in each comparison signal, and it is difficult to realize a sufficient operation margin. Therefore, the uniformity of the characteristics of the memory cell on the wafer is required. Further, since the memory cell area is large, integration and miniaturization are difficult.
[0006]
An object of the present invention is to provide an MRAM circuit whose characteristics do not depend on variations in characteristics of magnetoresistive elements depending on the location on the wafer. It is another object of the present invention to provide an MRAM circuit capable of reading with high sensitivity that eliminates the influence of wiring resistance as much as possible. It is another object of the present invention to provide an MRAM circuit having a circuit configuration effective for integration.
[0007]
[Means for Solving the Problems]
A magnetic random access memory circuit according to the present invention includes a plurality of word lines, a plurality of pairs of sense lines, and a pair of one of the plurality of word lines and a pair of the plurality of sense lines. A plurality of memory cells connected to one of the sense lines, each of which is one word line of the plurality of word lines and the other of the pair of sense lines of the pair of sense lines When writing information to a plurality of reference cells connected to a sense line, a predetermined memory cell and a reference cell, data should be written to both sense lines of a pair of sense lines corresponding to the memory cell and the reference cell. Means for flowing currents in opposite directions between the pair of sense lines corresponding to the information and flowing currents in a predetermined direction to the word lines corresponding to the memory cells and the reference cells. And wherein the Rukoto.
The memory cell and the reference cell can include magnetoresistive elements.
[0008]
Furthermore , the magnetic random access memory circuit according to the present invention is characterized in that, in the magnetic random access memory circuit, the memory cell and the reference cell further include a diode connected in series to the magnetoresistive element.
[0009]
Furthermore, the magnetic random access memory circuit according to the present invention is characterized in that, in the magnetic random access memory circuit, the memory cell and the reference cell further include a transistor connected in series to the magnetoresistive element.
[0010]
Furthermore, the magnetic random access memory circuit according to the present invention further comprises a row decoder for decoding a part of the address and a column decoder for decoding the remaining part of the address in the magnetic random access memory circuit described above. the decoding terminal coupled said plurality of pairs of sense lines, said decode terminal of the column decoder is connected to said plurality of word lines, the row decoder are two, said column decoder are two, the Each of the plurality of pairs of sense lines connects between the decode terminals of the two row decoders, and each of the plurality of word lines connects between the decode terminals of the two column decoders. Features.
[0011]
Furthermore, in the magnetic random access memory circuit according to the present invention, in the magnetic random access memory circuit described above, at the time of writing, the two row decoders cause currents in opposite directions to flow in both lines of the pair of sense lines in the selected row. The two column decoders are characterized in that a current flows through the word line of the selected column.
[0012]
Furthermore, in the magnetic random access memory circuit according to the present invention, in the magnetic random access memory circuit described above, at the time of reading, the row decoder and the column decoder store a cell pair at an intersection of a selected row and a selected column. A current having the same value is allowed to flow in the cell and the reference cell.
[0013]
Furthermore, in the magnetic random access memory circuit according to the present invention, in the magnetic random access memory circuit described above, the voltage at the terminal on the sense line side of the memory cell of the cell pair at the intersection of the selected row and the selected column at the time of reading. And comparing means for comparing the voltage at the terminal on the sense line side of the reference cell of the cell pair.
[0014]
Furthermore, in the magnetic random access memory circuit according to the present invention, in the magnetic random access memory circuit described above, the comparing means includes a comparator and two auxiliary lines each connected to two input terminals of the comparator. A plurality of transistors for connecting one of the two auxiliary lines to a sense line to which a memory cell in a selected row is connected, and a reference cell in the selected row on the other of the two auxiliary lines. And a plurality of transistors for connecting to a sense line to be connected.
[0015]
Furthermore, the magnetic random access memory according to the present invention is the above-described magnetic random access memory circuit, wherein in the magnetic random access memory circuit, means for flowing a current to the memory cell to be read and a reference cell paired therewith, and the reference to be paired with the memory cell to be read. Means is provided for detecting a voltage drop in the cells when a current is passed by a four-terminal method.
[0016]
Furthermore, the magnetic random access memory circuit according to the present invention is characterized in that in the magnetic random access memory circuit, the magnetoresistive element is a spin tunnel element.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described in detail with reference to FIGS.
[0018]
[Embodiment 1]
First, Embodiment 1 of the present invention will be described.
[0019]
FIG. 1 shows an MRAM circuit according to the first embodiment. The MRAM circuit includes a memory array 106, a decoder set, and a comparator 107. The memory array 106 includes a plurality of storage cells 21a, 21b, 21c, 22a, 22b, 22c and reference cells 21ra, 21rb, 21rc, 22ra, 22rb, 22rc that are paired with the storage cells 21a, 21b, 21c, 22a, 22b, 22rc. Arranged at the intersections of the word lines 2a, 2b, 2c and the sense lines 21, 21r, 22, 22r.
[0020]
The decoder set includes row decoders 102 and 103 and column decoders 104 and 105, which are connected to the address bus 101. The column decoder 104 has switch transistors 111, 112, and 113, and the column decoder 105 has switch transistors 121, 122, and 123, and the word lines 2a, 2b, and 2c are in a write state or a ground level state by ON / OFF thereof. Switch to. The row decoder 102 includes switch transistors 131, 132, 133, and 134, and the row decoder 103 includes switch transistors 141, 142, 143, and 144. When the row decoder 102 is on, the sense lines 21, 22, 21r, and 22r are connected to the row decoder 102. To a predetermined circuit.
[0021]
One end of the sense line (auxiliary line) 24 is connected to the sense lines 21 and 22 via pass transistors 151 and 153. The other end of the sense line 24 is connected to the plus side input terminal of the comparator 107. One end of the sense line (auxiliary line) 25 is connected to the sense lines 21r and 22r via pass transistors 152 and 154. The other end of the sense line 25 is connected to the negative side input terminal of the comparator 26.
[0022]
Reference numerals 21a, 21b, 21c, 22a, 22b, and 22c are assigned to memory cells. Reference cells 21ra, 21rb, 21rc, 22ra, 22rb, and 22rc are attached to reference cells, and disposing these in the vicinity of the memory cells can reduce the influence of wide variations in wiring resistance. It becomes possible. In this MRAM circuit, 1-bit information is stored in two spin tunnel elements (memory cell and reference cell). As a result, the S / N of the memory cell can be increased and the common-mode noise can be removed.
[0023]
FIG. 2 shows the structure of the memory cell 21a. Other memory cells 21b, 21c, 22a, 22b, 22c and reference cells 21ra, 21rb, 21rc, 22ra, 22rb, 22rc also have the same structure as the memory cell 21a.
[0024]
In the memory cell 21a, a first ferromagnetic layer 81 and a second ferromagnetic layer 82 are stacked with an insulating layer 83 interposed therebetween. The ferromagnetic layers 81 and 82 are made of a ferromagnetic material such as Ni—Fe—Co, and the insulating layer 83 is made of Al ₂ O _3, for example. These three layers 81, 82, 83 constitute a spin tunnel effect element. An interlayer insulating film 84 is disposed between the insulating layer 83 and the sense line 21. The word line 2a is disposed under the first ferromagnetic layer 81, and a magnetic field generated by the current is applied to the spin tunnel effect element. The sense line 21 is connected to the second ferromagnetic layer 82.
[0025]
Information is written to the ferromagnetic layers 81 and 82 by causing a word current to flow through the word line and a sense current to flow through the sense line, and the resultant magnetic field generated by them reverses the magnetization direction of the ferromagnetic layers 81 and 82. Done. Reading of information in the memory cell 21a is performed by detecting a voltage between the word line 2a and the sense line 21.
[0026]
FIG. 3 shows the relationship between the resistance of the memory cell (which corresponds to the output voltage) and the applied magnetic field. The horizontal axis indicates the direction and strength of the applied magnetic field. The vertical axis represents the resistance value of the memory cell 21a. As shown in FIG. 3, the relationship between the resistance of the memory cell and the applied magnetic field exhibits hysteresis characteristics. The resistance value of the cell 21a in the zero magnetic field shows the same value regardless of the magnetic field vector direction. When the magnetic field is increased from zero to H ₁ , only the magnetization direction of the ferromagnetic layer on one side of the memory cell is rotated by the combined magnetic field, the magnetization directions of the two ferromagnetic layers of the memory cell are opposite to each other, and the resistance increases. To do. When the combined magnetic field intensity increases from H ₁ to H ₂ and reaches H ₂ , the magnetization direction on the side where the magnetization direction has not changed also rotates, and the resistance decreases at H ₂ . Similarly, when a magnetic field in the opposite direction is applied, the same phenomenon occurs in the zero magnetic field, H ₃ and H ₄ .
[0027]
Next, a method of writing information to the memory cell 21a and the reference cell 21ra will be described.
[0028]
In order to select the sense lines 21 and 21r, the transistors 131, 141, 132, and 142 are turned on. In order to select the word line 2a, the transistors 111 and 121 are turned on. When information “1” is written in the memory cell 21a and information “0” is written in the reference cell, the sense currents 92 and 103 and the word current 91 are supplied to the sense lines 21 and 21r and the word line 2a, respectively. On the contrary, when information “0” is written in the memory cell 21a and information “1” is written in the reference cell 21ra, the sense currents 93 and 102 in the direction opposite to the sense currents 92 and 103 and the reference cell are “ The same word current 91 as in the case of writing 0 "information is supplied to the sense lines 21 and 21r and the word line 2a, respectively.
[0029]
Next, a method for reading information from the memory cell 21a and the reference cell 21ra will be described.
[0030]
In order to select the sense lines 21, 21r and the word line 2a, the transistors 131, 132, 121 are turned on. Next, a constant current is passed through the memory cell 21a and the reference cell 21ra. The sense current Is flows between the row decoder 102 and the column decoder 105 through the transistor 131, the sense line 21, the memory cell 21a, the word line 2a, and the transistor 121. On the other hand, the reference sense current Ir flows between the row decoder 102 and the column decoder 105 through the transistor 132, the sense line 21r, the memory cell 21ra, the word line 2a, and the transistor 121. In this state, the transistors 151 and 152 are turned on, and the comparator 107 detects the potential on the sense line side of the memory cell 21a and the reference cell 21ra. This is a method based on the so-called four-terminal method for measuring electrical conduction. That is, this is a measurement method in which a path through which current flows and a path for detecting voltage are provided separately. The four-terminal method is described, for example, on pages 165 to 167 of “Experimental Chemistry Lecture 9 Electricity and Magnetism (4th edition)” (edited by the Chemical Society of Japan). Since the memory cell 21a and the reference cell 21ra are arranged close to each other, the influence of the wiring resistance is small. The potentials on the sense line side of the memory cell 21a and the reference cell 21ra detected by the comparator 107 are the memory cell 21a and the reference cell 21ra, respectively. It is proportional to the resistance value of the reference cell 21ra. Binary information determined corresponding to the potential difference input to the comparator 107 is output to the bit line 26.
[0031]
Further, as shown in FIG. 4, by using a memory cell in which a spin tunnel effect element 401 and a diode 402 are connected in series between a sense line and a word line, the selectivity between the memory cells is further improved. That is, it is possible to reduce the influence of the non-selected memory cell on the selected memory cell due to the current flowing through the non-selected memory cell.
[0032]
[Embodiment 2]
Next, a second embodiment of the present invention will be described.
[0033]
FIG. 5 shows an MRAM circuit according to the second embodiment. This MRAM circuit includes a memory array 506 , a decoder set, and a comparator 107. The memory array 506 includes a plurality of storage cells 31a, 31b, 31c, 32a, 32b, and 32c, and reference cells 31ra, 31rb, 31rc, 32ra, 32rb, and 32rc that are paired therewith. These memory cells and reference cells are composed of spin tunnel effect elements and pass transistors connected in series, and are arranged at the intersections of the word lines 2a, 2b, 2c and the sense lines 21, 21r, 22, 22r. . In this MRAM circuit, 1-bit information is stored in two spin tunnel elements (memory cell and reference cell). As a result, the margin of the memory cell can be increased.
[0034]
Since the method of writing information to the memory cell 31a and the reference cell 31ra in the present embodiment is the same as that in the first embodiment, description thereof is omitted.
[0035]
Next, a method for reading information from the memory cell 31a and the reference cell 31ra will be described.
[0036]
In order to select the sense lines 21, 21r and the word line 2a, the transistors 131, 132, 121 are turned on. Next, the wiring 71 is set to a high potential state, and the transistor connected to the wiring 71 is turned on. Next, a constant current is passed through the memory cell 31a and the reference cell 31ra. The sense current Is flows between the row decoder 102 and the column decoder 105 through the transistor 131, the sense line 21, the memory cell 31a, the word line 2a, and the transistor 121. On the other hand, the reference sense current Ir flows between the row decoder 102 and the column decoder 105 through the transistor 132, the sense line 21r, the memory cell 31ra, the word line 2a, and the transistor 121. In this state, the transistors 151 and 152 are turned on, and the comparator 107 detects the potential on the sense line side of the memory cell 31a and the reference cell 31ra. This is a method based on the so-called four-terminal method.
[0037]
Since the memory cell 31a and the reference cell 31ra are arranged close to each other, the influence of the wiring resistance is small, and the potential on the sense line side of the memory cell 31a and the reference cell 31ra detected by the comparator 107 is the memory cell 31a and the reference cell 31ra. It is proportional to the resistance value of the reference cell 31ra. Binary information determined corresponding to the potential difference input to the comparator 107 is output to the bit line 26.
[0038]
【The invention's effect】
As described above, the characteristics of the MRAM circuit according to the present invention are stable without depending on the wide-range characteristics of the magnetoresistive element on the wafer by arranging the memory cell and the reference cell close to each other. To do.
[0039]
Further, according to the present invention, by using a measurement method based on the four-terminal method as a voltage detection method, it is possible to read out highly sensitive information that greatly eliminates the influence of wiring resistance and the like.
[0040]
Furthermore, even if the wiring resistance is increased by miniaturizing the wiring, the influence of the wiring resistance is small, so that the MRAM circuit according to the present invention can be highly integrated.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a magnetic random access memory circuit according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view and a plan view showing a structure of a magnetoresistive element used as a memory cell and a reference cell.
FIG. 3 is a graph showing the relationship between resistance and magnetic field of a magnetoresistive element.
FIG. 4 is a circuit diagram of a second example of a storage cell and a reference cell of the magnetic random access memory circuit according to the first embodiment of the invention.
FIG. 5 is a circuit diagram showing a configuration of a magnetic random access memory circuit according to a second embodiment of the present invention.
FIG. 6 is a circuit diagram showing a configuration of a magnetic random access memory according to a first conventional example.
FIG. 7 is a circuit diagram showing a configuration of a magnetic random access memory according to a second conventional example.
[Explanation of symbols]
2a, 2b, 2c Word line 21, 21r, 22, 22r, 24, 25 Sense line 21a, 21b, 21c, 22a, 22b, 22c Memory cell 21ra, 21rb, 21rc, 22ra, 22rb, 22rc Reference cell 26 Bit line 31a 31b, 31c, 32a, 32b, 32c Memory cells 31ra, 31rb, 31rc, 32ra, 32rb, 32rc Reference cells 111, 112, 113, 121, 122, 123 Transistors 131, 132, 133, 134 Transistors 141, 142, 143 144 Transistor 101 Address line 102, 103 Row decoder 104, 105 Column decoder 106, 506 Memory array 107 Comparator

Claims (9)

Multiple word lines,
A plurality of pairs of sense lines;
A plurality of memory cells each connected to one of the plurality of word lines and one sense line of the pair of sense lines of the plurality of pairs of sense lines;
A plurality of reference cells each connected to one word line of the plurality of word lines and the other sense line of the pair of sense lines of the pair of sense lines;
When writing information into a predetermined memory cell and reference cell, both sense lines of the pair of sense lines corresponding to the memory cell and reference cell correspond to information to be written and each of the pair of sense lines. Means for causing currents in opposite directions to flow between each other, and for causing current in a predetermined direction to flow through the word lines corresponding to the memory cell and the reference cell,
A magnetic random access memory circuit comprising: 2. The magnetic random access memory circuit according to claim 1 , wherein the memory cell and the reference cell further include a magnetoresistive element and a diode connected in series to the magnetoresistive element . 2. The magnetic random access memory circuit according to claim 1 , wherein the memory cell and the reference cell further include a magnetoresistive element and a transistor connected in series to the magnetoresistive element . The magnetic random access memory circuit according to any one of claims 1 to 3 ,
A row decoder that decodes part of the address;
A column decoder for decoding the remaining portion of the address;
The plurality of pairs of sense lines are connected to the decode terminal of the row decoder,
The plurality of word lines are connected to the decode terminal of the column decoder,
There are two row decoders, two column decoders, each of the plurality of pairs of sense lines is connected between the decode terminals of the two row decoders, and each of the plurality of word lines is A magnetic random access memory circuit for connecting between the decode terminals of each of the two column decoders. 5. The magnetic random access memory circuit according to claim 1 , wherein at the time of reading, the row decoder and the column decoder each store a memory cell of a cell pair at an intersection of a selected row and a selected column. And a magnetic random access memory circuit, wherein the same current flows through the reference cell. The magnetic random access memory circuit according to claim 5 ,
Comparing means for comparing the voltage of the sense line side terminal of the memory cell of the cell pair at the intersection of the selected row and the selected column with the voltage of the sense line side terminal of the reference cell of the cell pair at the time of reading. A magnetic random access memory circuit, further comprising: 7. The magnetic random access memory circuit according to claim 6 , wherein the comparing means includes a comparator, two auxiliary lines each connected to each of two input terminals of the comparator, and the two auxiliary lines. A plurality of transistors for connecting one of the lines to a sense line to which a memory cell in a selected row is connected; a sense line to which the other of the two auxiliary lines is connected to a reference cell in a selected row; A magnetic random access memory circuit comprising: a plurality of transistors for connection. 5. The magnetic random access memory circuit according to claim 1, wherein, at the time of reading, a means for passing a current to a memory cell to be read and a reference cell paired therewith, and a reference to be paired with the memory cell to be read out A magnetic random access memory comprising means for detecting a voltage drop in a cell when a current is passed by a four-terminal method. 9. The magnetic random access memory circuit according to claim 1 , wherein the magnetoresistive element is a spin tunnel element.

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