JP3802487B2 - Semiconductor integrated circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates generally to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit including a timing control circuit that adjusts the phase of a clock signal used for sampling an input signal.
2. Background Art In digital signal transmission and reproduction, a clock signal is used to sample a received or reproduced input signal. In such a case, a clock signal having an appropriate phase is generated based on a transition point of the input signal, or a plurality of phases are obtained for one sampling point by oversampling the input signal. A multi-phase clock signal is generated, and a clock signal having an appropriate phase is selected therefrom. Generally, the former method is selected to reduce the circuit scale and power consumption. The prior art will be described below for the former method.
Conventionally, a transition point of an input signal is detected, a clock signal is generated so that a position shifted by 50% of the bit period from the transition point becomes a sampling point, and the input signal is sampled using this clock signal. It was. Here, when the input signal is a differential signal, the position where the differential signal crosses corresponds to the transition point of the input signal.
By the way, in digital signal transmission and reproduction, waveform distortion and jitter are caused by stray capacitance in the signal transmission path, and waveform distortion and jitter are caused by intersymbol interference in the recording and reproduction system. When these waveform distortion and jitter become large, it becomes difficult to set the sampling point at the optimum position in the conventional timing control circuit. This is shown in FIGS.
1 to 3, large waveform distortion and jitter are generated in the differential input signal, and the position where the positive phase input signal In1 and the negative phase input signal In2 constituting the differential input signal cross is determined at one point. Not. As shown in FIG. 1, timings t1 to t4 at which the potential difference between the positive-phase input signal In1 and the negative-phase input signal In2 is maximized as a whole give an optimum sampling point. However, in reality, the sampling point is shifted forward or backward from the optimum position due to the influence of waveform distortion and jitter. For example, in FIG. 2, the sampling point is set based on the fastest timing at which the positive phase input signal In1 and the negative phase input signal In2 cross. On the other hand, in FIG. 3, the sampling point is set based on the latest timing at which the positive phase input signal In1 and the negative phase input signal In2 cross.
As described above, in the conventional timing control circuit, when a large waveform distortion or jitter exists, the potential difference between the positive phase input signal In1 and the negative phase input signal In2 constituting the differential input signal becomes small at the sampling point. Therefore, there is a problem that an error is likely to occur mainly due to this.
DISCLOSURE OF THE INVENTION Accordingly, in view of the above points, an object of the present invention is to provide a clock signal having an appropriate phase for sampling an input signal even when a large waveform distortion or jitter occurs in the input signal. A semiconductor integrated circuit including a timing control circuit to be generated is provided.
In order to solve the above problems, a semiconductor integrated circuit according to the present invention includes at least one integrating means for integrating a relative level of an input signal in a period between two consecutive pulses of a clock signal, At least one detection means for detecting a transition of the input signal in a period between two consecutive pulses and outputting a detection signal corresponding to the direction of the transition, and at least one according to the detection signal output from the at least one detection means At least one switching means for inverting the output signals of the two integrating means, and a phase control signal generating means for generating a phase control signal used for controlling the phase of the clock signal based on the output signals of the at least one switching means It comprises.
According to the above configuration, the phase of the clock signal is controlled by integrating the relative level of the input signal according to the transition direction of the input signal in the period between two consecutive pulses of the clock signal. Even when a large waveform distortion or jitter occurs, a clock signal having an appropriate phase for sampling the input signal can be generated.
BEST MODE FOR CARRYING OUT THE INVENTION FIG. 4 is a diagram showing a configuration of a timing control circuit included in a semiconductor integrated circuit according to a first embodiment of the present invention.
In FIG. 4, a clock signal generation circuit 1 generates a clock signal used for sampling an input signal based on bit frequency components extracted from input differential input signals In1 and In2. The phase of the clock signal output from the clock signal generation circuit 1 can be controlled by the phase control signal F / S.
Generally, when N is a natural number, the clock signal generation circuit 1 is configured to generate an N-phase clock signal having phases φ1 to φN for N pieces of data. The value of N can be set to 10, for example. In addition, since the phase makes a round through the phases φ1 to φN, the phase φ (N + 1) may be considered to be equal to the phase φ1. Further, the clock signal generation circuit 1 may output a serial clock signal including all the phase information of these N-phase clock signals.
The differential input signals In1 and In2 are also supplied to the first integration circuit 2 and the data transition detection circuit 3. Here, one first integration circuit 2, one data transition detection circuit 3, and one switch circuit 4 are combined to constitute one circuit block. Corresponding to the N-phase clock signal, the number of circuit blocks is also N.
Each circuit block operates by being supplied with two predetermined clock signals from among N-phase clock signals. In each circuit block, the differential signal output from the first integration circuit 2 is supplied to the corresponding switch circuit 4. The switching operation of the switch circuit 4 is controlled by a detection signal output from the corresponding data transition detection circuit 3.
The differential signals output from the N switch circuits 4 are combined and supplied to the second integration circuit 5. The second integration circuit 5 and the level detection circuit 6 constitute phase control signal generation means. This phase control signal generating means generates a phase control signal F / S used for controlling whether the phase of the clock signal is advanced or delayed based on the outputs of the N switch circuits 4, and generates the clock signal. Supply to circuit 1. That is, when the second integration circuit 5 integrates the differential signals output from the N switch circuits 4, the level detection circuit 6 outputs the difference component of the differential signal output from the second integration circuit 5. Is detected to generate a phase control signal F / S.
Next, the configuration and operation of the circuit shown in FIG. 4 will be described in detail.
The N first integrating circuits 2 generate difference components between the differential input signals In1 and In2 in the period φ1 to φ2, φ2 to φ3,..., Or φN to φ1 between two successive clock pulses. Integrate and output as a differential signal.
As shown in FIG. 5, the first integrating circuit 2 can be configured by connecting two capacitors C <b> 1 and C <b> 2 to the differential output of the differential amplifier circuit 8. The differential amplifier circuit 8 is supplied with a clock signal having a phase φi and a clock signal having a phase φ (i + 1) from among N-phase clock signals. The differential amplifier circuit 8 is activated only during a period φi to φ (i + 1) in which the clock signal having the phase φi is at a high level and the clock signal having the phase φ (i + 1) is at a low level. The difference components between the dynamic input signals In1 and In2 are integrated, and the obtained charges are stored in the capacitors C1 and C2, respectively.
Referring to FIG. 1 again, the data transition detection circuit 3 is based on the level of the differential input signal in the period φ1 to φ2, φ2 to φ3,..., Or φN to φ1 between two consecutive clock pulses. , Detecting that the data has transitioned, and outputting a detection signal corresponding to the direction of the transition.
The switch circuit 4 connects the output of the first integration circuit 2 to the input of the second integration circuit 5 only when the detection signal output from the data transition detection circuit 3 indicates that data has transitioned. At this time, when the data transitions from “0” to “1”, the non-inverting output of the first integration circuit 2 is connected to the positive phase input of the second integration circuit 5 and the first integration circuit. The inverted output of 2 is connected to the negative phase input of the second integrating circuit 5. On the other hand, when the data transitions from “1” to “0”, the inverted output of the first integrating circuit 2 is connected to the forward input of the second integrating circuit 5 and the first integrating circuit 2 The non-inverting output is connected to the negative phase input of the second integrating circuit 5. When data does not transition, the output of the first integration circuit 2 is not connected to the second integration circuit 5.
By operating in this way, as shown in FIG. 6, the sign of the integral value is determined according to the transition direction of the input signal. That is, in the period t1 to t2 in which the data transitions from “0” to “1”, the integral value is negative when In1 <In2, and the integral value is positive when In1> In2. On the other hand, in the period t2 to t3 in which the data transitions from “1” to “0”, the integral value is positive when In1 <In2, and the integral value is negative when In1> In2.
As shown in FIG. 6, when the sampling point is set at the optimum position, the area of the positive region is equal to the area of the negative region, and the positive integrated value and the negative integrated value cancel each other. As a result, the differential outputs of the first integrating circuit 2 (FIG. 1) are at the same level.
On the other hand, as shown in FIG. 7, when the sampling point comes before the optimum position, the area of the negative region becomes larger than the area of the positive region, and the first integration circuit 2 ( In the differential output of FIG. 1), the inverted output is larger than the non-inverted output.
On the other hand, as shown in FIG. 8, when the sampling point comes after the optimum position, the area of the positive region becomes larger than the area of the negative region, and the first integration circuit 2 (FIG. 1). In the differential output, the non-inverted output is larger than the inverted output.
The second integrating circuit 5 shown in FIG. 1 is provided for integrating the differential outputs of the N first integrating circuits 2 provided for the sampling phases φ1 to φN over the entire sampling period. . As shown in FIG. 9, the second integration circuit 5 can be constituted by two capacitors C3 and C4. The integration period of the second integration circuit is preferably longer than the integration period of the first integration circuit. Therefore, the capacitances of the capacitors C3 and C4 are made larger than the capacitances of the capacitors C1 and C2 (FIG. 5).
Referring to FIG. 1 again, the level detection circuit 6 detects the difference component between the differential signals Out1 and Out2 output from the second integration circuit 5, and outputs the phase control signal F / S based on the comparison result. . That is, the level detection circuit 6 sets the phase control signal F / S to the high level when Out1> Out2, and sets the phase control signal F / S to the low level when Out1 <Out2. Therefore, the phase control signal F / S becomes a low level when the sampling point comes before the optimum position, and the phase control signal F / S becomes high when the sampling point comes after the optimum position. Become a level.
The phase control signal F / S output from the level detection circuit 6 is supplied to the clock signal generation circuit 1. The clock signal generation circuit 1 delays the phase of the clock signal when the phase control signal F / S is at a low level, and advances the phase of the clock signal when the phase control signal F / S is at a high level. In this way, a kind of PLL (Phase Locked Loop) is configured, and the clock signal is adjusted to the optimum timing for sampling the input signal. The clock signal generation circuit 1 may be configured to include a voltage controlled oscillator (VCO), and may be controlled using an analog output signal (differential signal or single signal) of the second integration circuit.
Next, a second embodiment of the present invention will be described. FIG. 10 is a diagram showing a configuration of a timing control circuit included in a semiconductor integrated circuit according to the second embodiment of the present invention. In this embodiment, a variable delay circuit that delays an input N-phase clock signal in accordance with a phase control signal is used instead of the clock signal generation circuit in the first embodiment. When the same N-phase clock signal is also used in other circuits, it is more suitable to provide a variable delay circuit having a relatively small circuit scale than providing a separate clock signal generation circuit.
In the timing control circuit 10 shown in FIG. 10, the variable delay circuit 7 delays the supplied N-phase clock signals Ck1 to CkN according to the phase control signal F / S. Delayed N-phase clock signals φ1 to φN are supplied to a plurality of first integration circuits 2 and a plurality of data transition detection circuits 3. As in the first embodiment, one first integration circuit 2, one data transition detection circuit 3, and one switch circuit 4 are combined to form one circuit block. . Outputs of the plurality of switch circuits 4 included in the plurality of circuit blocks are combined and supplied to the second integration circuit 5. The level detection circuit 6 creates a phase control signal F / S for controlling whether the phase of the clock signal is advanced or delayed based on the output of the second integration circuit 5.
The phase control signal F / S output from the level detection circuit 6 is supplied to the variable delay circuit 7. The variable delay circuit 7 delays the phase of the clock signal when the phase control signal F / S is at a low level, and advances the phase of the clock signal when the phase control signal F / S is at a high level. In this way, the N-phase clock signal is adjusted to the optimum timing for sampling the input signal.
Next, a third embodiment of the present invention will be described. FIG. 11 is a diagram showing a configuration of a timing control circuit included in a semiconductor integrated circuit according to the third embodiment of the present invention. In the present embodiment, three systems of timing control circuits according to the second embodiment are used corresponding to three types of input signals.
In FIG. 11, it is assumed that three types of input signals are serial image data for each RGB. That is, R channel differential input signals InR1 and InR2 are input to the timing control circuit 10R, G channel differential input signals InG1 and InG2 are input to the timing control circuit 10G, and B channel differential input signals InB1 and InB2 are input. Is input to the timing control circuit 10B. N-phase clock signals Ck1 to CkN are supplied to these timing control circuits 10R to 10B. The variable delay circuit included in the timing control circuits 10R to 10B delays the supplied N-phase clock signals Ck1 to CkN according to the respective phase control signals.
Thus, the timing control circuit 10R outputs clock signals φR1 to φRN for sampling the R-channel differential input signals InR1 and InR2, and the timing control circuit 10G outputs the G-channel differential input signals InG1, Clock signals φG1 to φGN for sampling InG2 are output, and clock signals φB1 to φBN for sampling B channel differential input signals InB1 and InB2 are output from the timing control circuit 10B.
As described above, in the present embodiment, the N-phase clock signals Ck1 to CkN are commonly used among the three channels, so that the circuit scale can be reduced as compared with the case where the clock signal generation circuit is provided for each channel. Can do.
The present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be freely modified and changed within the scope described in the claims. is there.
According to the present invention, it is possible to generate a clock signal having an appropriate phase for sampling the input signal even if a large waveform distortion or jitter occurs in the input signal, thereby improving the phase margin of the clock signal. It is possible to reduce the error rate.
INDUSTRIAL APPLICABILITY The semiconductor integrated circuit according to the present invention can be used in an imaging device, a computer, or the like in which the phase of a clock signal used for sampling an input signal is adjusted.
[Brief description of the drawings]
The advantages and features of the present invention will become apparent when considered in conjunction with the following detailed description and drawings. In these drawings, the same reference numbers refer to the same components.
FIG. 1 is a diagram showing an optimum sampling point when a large waveform distortion or jitter occurs in a differential input signal.
FIG. 2 is a diagram illustrating a state in which the sampling point is shifted forward from the optimum position when large waveform distortion or jitter occurs in the differential input signal.
FIG. 3 is a diagram illustrating a state in which the sampling point is later shifted from the optimum position when large waveform distortion or jitter occurs in the differential input signal.
FIG. 4 is a diagram showing a configuration of a timing control circuit included in the semiconductor integrated circuit according to the first embodiment of the present invention.
FIG. 5 is a diagram showing a specific circuit example of the first integration circuit shown in FIG.
FIG. 6 is a diagram showing the relationship between the waveform of the input signal and the integral value when the sampling point is set at the optimum position.
FIG. 7 is a diagram showing the relationship between the waveform of the input signal and the integral value when the sampling point is before the optimum position.
FIG. 8 is a diagram showing the relationship between the waveform of the input signal and the integrated value when the sampling point is later than the optimum position.
FIG. 9 is a diagram showing a specific circuit example of the second integration circuit shown in FIG.
FIG. 10 is a diagram showing a configuration of a timing control circuit included in a semiconductor integrated circuit according to the second embodiment of the present invention.
FIG. 11 is a circuit diagram showing a configuration of a timing control circuit included in a semiconductor integrated circuit according to the third embodiment of the present invention.

Claims (15)

A semiconductor integrated circuit having a function of controlling the phase of a clock signal used for sampling an input signal,
At least one integrating means for integrating the relative level of the input signal in the period between two consecutive pulses of the clock signal;
At least one detection means for detecting a transition of the input signal in a period between two consecutive pulses of the clock signal and outputting a detection signal corresponding to the direction of the transition;
At least one switch means for inverting the output signal of the at least one integrating means according to a detection signal output from the at least one detecting means;
Phase control signal generating means for generating a phase control signal used for controlling the phase of the clock signal based on the output signal of the at least one switch means;
A semiconductor integrated circuit comprising: 2. The semiconductor integrated circuit according to claim 1, further comprising clock signal generating means for generating a clock signal with a phase according to the phase control signal generated by said phase control signal generating means. Clock signal generating means for generating an M-phase clock signal at a phase according to the phase control signal generated by the phase control signal generating means, where M is an integer of 2 or more;
M integration means for integrating the relative level of the input signal in a period between two consecutive pulses of the M phase clock signal;
M detection means for detecting a transition of the input signal and outputting a detection signal corresponding to the direction of the transition in a period between two consecutive pulses of the M-phase clock signal;
M switch means for inverting the output signals of the M integration means according to detection signals output from the M detection means,
Phase control signal generating means for generating a phase control signal used for controlling the phase of the clock signal based on the output signals of the M switch means;
The semiconductor integrated circuit according to claim 2, further comprising: 2. The semiconductor integrated circuit according to claim 1, further comprising variable delay means for delaying the phase of the input clock signal in accordance with the phase control signal generated by said phase control signal generating means. Variable delay means for delaying the phase of the input M-phase clock signal according to the phase control signal generated by the phase control signal generation means, where M is an integer of 2 or more;
M integration means for integrating the relative level of the input signal in a period between two consecutive pulses of the M phase clock signal;
M detection means for detecting a transition of the input signal and outputting a detection signal corresponding to the direction of the transition in a period between two consecutive pulses of the M-phase clock signal;
M switch means for inverting the output signals of the M integration means according to detection signals output from the M detection means,
Phase control signal generating means for generating a phase control signal used for controlling the phase of the clock signal based on the output signals of the M switch means;
5. The semiconductor integrated circuit according to claim 4, further comprising: The semiconductor integrated circuit according to claim 1, wherein the at least one integrating means includes an amplifier circuit and a capacitor, and converts a relative level of an input signal into a charge amount charged in the capacitor. The phase control signal generating means is
Second integrating means for integrating the output signal of the at least one switch means;
Level detecting means for generating a phase control signal used for controlling the phase of the clock signal by detecting the level of the output signal of the second integrating means;
The semiconductor integrated circuit according to claim 1, comprising: The semiconductor integrated circuit according to claim 7, wherein the second integration unit includes a capacitor. 9. The semiconductor integrated circuit according to claim 8, wherein the second integration unit includes a capacitor having a larger capacity than a capacitor of the at least one integration unit. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit has a function of controlling a phase of a clock signal used for sampling a differential input signal including the first input signal and the second input signal.
At least one integrating means for integrating a difference component between the first input signal and the second input signal in a period between two consecutive pulses of the clock signal and outputting a differential signal;
At least one detection means for detecting a transition of a difference component between the first input signal and the second input signal in a period between two consecutive pulses of the clock signal and outputting a detection signal corresponding to the direction of the transition When,
At least one switch means for switching a differential signal output from the at least one integration means according to a detection signal output from the at least one detection means;
Phase control signal generating means for generating a phase control signal used for controlling the phase of the clock signal based on the differential signal output from the at least one switch means;
A semiconductor integrated circuit comprising: The at least one integrating means includes a differential amplifier circuit and two capacitors, and converts a difference component between the first input signal and the second input signal into a charge amount charged in the two capacitors; The semiconductor integrated circuit according to claim 10. The phase control signal generating means is
Second integrating means for integrating the differential signal output from the at least one switch means;
Level detecting means for generating a phase control signal used for controlling the phase of the clock signal by detecting a difference component of the differential signal output from the second integrating means;
The semiconductor integrated circuit according to claim 10, comprising: The semiconductor integrated circuit according to claim 12, wherein the second integration means includes two capacitors. The semiconductor integrated circuit according to claim 13, wherein the second integration unit includes two capacitors each having a larger capacitance than each of the two capacitors of the at least one integration unit. A semiconductor integrated circuit having a function of controlling the phases of L types of clock signals used to sample L input signals, where L is an integer of 2 or more,
L variable delay means for delaying the phase of one type of input clock signal according to L phase control signals,
L timing control circuits, each of which has at least one integrating means for integrating the relative level of the input signal in the period between two consecutive pulses of the clock signal, and two consecutive clock signals At least one detection means for detecting a transition of the input signal in a period between pulses and outputting a detection signal corresponding to the direction of the transition; and the at least one integration according to the detection signal output from the at least one detection means At least one switching means for inverting the output signal of the means, and phase control used to control the phase of the clock signal in each of the L variable delay means based on the output signal of the at least one switching means The L timing control circuits including phase control signal generating means for generating a signal;
A semiconductor integrated circuit comprising:

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