JP3792329B2 - Internal clock generation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an internal clock generation circuit and a variable delay circuit used therefor, and more particularly to an internal clock generation circuit suitable for an integrated circuit operating at a high frequency and capable of arbitrarily controlling a phase delay, and a variable delay circuit used therefor. .
[0002]
[Prior art]
In recent years, semiconductor integrated circuits (LSIs) such as microprocessors and semiconductor memories are required to operate at a high frequency, and accordingly, a system clock for synchronizing the LSI chips or a circuit in each LSI chip. The frequency of the internal clock for synchronizing the signals is increasing.
[0003]
In order to synchronize an external clock such as a system clock supplied from the outside of the LSI chip with the LSI internal circuit, a phase locked loop (PLL) is used. The PLL is a circuit that controls the frequency of the oscillator according to the phase difference between the two frequencies. The mechanism of the PLL operation will be briefly described with reference to the block diagram of FIG.
[0004]
The PLL is generated by a phase comparator 31 that compares two phases, a loop filter 32 that generates a voltage control signal by filtering the phase difference comparison voltage signal output from the phase comparator 31, and the loop filter 32. And a voltage controlled oscillator 33 (VCO: Voltage Controlled Oscillator) that controls the frequency based on the voltage control signal.
[0005]
The clkin signal input from the external clock input terminal 35 is input again to the phase comparator 31 as the PLL1 signal via the phase comparator 31, the loop filter 32, and the VCO 33. Here, the phases of the clkin signal and the PLL1 signal are compared. If the phase of the PLL1 signal is delayed with respect to the clkin signal, the voltage control signal value generated by the loop filter 32 increases and the VCO 33 Increase the frequency output from.
[0006]
Conversely, when the phase of the PLL1 signal advances with respect to the clkin signal, the frequency output from the VCO 33 is similarly lowered so that the phase of the clkin signal and the PLL1 signal is not shifted.
Further, synchronization with the rising edge of the next clock that is sent for one cycle with respect to the clkin signal using a delay synchronization circuit (DLL: Delay Locked Loop) is also performed. The DLL performs an operation similar to that of the PLL, but a delay line is provided in order to create a function of delaying just one cycle. That is, it is for creating a delay for one cycle, and the usable frequency range is limited.
[0007]
[Problems to be solved by the invention]
As described above, the LSI chip is devised so that accurate signal transmission is performed by correcting the phase difference between the external clock and the internal clock using a PLL or DLL. However, in recent years, the operating frequency of LSIs has been greatly increased, and thus the signal amplitude has been reduced. For this reason, when an external signal is used in the internal circuit, it is necessary to perform amplification or the like in the input circuit, and a delay occurs when a signal passes through the input circuit or even the wiring from the input terminal to the input circuit.
[0008]
Furthermore, the operation speed of the LSI chip is affected by the environment surrounding the chip. For example, the oscillation frequency of the oscillator changes depending on the temperature and voltage value, and a delay occurs in the operation of the input circuit itself.
As a countermeasure for such an irregular delay, a variable delay circuit capable of changing the delay amount by an external instruction has been proposed. In this method, a delay amount is changed by connecting a plurality of transistors and selectively driving transistors as much as the current corresponding to the delay amount to control the delay circuit. If this method is used, it is possible to cope with a certain range of delay amount, but the current value can be changed only stepwise depending on the characteristics of the transistor to be selected, and it is difficult to finely adjust the delay amount.
[0009]
Further, adjusting only with an external signal is not sufficient for achieving accurate synchronization because an internal delay is not taken into consideration.
The present invention has been made based on the above circumstances, and in an LSI chip that operates at a high frequency, an external clock and an internal clock are accurately synchronized, and an internal clock generation circuit that does not cause a synchronization shift due to environmental changes and the same An object of the present invention is to provide a variable delay circuit suitable for use.
[0010]
Another object of the present invention is to provide a variable delay circuit in which the delay amount of the variable delay circuit can be set by a binary code.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, an internal clock generation circuit according to the present invention includes a differential input circuit to which a clock signal is input, a first variable delay circuit that delays the clock signal by one period, and the first An integration-type second variable delay circuit that delays the output of the variable delay circuit by zero or one period according to the control signal; and a phase comparison means that compares the clock signal with the output of the second variable delay circuit; A variable current source for supplying an integration current to the second variable delay circuit, and the second variable delay circuit based on the output of the phase comparison means Send control signal to The variable current source so that the phase of the clock signal and the output of the second variable delay circuit always coincide with each other when the second variable delay circuit is alternately switched between zero delay and one cycle delay by controlling. The control means for controlling the output current of the first variable delay circuit and the output of the first variable delay circuit are input, the integrated current from the variable current source is integrated based on the output clock of the first variable delay circuit, and the internal clock Occur, It has the same circuit configuration as the second variable delay circuit And a third variable delay circuit.
[0012]
The second variable delay circuit alternately switches between a zero delay with a delay amount of zero and a one-cycle delay corresponding to one cycle of the input clock. As an input to the phase comparison means, a clock that has been delayed by one cycle by the first variable delay circuit and a clock that has been delayed by two cycles by the first variable delay circuit and the second variable delay circuit are alternately input. Is done. When the delay amount of the second variable delay circuit is exactly zero delay or one period delay, the input phase shift of the phase comparison means is only the phase shift due to the first variable delay circuit. For this reason, first, the delay amount of the second variable delay circuit is set to zero delay, the delay amount of the first variable delay circuit is controlled to match the phase, and then the delay of the second variable delay circuit is set. The phase is set by setting the amount to one cycle delay and controlling the output current of the variable current source. In this way, the control means controls so that the phase of the input clock and the clock subjected to the one-cycle delay by the first variable delay circuit always match. Therefore, even when the delay amount of the second variable delay circuit fluctuates due to a temperature change or the like, the output current of the variable current source is controlled by this feedback loop so that the phase fluctuation is suppressed.
[0013]
On the other hand, the clock that has been delayed by one cycle by the first variable delay circuit is also supplied to the third variable delay circuit. If the third variable delay circuit has the same configuration as that of the second variable delay circuit, the same control signal as that of the second variable delay circuit can be input to the third variable delay circuit without causing fluctuations due to temperature changes. Delay can be obtained.
In order to achieve the above object, a variable delay circuit according to the present invention is a variable delay circuit that integrates a current supplied from a variable current source based on a clock signal input from the outside and delays the clock signal. Complementary short circuit between the source and drain of the first slave transistor and the first slave transistor and the second slave transistor whose gate is connected to the master transistor and whose source and drain are connected in series A slave transistor pair group in which a plurality of slave transistor pairs including a first selection transistor and a second selection transistor that complementarily short-circuits the source and drain of the second slave transistor are connected in series; The first selection transistor and the second selection transistor By switching the output current by changing the operation pattern of each pair, and is characterized in controlling the amount of delay.
[0014]
By setting each slave transistor pair in the slave transistor pair group to correspond to each bit of the binary code of the delay amount setting value, the delay amount can be easily set.
Further, the variable delay circuit according to the present invention for achieving the above object integrates the current supplied from the integration current control unit and the integration current control unit according to the input clock signal, and the clock signal In the variable delay circuit including an integration circuit unit that delays the integration circuit unit, the integration circuit unit includes a drive transistor that is driven by a current supplied from the integration current control unit, and a capacitor unit that accumulates electric charge by the drive transistor; Connected to the gate terminal of the drive transistor, has a capacity approximately equal to the gate-source capacity or the gate-drain capacity of the drive transistor, and according to a change in potential at the connection point of the drive transistor and the capacity means First gate potential correction means for changing the potential of the gate terminal of the driving transistor in the reverse direction; It is an feature.
[0015]
As the first gate potential correcting means, the integration circuit unit is different from the first integration unit having the first transistor of the first conductivity type as the drive transistor, and the first transistor of the first conductivity type. A second transistor having a second conductivity type and having a second integrator that complementarily operates with the first integrator, the gate of the first transistor and the source of the second transistor or A capacitor provided between the drains and having a capacity corresponding to the gate-source capacity of the first transistor can be used.
[0016]
Therefore, even minute delays caused by the temperature of the LSI chip and internal circuits can be canceled out, and accurate synchronization can be achieved particularly in an integrated circuit operating at high speed.
In the above description, the delay amount of the second variable delay circuit is described as being delayed by zero or one cycle. However, since the actual circuit cannot realize a complete zero delay, the second variable delay circuit has zero delay and 1 delay. Switching the cycle delay alternately means that the delay amount is actually changed between “minimum delay amount” and “minimum delay amount + 1 cycle”. The fact that the first variable delay circuit delays by one cycle actually means that the first variable delay circuit delays by “minimum delay amount + 1 cycle”.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing an example of an internal clock generation circuit according to an embodiment of the present invention. FIGS. 2 to 4 are variable current sources and second or third variable delay circuits used in the internal clock generation circuit. It is a specific circuit diagram. 2 to 4, (1) in FIG. 2 and (1) in FIG. 3, (2) in FIG. 3, (2) in FIG. 4, (3) in FIG. 3, and (3) in FIG. 3 ▼ are connected to each other.
[0018]
The internal clock generation circuit shown in FIG. 1 includes an input terminal 20 to which an external clock signal is input, an input terminal 21 to which a reference voltage is input, and a differential input circuit 1 that compares an external clock signal with a reference voltage and regenerates the clock. A first variable delay circuit 4 and a second variable delay circuit 5 connected in series for delaying an output of the differential input circuit 1, an inverter 3, a phase of the external clock signal, and a second variable delay circuit From the phase comparison circuit 2 that compares the phases of the outputs of 5, the control circuit 8 that generates a control signal for controlling the delay amount of the variable delay circuits 4 and 5 based on the output signal from the phase comparison circuit 2, The variable current source 6 that changes the output current according to the control signal and the third variable delay circuit 7 that generates the internal clock are provided. The variable delay circuits 5 and 7 are connected to the variable current source 6 and change the delay amount according to the output current of the variable current source 6. Details of the variable current source 6 and the variable delay circuits 5 and 7 will be described later with reference to FIGS.
[0019]
In the present embodiment, the clock generated by the third variable delay circuit 7 is taken out as the internal operation clocks 0 and 1 via the inverters 9 and 10. The internal operation clocks 0 and 1 are used, for example, as clocks for operating the memory itself.
In FIG. 1, an external clock input from an external clock input terminal 20 is amplified to obtain a voltage that can be handled by a digital circuit in the differential input circuit 1. In recent LSI chips, the amplitude of a signal is suppressed to be small in order to transmit a signal at a high frequency, and the signal is amplified to a sufficient amplitude for internal use by using the differential input circuit 1 or the like. When amplification is performed by the differential input circuit 1, a delay occurs in the clock. In the conventional phase comparison circuit shown in FIG. 6, the phase comparison is performed while being affected by the delay generated in the differential input circuit.
[0020]
The signal amplified by the differential input circuit 1 and output with some delay is then given an appropriate delay amount by the delay circuit. In this embodiment, variable delay circuits 4, 5, and 7 are provided as delay circuits. The second variable delay circuit 5 has a zero delay that does not delay the phase of the signal output from the first variable delay circuit 4 according to the control signal C1, and a one-cycle delay that delays 100 percent, that is, one cycle. Can be switched.
[0021]
The first variable delay circuit 4 delays so that the clock input to the phase comparison circuit 2 has a delay of exactly one cycle with respect to the external input clock when the second variable delay circuit 5 is zero delay. This is a delay circuit for adjusting the amount. Therefore, when the second variable delay circuit 5 has a one-cycle delay, the clock input to the phase comparison circuit 2 has a delay of exactly two cycles with respect to the external input clock.
[0022]
Clock synchronization is performed according to the following procedure. First, the first variable delay circuit 5 is set to zero delay by the control signal C1. Then, the first variable delay circuit 4 is controlled to adjust the delay amount so that the rising or falling edge of the clock output from the second variable delay circuit 5 coincides with the external input clock. Specifically, the phase is gradually advanced or delayed to control the phase difference to decrease, and this is repeated until both input phases coincide.
[0023]
Next, Step 2: The second variable delay circuit 5 is adjusted by the control signal C1 to set the phase shift to 100%. Then, by controlling the output current of the variable current source 6, the phase of the clock output from the second variable delay circuit 5 at that time is matched so that the phase is exactly two cycles shifted from the external input clock. The delay amount of the second delay circuit 5 is adjusted. In this way, the rising or falling edge of the clock output from the second variable delay circuit 5 in a state shifted by two cycles is matched with the external input clock. By repeating Step 1 and Step 2 alternately, the external input clock and the internal clock are synchronized.
[0024]
The third variable delay circuit 7 has the same configuration as that of the second variable delay circuit 5 and is configured to integrate the current from the same variable current source 6. As shown in FIG. The amount of delay is set by the same control signal as that of the second variable delay circuit 5. Therefore, when the phase shift of the second variable delay circuit 5 is corrected by a feedback loop including the input terminals 20 and 21, the differential input circuit 1, the variable delay circuits 4 and 5, the inverter 3, and the phase comparison circuit 2 in FIG. The phase shift of the third variable delay circuit 7 is automatically adjusted.
[0025]
Next, details of the variable current source 6 and the variable delay circuits 5 and 7 will be described with reference to FIGS.
The variable current source 6 adjusts the delay amount of the variable delay circuits 5 and 7 and is also used as a current source for the internal circuit at the subsequent stage. In FIG. 2, a block A is a span control unit and corresponds to the variable current source 6 of FIG. The variable delay circuits 5 and 7 shown in FIG. 1 are configured by the blocks B, C, and D in FIGS. Block B is a part for controlling the integrated current (integrated current control circuit), and the delay time is changed by changing the integrated current. Blocks C and D are integration circuits composed of integrators. The block E is a circuit that controls a clock output from the first variable delay circuit 4 and input to the block C and the block D, and uses a known technique including an RS flip-flop.
[0026]
The span controller A controls the span of the n-cycle clock itself (maximum delay amount and minimum delay amount width). The span control unit A includes PMOS transistors P1 to P6 and NMOS transistors N1 to N16. Here, the NMOS transistors N12 to N16 are switching transistors. The PMOS transistors P2, P3, P4, P5, and P6 each have a gate connected to the PMOS transistor P1 in common, and form a first current mirror circuit with the PMOS transistor P1. These first current mirror circuits allow the same predetermined currents iA1 to iA5 to flow in the previous current path with respect to the current iA flowing in the current path from the PMOS transistor P1 to the NMOS transistor N1.
[0027]
NMOS transistors N2 and N3, NMOS transistors N4 and N5, NMOS transistors N6 and N7, NMOS transistors N8 and N9, and NMOS transistors N10 and N11 each constitute a second current mirror circuit. The output current from each first current mirror circuit is superposed through these second current mirror circuits, and then output to the output terminal 51 as an output current.
[0028]
The output current of each first current mirror circuit changes according to the gate voltages of the NMOS transistors N12, N13, N14 and N15 connected to each second current mirror circuit. An ON / OFF signal is supplied from the control circuit 8 to the gates of the NMOS transistors N12, N13, N14 and N15.
At this time, since the gate voltage of the NMOS transistor N16 is fixed at Vdd, the second current mirror circuit of the NMOS transistors N10 and N11 receives 0 (zero) from the control circuit 8 to all terminals R0 to R3. The current value at that time is determined. This current value corresponds to the minimum delay amount that can be controlled by the span controller A. On the other hand, the gates of the NMOS transistors N12, N13, N14, and N15 are connected to the control circuit 8 of FIG. 1 through terminals R0, R1, R2, and R3, respectively. The maximum delay amount that can be controlled by the span controller A corresponds to the output current when all of the NMOS transistors N12, N13, N14, and N15 are turned on by controlling the voltages of the terminals R0 to R3.
[0029]
As described above, the span control unit A can switch the output current iS in 4 bits, that is, in 16 stages, in accordance with the on / off signals input to the terminals R0 to R3. The output current iS can be changed linearly by switching signals input to the terminals R0 to R3.
Next, the current iS output from the span controller A is input to the integral current control circuit B of the variable delay circuit. Since this variable delay circuit is composed of an integrator, the delay time is proportional to the reciprocal of the integrated current value. That is, assuming that the electrostatic capacitance formed by the downstream NMOS transistor N55 or N56 is C and the logical threshold value of the downstream inverter iv1 or iv2 is V, the charge amount Q is
Q = CV
The current I for charging the capacitance C is
I = Q / t
It is. Therefore, in order to make the set value of the delay amount proportional to the delay time, the current needs to be given by the reciprocal of the set value, which is realized by the NMOS transistor N20 and each of the NMOS transistors N21 to N32 and N33. Is a fifth current mirror circuit.
[0030]
The integration current control unit B includes three current mirror circuits, that is, a third current mirror circuit, a fourth current mirror circuit, and a fifth current mirror circuit. The third current mirror circuit is composed of a PMOS transistor P20 and a PMOS transistor P21, and adjusts the current supplied to the fifth current mirror circuit. As a result, a current iB corresponding to the output current iS from the span controller A flows from the PMOS transistor P21 to the NMOS transistor N20. The fourth current mirror circuit is composed of a PMOS transistor P22 and a PMOS transistor P23. As a result, a current iD corresponding to the current iC between the NMOS transistor N33 and the PMOS transistor P22 flows between the PMOS transistor P23 and the NMOS transistor N52.
[0031]
The fifth current mirror circuit is composed of an NMOS transistor N20 (master transistor) and a plurality of NMOS transistors N21 to N32 and N33 paired therewith. The NMOS transistors N21 to N32 and N33 have a gate connected to the NMOS transistor N20, and a source / drain connected in series. The NMOS transistors N21 to N32 are connected to NMOS transistors N40 to N51 (selection transistors) as switching transistors, respectively. The NMOS transistors N40 to N51 are short-circuited complementarily between the sources and drains of the NMOS transistors N21 to N32. The switching transistor is selectively operated to determine the output current iC.
[0032]
The NMOS transistors N22, N24, N26, N28, N30, and N32 (second slave transistors) to which the even-numbered symbols are attached are composed of transistors having different gate lengths L, respectively. In the present embodiment, the gate length L is set so that N22 has the smallest value, and sequentially increases in the order of N24, N26,. The NMOS transistors N21, N23, N25, N27, N29, and N31 (first slave transistors) to which odd-numbered symbols are attached all have the same minimum gate length L. ₀ This is a reference transistor having The NMOS transistor N33 defines the basic operation of the fifth current mirror circuit, and has a predetermined gate length L ₁ have.
[0033]
The gate widths W of the NMOS transistors N21 to N32 and N33 are all the same. Further, the gate length L of the NMOS transistors N22, N24, N26, N28, N30, and N32 to which even-numbered symbols are attached may be set so as to sequentially become smaller in the order of N22, N24,. Good.
The NMOS transistors N40 to N51 perform a switching operation, and switch between the gate length L adjusting transistors N22, N24, N26, N28, N30, N32 and the reference transistors N21, N23, N25, N27, N29, N31. I do. Each of C0 to C5 is a terminal for inputting a signal for controlling the delay amount, and one of C0 and C0b is inputted with a signal that becomes Vss when one is Vdd. For example, when an off signal is input to C0 (at this time, an on signal is input to C0b), the current flows through the switching transistor N41 and the reference transistor 21. On the other hand, when an ON signal is input to C0 (at this time, an OFF signal is input to C0b), the current flows through the adjustment transistor 22 and the switching transistor N40. At this time, only the adjustment or reference transistor through which the current has passed substantially constitutes the fifth current mirror circuit. C1-C5 and C1b-C5b operate similarly. Therefore, the NMOS transistors N21 and N22, N23 and N24, N25 and N26, N27 and N28, N29 and N30, and N31 and N32 are paired, and one of the pairs is always selected to operate. become.
[0034]
The output current of the fifth current mirror circuit is a total gate length of 6 × L when an on voltage is supplied to all the terminals C0 to C5 and an off voltage is supplied to all the terminals C0b to C5b. ₀ + L ₁ Is the minimum current, the current for the total gate length when the off voltage is supplied to all the terminals C0 to C5 and the on voltage is supplied to all the terminals C0b to C5b is the maximum current. The current value between the minimum current and the maximum current can be appropriately adjusted by selecting the on / off pattern of the NMOS transistors N40 to N51. Even if the switching transistors N40 to N51 are turned on, they do not contribute to the gate length of the fifth current mirror circuit.
[0035]
In this integration current control circuit B, the gates of all the mirror NMOS transistors N21 to N32 and N33 are mirror potentials, so the output current iC is proportional to the inverse of the gate length L. That is, by inputting a predetermined signal to the terminals C0 to C5 and C0b to C5b and switching the gate length L, the output current iC changes in proportion to 1 / L. Therefore, the gate length L is set to the set value. Then, this set value becomes proportional to the delay time. This set value gate length L may be controlled by 2 to the power of n. For example, in this embodiment, the gate length L can be set by 2 to the sixth power, that is, 6 bits. When C0 to C5 are all zero (000000), the minimum gate length is obtained. When C0 is “1” and C1 to C5 are zero (100,000), the gate length of the NMOS transistor N22 is larger than the minimum gate length. The gate length is increased by the difference from the gate length of the reference transistor N21. As a result, the current iC decreases, the integration time in the next integration circuits C and D increases, and the delay amount increases. In the case of (010000), the gate length becomes longer than the minimum gate length by the difference between the gate length of the NMOS transistor N24 and the reference transistor N23. In the case of (110000), the gate length is longer than the minimum gate length. However, the gate length is increased by the difference between the total gate length of the NMOS transistors N22 and N24 and the total gate length of the reference transistors N21 and N23. Thus, the ability to set the delay amount in the second power of 2, that is, binary, is particularly advantageous in performing digital control.
[0036]
In this current control circuit B, the total gate length can be controlled in units of the difference between the gate lengths of two or more transistors, and therefore can be set finely. Actually, a very fine delay amount can be set and control of about 30 ps is possible. Further, the current control circuit B has an advantage that the degree of freedom in circuit arrangement is improved as compared with the current control circuit by gate switching which has been conventionally proposed.
[0037]
Next, a current iD inverted with respect to the current iC obtained by the current control circuit B is generated by the PMOS transistors P22 and P23.
Block C is an integrating circuit for charging, and block D is an integrating circuit for discharging. The block C and the block D are formed symmetrically. In the block C, the PMOS transistor P60 constitutes the sixth current mirror circuit with the PMOS transistor P22 of the integration current control circuit B. In the block D, the NMOS transistor N60 is replaced with the NMOS transistor N52 of the integration current control circuit B. And the seventh current mirror circuit. These sixth and seventh current mirror circuits are configured such that an equal current flows through the blocks C and D so that the operations of the two blocks C and D are symmetric.
[0038]
The block C includes a PMOS transistor P60 (driving transistor) that is driven by a current supplied from the integration current control circuit B, an NMOS transistor N55 as a capacitor, a PMOS transistor P63 (switching transistor) that determines integration start, and a resetting transistor. NMOS transistor N64, PMOS transistor P61 as first gate potential correction means, and PMOS transistor P62 as second gate potential correction means. Similarly, the block D includes an NMOS transistor N60 (driving transistor) that is driven by the current supplied from the integration current control circuit B, an NMOS transistor N56 as a capacitive means, and an NMOS transistor N63 (switching transistor) that determines the start of integration. , A resetting PMOS transistor P64, an NMOS transistor N61 as first gate potential correcting means, and an NMOS transistor N62 as second gate potential correcting means.
[0039]
In block C, the PMOS transistor P60 charges the gate of the NMOS transistor N55 from Vss to Vdd. On the other hand, in the block D, the NMOS transistor N60 discharges the gate of the NMOS transistor N56 from Vdd to Vss. The two charge / discharge waveforms are symmetrical with respect to 0.5 Vdd because they are controlled by the sixth and seventh current mirror circuits with the same current. That is, the charge amount and the discharge amount are equal.
[0040]
The charge / discharge currents iE and iF do not become completely constant due to the influence of the voltages of node-P and node-N even when the gate voltages of the PMOS transistor P60 and the NMOS transistor N60 are completely constant. However, this effect can be relatively suppressed if it is up to about the logical threshold value (1/2 Vdd) of the inverter that monitors the completion of charging / discharging.
[0041]
What has the greatest influence is the effect of the capacitance (parasitic capacitance) generated between the gate and source of the PMOS transistor P60 and NMOS transistor N60 or between the gate and drain, and the gates of the PMOS transistor P60 and NMOS transistor N60. The voltage fluctuates, whereby the charge / discharge currents iE and iF change, and the charge / discharge waveform becomes non-linear. This occurs because the gate voltage of the PMOS transistor P60 increases due to the node-P, and conversely, the gate voltage of the NMOS transistor N60 decreases due to the node-N, and eventually the current decreases on both sides.
[0042]
In such a case, the charging capacitor is usually placed in the feedback loop of the inverting amplifier to prevent the influence by using the charging terminal as a virtual ground point. It becomes complicated. In addition, there is a problem that it cannot cope with high-speed operation.
However, by generating and balancing symmetrical charge / discharge waveforms as in this embodiment, it is possible to operate at high speed with a simple circuit. In this integrating circuit C, the PMOS transistor P61 is used as a first gate potential correcting means for changing the gate voltage of the PMOS transistor P60 in the reverse direction in accordance with the change in the potential at the connection point between the PMOS transistor P60 and the NMOS transistor N55. ing. That is, the PMOS transistor P61 functions as a balancer having a capacity equal to that of the PMOS transistor P60, and creates a voltage waveform in the opposite direction through the capacitor to achieve a balance. The PMOS transistor P61 is short-circuited between the source and the drain and operates as a capacitive element. The gate of the PMOS transistor P61 is connected to the gate of the PMOS transistor P60, and the source / drain of the PMOS transistor P61 is connected to the source or drain of the NMOS transistor N63 of the integrating circuit D. The gate length of the PMOS transistor P61 is set so that the gate-source (or drain) capacitance of the PMOS transistor P61 is substantially equal to the gate-source (or drain) capacitance of the PMOS transistor P60. Similarly, in the integration circuit D, the NMOS transistor N61 is used as a first gate potential correcting means for changing the gate voltage of the NMOS transistor N60 in the reverse direction, and the NMOS transistor N61 is used as a balancer of the NMOS transistor N60. work.
[0043]
The parasitic capacitance problem also occurs for the PMOS transistor P63 and the NMOS transistor N63 as switching transistors. For this reason, in the present embodiment, an NMOS transistor N62 and a PMOS transistor P62 are provided as second gate voltage correction means. The NMOS transistor N62 is short-circuited between the source and the drain and operates as a capacitive element. The gate of the NMOS transistor N62 is connected to the gate of the NMOS transistor N60, and the source / drain of the NMOS transistor N62 is connected to the gate of the PMOS transistor P63. The gate-source (or drain) capacitance of the NMOS transistor N62 is set substantially equal to the gate-source (or drain) capacitance of the PMOS transistor P63. The NMOS transistor N62 changes the gate voltage of the PMOS transistor P63 in the reverse direction according to the change in the potential at the connection point between the PMOS transistor P63 and the NMOS transistor N55. The PMOS transistor P62 is similarly configured. Thus, the PMOS transistor P62 and the NMOS transistor N62 function as balancers for canceling the influence of the NMOS transistor N63 and the PMOS transistor P63, respectively.
[0044]
Next, the timing of a series of operations in the integration circuits C and D will be described. First, as an initial state, the charge / discharge current is determined in advance by block A and block B. On the other hand, the integration node node-P of the block C is reset to Vss by the reset NMOS transistor N64. The integration node node-N of the block D is reset to Vdd by the resetting PMOS transistor P64. Now, when the signal tdin input to the integrating circuits C and D through the differential input circuit 1 via the differential input circuit 1 becomes Low, the RS flip-flop in the block E is set and td0 also becomes Low. At this time, each of the resetting transistors N64 and P64 is turned off, and the driving transistor P60 connected in series with the charging transistor N55 and the transistor N60 connected in series with the discharging transistor N56 are turned on. Charging / discharging is started. When each voltage exceeds the threshold value of the inverters iv1 and iv2, the output of the inverter is inverted, and at the same time, the RS flip-flop is reset to the initial state.
[0045]
FIG. 5 shows simulation results of the circuits of FIGS. 5A is a graph showing a change in the voltage of a node through which iC flows, that is, the gate voltage of the PMOS transistor P60, FIG. 5B is a graph showing a charging waveform of the node-P, and FIG. FIG. 5D is a graph showing a node-N discharge waveform. FIG. 5D is a graph showing a change in the voltage of the flowing node, that is, a change in the gate voltage of the NMOS transistor N60. Here, the simulation was performed with the integration current control circuit B changing the set value in several stages. In each figure, the horizontal axis is time (ns), and the vertical axis is voltage (V). As can be seen from FIGS. 5A and 5B, the gate voltage of the PMOS transistor P60 is almost constant and the charge waveform changes almost linearly. 5 (c) and 5 (d), it can be seen that the gate voltage of the NMOS transistor N60 is almost constant and the discharge waveform changes almost linearly.
[0046]
In this embodiment, the span control unit A controls the output current by changing the span in 16 digital steps. On the other hand, the integral current control circuit B controls the current by changing the set value of the delay amount in 64 digital steps. That is, one feature of the present invention is that the integrated currents iC and iD, and hence the delay amount, are generated by using two input systems of the span and the delay amount set value.
[0047]
Next, how to synchronize clocks in the internal clock generation circuit of this embodiment will be described. First, as shown in FIG. 1, the control circuit 8 sends a control signal C1 to the second variable delay circuit 5, and sets the second variable delay circuit 5 to zero delay. At this time, an external clock and a clock that has been delayed by one cycle by the first variable delay circuit 4 are input to the phase comparison circuit 2. Based on the signal from the phase comparison circuit 2, the control circuit 8 determines whether the phase of the clock subjected to the one-cycle delay is advanced or delayed with respect to the phase of the external clock, and the first variable delay circuit 4. A predetermined signal is sent to. Then, the first variable delay circuit 4 increases or decreases the delay amount by the minimum step. In this way, the control circuit 8 makes the phases of the external clock and the clock subjected to the one-cycle delay by the first variable delay circuit 4 coincide.
[0048]
Next, the control circuit 8 sends a control signal C1 to the second variable delay circuit 5, and sets the second variable delay circuit 5 to one cycle delay. At this time, the phase comparison circuit 2 receives an external clock and a clock that has been delayed by two cycles by the first variable delay circuit 4 and the second variable delay circuit 5. Based on the signal from the phase comparison circuit 2, the control circuit 8 determines whether the phase of the clock subjected to the two-cycle delay is advanced or delayed with respect to the phase of the external clock, and sends a predetermined current to the variable current source 6. Send a signal. Then, the variable current source 6 adjusts the span based on the signal. In this way, the control circuit 8 matches the phase of the external clock with the clock that has received the two-cycle delay by the first variable delay circuit 4 and the second variable delay circuit 5.
[0049]
By the way, when the span controller (variable current source) changes the span, the delay amount also changes. For this reason, the phase of the clock adjusted when the second variable delay circuit 4 is first set to zero delay is shifted. This can be said to be the fate of the circuit constituting the span control unit. Therefore, in the present embodiment, when the second variable delay circuit 5 is set to zero delay, the first variable delay circuit 4 is controlled to adjust the phase of the clock, and the second variable delay circuit 5 is The operation of controlling the variable current source 6 to adjust the phase of the clock when it is set to one cycle delay is alternately repeated, so that the second variable delay circuit 5 is finally set to zero delay, 1 The delay amount of the first variable delay circuit 4 and the current value of the variable current source 6 are set so that the phase shift of the clock when set to each of the period delays becomes zero. Thus, the external input clock and the internal clock are accurately synchronized.
[0050]
In addition, this invention is not limited to said embodiment, A various deformation | transformation is possible within the range of the summary.
[0051]
【The invention's effect】
As described above, in the internal clock generation circuit and the variable delay circuit according to the present invention, not only the transistor is selectively driven by the variable current source, but also the delay amount is changed using a direct phase difference with the external clock. Therefore, a minute delay due to the temperature of the LSI chip or an internal circuit can be canceled out, and accurate synchronization can be achieved particularly in an integrated circuit operating at a high speed.
[0052]
In addition to controlling the delay of the clock, it is possible to control the irregularly generated delay in the internal input circuit by automatically adjusting the span itself, so that the frequency is high. Suitable for integrated circuits.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of an internal clock generation circuit according to an embodiment of the present invention.
FIG. 2 is a specific circuit diagram of a variable current source used in the internal clock generation circuit.
FIG. 3 is a specific circuit diagram of a second or third variable delay circuit used in the internal clock generation circuit.
FIG. 4 is a specific circuit diagram of a second or third variable delay circuit used in the internal clock generation circuit.
FIG. 5 is a diagram showing simulation results of the circuits of FIGS. 2 to 4;
FIG. 6 is a schematic diagram of a conventional delay circuit.
[Explanation of symbols]
1 Differential input circuit
2 Phase comparison circuit
3 Inverter
4 First variable delay circuit
5 Second variable delay circuit
6 Variable current source
7 Third variable delay circuit
8 Control circuit
A Span controller
B Integral current controller
C, D integration circuit

Claims (10)

A differential input circuit to which a clock signal is input; and
A first variable delay circuit for delaying the clock signal by one period;
An integration type second variable delay circuit that delays the output of the first variable delay circuit by zero or one period according to a control signal;
Phase comparison means for comparing the clock signal and the output of the second variable delay circuit;
A variable current source for supplying an integration current to the second variable delay circuit;
When the second variable delay circuit is alternately switched between a zero delay and a one-cycle delay by sending a control signal to the second variable delay circuit based on the output of the phase comparison means and controlling it, the clock always Control means for controlling the output current of the variable current source so that the phase of the signal and the output of the second variable delay circuit match,
The output of the first variable delay circuit is input, generates an internal clock integrated to the integrated current from the variable current source based on the output clock of the first variable delay circuit, the second variable delay of A third variable delay circuit having the same circuit configuration as the circuit ;
An internal clock generation circuit comprising:   2. The control unit according to claim 1, wherein the control unit controls the first variable delay circuit so that a phase difference of the phase comparison unit becomes zero when the second variable delay circuit is set to zero delay. An internal clock generation circuit which controls the variable current source so that a phase difference of the phase comparison means becomes zero when the variable delay circuit is set to one cycle delay. According to claim 1 or 2, wherein the second variable delay circuit, which delays the clock signal by integrating the current supplied on the basis of the clock signal input from the outside from the variable current source,
A master transistor,
A first slave transistor and a second slave transistor, whose gates are connected to the master transistor and whose source and drain are connected in series, and the first and the first slave transistors, which are complementarily short-circuited between the source and drain A plurality of slave transistor pairs, each of which includes a selection transistor and a second selection transistor that complementarily short-circuits between the source and drain of the second slave transistor,
An internal clock generation circuit that controls an amount of delay by switching an output current by changing an operation pattern of each pair of the first selection transistor and the second selection transistor. 4. The internal clock according to claim 3, wherein the first slave transistor of the slave transistor pair has a common gate length, and the second slave transistor has a different gate length for each of the slave transistor pairs. Generation circuit . 5. The internal clock generation circuit according to claim 4, wherein the second slave transistors of the pair of slave transistors are set so that the gate length sequentially increases or decreases in the order in which they are connected in series. In any one of claims 3 to 5, the internal clock generation circuit the slave transistor pair groups of the respective slave transistor pair is characterized in that in correspondence with each bit of the binary code of the delay amount set value. 3. The second variable delay circuit according to claim 1, wherein the second variable delay circuit integrates the current supplied from the integration current control unit and the integration current control unit according to an input clock signal, and delays the clock signal. and a integration circuit for the integration circuit portion,
A driving transistor driven by a current supplied from the integral current control unit;
Capacitive means for accumulating charge by the drive transistor;
Connected to the gate terminal of the drive transistor, has a capacity approximately equal to the gate-source capacity or the gate-drain capacity of the drive transistor, and according to a change in potential at the connection point of the drive transistor and the capacity means First gate potential correction means for changing the potential of the gate terminal of the driving transistor in the reverse direction;
An internal clock generation circuit comprising: 8. The integration circuit unit according to claim 7, wherein the integration circuit unit includes a first integration unit having a first transistor of the first conductivity type as the drive transistor, and a second different from the first transistor of the first conductivity type. A second integration unit that has a second transistor having the following conductivity type and performs a complementary operation with the first integration unit, and the gate of the first transistor and the source or drain of the second transistor An internal clock generation circuit, wherein a capacitor having a capacity corresponding to the gate-source capacity of the first transistor is connected as the first gate potential correction means . In Claim 8, each of the first integration unit and the second integration unit of the integration circuit unit,
A switching transistor having an integration clock signal as a gate input between the driving transistor and the capacitor means;
Connected to the gate terminal of the switching transistor, has a capacity substantially equal to the gate-source capacity or the gate-drain capacity of the switching transistor, and according to the change in potential at the connection point of the switching transistor and the capacity means Second gate potential correction means for changing the potential of the gate terminal of the driving transistor in the reverse direction;
An internal clock generation circuit comprising: 10. The first integration unit according to claim 9, wherein the first integration unit includes a third transistor of the first conductivity type as the switching transistor, and the second integration unit is a third of the first conductivity type. A fourth transistor having a second conductivity type different from that of the third transistor, and a gate-source capacitance of the third transistor between the gate of the third transistor and the gate of the fourth transistor. An internal clock generating circuit, wherein a capacitor having a corresponding capacity is connected as the second gate voltage correcting means .

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