JP3790063B2 - Multilayer wiring board, manufacturing method thereof, and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring board, a manufacturing method thereof, and a semiconductor device, and more particularly to a technique useful for realizing fine wiring in a build-up multilayer wiring board provided as a semiconductor package.
[0002]
[Prior art]
In recent years, printed wiring boards have been required to be lightweight, and miniaturization and high wiring are required to mount PGA (pin grid array), BGA (ball grid array), etc., which are small and multi-pinned. Densification is required. However, since the conventional printed wiring board requires a large area for forming the via hole, the degree of freedom in design is limited, and it is difficult to miniaturize the wiring. Therefore, a printed wiring board (build-up multilayer wiring board) using a build-up method has been put into practical use in recent years.
[0003]
Many types of build-up multilayer wiring boards can be manufactured by combining interlayer insulating layer materials and via hole formation processes, and the manufacturing process generally includes formation of insulating layers and vias in insulating layers. -The formation of holes and the formation of conductor patterns (wirings) including the insides of via holes are sequentially repeated.
[0004]
In such a manufacturing process, when a wiring is formed, a subtractive method, a semi-additive method, or a full additive method is mainly used.
The subtractive method is a conventionally known method. In general, a photosensitive etching resist film or the like is formed on a wiring (conductor film) formed on a flat insulating film, and wiring is performed by etching. This is a technique for forming a wiring by removing a conductor film other than the portion.
[0005]
In addition, the semi-additive method generally means that after electroless copper plating is performed on the entire surface of a wiring substrate (insulating substrate) that has been drilled, a wiring pattern is formed with a plating resist, and an exposed copper plating film is formed. This is a method of forming wiring by forming an electrode and growing electrolytic plating only on this portion.
The full additive method is generally a method of forming wiring by exposing and developing a plating resist so that only the wiring portion is opened and electroless copper plating is grown only on the opened portion.
[0006]
[Problems to be solved by the invention]
As described above, in the subtractive method, the conductor film other than the wiring portion is removed by etching using the resist film formed on the wiring (conductor film) as a mask. For example, isotropic etching was performed. In this case, the portion of the conductor film close to the edge portion of the resist film progresses faster than the portion farther away, so that the portion is further etched, and the cross-sectional shape of the conductor film becomes a trapezoidal shape. There was a problem that (side etching) occurred. This appears more prominently as the conductor film becomes thicker, and is particularly likely to occur when the adhesion of the resist film to the conductor film is poor.
[0007]
Further, if such a side-etched portion exists in the conductor film that defines the wiring pattern, the portion is lost due to the pressure of the shower during the cleaning process performed in a later process (that is, the wiring layer) There is also a problem that a so-called “wiring jump” occurs.
In the subtractive method, when the minimum line width of the wiring pattern is about 100 μm or less, the yield is lowered and it is difficult to mass-produce. For this reason, it has been difficult to realize fine wiring with the current technology.
[0008]
On the other hand, in the full additive method, for example, when a dry film is used as the plating resist, the development accuracy of the dry film becomes the pattern accuracy as it is, so that fine wiring can be realized.
However, the full additive method, like the semi-additive method, performs electroless plating when forming the wiring (pattern), so the plating species remaining on the surface of the insulating film may adversely affect electromigration. there were.
[0009]
The present invention has been created in view of the problems in the prior art, and realizes fine wiring at a level close to that of the full additive method without inconveniences such as side etching and electromigration. It is an object of the present invention to provide a multilayer wiring board that can contribute to the formation of holes, a manufacturing method thereof, and a semiconductor device.
[0010]
[Means for Solving the Problems]
In order to solve the above-described problems of the prior art, according to one aspect of the present invention, a step of forming a second insulating layer on the first insulating layer having the first wiring formed on the surface thereof; Forming a peelable resin film having a pattern patterned so as to follow the shape of the second wiring on the second insulating layer; and the upper end of the resin film on the pattern forming side Embedding in the second insulating layer until it coincides with the upper end of the insulating layer, peeling and removing the resin film, thereby forming a recess in the second insulating layer, and in the recess wherein the step of forming a via hole reaching the first wiring, the via hole and the forming a metal film on the second insulating layer so as to fill the recess interlayer connection portion and the second wiring forming a, of the wiring required the same steps as the steps Method for manufacturing a multilayer wiring board which comprises a step of repeating until the number is provided.
[0011]
According to the method for manufacturing a multilayer wiring board according to the present invention, when forming the wiring (second wiring), the wiring is not formed on the flat insulating film as in the prior art, but the second insulating film is formed. Since the via hole and the recess formed in the layer are embedded (that is, the wiring is embedded in the second insulating layer), the problem as seen in the conventional pattern forming method is solved. Can do. That is, the etching process used in the subtractive method is not performed, and the electroless plating used in the semi-additive method or the full additive method is not performed. Absent.
[0012]
As a result, it is possible to realize a fine wiring of a level close to that of the full additive method, and the diameter of the via hole included in the fine wiring can be reduced accordingly. That is, a via hole having a high aspect ratio can be formed.
Moreover, according to the other form of this invention, the multilayer wiring board manufactured by the manufacturing method of the multilayer wiring board mentioned above is provided.
[0013]
Furthermore, according to another aspect of the present invention, a side on which pins or balls are provided in a PGA type or BGA type wiring board configured by using the multilayer wiring board manufactured by the above-described method for manufacturing a multilayer wiring board. A semiconductor device is provided in which an electronic component, a semiconductor device, or the like is mounted on a surface opposite to the surface.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a build-up multilayer wiring board according to an embodiment of the present invention will be described with reference to FIGS.
First, in the first step (see FIG. 1A), two layers are respectively formed on the copper (Cu) wiring 11 patterned on both surfaces of a core base material (core substrate 10 in the present embodiment) serving as a base of the wiring board. Insulating layers 12 and 13 having a structure are formed. That is, the nonwoven fabric-containing insulating layer 12 is formed with a thickness of about 25 μm on the Cu wiring 11 on the core substrate 10, and the thermosetting insulating layer 13 is further formed thereon with a thickness of about 30 μm.
[0015]
In the illustrated example, for the sake of simplification, the cross-sectional structure of only one side of the core substrate 10 is shown, and this also applies to FIG.
For the material of the upper thermosetting insulating layer 13, it is sufficient if it has a property of being cured by a crosslinking reaction and exhibiting a thermally stable state when heated in a later step, such as an epoxy resin, A phenol resin or the like is used. On the other hand, it is desirable that the insulating layer 12 with the nonwoven fabric as a lower layer is made of a material having a low dielectric constant and that the film thickness can be controlled stably (film thickness control stability). For this purpose, for example, a liquid crystal polymer, an aramid fiber, or the like is used as the nonwoven fabric, and an epoxy resin, a polyimide resin, or the like is used as the insulating layer.
[0016]
Further, the core substrate 10 constitutes an insulating layer, and constitutes the core layer (first layer) of the build-up multilayer wiring substrate together with the Cu wiring 11 (conductor layer) formed thereon. As the material of the core substrate 10, for example, glass-epoxy resin, glass BT (bismaleimide-triazine) resin, or the like is used. The core layer is produced, for example, by forming a copper (Cu) wiring pattern by performing resist coating or etching on a copper-clad resin plate (such as a glass-epoxy resin composite plate) with a copper foil attached to the surface. obtain.
[0017]
In the next step (see FIG. 1B), a peelable resin film (in this embodiment, a dry film) used as a positive resist is formed on the thermosetting insulating layer 13, and a mask (not shown) is formed. The dry film is patterned so as to conform to the shape of the second layer wiring, and exposure and development with an alkaline solution are performed. As a result, a dry film 14 patterned in the shape of the second-layer wiring as shown in the figure is formed on the thermosetting insulating layer 13. The film thickness of the dry film 14 thus formed defines the film thickness of the second-layer wiring, and is selected to be about 25 μm in this embodiment.
[0018]
In the next step (see FIG. 1C), the patterned dry film 14 is not destroyed (that is, the shape of the dry film 14 is accurately maintained), and the Cu wiring 11 on the core substrate 10 is formed. The insulating layer 13 is cured while embedding the dry film 14 in the insulating layer 13 by applying heat to melt the thermosetting insulating layer 13 while being pressed from both sides of the substrate so as not to break.
[0019]
In the next step (see FIG. 2A), the dry film 14 (see FIG. 1C) is peeled off and removed using a weak alkaline chemical solution (for example, an aqueous solution of sodium hydroxide (NaOH)). As a result, the recess 16 is formed in the portion (indicated by the broken line) where the dry film 14 is formed in the thermosetting insulating layer 13 as shown in the figure. The recess 16 has the same thickness as that of the dry film 14, that is, the thickness of the second wiring layer.
[0020]
In the next step (see FIG. 2B), a portion of the thermosetting insulating layer 13 and the nonwoven fabric-containing insulating layer 12 corresponding to the position of the Cu wiring 11 on the core substrate 10 in the recess 16 are formed by laser drilling. A via hole 17 is formed with a diameter of about 35 μm. As the laser, a YAG laser, an excimer laser, or a CO ₂ laser is used.
[0021]
Thereafter, processing (deburring, desmear, etc.) for removing resin pieces and dirt generated by the drilling processing is performed.
In the next step (see FIG. 2C), a copper (Cu) plating film or vapor deposition film is formed on the entire surface of the substrate so as to fill the via hole 17 and the recess 16 by electrolytic panel plating or vapor deposition. As a result, an interlayer connection portion (via-hole conduction portion) 18 and a second-layer wiring portion 19 are formed. However, at this stage, since only electrolytic panel plating or vapor deposition processing is performed, uneven portions remain on the substrate surface as shown.
[0022]
In the next step (see FIG. 3A), the uneven portion of the substrate surface described above is polished and flattened by mechanical polishing. In the figure, reference numeral 20 denotes fine abrasive grains used for polishing, and flattening is performed by processing the substrate surface by mechanical pushing and scratching action of the fine abrasive grains.
In the next step (see FIG. 3B), leveling (removal of the surface portion of the metal film) is performed by wet etching until the second-layer wiring portion 19 is exposed. In the drawing, the portion indicated by a broken line represents a portion removed by etching. At this stage, the final second-layer Cu wiring 21 is formed.
[0023]
In the last step (see FIG. 3C), the third insulating layer (with non-woven fabric) is formed on the second Cu wiring 21 (conductor layer) in the same manner as the step shown in FIG. The insulating layer 22 and the thermosetting insulating layer 23) are formed in a two-layer structure, and the same processes as those shown in FIGS. 1B to 3B are repeated.
Then, the above steps are repeated as appropriate until the required number of layers is obtained, and insulating layers including via holes and conductor layers (Cu wiring) are alternately stacked.
[0024]
As described above, according to the method for manufacturing a build-up multilayer wiring board according to the present embodiment, when forming a wiring in each layer (excluding the core layer), an etching process as used in the subtractive method, or The wiring is embedded in the insulating layer by electrolytic panel plating or vapor deposition without performing electroless plating as used in the semi-additive method or the full additive method, as seen in the conventional pattern formation method. Problems (side etching, wiring jump, electromigration, etc.) can be solved.
[0025]
As a result, it is possible to realize fine wiring at a level close to that of the full additive method, and it is possible to reduce the diameter of the via hole included in the fine wiring. This contributes to the formation of high aspect ratio via holes.
In addition, since each layer (excluding the core layer) has an insulating layer having a two-layer structure (insulating layer containing nonwoven fabric and thermosetting insulating layer), for example, when looking at the second layer, It can function as a buffer layer between the Cu wiring 11 on the lower layer side and the thermosetting insulating layer 13 on the upper layer. That is, when pressing is performed by pressing from both sides of the substrate (see FIG. 1C), an excessive force due to the pressing is prevented from spreading to the Cu wiring 11 and the Cu wiring 11 is not destroyed (that is, Cu The shape and the like of the wiring 11 can be maintained accurately).
[0026]
FIG. 4 illustrates an application example of the build-up multilayer wiring board according to the above-described embodiment.
In the illustrated example, the build-up multilayer wiring board of the above-described embodiment is realized in the form of a PGA type wiring board in which a large number of pins serving as external connection terminals of a plastic type semiconductor package are erected on one surface of the board. In this case, an example of the configuration is schematically shown. In the wiring board, an electronic component, a semiconductor device or the like (semiconductor chip 31 in the illustrated example) is mounted on the surface opposite to the side where the pins 30 are provided. 1 shows the configuration of a semiconductor device.
[0027]
In the drawing, hatched portions represent wirings or interlayer connection portions (via-hole conduction portions) formed by a copper (Cu) plating film or vapor deposition film. Reference numeral 24 is a third-layer Cu wiring (conductor layer), 32 is a solder bump provided on the chip 31, 33 is an underfill agent such as epoxy resin, and 34 is hardened by ultraviolet (UV) irradiation. A solder resist layer made of resin, 35 is solder, and 36 is a through hole provided in the core substrate 10 (not shown in FIGS. 1 to 3 for simplicity of explanation).
[0028]
The pins 30 are joined as follows, for example. First, the portion of the solder resist layer 34 corresponding to the region of the conductor layer (Cu wiring defined as a pad) to which the pins 30 are to be bonded is irradiated with UV, exposed and developed to form openings. Next, an appropriate amount of solder 35 is placed on the pad in the opening, and the head of the T-shaped pin 30 having a large-diameter head is disposed thereon, and reflow is performed to perform solder 35. And pin 30 is fixed. On the other hand, the chip 31 and the wiring board are connected by pressing the solder bumps 32 against the pads (Cu wiring) of the wiring board by thermocompression bonding or the like.
[0029]
In the configuration example shown in FIG. 4, the case where the build-up multilayer wiring board of the above-described embodiment is realized in the form of a PGA type wiring board is described. However, such a build-up multilayer wiring board is realized in the form of a BGA type wiring board. It will be apparent to those skilled in the art that the same applies to
In the above-described embodiment, the case where the insulating layer formed on the Cu wiring has a two-layer structure has been described. However, the structure of the insulating layer is not limited to this. In short, if the insulating layer as a whole has the low dielectric constant, the film thickness control stability, and the thermosetting property, it may be a multilayer structure other than two layers or a single layer structure. Is possible.
[0030]
Moreover, in embodiment mentioned above, although the core board | substrate 10 is used for the core base material used as the base of a wiring board, it may replace with this and may use the film which consists of polyimide resins. In this case, the core layer is formed by, for example, applying a polyimide-based thermoplastic adhesive on the surface of a polyimide resin film, hot pressing and bonding a copper (Cu) foil thereon, and performing photoetching or the like to form a wiring pattern. Can be produced.
[0031]
【The invention's effect】
As described above, according to the present invention, by embedding wiring in a flat insulating layer by electrolytic panel plating or vapor deposition, it is possible to solve the problems as seen in the conventional pattern forming method and It can achieve fine wiring at a level close to that of the additive method, and thus contribute to the formation of via holes with a high aspect ratio.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process (No. 1) of a buildup multilayer wiring board according to an embodiment of the present invention.
2 is a cross-sectional view showing a manufacturing process (No. 2) following the manufacturing process of FIG. 1; FIG.
3 is a cross-sectional view showing a manufacturing process (No. 3) subsequent to the manufacturing process of FIG. 2; FIG.
FIG. 4 is a cross-sectional view showing an application example of a buildup multilayer wiring board according to an embodiment of the present invention.
[Explanation of symbols]
10 ... Core substrate (core substrate serving as the base of the wiring substrate)
11, 19, 21, 24 ... Cu wiring (conductor layer)
DESCRIPTION OF SYMBOLS 12, 22 ... Insulating layers 13 and 23 with nonwoven fabric ... Thermosetting insulating layer 14 ... Dry film 16 ... Recess 17 ... Via hole 18 ... Interlayer connection part (conduction part of via hole)
30 ... Pin 31 ... Semiconductor chip 32 ... Solder bump 33 ... Underfill agent 34 ... Solder resist layer 35 ... Solder

Claims (9)

Forming a second insulating layer on the first insulating layer having the first wiring formed on the surface;
Forming a peelable resin film having a pattern patterned to conform to the shape of the second wiring on the second insulating layer;
Burying the pattern forming side of the resin film in the second insulating layer until the upper end thereof coincides with the upper end of the second insulating layer;
Peeling and removing the resin film, thereby forming a recess in the second insulating layer;
Forming a via hole reaching the first wiring in the recess;
Forming an interlayer connection and a second wiring by forming a metal film on the second insulating layer so as to fill the via hole and the recess;
And a step of repeating the same steps as the above steps until the required number of wiring layers is reached.   The step of forming the interlayer connection portion and the second wiring is performed by electrolytic panel plating or vapor deposition, so that a metal of a plating film or vapor deposition film is formed on the entire surface of the second insulating layer so as to fill the via hole and the concave portion. 2. The method of claim 1, further comprising: forming a film; planarizing a surface of the metal film; and removing a surface portion of the metal film until the second wiring is exposed. The manufacturing method of the multilayer wiring board as described.   The step of forming the second insulating layer is characterized in that the second insulating layer is formed of a material having a low dielectric constant, a film thickness control stability, and a thermosetting property. 2. A method for producing a multilayer wiring board according to 1.   The step of forming the second insulating layer includes a step of forming a third insulating layer having a low dielectric constant and film thickness control stability on the first insulating layer, and a step of forming the third insulating layer. A method for producing a multilayer wiring board according to claim 3, further comprising a step of forming a fourth insulating layer having thermosetting properties thereon.   In the step of embedding the resin film in the second insulating layer, the resin film is embedded in the insulating layer by pressing from both sides by pressing and melting the upper end portion of the second insulating layer by applying heat. The method for producing a multilayer wiring board according to claim 1.   The method for producing a multilayer wiring board according to claim 1, wherein a dry film is used as the peelable resin film. 2. The method for manufacturing a multilayer wiring board according to claim 1 , wherein in the step of forming the via hole, the via hole is formed by a YAG laser, an excimer laser, or a CO2 laser.   The multilayer wiring board manufactured by the manufacturing method of the multilayer wiring board as described in any one of Claim 1 to 7.   A semiconductor device, wherein a semiconductor element is mounted on the multilayer wiring board manufactured by the method for manufacturing a multilayer wiring board according to claim 1.

Images