JP3789123B2 - Semiconductor device and solid-state imaging device using the same - Google Patents

Description

  The present invention relates to a semiconductor device and a solid-state imaging device using the same, and more particularly to improvement of a reset circuit of the semiconductor device.

  Conventionally, as a reset circuit of a semiconductor device, for example, there is a synchronous reset circuit disclosed in Patent Document 1, but an asynchronous reset is often used for a semiconductor device that needs to be reset at a cold start when power is turned on. However, when the asynchronous reset release timing and the clock rise timing become very close, the operation of the flip-flop cannot be determined.

  FIG. 6 shows a reset circuit of a conventional semiconductor device for solving this problem. The reset circuit includes a plurality of flip-flop groups 6 to 8 each having a data terminal D, a clock terminal C, an output terminal Q, and an asynchronous reset terminal R, a clock input terminal 2 to which a clock signal is input, and an operation of the clock signal. An asynchronous reset input terminal 1 to which a reset signal asynchronous with the timing is input, and a reset buffer 5a for distributing the reset signal input from the asynchronous reset input terminal 1 to the asynchronous reset terminals R of the flip-flop groups 6 to 8 5d and a two-stage synchronization flip-flop (data terminal D, clock terminal C, and output terminal Q) that synchronizes the reset signal input from the asynchronous reset input terminal 1 with the clock signal input from the clock input terminal 2. And data input terminals 106A to 106 to which signals are input. AND gates 103 to 105 for releasing the reset operation of the flip-flop groups 6 to 8 in synchronization with the clock signal, and clock buffers 3 a to 3 e for distributing the clock signal input from the clock input terminal 2 Consists of.

  Among these, the clock buffers 3a to 3e are flip-flops in the placement and wiring design process of the semiconductor device in order to distribute the clock signal input from the clock input terminal 2 to the clock terminals C of the flip-flop groups 6 to 8 at the same timing. The buffers are inserted according to the arrangement of the groups, and are connected in a tree shape.

  The reset buffers 5a to 5d also distribute the reset signal input from the asynchronous reset input terminal 1 to the asynchronous reset terminals R of the flip-flop groups 6 to 8 at the same timing. It is a buffer inserted according to the arrangement of flip-flops, and is connected in a tree shape.

  The operation of the conventional circuit will be described below with reference to FIGS.

  FIG. 7 is a timing chart showing the operation of the reset circuit of the conventional example shown in FIG. In the figure, (a) is the waveform of the power supply voltage, (b) is the waveform of the clock signal input to the clock input terminal 2, and (c) is the waveform of the asynchronous reset signal input to the asynchronous reset terminal 1 (asynchronous reset waveform). ; Low state is a reset start signal, High state is a reset release signal), (d) is a waveform of a clock signal (clock terminal) input to each clock terminal C of the flip-flop groups 6 to 8 and the synchronization flip-flops 101 and 102; (Waveform), (e) is the waveform of the signal input to the asynchronous reset terminal R of the flip-flop group 6, (f) is the waveform of the signal input to the asynchronous reset terminal R of the flip-flop group 7, (g) Is the waveform of the signal input to the asynchronous reset terminal R of the flip-flop group 8, and (h) is output from the output terminal Q of the synchronization flip-flop 102. Synchronous reset signal waveform (T1 synchronous reset waveform), (i) shows a signal waveform outputted from the output terminal Q of the flip-flop group 6-8 (flip flop output waveform), respectively.

  First, as shown in FIG. 7A, the power is turned on and the power supply voltage rises, and then, as shown in FIG. 7B, a clock signal is input to the clock input terminal 2 at time t1.

  Next, as shown in FIG. 7C, after the operation of the power supply voltage and the clock signal is stabilized, the logic level of the asynchronous reset signal is set to the High state asynchronously with the operation timing of the clock signal between the times t2 and t3. By doing so, the reset release signal is input to the asynchronous reset input terminal 1.

  At this time, the waveforms of the clock terminals C of the flip-flop groups 6 to 8 and the clock terminals C of the synchronization flip-flops 101 and 102 are caused by the cell delay and the wiring delay of the clock buffers 3a to 3e as shown in FIG. A delay of time d11 occurs from the waveform input to the clock input terminal 2.

  Similarly, the waveform of the asynchronous reset terminal R of the flip-flop groups 6 to 8 is also delayed from the input waveform of the asynchronous reset input terminal 1 due to cell delay and wiring delay of the reset buffers 5a to 5d. At this time, the waveform of the asynchronous reset terminal R of the flip-flop group 6 is shown in FIG. 7 (e), the waveform of the asynchronous reset terminal R of the flip-flop group 7 is FIG. 7 (f), and the waveform of the asynchronous reset terminal R of the flip-flop group 8. However, as shown in FIG. 7G, the delay of the asynchronous reset signal (reset release signal) to the asynchronous reset terminal R of each flip-flop varies (see times d12 to d14).

  At this time, when the reset release timing of the asynchronous reset signal and the operation timing of the rising edge of the clock signal are very close, the asynchronous reset release is performed at times t3 to t4 in the flip-flop group 6 as shown in FIG. Since the reset release timing of the asynchronous reset signal delayed by time d12 is earlier than the timing of the rising edge e1 of the third clock signal delayed by time d11 at times t3 to t4, the operation of the rising edge e1 In the flip-flop groups 7 to 8, the reset release timing of the asynchronous reset signal delayed by the times d13 and d14 from time t4 to t5 is later than the operation timing of the rising edge e1 of the third clock signal. Therefore, the operation timing of the rising edge e2 of the next clock signal is It is carried out in the timing.

  In this case, if the reset release of the flip-flop groups 6 to 8 is performed only by the reset release signal of the asynchronous reset signal, the reset is released at different timings as described above, and thus malfunction occurs.

  However, the data terminals D of the flip-flop groups 6 to 8 are connected to the AND gates 103 to 105, and the input terminals of the AND gates 103 to 105 are synchronized with the input signals from the data input terminals 106A to 106C. A synchronous reset signal synchronized with the clock signal is input by the inverting flip-flops 101 to 102, and operates as a synchronous reset circuit by performing a logical operation that takes a logical product (AND) of both inputs.

  Moreover, the input waveform of the synchronous reset signal input to the AND gates 103 to 105, that is, the T1 synchronous reset waveform output from the synchronization flip-flop 102 is the reset release of the asynchronous reset signal as shown in FIG. Since the logic level changes from the Low state to the High state in synchronization with the operation timing of the rising edge e2 of the second clock signal after the signal is input, it is input to the data terminals D of the flip-flop groups 6-8. The logic level of the waveform is fixed to the Low state until the rising edge e2 of the clock signal shown in FIG.

  Accordingly, the output waveforms of the flip-flop groups 6 to 8 are simultaneously released from reset at the operation timing of the rising edge e3 of the clock signal shown in FIG. 7 (d), as shown in FIG. 7 (i). The operations of groups 6-8 start.

As described above, according to the reset circuit shown in FIG. 6, the reset at the cold start is possible, and the malfunction of the flip-flop due to the reset release timing can be prevented.
Japanese Patent Laid-Open No. 7-168652

  However, in the conventional reset circuit described above, since the synchronous reset signal is input to the data terminal of the flip-flop, a synchronous reset circuit is required for the input data of the flip-flop, which increases the circuit scale and the input data signal. There is a problem of increasing the delay time.

  Furthermore, since the wiring of the synchronous reset signal is connected without considering the arrangement position of the flip-flop in the layout wiring design process, the wiring length of the synchronous reset signal tends to be long. There was a problem of increasing the area.

  The present invention has been made in consideration of such a conventional situation, and an object of the present invention is to prevent a flip-flop from malfunctioning when an asynchronous reset is canceled in a semiconductor device that needs to be reset at a cold start upon power-on. And

  The present invention has been made in view of the above problems, and in a semiconductor device having a plurality of flip-flops having an asynchronous reset terminal and operating in synchronization with a clock, the asynchronous input from the outside of the semiconductor device Synchronous reset release means for synchronizing the reset end timing of the reset signal with the clock of the flip-flop to be initialized, and the reset signal generated by the synchronous reset release means at substantially the same timing at the asynchronous reset terminal of the flip-flop The flip-flop is started to be reset asynchronously with the clock, and the reset is released in synchronization with the clock.

  That is, according to the first aspect of the present invention, in a semiconductor device having an asynchronous reset terminal and having a plurality of flip-flops operating in synchronization with the operation timing of the input clock signal, the clock signal is input. A clock input terminal, an asynchronous reset input terminal to which a reset start signal and a reset release signal forming an asynchronous reset signal are input, and an asynchronous reset of the asynchronous reset input terminal and the plurality of flip-flops And a plurality of flip-flops to be initialized from the clock input terminal when the reset release signal is input from the asynchronous reset input terminal. The operation timing of the clock signal input to the Synchronous reset canceling means for generating a synchronous reset cancel signal in synchronization with the timing, and connected between the synchronous reset canceling means and the asynchronous reset terminals of the plurality of flip-flops, the signal from the synchronous reset canceling means, Means for distributing to each of the asynchronous reset terminals of the plurality of flip-flops to be initialized, and for the plurality of flip-flops to be initialized, the operation timing of the clock signal based on the reset start signal; The reset operation is started asynchronously, and the reset operation is released in synchronization with the operation timing of the clock signal based on the synchronous reset release signal.

In the second aspect of the present invention, the synchronous reset cancellation means includes an asynchronous reset terminal to which the reset signal is input, a clock terminal to which the clock signal is input, and a data terminal to which the reset signal is input. The synchronous reset release means generates an asynchronous reset start signal asynchronous with the operation timing of the clock signal when the reset start signal is input, and the reset release signal When input, the reset release operation timing by the reset release signal is synchronized with the operation timing of the clock signal input to the clock terminal to generate a synchronous reset release signal, and the plurality of initialization targets Based on the asynchronous reset start signal, the clock is sent to the flip-flop. Starting the reset operation to the operation timing and asynchronous click signal, and cancels the reset operation in synchronization with the operation timing of the clock signal based on the synchronization reset release signal.
According to a third aspect of the present invention, in addition to the second aspect of the present invention, the synchronous reset canceling means includes a plurality of synchronization flip-flops. In the fourth aspect of the present invention, the synchronization reset canceling means includes a plurality of synchronization flip-flops having at least a synchronization flip-flop having a clock terminal to which the clock signal is input and a data terminal to which the reset signal is input. Flip-flop, a first input terminal to which the reset signal is input, and a second input terminal to which the outputs of the plurality of synchronization flip-flops are input, the first and second input terminals A first output obtained by causing a logic level to transition to one of High and Low asynchronously with the operation timing of the clock signal, and in synchronization with the operation timing of the clock signal. A combinational logic circuit for generating a second output obtained by returning the logic level to the other of High and Low; A reset operation is started asynchronously with the operation timing of the clock signal based on the first output with respect to the plurality of flip-flops to be initialized, and the clock signal based on the second output The reset operation is canceled in synchronization with the operation timing. Furthermore, the solid-state imaging device according to the fifth aspect of the present invention is driven by a drive pulse generated by any one of the semiconductor devices described above.

  Furthermore, an imaging system according to a sixth aspect of the present invention provides a solid-state imaging device driven by a driving pulse generated by any one of the semiconductor devices described above, and an analog signal output from the solid-state imaging device as a digital signal. It has a means for converting and a means for processing the digital signal.

  According to the present invention, a reset at a cold start is possible, a malfunction of the flip-flop due to the reset release timing can be prevented, and a synchronous reset circuit for the input data of the flip-flop becomes unnecessary. . For this reason, the circuit scale can be reduced and the signal delay time of the input data can be reduced. Further, since the signal wiring for the synchronous reset circuit is not necessary, the wiring area can be reduced and the chip area of the semiconductor device can be reduced.

  Next, the best mode for carrying out a semiconductor device and a solid-state imaging device using the same according to the present invention will be described in detail with reference to FIGS.

  FIG. 1 is a block diagram of a semiconductor device according to the first embodiment. The semiconductor device includes a plurality of flip-flop groups 6 to 8 each having a data terminal D, a clock terminal C, an asynchronous reset terminal R, and an output terminal Q, a clock input terminal 2 to which a clock signal is input, and an operation of the clock signal. Between the asynchronous reset input terminal 1 to which a reset signal (reset start signal and reset release signal) asynchronous with timing is input, and the asynchronous reset input terminal 1 and the asynchronous reset terminals R of the plurality of flip-flop groups 6 to 8. A synchronous reset cancellation circuit 9 composed of connected and two-stage synchronization flip-flops (having a data terminal D, a clock terminal C, an asynchronous reset terminal R, and an output terminal Q) 4a and 4b; And a plurality of resets connected between the asynchronous reset terminals R of the flip-flop groups 6-8. Comprises a buffer 5a to 5d, a plurality of connected between the clock input terminal 2 and a plurality of flip-flop group 6-8 and the clock buffer 3 a to 3 d.

  The asynchronous reset input terminal 1 is a terminal for inputting a reset signal for initializing the entire semiconductor device. Asynchronous reset of the flip-flop groups 6 to 8 is performed via the synchronous reset cancellation circuit 9 and the reset buffers 5a to 5d. Connected to terminal R.

  The clock input terminal 2 is a terminal for inputting a clock pulse for controlling the flip-flop of the semiconductor device. The clock input terminal 2 is connected to the clock terminal C of each of the flip-flop groups 6 to 8 through the clock buffers 3a to 3d, and in parallel therewith. It is connected to the synchronous reset cancellation circuit 9.

  The asynchronous reset terminal R of the two-stage synchronization flip-flops 4a and 4b constituting the synchronous reset cancellation circuit 9 is connected to the asynchronous reset input terminal 1 and the clock terminal C is connected to the clock input terminal 2 in parallel. The data terminal D of the first synchronization flip-flop is connected to the asynchronous reset input terminal 1. The output terminal Q of the first-stage synchronization flip-flop is connected to the data terminal D of the second-stage synchronization flip-flop. The output terminal Q of the second-stage synchronization flip-flop is connected to the asynchronous reset terminal R of each flip-flop group 6-8 via the reset buffers 5a-5d as the output terminal of the synchronous reset cancellation circuit 9.

  The two-stage synchronization flip-flops 4a to 4b and the plurality of flip-flop groups 6 to 8 change the state of the signal input to the data terminal D at the operation timing of the rising edge of the clock signal input to the clock terminal C, respectively. The current operation state is reset regardless of the input state of the data terminal D and the clock terminal C by the input of the asynchronous reset terminal R by capturing and holding until the operation timing of the rising edge of the next clock signal.

  The clock buffers 3a to 3d are inserted between the clock input terminal 2 and the clock terminals C of the flip-flop groups 6 to 8 in accordance with the arrangement positions of the flip-flop groups 6 to 8 in the placement and wiring design process of the semiconductor device. The cell delays of the clock buffers 3a to 3d are connected so as to form a tree and the waveforms input from the clock input terminal 2 reach the clock terminals C of the flip-flop groups 6 to 8 almost identically. The delay of the wiring connecting them (wiring delay) is adjusted.

  Similarly to the above, the reset buffers 5a to 5d are also connected to the output terminals of the synchronous reset cancellation circuit 9 and the flip-flop groups 6 to 8 in accordance with the arrangement positions of the flip-flops 6 to 8, respectively, in the placement and wiring design process of the semiconductor device. Are connected between the asynchronous reset terminals R, connected in a tree shape, and the waveform output from the output terminal Q of the synchronous reset canceling circuit 9 is almost equal to each asynchronous reset terminal R of the flip-flop groups 6-8. The cell delays of the reset buffers 5a to 5d and the delays of the wirings connecting the respective buffers (wiring delays) are adjusted so as to reach the same.

  Here, a delay (clock delay) from the clock input terminal 2 to each clock terminal C of the flip-flop groups 6 to 8, and an asynchronous reset terminal R of the flip-flop groups 6 to 8 from the output terminal Q of the synchronous reset release circuit 9. The delay until (reset delay) is adjusted to be almost the same.

  The synchronous reset cancellation circuit 9 is composed of two stages of synchronization flip-flops 4a and 4b, and its clock terminal C is connected to the clock input terminal 2 without going through the clock buffers 3a to 3d.

  The asynchronous reset terminal R of the synchronization flip-flops 4 a and 4 b and the data terminal D of the synchronization flip-flop 4 a are connected to the asynchronous reset input terminal 1. Further, the output terminal Q of the first-stage synchronization flip-flop 4a is connected to the data terminal D of the second-stage synchronization flip-flop 4b, and a countermeasure against metastable of the flip-flop is taken. Further, the output terminal Q of the second-stage synchronization flip-flop 4b is an output terminal of the synchronous reset cancellation circuit 9, and is connected to the asynchronous reset terminal R of the flip-flop groups 6-8 via the reset buffers 5a-5d. The

  Next, the operation of this embodiment will be described with reference to FIGS.

  FIG. 2 is a flowchart showing the operation of the semiconductor device shown in FIG. In the figure, (a) is the waveform of the power supply voltage, (b) is the waveform of the clock signal input to the clock input terminal 2, and (c) is the waveform of the asynchronous reset signal input to the asynchronous reset terminal 1 (asynchronous reset waveform). The Low state is a reset start signal, the High state is a reset release signal), (d) is the output waveform (T1 waveform) of the synchronization flip-flop 4a, (e) is the output waveform (T2 waveform) of the synchronization flip-flop 4b, (F) is a waveform of a clock signal (clock terminal waveform) input to each clock terminal C of the flip-flop groups 6 to 8, and (g) is a waveform of a signal input to the asynchronous reset terminal R of the flip-flop group 6. , (H) is a waveform of a signal input to the asynchronous reset terminal R of the flip-flop group 7, and (i) is input to the asynchronous reset terminal R of the flip-flop group 8. Signal waveform, (j) shows the signal waveform outputted from the output terminal Q of the flip-flop group 6-8 (flip flop output waveform), respectively.

  First, as shown in FIG. 2A, the power is turned on and the power supply voltage rises, and then the first clock signal is input to the clock input terminal 2 as shown in FIG. 2B (time t1). ).

  Next, as shown in FIG. 2C, after the operation of the power supply voltage and the clock signal is stabilized, the logic level of the asynchronous reset signal to be input to the asynchronous reset terminals R of the flip-flop groups 6 to 8 is set to the High state. As a result, the reset release signal is input to the asynchronous reset input terminal 1.

  Here, since the asynchronous reset input terminal 1 is connected to the asynchronous reset terminals R of the synchronization flip-flops 4a to 4b, the reset start signal of the synchronous reset release circuit 9 is asynchronous as shown in FIG. The flip-flop groups 6 to 8 can be initialized by functioning as a reset signal and setting the logic level of the asynchronous reset signal input to the asynchronous reset input terminal 1 to the low state even in the cold start state.

  Since the asynchronous reset input terminal 1 is also connected to the data terminal D of the synchronization flip-flop 4a, the reset release signal corresponding to the high logic level is the clock terminal C of the synchronization flip-flop 4a. Are synchronized so as to be synchronized with the operation timing (time t3) of the rising edge e1 of the clock signal input to.

  At this time, as shown in FIG. 2 (c), when reset release is performed at the same time t2 as the rising edge of the second clock signal, the signal waveform (T1 waveform) of the output terminal Q of the synchronization flip-flop 4a However, as shown in FIG. 2D, a metastable occurs although the period is very short. In order not to propagate this metastable to the asynchronous reset terminal R of the flip-flop groups 6 to 8, the metastable is synchronized again with the clock signal by the synchronization flip-flop 4b of the next stage.

  As a result, the output of the second-stage synchronization flip-flop 4b, that is, the T2 waveform that is the output of the synchronous reset cancellation circuit 9, is the fourth waveform shown in FIG. A reset release signal is generated in synchronization with the operation timing (time t4) of the rising edge e2 of the clock signal. At this time, the reset release signal is delayed by a time d2 corresponding to the cell delay of the flip-flop with respect to the operation timing (time t4) of the rising edge e2 of the fourth clock signal.

  Further, the input waveform of each clock terminal C of the flip-flop groups 6 to 8 is time d1 from the input waveform of the clock input terminal 2 due to the cell delay and the wiring delay of the clock buffers 3a to 3d as shown in FIG. A minute delay occurs.

  Similarly, the input waveform of each asynchronous reset terminal R of the flip-flop groups 6 to 8 is also delayed from the waveform of the output terminal of the synchronous reset cancellation circuit 9 due to cell delay and wiring delay of the reset buffers 5a to 5d. The delay time is almost the same as the delay time d1.

  Here, as a result of the placement and routing design process, the delay between the synchronous reset cancellation circuit 9 and the asynchronous reset terminal R of the flip-flop groups 6 to 8 varies. For example, the waveform of the asynchronous reset terminal R of the flip-flop group 6 is shown in FIG. 2 (g), the waveform of the asynchronous reset terminal R of the flip-flop group 7 is as shown in FIG. 2 (h), and the waveform of the asynchronous reset terminal R of the flip-flop group 8 is as shown in FIG. 2 (i). Consider a case in which d3, d4, and d5 vary.

  At this time, the operation timing (time t4) of the rising edge e2 of the fourth clock signal shown in FIG. 2 (c) is the clock shown in FIG. 2 (f) at each clock terminal C of the flip-flop groups 6-8. Corresponding to the operation timing of the signal rising edge e3 (time delayed by time d1 from time t4), the delay time is d1.

  On the other hand, as shown in FIG. 2C, the reset release signal synchronized at the operation timing (time t2) of the rising edge e2 of the fourth clock signal is sent from the synchronous reset release circuit 9 to the flip-flop group 6. The time to reach the asynchronous reset terminal R is d2 + d3. Similarly, the time for the reset release signal to reach the asynchronous reset terminal R of the flip-flop groups 7 and 8 from the synchronous reset release circuit 9 is d2 + d4 and d2 + d5, respectively.

  The delay time d2 is due to the cell delay of the synchronization flip-flop 4a and is sufficiently large with respect to the delay variation of d3 to d5. Therefore, the synchronization reset release timing of the flip-flop groups 6 to 8 is as shown in FIG. ) Is sufficiently delayed from the operation timing of the rising edge e3 of the fourth clock signal (time delayed by d1 from time t4). As a result, the flip-flop groups 6 to 8 are simultaneously released from reset at the operation timing of the rising edge e4 of the fourth clock signal shown in FIG. 2 (f), and output a waveform as shown in FIG. 2 (j). To do.

  Therefore, according to the present embodiment, even if the reset release signal is input at any operation timing as described above, the reset release is performed by the synchronous reset release circuit 9 in synchronization with the operation timing of the clock signal. Can be prevented from malfunctioning.

  FIG. 3 is a block diagram of the semiconductor device according to the present embodiment. In this semiconductor device, the synchronous reset cancellation circuit 9 shown in FIG. 1 has two stages of synchronization flip-flops (having a data terminal D, a clock terminal C, and an output terminal Q) 4c to 4d, and an AND gate (combination logic circuit) 10. Except that the clock buffers 3a and 3e are connected between the clock input terminal 2 and the synchronization flip-flops 4c to 4d to which the clock pulse is supplied. 1 has the same configuration as in FIG. 1, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the synchronous reset cancellation circuit 9, the data terminal D of the first-stage synchronization flip-flop 4 c is connected to the asynchronous reset input terminal 1. The output terminal Q of the first-stage synchronization flip-flop 4c is connected to the data terminal D of the second-stage synchronization flip-flop 4d. The output terminal Q of the second-stage synchronization flip-flop 4d is connected to one of the two input terminals of the AND gate 10. The other of the two input terminals of the AND gate 10 is connected to the asynchronous reset input terminal 1, and the output terminal of the AND gate 10 serves as an output terminal of the synchronous reset cancel circuit 9 via each of the flip-flops via the reset buffers 5a to 5d. Connected to asynchronous reset terminals R of groups 6-8.

  Next, the operation of this embodiment will be described with reference to FIGS.

  FIG. 4 is a flowchart showing the operation of the semiconductor device shown in FIG. In the figure, (a) shows the waveform of the power supply voltage, (b) shows the waveform of the clock signal input to the clock input terminal 2, and (c) shows the clocks of the flip-flop groups 6 to 8 and the synchronization flip-flops 4c and 4d. Waveform of clock signal input to terminal C (clock terminal waveform), (d) is a waveform of asynchronous reset signal input to asynchronous reset terminal 1 (asynchronous reset waveform; Low state is reset start signal, High state is reset release (E) is an output waveform (T1 waveform) of the synchronization flip-flop 4a, (f) is an output waveform (T2 waveform) of the synchronous reset release circuit 9, and (g) is an asynchronous reset terminal of the flip-flop group 6. The waveform of the signal input to R, (h) is the waveform of the signal input to the asynchronous reset terminal R of the flip-flop group 7, and (i) is the flip-flop group. Asynchronous reset terminal signal waveform input to the R of, (j) shows the signal waveform outputted from the output terminal Q of the flip-flop group 6-8 (flip flop output waveform), respectively.

  First, as shown in FIG. 4A, after the power is turned on and the power supply voltage rises, the first clock signal is input to the clock input terminal 2 as shown in FIG. 4B (time t1). ).

  At this time, as shown in FIG. 4C, the clock waveforms of the clock terminals C of the flip-flop groups 6-8 and the clock terminals C of the synchronization flip-flops 4c-4d are the cell delay and wiring delay of the clock buffers 3a-3e. Thus, a delay of time d1 occurs from the waveform of the clock signal input to the clock input terminal 2.

  Next, as shown in FIG. 4D, after the operation of the power supply voltage and the clock signal is stabilized, the logic level of the asynchronous reset signal to be input to the asynchronous reset terminals R of the flip-flop groups 6 to 8 is set to the High state. As a result, the reset release signal is input to the asynchronous reset input terminal 1.

  At this time, since the asynchronous reset input terminal 1 is connected to the data terminal D of the synchronization flip-flop 4c, the reset release signal corresponding to the logic level in the High state is applied to the clock terminal C of the synchronization flip-flop 4c. Synchronization is performed so as to synchronize with the operation timing of the rising edge of the input clock signal. Here, as shown in FIG. 4D, at the same time as the rising edge of the third clock signal supplied to the synchronization flip-flop 4c (time delayed by time d1 from time t3), the asynchronous reset signal When reset is released with the logic level set to the high state, the T1 waveform output from the output terminal Q of the synchronization flip-flop 4c is a very short period as shown in FIG. Is then synchronized to synchronize with the operation timing of the rising edge e1 of the fourth clock signal (time d1 delayed from time t4). Since the metastable at this time is not propagated to the asynchronous reset terminals R of the flip-flop groups 6 to 8, the next-stage synchronization flip-flop 4d synchronizes again with the clock signal.

  Next, the output waveform from the second-stage synchronization flip-flop 4d and the output waveform of the asynchronous reset input terminal 1 are input to the AND gate 10, and a logical operation is performed to obtain the logical product (AND) of the logical levels of both waveforms. As a result, as shown in FIG. 4 (f), the output waveform of the synchronous reset cancellation circuit 9 (output waveform of the AND gate 10) T2 is the rising edge e2 of the fifth clock signal shown in FIG. 4 (c). A reset release signal synchronized with the operation timing (time delayed by time d1 from time t5) is generated.

  In the case of the configuration of this embodiment, if reset release is performed before the logic level of the output waveform from the output terminal Q of the synchronization flip-flop 4d is determined to be in the low state, the asynchronous reset terminals of the flip-flop groups 6 to 8 Although it is conceivable that the operation of R becomes indefinite and causes a malfunction, this embodiment improves this point as described below.

  The reset release signal at the output terminal D of the synchronous reset release circuit 9 is the cell delay of the synchronization flip-flop 4d with respect to the operation timing of the rising edge e2 of the fifth clock signal (time delayed by time d1 from time t5). A delay is caused by d2, which is the sum of the cell delays of the AND gate 10. The waveform of the asynchronous reset terminal R is further delayed from the output terminal of the synchronous reset cancellation circuit 9 due to the cell delay and the wiring delay of the reset buffers 5a to 5d, and the delay time is substantially the same as d1 described above. .

  Here, consider a case where the delay between the synchronous reset cancellation circuit 9 and the asynchronous reset terminals R of the flip-flop groups 6 to 8 varies as a result of the placement and routing design process.

  For example, the waveform of the asynchronous reset terminal R of the flip-flop group 6 is shown in FIG. 4G, the waveform of the asynchronous reset terminal R of the flip-flop group 7 is FIG. Even if the delay times vary as d3, d4, and d5 as shown in FIG. 4 (i), the operation timing (3) of the rising edge e3 of the sixth clock signal shown in FIG. If the reset release signal arrives sufficiently before the time t1 delayed from the time t6), the flip-flop groups 6 to 8 are simultaneously released from the reset at the operation timing of the rising edge e3 of the clock signal, and FIG. ) Will be output.

  That is, in this embodiment, in the place and route design process, the delay time from the output of the synchronous reset cancellation circuit 9 to the asynchronous reset terminal R of the flip-flop groups 6 to 8 is sufficiently smaller than one cycle of the clock signal. If the tree-like placement and routing of the reset buffers 5a to 5d is designed, the flip-flop can be prevented from malfunctioning at any timing as in the case of the first embodiment.

  FIG. 5 is a block diagram of a solid-state imaging device using the semiconductor device according to this embodiment. The present embodiment is an imaging system including an oscillator 21, a pulse generator 22 using the above-described semiconductor device, a solid-state imaging device 26, an analog-digital conversion device 27, and a digital signal processing device 28. The device 22 is a semiconductor device including the above-described synchronous reset cancellation circuit 23, and the above-described frequency dividing circuit 24 and pulse generation circuit 25 having the flip-flop group to be initialized. This imaging system is used for a digital camera, for example.

  Next, the operation of this embodiment will be described with reference to FIG.

  First, the clock 32 generated by the oscillator 21 is input to the pulse generator 22 and distributed to the frequency divider 24 and the pulse generator 25. The frequency dividing circuit 24 and the pulse generating circuit 25 have a plurality of flip-flops, and the clock 32 from the oscillator 21 is input to the clock input terminal of each flip-flop. The output of the flip-flop constituting the pulse generation circuit 25 is input as a drive pulse 34 to the solid-state imaging device 26 and as an AD clock 35 to an analog-digital conversion device 27, respectively. The solid-state imaging device 26 operates by inputting the drive pulse 34 and outputs an analog signal 36. The analog signal 34 is input to an analog-digital converter 27 and is sequentially converted into a digital signal 37 by an AD clock 35. The digital signal 37 is taken into the digital signal processor 28 using the frequency-divided clock 33 output from the frequency-dividing circuit as a trigger.

  The pulse generator 22 is initialized by a reset signal 30 that is asynchronous with the clock 32 from the oscillator 21. The internal reset signal 31 output from the synchronous reset cancellation circuit 23 is input to the asynchronous reset terminal of the flip-flop included in the pulse generation circuit 25 and the frequency dividing circuit 24. The internal reset signal 31 functions as an asynchronous reset signal at the time of resetting by the synchronous reset canceling circuit 23 and is synchronized with the clock 32 from the oscillator 21 at the time of reset canceling, similarly to the output signal of the synchronous reset canceling circuit of the above-described embodiment. Therefore, the pulse generation circuit 25 and the frequency dividing circuit 24 can be prevented from malfunctioning regardless of the timing at which the reset release signal is input to the reset signal 30. When the pulse generator 22 is cold-started, the logic levels of the drive pulse 34, AD clock 35, and frequency-divided clock 33 are low until a reset release signal asynchronous with the clock 32 is input as the reset signal 30. Since the state is fixed, malfunction of the solid-state imaging device 26, the analog-digital conversion device 27, and the digital signal processing device 28 can be prevented.

1 is a block diagram showing a configuration of a semiconductor device according to a first example of the present invention. 2 is a timing chart for explaining the operation of the semiconductor device shown in FIG. 1. It is a block diagram which shows the structure of the semiconductor device which concerns on 2nd Example of this invention. 3 is a timing chart for explaining the operation of the semiconductor device shown in FIG. 2. It is a block diagram which shows the structure of the solid-state imaging device using the semiconductor device which concerns on 3rd Example of this invention. It is a block diagram which shows the structure of the semiconductor device of a prior art example. 7 is a timing chart illustrating operation of the semiconductor device illustrated in FIG. 6.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Asynchronous reset input terminal 2 Clock input terminal 3a, 3b, 3c, 3d, 3e Clock buffer 4a, 4b, 4c, 4d Synchronization flip-flop 5a, 5b, 5c, 5d Reset buffer 6, 7, 8 Flip-flop group 9 Synchronization Reset release circuit 10 AND gate 21 Oscillator 22 Pulse generator 23 Synchronous reset release circuit 24 Frequency divider 25 Pulse generator 26 Solid-state imaging device 27 Analog-digital converter 28 Digital signal processor 30 Reset signal 31 Internal reset signal 32 Clock 33 Frequency division clock 34 Drive pulse 35 AD clock 36 Analog signal 37 Digital signal 101, 102 Synchronization flip-flops 103, 104, 105 Synchronous reset circuits 106A, 106B, 106C using AND gates Data input terminals

Claims (6)

In a semiconductor device having an asynchronous reset terminal and having a plurality of flip-flops that operate in synchronization with the operation timing of an input clock signal,
A clock input terminal to which the clock signal is input;
An asynchronous reset input terminal to which a reset start signal and a reset release signal that form a reset signal asynchronous with the operation timing of the clock signal are input;
Connected between the asynchronous reset input terminal and the asynchronous reset terminals of the plurality of flip-flops, and when the reset release signal is input from the asynchronous reset input terminal, the reset release operation timing by the reset release signal is set. Synchronous reset cancellation means for generating a synchronous reset cancellation signal in synchronization with the operation timing of the clock signal input to the plurality of flip-flops to be initialized from the clock input terminal,
Means for connecting the synchronous reset cancellation means and the asynchronous reset terminals of the plurality of flip-flops, and distributing a signal from the synchronous reset cancellation means to the asynchronous reset terminals of the plurality of flip-flops to be initialized; Have
For the plurality of flip-flops to be initialized, the reset operation is started asynchronously with the operation timing of the clock signal based on the reset start signal, and the operation timing of the clock signal based on the synchronous reset release signal A semiconductor device, wherein the reset operation is released in synchronization. The synchronous reset cancellation means
A synchronization flip-flop having an asynchronous reset terminal to which the reset signal is input, a clock terminal to which the clock signal is input, and a data terminal to which the reset signal is input;
The synchronous reset cancellation means
When the reset start signal is input, an asynchronous reset start signal that is asynchronous with the operation timing of the clock signal is generated, and when the reset release signal is input, the reset release operation timing by the reset release signal Is synchronized with the operation timing of the clock signal input to the clock terminal to generate a synchronous reset release signal,
A reset operation is started asynchronously with the operation timing of the clock signal based on the asynchronous reset start signal for the plurality of flip-flops to be initialized, and the operation timing of the clock signal based on the synchronous reset release signal The semiconductor device according to claim 1, wherein the reset operation is released in synchronization with the signal.   The semiconductor device according to claim 2, wherein the synchronization reset cancellation unit includes a plurality of synchronization flip-flops. The synchronous reset cancellation means
A plurality of synchronization flip-flops having at least a synchronization flip-flop having a clock terminal to which the clock signal is input and a data terminal to which the reset signal is input;
A first input terminal to which the reset signal is input, and a second input terminal to which the outputs of the plurality of synchronization flip-flops are input, and a logical operation on the inputs of the first and second input terminals A first output obtained by transitioning a logic level to one of High and Low asynchronously with the operation timing of the clock signal, and the logic level in synchronization with the operation timing of the clock signal. A combinational logic circuit that generates a second output that is returned to the other state of High and Low, and
The reset operation is started asynchronously with the operation timing of the clock signal based on the first output for the plurality of flip-flops to be initialized, and the operation timing of the clock signal based on the second output The semiconductor device according to claim 1, wherein the reset operation is released in synchronization with the signal.   5. A solid-state imaging device driven by a driving pulse generated by the semiconductor device according to claim 1.   5. A solid-state imaging device driven by a driving pulse generated by the semiconductor device according to claim 1, means for converting an analog signal output from the solid-state imaging device into a digital signal, and the digital signal And a means for processing the camera.