JP3785353B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a lithography technique for patterning in a self-aligned manner with respect to a base pattern.
[0002]
[Prior art]
Among microfabrication techniques, a technique for improving the overlay accuracy between masks is one of the most important techniques. Generally, the overlay accuracy needs to be about 20% of the minimum dimension, and it is necessary to improve the overlay accuracy at the same time as miniaturization progresses.
[0003]
Therefore, in the known alignment method, there are a reduction projection exposure apparatus which is currently used as an exposure apparatus, a method using a television image, a method using a laser beam, and the like. For example, relative alignment between a mask and a wafer is an important element for improving performance. In particular, in recent alignment in an exposure apparatus, in order to achieve high integration of semiconductor elements, a device having alignment accuracy of, for example, submicron or less is required. In many alignment apparatuses, a so-called alignment pattern (also referred to as an “alignment mark”) for alignment is provided on a so-called scribe line on the mask and wafer surface, and is obtained from the alignment mark on the mask and the alignment mark on the wafer. The position information is used to align the mask and the wafer.
[0004]
[Problems to be solved by the invention]
However, the conventional method for manufacturing a semiconductor device using the alignment method using the alignment mark between the mask and the wafer has the following problems. That is, in order to increase the alignment accuracy on the base substrate, it is necessary to improve the alignment optical system and the resolution of the detection device. However, it is still not sufficient, and as shown in FIG. 12A, an attempt is made to pattern the resist pattern 3 to fill the width between the upper surfaces 1 facing each other in the recess 2 surrounded by the upper surface 1 of the step. When the upper surface 1 is very fine, an alignment shift as shown in FIG. 12 (b) occurs.
[0005]
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device using a lithography technique capable of patterning without causing misalignment even in the case of a fine base pattern.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a first invention is a method for manufacturing a semiconductor device comprising a step of forming a resist pattern in close contact with a side wall of a step on a lower surface of the step in a base having a step formed on the surface. The step of forming the resist pattern includes: a resist coating step for applying a resist flatly on the surface of the base; a pretreatment step for reducing the thickness of the applied resist; and An exposure process in which overlap exposure is performed using a mask having an exposure pattern or a light-shielding pattern formed so as to overlap with the upper surface of the step at a portion in close contact with the side wall of the step, and the film thickness of the resist by subsequent development Is characterized by including a thinning process for making the film thinner and a developing process.
[0007]
According to the above configuration, in the pretreatment step, pretreatment for reducing the thickness of the applied resist is performed, and before development, in the thinning step, the resist film thickness is reduced by subsequent development. Thus, a thinning process is performed. At that time, the resist is thinned to the upper surface of the underlying step, so that the resist is left in a self-aligned manner only on the lower surface of the underlying step. Therefore, by performing overlap exposure so as to overlap the upper surface in the exposure step, the resist pattern that is in close contact with the side wall of the step at the position where the overlap exposure is performed in the development step is performed on the lower surface. Formed on top.
[0008]
In one embodiment, in the method of manufacturing a semiconductor device according to the first invention, a negative resist is applied in the resist coating step, and the exposure is performed on the surface of the negative resist in the pretreatment step. Then, a chemical solution that deactivates the acid generated in the negative resist is applied, and in the thinning step, the chemical solution is evenly diffused to the vicinity of the upper surface of the base step in the negative resist.
[0009]
According to this embodiment, even the negative resist in the portion exposed in the exposure step is thinned to the upper surface of the base step in the development step. Therefore, a resist pattern that has the shape of an exposure pattern and is in close contact with the side wall of the step is formed only on the lower surface of the step, where the overlap exposure is performed. The chemical solution may be applied after the exposure step.
[0010]
In one embodiment, in the method of manufacturing a semiconductor device according to the first aspect of the invention, a positive resist is applied in the resist coating step, and the positive resist is applied to the surface of the positive resist in the pretreatment step. A chemical solution that causes a deprotection reaction is applied to the mold resist, and in the thinning step, the chemical solution is evenly diffused to the vicinity of the upper surface of the base step in the positive resist.
[0011]
According to this embodiment, even a portion of the positive resist that has not been exposed in the exposure process is thinned to the upper surface of the base step in the development process. Therefore, a resist pattern having a light shielding pattern shape and in close contact with the side wall of the step is formed only on the lower surface of the step at the location where the overlap exposure is performed. The chemical solution may be applied after the exposure step.
[0012]
By the way, in the said 1st invention, the process of diffusing the said chemical | medical solution to the upper surface of the level | step difference of a base | substrate is set as the "thinning process." Originally, “resist thinning” should mean “diffusion of the chemical solution” and “removal of the resist in the region where the chemical solution is diffused”, but the latter is performed simultaneously with patterning by the development process. Only the former is included in the thinning process.
[0013]
According to a second aspect of the present invention, there is provided a semiconductor device manufacturing method including a step of forming a resist pattern in close contact with a side wall of the step on a lower surface of the step in a base having a step formed on the surface. The step of forming a resist is a resist coating step of applying a positive resist flatly on the underlying surface, and a light shielding formed so as to overlap the upper surface of the step at a portion where the resist pattern is in close contact with the side wall of the step. A first exposure step of performing overlap exposure using a mask having a pattern, a second exposure step of exposing the entire surface of the positive resist up to the vicinity of the upper surface of the step, and a development step. Yes.
[0014]
According to the above configuration, the portion of the positive resist that has not been exposed in the first exposure process is exposed to the vicinity of the upper surface of the base step in the second exposure process. Therefore, in the development process, the positive resist in the portion not exposed in the first exposure process is thinned to the upper surface. Therefore, a resist pattern having a light-shielding pattern shape and in close contact with the side wall of the step is formed only on the lower surface of the step in the base at the place where the overlap exposure is performed. Any of the first exposure step and the second exposure step may be performed first.
[0015]
According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method including a step of forming a resist pattern only on the upper surface or only the lower surface of the step in the base having a step formed on the surface, wherein the resist pattern is formed. In the process, the film thickness on the upper surface is any one of the X values obtained by the following equation (5) on the surface of the base, and the film thickness on the lower surface is obtained by the following equation (6). It includes a resist coating process for coating a resist so as to have any one of the Y values, an exposure process, and a development process.
X = {(exposure light wavelength) / 4} / (refractive index of resist) · (2n−1) (5)
Y = {(exposure light wavelength) / 4} / (refractive index of resist) · 2 m (6)
Where n and m are natural numbers
[0016]
According to the above configuration, the film thickness on the lower surface of the step in the base is the film thickness with the highest resist sensitivity, and the film thickness on the upper surface in the step is the film thickness with the lowest resist sensitivity. The resist is applied so that Therefore, only the resist on the lower surface having the highest sensitivity is exposed by the exposure process. As a result, when a negative resist is used, a resist pattern in close contact with the side wall of the step is formed in a self-aligned manner only on the lower surface. When a positive resist is used, a resist pattern is formed in a self-aligned manner only on the upper surface.
[0017]
According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method including a step of forming a resist pattern only on the upper surface or only the lower surface of the step in the base having a step formed on the surface, wherein the resist pattern is formed. In the process, the film thickness on the upper surface is any one of the X values obtained by the following equation (7) on the surface of the base, and the film thickness on the lower surface is obtained by the following equation (8). It includes a resist coating process for coating a resist so as to have any one of the Y values, an exposure process, and a development process.
X = {(exposure light wavelength) / 4} / (refractive index of resist) · 2n (7)
Y = {(exposure light wavelength) / 4} / (refractive index of resist) · (2m−1) (8)
Where n and m are natural numbers
[0018]
According to the above configuration, the film thickness on the upper surface of the base step is the highest film thickness of the resist, and the film thickness on the lower surface of the step is the lowest resist sensitivity. The resist is applied so as to have a film thickness. Therefore, only the resist on the upper surface having the highest sensitivity is exposed by the exposure process. As a result, when a negative resist is used, a resist pattern is formed in a self-aligned manner only on the upper surface. When a positive resist is used, a resist pattern in close contact with the side wall of the step is formed in a self-aligned manner only on the lower surface.
[0019]
In one embodiment, in the method of manufacturing a semiconductor device according to any one of the third invention and the fourth invention, each of the values of X and Y is ± Z (Z = {(exposure light wavelength)). / 8} / (the refractive index of the resist)).
[0020]
According to this embodiment, an error of 1/2 of the difference between the film thickness with the highest resist sensitivity and the film thickness with the lowest resist is allowed in the film thickness on the upper and lower surfaces of the step. Therefore, it becomes easy to control the film thickness at the time of applying the resist, and a resist pattern can be easily formed in a self-aligning manner.
[0021]
According to a fifth aspect of the present invention, there is provided a semiconductor device manufacturing method including a step of forming a resist pattern only on the upper surface or only the lower surface of the step in the base having a step formed on the surface, wherein the resist pattern is formed. The step of performing includes a resist coating step of applying a resist to the surface of the base, an exposure step of performing exposure while focusing on either the upper surface or the lower surface, and a developing step. Yes.
[0022]
According to the above configuration, the resist applied on the base on which the step is formed is exposed while focusing on either the upper surface or the lower surface of the step. Therefore, when a negative resist is used and the focus is focused on the upper surface of the base, a resist pattern is formed in a self-aligned manner only on the upper surface. A resist pattern is formed in a self-aligned manner only on the lower surface. In addition, when a positive resist is used to focus on the upper surface of the base, a resist pattern is formed in a self-aligned manner only on the lower surface, whereas when a focus is applied to the lower surface, A resist pattern is formed in a self-aligning manner only on the upper surface.
[0023]
According to a sixth aspect of the present invention, there is provided a semiconductor device manufacturing method including a step of forming a resist pattern in close contact with a side wall of the step on a lower surface of the step in a base having a step formed on the surface. The step of forming includes: a resist coating step for applying a resist to the surface of the base; an exposure step for exposing the base surface to light by applying light from an oblique direction; and a development step. It is said.
[0024]
According to the above configuration, exposure is performed by irradiating the resist applied on the base on which the step is formed with light from an oblique direction with respect to the surface of the base. As a result, there is a portion on the lower surface of the step that is shaded by the side wall of the step and is not exposed to light. Therefore, by using a positive resist, a resist pattern in close contact with the side wall of the step is formed on the lower surface.
[0025]
In one embodiment, in the method of manufacturing a semiconductor device according to the sixth aspect of the invention, in the exposure step, exposure is performed by applying light from a plurality of directions.
[0026]
According to this embodiment, for example, two directions opposite to the side wall of the step are included in a plurality of directions to which the exposure light is applied, and if a positive resist is used, two side walls opposed to each other are used. In the center portion on the lower surface sandwiched between the two, there is a portion that is not exposed to the shadows of the two side walls. Therefore, in this case, a resist pattern in which both ends are in close contact with the side wall is formed at the center on the lower surface by development.
[0027]
In one embodiment, in the method of manufacturing a semiconductor device according to the sixth aspect of the invention, in the exposure process in which exposure is performed by applying light from a plurality of oblique directions, the resist is not patterned by a single exposure. Exposure is performed with light intensity.
[0028]
According to this embodiment, for example, when the exposure is performed from two opposite directions with respect to the side wall of the step, and the positive resist is used, the two side walls on the lower surface sandwiched between the two corresponding side walls. A portion of the side wall is shadowed by this side wall and is exposed only once. Therefore, in this case, a resist pattern in close contact with the two side walls on the lower surface is formed by development.
[0029]
The seventh invention is a method of manufacturing a semiconductor device having a step of forming a resist pattern only on the lower surface of the step in the base having a step formed on the surface, the step of forming the resist pattern comprising A resist coating step for applying a negative resist flatly on the surface of the base; and a pretreatment step for applying a chemical solution that deactivates the acid generated in the negative resist by subsequent exposure to the negative resist surface. And an exposure process for exposing the entire surface of the negative resist, and the chemical solution is uniformly diffused to the vicinity of the upper surface of the base step in the negative resist, and the film thickness of the negative resist is developed by subsequent development. Is characterized by including a thinning process for making the film thinner and a developing process.
[0030]
According to the above configuration, the chemical solution for deactivating the acid generated in the negative resist applied in the pretreatment step is exposed to the entire surface, and then in the thinning step, the step of the base in the negative resist is performed. Evenly diffuses to the vicinity of the upper surface. Accordingly, the portion of the negative resist in which the acid generated by the exposure is deactivated is dissolved and removed by development, and the film thickness of the negative resist is reduced to the upper surface of the step. Thus, the negative resist is left on the lower surface of the step in the base, and a resist pattern is formed in a self-aligned manner only on the lower surface.
[0031]
Further, an eighth invention is a method of manufacturing a semiconductor device having a step of forming a resist pattern only on the lower surface of the step in the base having a step formed on the surface, the step of forming the resist pattern comprising A resist coating step for flatly applying a positive resist on the surface of the base, a pretreatment step for applying a chemical solution causing a deprotection reaction to the positive resist on the surface of the positive resist, and the chemical solution Including a thinning step and a developing step in which the film thickness of the positive resist is reduced by subsequent development. It is characterized by.
[0032]
According to the above configuration, the chemical solution that causes the deprotection reaction to the positive resist applied in the pretreatment process is evenly diffused to the vicinity of the upper surface of the base step in the positive resist in the thinning process. . Accordingly, the portion of the positive resist that has undergone the deprotection reaction is dissolved and removed by development, and the film thickness of the positive resist is reduced to the upper surface of the step. Thus, the positive resist is left on the lower surface of the step in the base, and a resist pattern is formed in a self-aligned manner only on the lower surface.
[0033]
The ninth invention is a method of manufacturing a semiconductor device having a step of forming a resist pattern only on the lower surface of the step in the base having a step formed on the surface, the step of forming the resist pattern comprising And a resist coating process for flatly applying a positive resist on the surface of the base, an exposure process for exposing the entire surface of the positive resist up to the upper surface of the step of the base, and a development process. Yes.
[0034]
According to the above configuration, in the exposure step, the entire surface is exposed to the vicinity of the upper surface of the base step in the applied positive resist. Therefore, the exposed portion of the positive resist is dissolved and removed by development, and the thickness of the positive resist is reduced to the upper surface. Thus, the positive resist is left on the lower surface of the step in the base, and a resist pattern is formed in a self-aligned manner only on the lower surface.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
<First embodiment>
FIG. 1 is a diagram showing the structure of a transistor formed partway through the semiconductor device manufacturing method of the present embodiment. 1A is a cross-sectional view, and FIG. 1B is a plan view. Here, FIG. 1A is a cross-sectional view taken along the line AA ′ in FIG.
[0036]
In the transistor shown in FIG. 1, an insulating film 12, a polycrystalline silicon film 13 having a thickness of about 0.25 μm, and a silicon oxide film 14 having a thickness of about 0.20 μm are deposited on a silicon substrate 11. Next, a resist (not shown) is patterned using a lithography technique, and after processing the silicon oxide film 14 using the resist as a mask, the resist is removed. Next, using the patterned silicon oxide film 14 as a mask, the polycrystalline silicon film 13 and the insulating film 12 are processed to form a gate electrode and a gate oxide film, and then the silicon nitride film 15 is deposited to a thickness of about 50 nm. Deposit on the entire surface. In this way, a step formed by the convex portion 16 covered with the silicon nitride film 15 is formed. In the following, for convenience of explanation, a region below the upper surface of the convex portion 16 formed by the sidewall of the convex portion 16 and the silicon nitride film 15 surrounded by the convex portion 16 is referred to as the concave portion 17. I will say.
[0037]
Here, the polycrystalline silicon film 13 as the gate electrode is processed to have a length of 0.24 μm and a width of 2.5 μm. Further, the height of the convex portion 16 is 0.45 μm. Hereinafter, a method of patterning in a self-aligned manner only in the recesses 17 due to the above steps will be described with respect to the state shown in FIG. In FIG. 2 used at that time, the silicon substrate 11 is omitted, and the insulating film (gate oxide film) 12, the polycrystalline silicon film (gate electrode) 13, the silicon oxide film 14 and the silicon nitride film 15 are not distinguished. These are representatively represented only by the outline of the silicon nitride film 15 located in the outermost layer. 2A to 2E, the upper stage is a cross-sectional view, and the lower stage is a plan view.
[0038]
In the present embodiment, as shown in FIG. 2, by applying a negative resist on a stepped base, applying an upper antireflection film containing a basic compound thereon, exposing and developing, In this method, the resist is patterned only in the recesses 17. Hereinafter, description will be made sequentially with reference to FIG.
[0039]
First, polyvinyl phenol having a t-butoxycarbonyl group introduced in 30% of the side chain as a base resin, 100 parts of this base resin (parts by weight, the same applies hereinafter), 20 parts of methylated methylol melamine as a crosslinking agent, Then, 5 parts of triphenylsulfonium triflate as a photoacid generator is dissolved in 400 parts of ethyl lactate as a solvent to form a negative resist. Then, as shown in FIG. 2A, the negative resist 21 is spin-coated on the base on which the convex portions 16 are formed so that the surface becomes flat at a low rotation of 3000 rpm or less.
[0040]
When the resist 21 is applied, the resist 21 is applied more flatly as it has a lower viscosity (5 cp or less) and is not affected by the underlying step. In other words, low viscosity and low-speed rotation can suppress the occurrence of striation (coating unevenness that occurs as a comet has a tail extending outward from the center side of the wafer) and can be applied very flatly. . Furthermore, the thicker the resist 21 is applied, the more flattened it is without being influenced by the underlying step. However, if it is still difficult to flatten the surface of the resist 21 due to an excessively large base level difference or unevenness, the unevenness of the base itself can be obtained by inserting a dummy pattern in the base. Must be made as uniform as possible. Next, the resist 21 is pre-baked, and the temperature of the pre-bake is preferably about 110 ° C. in consideration of uniformity and rate stability in the subsequent thin film forming step. However, it is possible even at a temperature of 80 ° C to 130 ° C. Even when other resists are used, a temperature higher than the pre-baking temperature used in normal photolithography is preferable.
[0041]
Next, as a pretreatment step for reducing the resist film thickness in the development step, as shown in FIG. 2 (b), the upper antireflection film 22 containing the basic compound is made as uniform as possible without causing uneven coating. Apply to. In that case, if uneven coating occurs, uneven diffusion occurs when the base is diffused later. Therefore, the coating is uniformly performed by spin coating at a high rotation speed of 5000 rpm or more as much as possible.
[0042]
The upper antireflection film 22 is suitably TSP9A (manufactured by Tokyo Ohka Kogyo Co., Ltd.) containing 5% by weight of a basic compound N-methylpyrrolidone (NMP). However, the NMP content may be 2 to 15% by weight. In addition, as the upper antireflection film 22, Aquatar manufactured by Clariant Co., Ltd. can be used. The basic compound contained in the upper antireflection film 22 may be aromatic amines, aliphatic amines, isopropylamine, alkylamines, dichloroamine, anison, and derivatives thereof. .
[0043]
By the way, the film thickness of the resist is usually smaller than the film thickness after application of about 5% by the pre-bake or the like. Also, in the developing process, the film thickness is usually thinner than 5% to 10% after coating. However, “reducing the resist film thickness” means not reducing the film thickness as described above but actively reducing the film thickness of the resist more than the film thickness after coating. In this way, the resist is left only in the concave portion 17 until the resist on the convex portion 16 disappears or is made thinner than the height of the convex portion 16.
[0044]
In this case, as described above, by flattening the surface of the resist 21, the resist 21 can be left thick in the concave portion 17 even if the thickness of the resist 21 is reduced to the upper surface of the convex portion 16. In addition, a resist pattern can be formed in a wide area in the recess 17. Further, by leaving the resist 21 only in the concave portion 17, it is possible to reliably form a resist pattern only in the concave portion 17 in a subsequent exposure step without considering the influence of misalignment. It becomes.
[0045]
Next, as shown in FIG. 2C, using a KrF excimer laser (wavelength 248 nm) stepper, the exposure amount is 580 J / m, the numerical aperture (NA) is 0.6, and the coherency (σ) is 0.65. Exposure is performed under the following conditions. However, 23 is a laser beam and 24 is a mask. Here, the exposure is performed by overlapping the portions of the resist pattern that are desired to adhere. That is, the exposure pattern 25 is closer to the portion than the resist pattern 29 (see FIG. 2E) to be finally formed (in this case, both ends of the resist pattern 29 are in close contact with the convex portion 16. Therefore, the resist pattern 29 is set to have a size of about 0.05 μm. Thus, the portion of the exposure pattern 25 to be in close contact with the convex portion 16 is overlapped. As a result, the exposure can be performed even if an alignment deviation occurs in the portion to be closely adhered in the exposure pattern 25, and the influence of the alignment deviation at the time of exposure can be prevented.
[0046]
In order to pattern a pattern having a length of 0.24 μm into a better shape during the exposure, the exposure amount is 580 J / m, the numerical aperture (NA) is 0.6, and the coherency (σ) is 0.65. The condition of the degree is the best. The above conditions depend on the exposure apparatus. Further, the place where the overlap exposure is performed and the overlap amount may be within a range in which misalignment can be considered.
[0047]
Next, PEB (post-exposure baking) is performed on the upper antireflection film 22 containing the basic compound and the resist 21 under the conditions of 130 ° C. and 90 seconds to thin the resist 21. At that time, due to the effect of the chemical solution applied in the pretreatment, the basic compound in the upper antireflection film 22 is made higher than the upper surface of the convex portion 16 in the resist 21 (resist as shown in FIG. 2D). (Upper layer) 26 is diffused. By doing so, the diffused basic compound deactivates the acid generated in the exposed portion (exposed portion upper layer) 27 in the resist upper layer 26 by the exposure. As a result, crosslinking of the resist 21 in the exposed portion upper layer 27 where the acid has been deactivated is suppressed. However, the basic compound is not diffused in the exposed portion lower layer 28 below the exposed portion upper layer 27 in the exposed region, and the acid generated by the exposure is not deactivated. Therefore, cross-linking of the resist 21 in the exposed portion lower layer 28 is not suppressed, and cross-linking occurs.
[0048]
Next, development is performed for 60 seconds with a developing solution (for example, 2.38% TMAH (tetramethylammonium hydroxide) aqueous solution: NMD-W manufactured by Tokyo Ohka Kogyo Co., Ltd.). By this development, the resist 21 that is not crosslinked during the exposure (that is, the resist 21 other than the exposed portion lower layer 28) is dissolved in the developer and removed. In this way, as shown in FIG. 2 (e), only the resist 21 of the exposed portion lower layer 28 remains and a resist pattern 29 is formed.
[0049]
At that time, the resist pattern 29 is thinned by the effect of the chemical applied by the pretreatment of FIG. Specifically, the resist 21 of the exposed portion upper layer 27 is affected by an increase in the amount of film reduction. As a result, the exposed portion upper layer 27 dissolves simultaneously with the patterning of the resist pattern 29 during the developing solution treatment. Next, a post-bake (bake after developing solution treatment) is performed at 110 ° C. for 60 seconds.
[0050]
As described above, overlap exposure is performed in order to prevent the influence of misalignment during the exposure. Therefore, the exposure pattern 25 is set to be longer at both ends than the length of the resist pattern 29 to be finally formed. As a result, the exposed portion upper layer 27 is applied to the upper surface of the convex portion 16 at both ends of the exposed pattern 25. However, since the exposed portion upper layer 27 is removed by the above-described thinning, portions extending from both ends of the resist pattern 29 onto the convex portion 16 are removed, the desired length is provided, and both ends are on the side walls of the convex portion 16. The resist pattern 29 that is in close contact is obtained. In this case, the thinning of the resist pattern 29 can be controlled by the alkali concentration in the upper antireflection film 22, the temperature / time of the PEB, and the like.
[0051]
As described above, when the resist pattern 29 in which both ends are in close contact with the convex portions 16 facing each other is formed in the concave portion 17 surrounded by the convex portions 16 as follows. That is, a negative resist 21 is applied to the base on which the convex portions 16 are formed so that the surface is flat, prebaked, and the upper antireflection film 22 containing a basic compound is uniformly applied. Then, exposure is performed using a mask 24 having an exposure pattern 25 set to be about 0.05 μm longer at both ends than the length of a desired resist pattern 29. Thus, overlap exposure is performed to prevent the influence of misalignment during exposure.
[0052]
Next, PEB is performed to diffuse the basic compound in the upper antireflection film 22 into the resist upper layer 26 that is the upper layer of the convex portion 16 in the resist 21. In this way, the diffused basic compound deactivates the acid generated in the exposed portion upper layer 27 by the above exposure and suppresses the crosslinking of the resist 21. Then, by developing, the resist 21 other than the exposed portion lower layer 28 is dissolved and removed to form a resist pattern 29.
[0053]
In that case,
(1) By performing overlap exposure, the influence of misalignment of the exposure pattern 25 is prevented, and a resist pattern 29 in which both ends are in close contact with the side wall of the convex portion 16 can be formed.
(2) Cross-linking due to exposure of the exposed portion upper layer 27 is suppressed by the above-described thinning and removed by development. As a result of the overlap exposure dew of (1), portions extending from both ends of the resist pattern 29 onto the convex portion 16 are removed. The resist pattern 29 having a desired length can be formed.
[0054]
In this way, as shown in FIG. 2 (e), it is possible to pattern a resist pattern 29 in which only necessary portions are in close contact with the convex portion 16 and there is no misalignment at those portions. Further, since the height of the resist pattern 29 is reduced by thinning the film, and the bottom surface of the resist pattern 29 is not only in close contact with the base, but also the side surfaces are in close contact with each other, the resist pattern 29 is not deformed or collapsed. It can be prevented. Further, since it is not necessary to provide an alignment margin for the base pattern, the semiconductor device finally formed can be miniaturized.
[0055]
In the pretreatment step of FIG. 2B, the upper antireflection film 22 is applied on the positive resist 21, but the upper antireflection film 22 is not limited thereto. For example, any material that can be applied to the surface such as CEL (contrast enhanced layer) and contains a basic compound, or a material that can deactivate the acid generated in the resist 21 by exposure may be used. That is, as a substance capable of deactivating the acid, any substance having a PH value of (14−X) may be used as long as the strength of the generated acid is “X”. However, the PH value can be reduced even if there is an error of about ± 10%. The basic compound may be applied even after exposure.
[0056]
<Second Embodiment>
FIG. 3 shows a method for patterning a resist in a concave portion of a base having a convex portion in the present embodiment. In addition, the base | substrate which has a convex part is the same as the base | substrate shown in FIG. 1 in the said 1st Embodiment. Also, in FIG. 3, only the outline of the silicon nitride film 15 located in the outermost layer is representatively expressed, and the upper stage is a sectional view and the lower stage is a plan view.
[0057]
In the first embodiment, a negative resist is used as the resist. However, in the present embodiment, as shown in FIG. 3, a positive resist is applied to a ground with a step, and an acidic compound is formed thereon. The resist is patterned only in the recesses 17 by applying an upper antireflection film containing it, exposing it and developing it. In the following, description will be made sequentially with reference to FIG.
[0058]
First, as shown in FIG. 3A, a positive resist 31 is applied to the base on which the convex portions 16 are formed. Here, as the positive resist 31, a “Random copolymer of poly (poly (4-vinylphenol)” hydroxyl group is partially substituted with a tertiary butyl acetate group “t-butoxycarbonylmethoxy group” as a dissolution inhibiting group. pt-butoxycarbonylmethoxystyrene) and poly (4-vinylphenol) ”(BOCM-PVP) were used as resist polymers. As the polyvinylphenol, Maruzen Petrochemical PHM-C (Mw = 5100) was used. In this case, the introduction rate of the dissolution inhibiting group is 26 mol%. An onium salt “Triphenylsulphonium trifluoromethanesulphonate” (TPS-OTf) manufactured by Midori Chemical was used as the acid generator. As shown in FIG. 3A, a resist 31 is prepared by dissolving a 200: 1 mixture of BOCM-PVP and an onium salt in ethyl cellosolve acetate (ECA) at a concentration of 25 wt%. Spin coating is applied as in the case of the form. Then, as shown in FIG. 3B, the upper antireflection film 32 containing an acidic compound is spin-coated as uniformly as possible. The process of FIG. 3B is a pretreatment process for thinning the film in the development process.
[0059]
In that case, as in the case of the first embodiment described above, uneven application causes an influence when the acid is diffused later, so that the application is performed uniformly by applying as high a rotation as possible. The acidic compound in the upper antireflection film 32 is trifluoromethanesulfonic acid, which is suitably 5% by weight, but may be 2% by weight to 15% by weight. Further, the upper antireflection film 32 may be Aquatar manufactured by Clariant Corporation.
[0060]
Next, exposure is performed as shown in FIG. In addition, 33 is a laser beam and 34 is a mask. In this case, since the positive resist 31 is used as the resist, the exposure pattern of the mask 34 is opposite to that in FIG. 2C in the first embodiment, and the light transmission region / non-transmission region. Is reversed. Then, post-exposure baking (PEB), which is one step of the development process, is performed. The PEB thins the resist 31, and as shown in FIG. 3D, the acid in the upper antireflection film 32 applied as a pretreatment step diffuses to the resist 31 side. An upper layer (resist upper layer) 36 above the upper surface of the portion 16 causes a deprotection reaction. That is, the unexposed portion (unexposed portion upper layer) 37 included in the resist upper layer 36 also causes a deprotection reaction.
[0061]
Next, a developing solution treatment and a post-bake are performed in the development process. During this developer processing, the resist is thinned by the effect of the chemical applied in the pre-processing step. Specifically, the exposed region in the resist 31 and the region where the deprotection reaction has occurred in the unexposed portion (that is, the resist 31 other than the unexposed portion lower layer 28) are dissolved and removed in the developer in the same manner as the patterning. Thus, as shown in FIG. 3E, only the resist 31 of the unexposed portion lower layer 38 remains and a resist pattern 39 is formed. As a result, as a result of the overlap exposure, portions extending from the both ends of the resist pattern 39 onto the convex portion 16 can be removed, and the resist pattern 39 having a desired length is formed. In this case, the thinning of the resist 31 can be controlled by the acid concentration of the upper antireflection film 32, the temperature / time of the PEB, and the like. The strength of the acid contained in the upper antireflection film 32 is preferably the same as the acid generated during exposure.
[0062]
As described above, in the present embodiment, when the resist pattern 39 in which both ends are in close contact with the convex portions 16 facing each other is formed in the concave portion 17 surrounded by the convex portions 16 as follows. To. That is, a positive resist 31 is applied to the base on which the convex portions 16 are formed so that the surface is flat, and the upper antireflection film 32 containing an acidic compound is uniformly applied. Then, exposure is performed using a mask 34 having a light-shielding pattern 35 set to be about 0.05 μm longer at both ends than the length of a desired resist pattern 39. Thus, overlap exposure is performed to prevent the influence of misalignment during exposure.
[0063]
Next, the PEB is thinned to diffuse the acidic compound in the upper antireflection film 32 into the resist upper layer 36. Thus, a deprotection reaction is caused in the unexposed portion upper layer 37 by the diffused acidic compound. Then, by developing, the resist pattern 39 is formed by dissolving and removing the resist 31 other than the unexposed portion lower layer 38 where the deprotection reaction has not occurred.
[0064]
In that case, as in the case of the first embodiment, by performing the overlap exposure, the influence of misalignment of the light shielding pattern 35 is prevented, and the resist pattern 39 whose both ends are in close contact with the side wall of the convex portion 16 is formed. Can be formed. In addition, a deprotection reaction is caused by thinning the upper layer 37 of the unexposed portion and removed by development. As a result, portions extending from the both ends of the resist pattern 39 onto the convex portion 16 can be removed, and the resist pattern 39 having a desired length can be formed.
[0065]
In this way, as shown in FIG. 3E, only a necessary portion is brought into close contact with the convex portion 16 and a resist pattern 39 having no misalignment can be patterned. Further, since the height of the resist pattern 39 is reduced by the thinning of the film and the bottom surface of the resist pattern 39 is not only in close contact with the base, but also the side surfaces are in close contact with each other, the resist pattern 39 is not deformed or collapsed. It can be prevented.
[0066]
It should be noted that the object applied on the positive resist 32 is not the upper antireflection film 32, but is an object that is applied to the surface of the CEL or the like and that contains an acid, or that can decompose the resist 32 with an acid. If it is. In this case, the acid value is preferably the same strength as the acid generated in the resist 32 by exposure, and the PH value can be reduced even if there is an error of about ± 10%. The acidic compound may be applied after exposure.
[0067]
<Third Embodiment>
FIG. 4 shows a method for patterning a resist in a concave portion of a base having a convex portion in the present embodiment. In addition, the base | substrate which has a convex part is the same as the base | substrate shown in FIG. 1 in the said 1st Embodiment. Also, in FIG. 4, only the outline of the silicon nitride film 15 located in the outermost layer is representatively expressed, and the upper stage is a sectional view and the lower stage is a plan view.
[0068]
In the present embodiment, as in the first and second embodiments, the upper layer antireflection films 22 and 32 are not formed as a pre-processing step for thinning the resist, and the transmittance is applied to the stepped base. In this method, a low positive type resist is applied, and a region to be thinned is exposed to reduce the resist film thickness to perform patterning. Hereinafter, description will be made sequentially with reference to FIG.
[0069]
First, as shown in FIG. 4A, a dye-containing positive resist 41 (with a transmittance of 40% at a resist film thickness of 0.1 μm) is applied to the base on which the convex portions 16 are formed. In order to facilitate the subsequent thin film control, the transmittance of the resist 41 is preferably about 20% to 50% at a resist film thickness of 0.1 μm. Next, as shown in FIG. 4B, similarly to the case of the second embodiment, the light-shielding pattern 44 is set to be about 0.05 μm longer at both ends than the length of the desired resist pattern 47. Exposure is performed using a mask 43. Thus, overlap exposure is performed to prevent the influence of misalignment during exposure. Reference numeral 42 denotes a laser beam.
[0070]
Next, as shown in FIG. 4C, the entire coating region is exposed with an exposure amount that allows light to reach only the upper layer (resist upper layer) 45 above the upper surface of the convex portion 16 in the resist 41. At that time, a deprotection reaction occurs in the exposed resist upper layer 45. That is, an unexposed portion in the first overlap exposure included in the resist upper layer 45 is also exposed to cause a deprotection reaction. Further, since the resist 41 contains a dye and is coated thicker, it is easy to control the depth that light reaches upon exposure. That is, by adjusting the exposure amount at the second exposure, the transmittance of the resist 41, and the temperature of the PEB, the thinning of the resist 41 can be easily controlled at the next development.
[0071]
Next, by developing, an exposure area in the first or second exposure of the resist 41 (that is, the resist 21 other than the unexposed portion lower layer 46 that is unexposed in both the first and second exposures) is formed. And dissolved in the developer to be removed. Thus, as shown in FIG. 4E, only the resist 41 of the unexposed lower layer 46 remains, and a resist pattern 47 is formed. As a result, portions extending from the both ends of the resist pattern 47 onto the convex portion 16 can be removed, and the resist pattern 47 having a desired length is formed.
[0072]
As described above, in the present embodiment, the positive resist 41 is applied as a resist, and the light shielding patterns 44 that are longer at both ends than the length of the desired resist pattern 47 are provided as in the second embodiment. First exposure (overlap exposure) is performed using the mask 43. Subsequently, a second exposure is performed on the entire coated region with an exposure amount that allows light to reach only the resist upper layer 45. In this way, the second exposure allows the resist upper layer 45 to be removed by causing a deprotection reaction even in a region not exposed at the time of the first exposure, and the upper layer reflection containing an acidic compound in the second embodiment. The prevention film 32 and its coating process can be made unnecessary. Therefore, cost reduction and process shortening can be achieved.
[0073]
In that case, as in the case of each of the above-described embodiments, the overlap exposure prevents the effect of misalignment of the light shielding pattern 44, thereby forming a resist pattern 47 in which both ends are in close contact with the side wall of the convex portion 16. it can. Further, by removing the resist upper layer 45, portions extending from both ends of the resist pattern 47 onto the convex portion 16 can be removed, and the resist pattern 47 having a desired length can be formed.
[0074]
In this way, as shown in FIG. 4D, it is possible to pattern a resist pattern 47 in which only necessary portions are in close contact with the convex portions 16 and there is no misalignment at those portions. In addition, since the height of the resist pattern 47 is reduced by thinning the film and the bottom surface of the resist pattern 47 is not only in close contact with the base, but also the side surfaces are in close contact with each other, the resist pattern 47 is not deformed or collapsed. It can be prevented.
[0075]
It should be noted that the positive resist 41 has a low transmittance to a certain extent, and it is easier to control the thinning. However, even if the resist 41 has a low transmittance, it is possible to reduce the thickness of the resist 41 in the same manner by exposing the entire surface of the coating region with a small exposure amount. Can be controlled. Further, the exposure for thinning the resist pattern 47 and the exposure for patterning the resist pattern 47 may be performed first.
[0076]
<Fourth embodiment>
FIG. 5 shows a method for patterning a resist in a concave portion of a base having a convex portion in the present embodiment. In addition, the base | substrate which has a convex part is the same as the base | substrate shown in FIG. 1 in the said 1st Embodiment. Also, in FIG. 5, only the outline of the silicon nitride film 15 located in the outermost layer is representatively expressed, and the upper stage is a sectional view and the lower stage is a plan view.
[0077]
In this embodiment, the resist is patterned only in the inner recesses between the protrusions on the base using a resist having a large film thickness dependency of sensitivity. In the following, description will be made sequentially with reference to FIG.
[0078]
First, based on the following equation, the period of the resist swing curve of the negative resist having a large sensitivity dependency on the film thickness is obtained.
0.248 μm (exposure wavelength) ÷ 2 ÷ 1.777 (resist refractive index) = 0.09797 μm
[0079]
Actually, the resist swing curve period may vary depending on the influence of the above-mentioned ground, etc., so it is also very important to experimentally measure the period of the resist swing curve using the ground and the exposure mask on which patterning is actually performed. is there. In that case, it is best to perform patterning using an exposure mask that actually performs patterning and to examine the sensitivity with the line width after patterning.
[0080]
Using the results actually measured by the above-described method, when the film thickness is represented on the horizontal axis and the exposure amount is represented on the vertical axis, a resist swing curve sensitivity curve as shown in FIG. 6 is obtained. The difference in the reference film thickness of the resist between the portion with the lowest sensitivity (point A) and the portion with the highest sensitivity (point B) shown in FIG. 6 is measured. Using the value of the reference film thickness difference between the lowest and highest sensitivity measured in this way, the difference in film thickness between the convex portions 16 and the concave portions 17 of the resist applied to the base. Is adjusted to be a natural number times the reference film thickness difference. When the resist shown in FIG. 6 is used, the height of the convex portion 16 is preferably a natural number multiple of 0.035 μm, which is ½ of the period of the resist swing curve. Thus, the value of the natural number times the difference between the point B and the point A in the sensitivity curve of the swing curve shown in FIG. However, the actual height and the optimum height of the convex portion 16 may be different from each other by about ½ of the optimum height of the convex portion 16 (= exposure light wavelength ÷ 8 ÷ resist refractive index).
[0081]
Next, as shown in FIG. 5A, the negative resist 51 having a large film thickness dependence of the sensitivity is applied to the film thickness H in the concave portion 17. ₁ Is applied so that the resist 51 has the highest sensitivity. On the other hand, the film thickness H at the convex portion 16 ₂ The resist 51 has the lowest film thickness. In that case, as described above, the film thicknesses at the concave portions 17 and the convex portions 16 may be deviated by about ½ of the difference between the points B and A shown in FIG. .
[0082]
Next, as shown in FIG. 5B, similarly to the case of the first embodiment, the exposure pattern 54 is set to be about 0.05 μm longer at both ends than the length of the desired resist pattern 55. The mask 53 is used to expose the recess 17 with the minimum exposure amount that can be patterned. Thus, overlap exposure is performed to prevent the influence of misalignment during exposure. Reference numeral 52 denotes a laser beam. Then, by developing, as shown in FIG. 5C, only the resist 51 in the exposed portion remains and a resist pattern 55 is formed.
[0083]
At that time, the portion where the exposure pattern 54 and the convex portion 16 overlap is exposed at the lowest exposure amount that can be patterned in the concave portion 17 with the lowest sensitivity of the resist 51 as described above. The resist 51 is not exposed to light. Therefore, the resist 51 in the overlapped portion is dissolved and removed during development, and as a result, a resist pattern 55 in which both ends are in close contact with the side wall of the convex portion 16 is obtained.
[0084]
As described above, in the present embodiment, the negative resist 51 whose sensitivity is highly dependent on the film thickness is replaced with the film thickness H in the recess 17. ₁ Is the film thickness with the highest sensitivity of the resist 51, while the film thickness H at the convex portion 16 is ₂ Is applied so that the sensitivity of the resist 51 is the lowest. Similar to the first embodiment, overlap exposure is performed using a mask 53 having exposure patterns 54 that are longer at both ends than the length of the desired resist pattern 55. By doing so, the portion where the exposure pattern 54 and the convex portion 16 overlap is not exposed because the sensitivity of the resist 51 is the lowest, and both ends are in close contact with the side wall of the convex portion 16 only in the concave portion 17. A resist pattern 55 having a desired length can be formed.
[0085]
Therefore, as shown in FIG. 5C, it is possible to pattern the resist pattern 55 in which only necessary portions are in close contact with the convex portion 16 and there is no misalignment at those portions. In addition, since the bottom surface of the resist pattern 55 is not only in close contact with the base, but also on the side surface, deformation and collapse of the resist pattern 55 can be prevented.
[0086]
In the present embodiment, the resist 51 having a large film thickness dependency of sensitivity is used. However, the sensitivity is not limited to a certain level even if it is a normal resist instead of a resist having a large film thickness dependency of sensitivity. This embodiment can be applied because it depends. Further, in the present embodiment, the negative resist 51 is applied so that the film thickness in the recess 17 of the base is the film thickness at which the sensitivity of the resist 51 is the highest. However, conversely, it is also possible to apply so that the film thickness at the convex portion 16 is the film thickness at which the sensitivity of the resist 51 is the highest. In this case, as shown in FIG. 7, a resist pattern 56 that is not misaligned with respect to the step between the convex portion 16 and the concave portion 17 is patterned only on the upper convex portion 16.
[0087]
In the present embodiment, the negative resist 51 is used, but on the contrary, the positive resist is used, and the film thickness at the concave portion 17 of the base becomes the highest film thickness with the highest sensitivity of the resist. It is also possible to apply so that the film thickness at 16 is the film thickness at which the sensitivity of the resist 51 is the lowest. In that case, exposure is performed using a mask having a light-shielding pattern that is longer at both ends than the length of the desired resist pattern 55, and as shown in FIG. The resist pattern 57 can be patterned. At this time, a resist pattern 58 is also formed on the entire upper surface of the convex portion 16 in a self-aligned manner with respect to the step between the convex portion 16 and the concave portion 17.
[0088]
Furthermore, using the positive resist, the thickness of the underlying recess 17 is the lowest resist sensitivity, and the thickness of the convex 16 is the resist 51 having the highest sensitivity. It is also possible to apply so that. In that case, a resist pattern having no misalignment is formed on the entire surface of the recess 17 in a self-aligned manner with respect to the step between the protrusion 16 and the recess 17. As described above, when a resist pattern is formed on the entire surface of the recess 17 using a positive resist, it is possible to further pattern the formed resist pattern.
[0089]
Further, using the negative resist, the film thickness at the convex portion 16 is set to a film thickness having high resist sensitivity, while the film thickness at the concave portion 17 is set to a film thickness having low resist sensitivity so that a desired portion in the convex portion 16 is obtained. The resist pattern can be formed on a desired portion above the convex portion 16 by exposing to. Further, by reversing the sensitivities of the convex portion 16 and the concave portion 17 and exposing a desired portion in the concave portion 17, the resist pattern can be formed only on the opposite concave portion 17.
[0090]
In addition, the positive resist is used to make the film thickness at the convex part 16 high in resist sensitivity, while the film thickness in the concave part 17 is made low in resist sensitivity so that a desired portion in the convex part 16 is obtained. By performing the exposure, a resist pattern can be formed on the entire surface in the recess 17 and a desired portion on the protrusion 16. Further, by reversing the sensitivity of the convex portion 16 and the concave portion 17 and exposing a desired portion in the concave portion 17, a resist pattern can be formed on the entire surface of the convex portion 16 and the desired portion in the concave portion 17. .
[0091]
In this embodiment, a resist whose sensitivity is highly dependent on the film thickness is used, but the same effect can be obtained even if the sensitivity of the resist is changed in the direction of the film thickness due to other physical requirements. That is, the step is so large that the exposure light does not reach. Since there is a substance capable of absorbing light, the exposure light is absorbed every time it is repeatedly reflected in the resist layer, and the sensitivity is deteriorated. Since there is a substance that can efficiently reflect the exposure light, the number of reflections increases and the sensitivity is improved. Due to physical requirements such as the above, a low-sensitivity portion and a high-sensitivity portion are formed in the coated resist. By doing so, patterning can be performed in a self-aligned manner with respect to the boundary where the sensitivity of the resist changes.
[0092]
<Fifth embodiment>
FIG. 9 shows a method of patterning a resist in a concave portion of a base having a convex portion in the present embodiment. In addition, the base | substrate which has a convex part is the same as the base | substrate shown in FIG. 1 in the said 1st Embodiment. Also, in FIG. 9, only the outline of the silicon nitride film 15 located in the outermost layer is representatively represented, and the upper stage is a sectional view and the lower stage is a plan view.
[0093]
In the present embodiment, the resist is patterned only in the recesses 17 using the depth of focus (DOF) of the resist. In the following, description will be made sequentially with reference to FIG.
[0094]
First, the best position of focus on the stepper (position where patterning can be performed with good shape) is aligned with the concave portion 17. In this case, the height of the convex portion 16 is set so as not to leave a resist pattern because it is not the best focus position.
[0095]
Next, as shown in FIG. 9A, a negative resist 61 having a narrow DOF (that is, a resist in which a pattern is not formed by slightly increasing or decreasing the focus value from the best focus position) is applied. Next, as in the case of the first embodiment, a mask 63 having an exposure pattern 64 set to be about 0.05 μm longer at both ends than the length of a desired resist pattern 65 is used, as shown in FIG. ) Expose as shown. Thus, overlap exposure is performed to prevent the influence of misalignment during exposure. Reference numeral 62 denotes a laser beam. Then, by developing, as shown in FIG. 9C, only the resist 61 in the exposed portion remains and a resist pattern 65 is formed.
[0096]
At this time, since the portion where the exposure pattern 64 and the convex portion 16 overlap is not the best focus position as described above, the resist 61 is not exposed. Therefore, the resist 61 in the overlapped portion is dissolved and removed during development, and as a result, a resist pattern 65 in which both ends are in close contact with the side wall of the convex portion 16 is obtained.
[0097]
In this way, it is possible to pattern the resist pattern 65 in which only necessary portions are in close contact with the convex portion 16 and there is no misalignment at that portion. Further, since the bottom surface of the resist pattern 65 is not only in close contact with the base, but also on the side surface, deformation and collapse of the resist pattern 65 can be prevented.
[0098]
In this method using DOF, the larger the numerical aperture (NA) of the stepper, the more the same effect as using the resist 61 having a narrow DOF can be obtained.
[0099]
<Sixth embodiment>
FIG. 10 shows a method of patterning a resist in a concave portion of a base having a convex portion in the present embodiment. In addition, the base | substrate which has a convex part is the same as the base | substrate shown in FIG. 1 in the said 1st Embodiment. Also, in FIG. 10, only the outline of the silicon nitride film 15 located in the outermost layer is representatively expressed, and the upper stage is a cross-sectional view and the lower stage is a plan view.
[0100]
In this embodiment, the resist is patterned by exposing a base having a convex portion to the surface of the wafer from an oblique direction. In the following, description will be made sequentially with reference to FIG.
[0101]
First, as shown in FIG. 10A, a chemically amplified positive resist 71 is applied to the base having the convex portions 16. In that case, in order to expose the side wall of the convex portion 16 at an angle later, in consideration of the influence of reflection, the dye-containing resist used in the third embodiment may be used, or the surface of the resist 71 may be It is preferable to form the upper antireflection film or the like used in the first and second embodiments.
[0102]
Next, the irradiation direction of the laser beam 72 in the exposure apparatus using the excimer laser is set so that it is aligned in a certain direction and is obliquely straight with respect to the surface of the wafer. Then, as shown in FIG. 10B, the entire surface is exposed at an angle such that the laser beam 72 does not strike the center of the recess 17. Further, as shown in FIG. 10C, the laser beam 72 is once again irradiated at a target angle with respect to a surface perpendicular to the wafer surface and extending in the direction of the wall surface of the convex portion 16. The whole surface is exposed obliquely from the direction. Reference numeral 73 denotes an area of the resist 71 that is exposed once. Thus, by performing the exposure twice, a portion of the central portion in the concave portion 17 that is not exposed at all becomes a shadow of the convex portion 16. At that time, by adjusting the exposure angle, the width and height of the non-exposed portion at the center of the concave portion 17 can be changed, and the size and shape of the formed resist pattern 74 can be changed. .
[0103]
Next, by developing, the resist 71 in the portion exposed by the two exposures is dissolved and removed. Thus, the unexposed portion in the central portion of the lower surface of the concave portion 17 is formed as a resist pattern 74 as shown in FIG.
[0104]
At that time, the upper surface of the convex portion 16 is uniformly exposed by the laser light 72 from two directions that are aligned and straight. Therefore, the resist pattern 74 including the corner portion is not formed on the upper surface of the convex portion 16 after development.
[0105]
In this way, it is possible to pattern the resist pattern 74 in which only necessary portions are in close contact with the convex portion 16 and there is no misalignment at that portion. Further, since the bottom surface of the resist pattern 74 is not only in close contact with the base, but also on the side surface, deformation and collapse of the resist pattern 74 can be prevented.
[0106]
<Seventh embodiment>
FIG. 11 shows a method of patterning a resist in a concave portion of a base having a convex portion in the present embodiment. In addition, the base | substrate which has a convex part is the same as the base | substrate shown in FIG. 1 in the said 1st Embodiment. Also, in FIG. 11, only the outline of the silicon nitride film 15 located in the outermost layer is representatively represented, and the upper stage is a cross-sectional view and the lower stage is a plan view.
[0107]
In the sixth embodiment, the resist pattern 74 is formed in the central portion in the recess 17 by two oblique exposures. On the other hand, in the present embodiment, a resist pattern is formed on the side wall of the convex portion 16 by two oblique exposures. In the following, description will be made sequentially with reference to FIG.
[0108]
First, as shown in FIG. 11A, a positive resist 81 is applied to the base having the convex portions 16. Next, as shown in FIGS. 11 (a) and 11 (b), a surface that is perpendicular to the wafer surface and extends in the direction of the wall surface of the protrusion 16 as in the case of the sixth embodiment. The laser beam 82 is exposed twice at two target angles. At this time, both exposures are performed with a small exposure amount such that the resist 81 is not exposed in one exposure (exposure amount to be exposed in two exposures).
[0109]
By doing so, as shown in FIG. 11C, a portion 84 exposed twice by the laser beam 82 is formed in the central portion in the concave portion 17, and 1 is formed along the side wall of the convex portion 16 in the concave portion 17. A portion 83 is formed which is exposed only once (that is, not exposed). Therefore, by developing, a resist side wall (resist pattern) 85 is formed on the side wall of the convex portion 16 as shown in FIG. At this time, the size and shape of the resist pattern 85 can be changed by adjusting the exposure angle.
[0110]
By the way, the resists 21, 31, 41, 51, 61, 71, 81 used in the above-described embodiments are obtained by changing the formed resist patterns 29, 39, 47, 55, 56, 57, 58, 65, 74, 85, respectively. Any mask can be used as long as it can withstand etching in the next manufacturing process. The resist coating method and the level of flattening are the thinnest (that is, the lowest) resist pattern when removal and patterning of the resist upper layer, which is an upper layer than the upper surface of the convex portion 16 in each resist, are completed. Any coating method or flatness may be used so that the portion has a film thickness that can withstand the etching.
[0111]
As for the resist thinning method (resist upper layer removal), the chemical solution is diffused and developed as in the first and second embodiments, and the exposed and developed as in the third embodiment. Any method can be used as long as it can thin the resist, such as dry etching, RIE (reactive ion etching), wet etching, polishing, or CMP (chemical mechanical polishing). However, it is advantageous in terms of cost to reduce the thickness of the film by exposure, as in the method of developing by spreading the chemical solution after exposure or the method of developing by exposure, because there is no need for new equipment investment.
[0112]
In addition, a resist having a larger amount of film loss than a normal resist may be used without providing a step of removing the resist upper layer. Further, a developer having a larger amount of film loss than a normal developer may be used. In addition, when a “resist that can be applied only in the concave portion 17” or “a resist in which a portion coated on the convex portion 16 is removed in the development process” is realized, such a resist may be used. Good.
[0113]
Further, the exposure is not limited to the KrF excimer laser beam, but may be any one that can sensitize a resist such as i-line, electron beam, X-ray, ArF excimer laser beam or EUV (extreme ultraviolet) light. . The development is not limited to the above-mentioned NMD-W developer, and any material that can develop a photosensitive resist such as an organic solvent may be used. As for the overlap exposure method, in addition to the method in which the mask exposure pattern and the light shielding pattern itself are made larger than the desired resist pattern in advance as in each of the above embodiments, the exposure amount increasing method and the scan exposure (during exposure) An exposure method that moves the stage may be used.
[0114]
In the first to fifth embodiments, the resist patterns 29, 39, 47, 55, 57, and 65 are formed by exposure using the masks 24, 34, 43, 53, and 63. . However, the present invention is not limited to this, and it is also possible to perform ion implantation, etching, or the like by only removing the resist upper layer and using the resist remaining in the recesses 17 as a mask.
[0115]
In the sixth and seventh embodiments, the laser beam is exposed twice at two target angles with respect to the surface perpendicular to the wafer surface and extending in the direction of the wall surface of the convex portion 16. However, the resist can be left on the entire surface of the recess 17 by setting the exposure angle at that time to be closer to parallel with the wafer. As described above, the resist itself remaining in the recess 17 can be used as a processing mask or an implantation mask.
[0116]
In each of the above embodiments, as an example of the step formed on the base, the case where the protrusion 16 is formed is described as an example. However, the level difference in the present invention is not limited to this, and includes all of the upper and lower surfaces and all the side walls that are connected to both sides.
[0117]
【The invention's effect】
As apparent from the above, in the method of manufacturing the semiconductor device according to the first aspect of the present invention, when a resist pattern is formed on the lower surface of the step in the base, the resist is applied flatly on the surface of the base, and the resist is formed into a thin film. Pre-processing is performed, overlap exposure is performed using a mask having an exposure pattern or a light-shielding pattern that overlaps the upper surface of the step at a portion where the resist pattern is in close contact with the side wall of the step, and subsequent development Since the development is performed after thinning the resist so that the resist becomes thin, the development can reduce the thickness of the resist.
[0118]
Therefore, a resist pattern can be formed only on the lower surface by thinning the resist to the upper surface of the step on the base. In that case, since the overlap exposure is performed so as to overlap the upper surface, a resist pattern in close contact with the side wall can be formed in a self-aligned manner at the place where the overlap exposure is performed.
[0119]
That is, according to the present invention, it is possible to reliably form a resist pattern in a self-aligned manner only on the lower surface without considering the influence of the misalignment. Further, by thinning the resist to the upper surface, the resist pattern does not run on the upper surface. Further, the height of the formed resist pattern is lowered by the above-mentioned thinning. Therefore, deformation and collapse of the resist pattern can be prevented, and the yield can be improved. Furthermore, since it is not necessary to provide an alignment margin for the underlying pattern, the resulting semiconductor device can be miniaturized.
[0120]
In one embodiment of the method for manufacturing a semiconductor device, a negative resist is applied at the time of applying the resist, and a chemical that deactivates the acid generated by the exposure is applied to the surface of the negative resist at the time of the pretreatment, When the film is thinned, the chemical solution is evenly diffused to the vicinity of the upper surface of the base step in the resist, so that the exposed negative resist can be thinned to the upper surface. Therefore, a resist pattern can be formed only on the lower surface of the step, which is in close contact with the side wall at the place where the overlap exposure is performed and does not run on the upper surface.
[0121]
In one embodiment, the semiconductor device manufacturing method includes applying a positive resist during the resist coating, applying a chemical solution that causes a deprotection reaction to the surface of the positive resist during the pretreatment, and performing the thinning. Since the chemical solution is evenly diffused to the vicinity of the upper surface of the base step in the resist, a positive resist that is not exposed can be thinned to the upper surface. Therefore, a resist pattern can be formed only on the lower surface of the step, in close contact with the side wall of the step at the position where the overlap exposure is performed, and without running on the upper surface.
[0122]
According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein when a resist pattern is formed on a lower surface of a step in a base, a positive resist is applied flatly on the surface of the base, and the resist pattern is a side wall of the step. Overlap exposure (first exposure) is performed using a mask having a light-shielding pattern that overlaps the upper surface of the step at the portion in close contact with the upper surface, and the entire surface is exposed up to the vicinity of the upper surface of the underlying step in the resist (second exposure). Then, since development is performed, the positive resist that is not exposed in the first exposure step can be exposed to light by the second exposure to be thinned to the upper surface.
[0123]
Therefore, according to the present invention, the influence of the alignment deviation is not considered, and only the lower surface of the step is in close contact with the side wall at the place where the overlap exposure is performed, and the ride on the upper surface is performed. It is possible to form a resist pattern with no self alignment. Furthermore, the height of the resist pattern can be lowered by the thinning, the deformation and collapse of the resist pattern can be prevented, and the yield can be improved. Furthermore, it is not necessary to provide an alignment margin for the underlying pattern, and the resulting semiconductor device can be miniaturized.
[0124]
Further, in the method of manufacturing the semiconductor device according to the third aspect of the present invention, when the resist pattern is formed only on the upper surface or the lower surface of the step in the base, the film thickness on the upper surface is expressed by the following formula ( After applying and exposing a resist so that it becomes one of the X values obtained in 9) and the film thickness on the lower surface becomes one of the Y values obtained in the following formula (10) Since the development is performed, only the resist on the lower surface having the highest sensitivity can be exposed by the exposure. Therefore, when a negative resist is used, a resist pattern in close contact with the side wall of the step can be formed in a self-aligned manner only on the lower surface. When a positive resist is used, a resist pattern can be formed in a self-aligned manner only on the upper surface. That is, it is not necessary to provide an alignment margin for the underlying pattern, and the resulting semiconductor device can be miniaturized.
X = {(exposure light wavelength) / 4} / (refractive index of resist) · (2n−1) (9)
Y = {(exposure light wavelength) / 4} / (refractive index of resist) · 2 m (10)
Where n and m are natural numbers
[0125]
In addition, in the method for manufacturing a semiconductor device according to the fourth aspect of the present invention, when a resist pattern is formed only on the upper surface or only the lower surface of the step in the base, the film thickness on the upper surface is expressed by the following formula ( 11), a resist is applied so that the film thickness on the lower surface is any one of the Y values obtained by the following formula (12), and after exposure, Since the development is performed, only the resist on the upper surface having the highest sensitivity can be exposed by the exposure. Therefore, when a negative resist is used, a resist pattern can be formed in a self-aligned manner only on the upper surface. When a positive resist is used, a resist pattern that is in close contact with the side wall of the step can be formed in a self-aligned manner only on the lower surface. That is, it is not necessary to provide an alignment margin for the underlying pattern, and the resulting semiconductor device can be miniaturized.
X = {(exposure light wavelength) / 4} / (refractive index of resist) · 2n (11)
Y = {(exposure light wavelength) / 4} / (refractive index of resist) · (2m−1) (12)
Where n and m are natural numbers
[0126]
In the semiconductor device manufacturing method of one embodiment, each of the values of X and Y is in a range of ± Z (Z = {(exposure light wavelength) / 8} / (resist refractive index)). As a result, an error of 1/2 of the difference between the film thickness with the highest resist sensitivity and the film thickness with the lowest sensitivity can be allowed for the film thickness on the upper and lower surfaces of the step. Therefore, control of the film thickness at the time of application of the resist can be facilitated.
[0127]
According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: applying a resist to the surface of the base when the resist pattern is formed only on the upper surface or the lower surface of the step in the base; Since exposure is performed after focusing on one of the above, development is performed, so when focusing on the upper surface of the step using a negative resist, only on the upper surface, on the lower surface When focused, a resist pattern can be formed in a self-aligned manner only on the lower surface. In addition, when a positive resist is used, the resist pattern is self-aligned only on the lower surface when focused on the upper surface, and only on the upper surface when focused on the lower surface. Can be formed. Therefore, it is not necessary to provide an alignment margin for the underlying pattern, and the resulting semiconductor device can be miniaturized.
[0128]
According to a sixth aspect of the present invention, when a resist pattern is formed on the lower surface of the step in the base, a resist is applied to the surface of the base, the surface of the base is exposed from an oblique direction, and then developed. As a result, there is a portion on the lower surface of the step in the base that does not receive light due to the shadow of the side wall. Therefore, by using a positive resist, a resist pattern in close contact with the side wall can be formed in a self-aligned manner on the lower surface without using an exposure mask. That is, since it is not necessary to provide an alignment margin for the underlying pattern, the resulting semiconductor device can be miniaturized.
[0129]
In the method of manufacturing a semiconductor device according to one embodiment, since the exposure is performed from a plurality of directions in the exposure step, for example, by exposing from two directions opposite to the wall surface of the step, In the central part on the lower surface sandwiched between the side walls, there is a portion that is not exposed once even in the shadow of the two side walls. Therefore, in that case, if a positive resist is used, a resist pattern in which both ends are in close contact with the side wall can be formed in the central portion on the lower surface.
[0130]
Further, in the method of manufacturing a semiconductor device of one embodiment, when performing exposure from the plurality of oblique directions, the exposure is performed with an amount of light that does not pattern the resist in a single exposure. By exposing from two opposite directions, a portion of the lower surface sandwiched between the two opposing side walls is exposed to the shadows of the side walls along the two side walls. Therefore, in that case, if a positive resist is used, a resist pattern in close contact with the two side walls on the lower surface can be formed.
[0131]
According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein when a resist pattern is formed only on a lower surface of a step in a base, a negative resist is applied flatly on the surface of the base, and the surface of the negative resist is formed. A chemical solution that deactivates the acid generated by the exposure is applied to the entire surface, and the entire surface is exposed. The chemical solution is evenly diffused to the vicinity of the upper surface of the step in the resist. The negative resist can be thinned to the upper surface of the step. Therefore, a resist pattern which does not run on the upper surface can be formed in a self-aligned manner only on the lower surface of the step in the base.
[0132]
In addition, according to the eighth aspect of the present invention, when the resist pattern is formed only on the lower surface of the step in the base, a positive resist is applied flatly on the surface of the base and is removed from the surface of the resist. Since a chemical solution that causes a protective reaction is applied and the chemical solution is evenly diffused to the vicinity of the upper surface of the base step in the resist, development is performed, so that the positive resist is removed from the step by the deprotection reaction. The film can be thinned to the upper surface. Therefore, a resist pattern that does not run on the upper surface can be formed in a self-aligned manner only on the lower surface of the step in the base.
[0133]
According to a ninth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein when a resist pattern is formed only on a lower surface of a step in a base, a positive resist is applied flatly on the surface of the base, Since development is performed after the entire surface up to the vicinity of the upper surface of the step of the base is formed, the positive resist can be thinned to the upper surface of the step by the entire surface exposure. Therefore, a resist pattern which does not run on the upper surface can be formed in a self-aligned manner only on the lower surface of the step in the base.
[Brief description of the drawings]
FIG. 1 is a diagram showing a structure of a transistor formed partway through a semiconductor device manufacturing method according to the present invention.
FIG. 2 is a diagram showing a method of patterning a resist in a recess using the transistor structure shown in FIG. 1 as a base.
FIG. 3 is a diagram showing a patterning method different from FIG.
4 is a diagram showing a patterning method different from those in FIGS. 2 and 3. FIG.
FIG. 5 is a diagram showing a patterning method different from those in FIGS.
FIG. 6 is a diagram showing a sensitivity curve of a resist having a large film thickness dependence of sensitivity.
7 is a diagram showing a resist pattern when a resist exhibiting sensitivity film thickness dependence opposite to that in FIG. 6 is used in FIG.
8 is a view showing a resist pattern when a positive resist is used in FIG.
FIG. 9 is a diagram showing a patterning method different from those in FIGS.
FIG. 10 is a diagram showing a patterning method different from those in FIGS.
FIG. 11 is a diagram showing a patterning method different from those in FIGS.
FIG. 12 is a diagram showing an example of a resist pattern obtained when an alignment method using a conventional alignment mark is applied.
[Explanation of symbols]
11 ... Silicon substrate,
12 ... Insulating film (gate oxide film),
13 ... polycrystalline silicon film (gate electrode),
15 ... Silicon nitride film,
16 ... convex part,
17 ... recess,
21 ... Negative resist,
22, 32 ... upper antireflection film,
23, 33, 42, 52, 62, 72, 82 ... laser light,
24, 34, 43, 53, 63 ... masks,
25, 54, 64 ... exposure pattern,
26, 36, 45 ... resist upper layer,
27 ... upper layer of exposed part,
28 ... lower layer of the exposed part,
29, 39, 47, 55, 56, 57, 58, 65, 74, 85 ... resist pattern,
31, 81... Positive resist,
35, 44 ... shading pattern,
37 ... upper layer of unexposed part,
46 ... Unexposed lower layer,
41 ... Positive resist containing dye,
51. Negative resist having a large film thickness dependence of sensitivity.
61 ... Negative resist with a narrow DOF,
71. Chemically amplified positive resist,
73, 83 ... areas exposed once,
84: Area exposed twice.

Claims (14)

A method for manufacturing a semiconductor device comprising a step of forming a resist pattern in close contact with a side wall of a step on a lower surface of the step in a base having a step formed on a surface,
The step of forming the resist pattern includes:
A resist coating process for flatly applying a resist to the surface of the base;
A pretreatment step for reducing the thickness of the coated resist;
An exposure step of performing overlap exposure using a mask having an exposure pattern or a light-shielding pattern formed so as to overlap the upper surface of the step at a portion where the resist pattern is in close contact with the side wall of the step;
A thinning step for reducing the film thickness of the resist by subsequent development;
A method for manufacturing a semiconductor device, comprising a developing step. In the manufacturing method of the semiconductor device according to claim 1,
In the resist coating process, a negative resist is applied,
In the pretreatment step, a chemical solution that deactivates the acid generated in the negative resist by the exposure is applied to the surface of the negative resist.
In the thinning process, the chemical solution is uniformly diffused to the vicinity of the upper surface of the base step in the negative resist. In the manufacturing method of the semiconductor device according to claim 1,
In the resist coating process, a positive resist is applied,
In the pretreatment step, a chemical solution that causes a deprotection reaction on the positive resist is applied to the surface of the positive resist.
In the thinning step, the chemical solution is uniformly diffused to the vicinity of the upper surface of the base step in the positive resist. A method for manufacturing a semiconductor device comprising a step of forming a resist pattern in close contact with a side wall of a step on a lower surface of the step in a base having a step formed on a surface,
The step of forming the resist pattern includes:
A resist coating step of flatly applying a positive resist on the surface of the base;
A first exposure step of performing an overlap exposure using a mask having a light shielding pattern formed so as to overlap the upper surface of the step at a portion where the resist pattern is in close contact with the side wall of the step;
A second exposure step for exposing the entire surface up to the vicinity of the upper surface of the base step in the positive resist;
A method for manufacturing a semiconductor device, comprising a developing step. A method of manufacturing a semiconductor device comprising a step of forming a resist pattern only on the upper surface or only the lower surface of the step in the base having a step formed on the surface,
The step of forming the resist pattern includes:
On the surface of the base, the film thickness on the upper surface is one of the X values obtained by the following equation (1), and the film thickness on the lower surface is the Y value obtained by the following equation (2). A resist coating step of coating a resist so as to be any one of
An exposure process;
A method for manufacturing a semiconductor device, comprising a developing step.
X = {(exposure light wavelength) / 4} / (refractive index of resist) · (2n−1) (1)
Y = {(exposure light wavelength) / 4} / (refractive index of resist) · 2 m (2)
Where n and m are natural numbers A method of manufacturing a semiconductor device comprising a step of forming a resist pattern only on the upper surface or only the lower surface of the step in the base having a step formed on the surface,
The step of forming the resist pattern includes:
On the surface of the base, the film thickness on the upper surface is one of the X values obtained by the following equation (3), and the film thickness on the lower surface is the Y value obtained by the following equation (4). A resist coating step of coating a resist so as to be any one of
An exposure process;
A method for manufacturing a semiconductor device, comprising a developing step.
X = {(exposure light wavelength) / 4} / (refractive index of resist) · 2n (3)
Y = {(exposure light wavelength) / 4} / (refractive index of resist) · (2m−1) (4)
Where n and m are natural numbers In the manufacturing method of the semiconductor device as described in any one of Claim 5 or Claim 6,
Each of the values of X and Y is within a range of ± Z (Z = {(exposure light wavelength) / 8} / (resist refractive index)). A method of manufacturing a semiconductor device comprising a step of forming a resist pattern only on the upper surface or only the lower surface of the step in the base having a step formed on the surface,
The step of forming the resist pattern includes:
A resist coating step of coating a resist on the surface of the base;
An exposure step of performing exposure while focusing on either the upper surface or the lower surface;
A method for manufacturing a semiconductor device, comprising a developing step. A method for manufacturing a semiconductor device comprising a step of forming a resist pattern in close contact with a side wall of a step on a lower surface of the step in a base having a step formed on a surface,
The step of forming the resist pattern includes:
A resist coating step of coating a resist on the surface of the base;
An exposure step of performing exposure by applying light from an oblique direction to the surface of the base;
A method for manufacturing a semiconductor device, comprising a developing step. In the manufacturing method of the semiconductor device according to claim 9,
In the exposure step, the semiconductor device manufacturing method is characterized in that exposure is performed by applying light from a plurality of directions. In the manufacturing method of the semiconductor device according to claim 10,
The method of manufacturing a semiconductor device, wherein, in the exposure step, the exposure is performed with an amount of light such that the resist is not patterned by one exposure. A method for manufacturing a semiconductor device, comprising a step of forming a resist pattern only on the lower surface of the step in the base having a step formed on the surface,
The step of forming the resist pattern includes:
A resist coating step of flatly applying a negative resist to the surface of the base;
A pretreatment step of applying a chemical solution that deactivates the acid generated in the negative resist by subsequent exposure to the negative resist surface;
An exposure process for exposing the entire surface of the negative resist;
A thinning process in which the chemical solution is uniformly diffused to the vicinity of the upper surface of the base step in the negative resist, and the film thickness of the negative resist is reduced by subsequent development,
A method for manufacturing a semiconductor device, comprising a developing step. A method for manufacturing a semiconductor device, comprising a step of forming a resist pattern only on the lower surface of the step in the base having a step formed on the surface,
The step of forming the resist pattern includes:
A resist coating step of flatly applying a positive resist on the surface of the base;
A pretreatment step of applying a chemical solution that causes a deprotection reaction to the positive resist on the positive resist surface;
A thinning step for uniformly diffusing the chemical solution to the vicinity of the upper surface of the base step in the positive resist so that the film thickness of the positive resist is reduced by subsequent development;
A method for manufacturing a semiconductor device, comprising a developing step. A method for manufacturing a semiconductor device, comprising a step of forming a resist pattern only on the lower surface of the step in the base having a step formed on the surface,
The step of forming the resist pattern includes:
A resist coating step of flatly applying a positive resist on the surface of the base;
An exposure process for exposing the entire surface up to the vicinity of the upper surface of the base step in the positive resist;
A method for manufacturing a semiconductor device, comprising a developing step.

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