JP3776042B2 - IC card - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an IC card, and more particularly, to a non-contact type IC card that transmits / receives data to / from the outside without being contacted and receives power supply from the outside.
[0002]
[Background Art and Problems to be Solved by the Invention]
In recent years, IC card system commercialization has been actively promoted in various industries in Japan. For example, in the telephone industry, IC telephone cards have already been sold and public telephones compatible with IC cards have been installed. In the railway industry, the practical use of an IC commuter pass system is scheduled for several years. Furthermore, introduction of an IC card as an alternative to an ID such as a driver's license or insurance card is also being considered.
[0003]
There are two types of IC cards: contact type and non-contact type. In a contact type IC card, an external terminal is brought into contact with a reader / writer to transmit / receive data or receive power supply. In contrast, in a non-contact type IC card, data is transmitted / received to / from a reader / writer and power is supplied from the reader / writer by a built-in antenna in a non-contact manner. Furthermore, non-contact type IC cards currently being developed by various companies are scheduled to support an ISO 14443-3 anti-collision function that allows one reader / writer to simultaneously read and write a plurality of IC cards. By having this anti-collision function, for example, by passing a hospital non-contact IC card and a financial non-contact IC card over the reader / writer at the same time, exchange of information such as medical results and payment of expenses related to this, etc. You can expect effects such as ending at once.
[0004]
In the non-contact type IC card, since the power supply is received wirelessly, the power supply is unstable compared to the contact type. Therefore, when receiving data from the reader / writer and storing it in the built-in non-volatile memory, or reading data from the non-volatile memory and sending it to the reader / writer, the influence of noise generated by the operation of the non-volatile memory Data may not be transmitted or received normally. Furthermore, even when one reader / writer reads and writes a plurality of IC cards at the same time, one non-contact type IC card stores received data in the nonvolatile memory or reads data from the nonvolatile memory to read / write the reader / writer. The transmission / reception of the other IC card may not be performed normally due to the effect of noise generated during transmission.
[0005]
An object of the present invention is to provide an IC card that can suppress the influence of noise generated by the operation of a nonvolatile memory.
[0006]
[Means for Solving the Problems and Effects of the Invention]
According to the present invention, an IC card is a non-contact type IC card that performs contactless data transmission / reception and receives power supply from the outside, and includes a transmission circuit, a buffer memory, a DMA circuit, A non-volatile memory, a CPU, and state control means are provided. The transmission circuit exchanges data with the outside. The DMA circuit transfers data received by the transmission circuit to the buffer memory, and transfers data stored in the buffer memory to the transmission circuit. The CPU writes / reads data to / from the buffer memory and the nonvolatile memory. The state control circuit stops the operations of the nonvolatile memory and the CPU when the transmission circuit transmits / receives data to / from the outside.
[0007]
In the IC card, the nonvolatile memory and the CPU stop operating when the transmission circuit transmits / receives data to / from the outside. Thereby, the influence with respect to the transmission circuit of the noise which generate | occur | produces with operation | movement of a non-volatile memory and CPU can be suppressed. As a result, the reliability of transmission / reception by the transmission circuit can be improved. Further, even when one reader / writer reads / writes a plurality of IC cards at the same time, when the transmission circuit in each IC card transmits / receives data to / from the outside, the nonvolatile memory in each IC card and Since the CPU stops operating, mutual interference due to mutual noise generation can be prevented, and reliability in transmission / reception of a plurality of IC cards can be improved.
[0008]
Preferably, data transmitted and received by the transmission circuit is a data bit every predetermined period. Column Is what appears. Further, the transmission circuit has a certain data bit. Column Send / receive period and other data bits Column An interrupt signal is generated in a period between the transmission and reception periods. The DMA circuit performs transfer processing in response to the interrupt signal.
[0009]
In the IC card, a data bit is transmitted by a transmission circuit. Column Period during which data is transmitted and received and other data bits Column The transfer processing by the DMA circuit is performed in a period between the transmission and reception periods. As a result, it is possible to prevent the data being transmitted / received by the transmission circuit from being garbled due to the influence of noise generated by the operation of the DMA circuit.
[0010]
Preferably, the data received by the transmission circuit conforms to the provisions of ISO / IEC 144443-3. Frame structure and character It has a configuration. The transmission circuit includes normal waveform storage means, error prediction waveform storage means, waveform detection means, and collation means.
[0011]
The normal waveform storage means is defined by ISO / IEC144443-3. SOF (Start Of Frame) Store the waveform pattern. The error prediction waveform storage means stores a waveform pattern including an error predicted in advance for data received by the transmission circuit. The waveform detection circuit detects a waveform pattern of data received by the transmission circuit. When the waveform pattern detected by the waveform detection means matches the waveform pattern stored in the normal waveform storage means or the waveform pattern stored in the error prediction waveform storage means, the collating means outputs the data received by the transmission circuit. Correct based on the normal waveform pattern.
[0012]
According to the IC card, when the data received by the transmission circuit includes an error, the error is corrected.
[0013]
Preferably, the data received by the transmission circuit conforms to the provisions of ISO / IEC 144443-3. Frame structure and character It has a configuration. The transmission circuit includes an analog circuit unit. The analog circuit unit converts externally received data into digital data. Recovery Adjust and output. The IC card further includes preset signal generating means. The preset signal generating means provides the analog circuit unit with a preset signal that is active for a predetermined period in a period other than the period in which the transmission circuit is receiving data. The analog circuit unit sets the output to a logic high level in response to the active preset signal.
[0014]
According to the IC card, even when the signal output from the analog circuit unit becomes a logic low level during a period other than the period during which the transmission circuit is receiving data, the signal is output from the analog circuit unit. It is possible to prevent the transmission circuit from entering the reception state when the signal is at the logic low level.
[0015]
Preferably, the data received by the transmission circuit conforms to the provisions of ISO / IEC 144443-3. Frame structure and character It has a configuration. The transmission circuit includes an analog circuit unit. The analog circuit unit converts externally received data into digital data. Recovery Adjust and output. The IC card further includes hold signal generation means. The hold signal generating means applies an active hold signal to the analog circuit unit during a period other than the period during which the transmission circuit is receiving data. In response to the active hold signal, the analog circuit unit sets the output to a logic high level during a period other than the period during which the transmission circuit is receiving data.
[0016]
In the IC card, the hold signal generating means gives an active hold signal to the analog circuit unit during a period other than the period during which the transmission circuit is receiving data. In response to the active hold signal, the analog circuit unit sets the output to a logic high level. As a result, it is possible to prevent the transmission circuit from entering the reception state when the signal output from the analog circuit unit is at the logic low level.
[0017]
Preferably, the IC card further includes a resume circuit. The resume circuit stores the progress of the writing process up to the point of interruption when the data writing process to the nonvolatile memory by the CPU is interrupted. The CPU resumes the writing process to the nonvolatile memory based on the progress state stored in the resume circuit.
[0018]
In the IC card, even when the writing process to the nonvolatile memory is interrupted, the writing process can be resumed from the state at the time of the interruption.
[0019]
Preferably, the state control circuit includes a time count circuit. The time count circuit starts counting time in response to the CPU being stopped, stops counting time in response to the next return of the CPU to the operating state, and outputs the count value to the CPU To do.
[0020]
When the CPU returns from the stopped state to the operating state, the CPU needs to know the time during which the CPU was in the stopped state. When the timer attached to the CPU is used in order to know the time when the CPU is stopped, the CPU operates at regular intervals even when the transmission circuit performs transmission / reception. Noise is generated by the operation of the CPU, and this noise may affect the data transmission circuit.
[0021]
In the IC card, since the time count circuit is provided, the CPU can be completely stopped when the transmission circuit performs transmission / reception. Thereby, it is possible to inform the CPU of the time of the stop state without generating noise due to the operation of the CPU.
[0022]
Preferably, the IC card further includes a time monitoring circuit. The time monitoring circuit starts counting time in response to the CPU being stopped, and outputs a timeout signal to the CPU when the CPU does not return to the operating state until the count value reaches a predetermined value. To do. The CPU enters an operating state in response to a timeout signal from the time monitoring circuit.
[0023]
In the IC card, since the time monitoring circuit is provided, it is possible to prevent the CPU from continuing to be stopped.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
[0025]
(First embodiment)
<Configuration>
FIG. 1 is a block diagram showing the configuration of an IC card according to the first embodiment of the present invention. Referring to FIG. 1, the IC card includes an antenna 101, a data transmission circuit 102, a DMA circuit 103, a data RAM 104, a CPU 105, a nonvolatile memory 106, and a state control circuit 107.
[0026]
The antenna 101 receives a signal transmitted from a reader / writer (not shown), and transmits a signal to the reader / writer. This transmission / reception is performed in a contactless manner using radio waves as a medium. The antenna 101 receives power from the reader / writer using electromagnetic waves as a medium. This power source is an operating power source for the IC card.
[0027]
The data transmission circuit 102 processes the signal received by the antenna 101 and transfers it to the DMA circuit 103. Further, the data transmission circuit 102 processes the signal transferred from the DMA circuit 103 and supplies the processed signal to the antenna 101. Further, the data transmission circuit 102 gives an interrupt signal C1 to the state control circuit 110 in a predetermined case.
[0028]
The DMA circuit 103 writes the signal from the data transmission circuit 102 to the data RAM 104 and transfers the signal read from the data RAM 104 to the data transmission circuit 102.
[0029]
The CPU 105 writes / reads data to / from the data RAM 104 and the nonvolatile memory 106. In addition, the CPU 105 gives a command signal CMD to the state control circuit 107.
[0030]
The state control circuit 107 controls the state control signal S1 for the nonvolatile memory 106, the state control signal S2 for the CPU 105, the state control signal S3 for the data transmission circuit 102, and the state control for the DMA circuit 103. A signal S4 is supplied to the data RAM 104 as a state control signal S5.
[0031]
The nonvolatile memory 106, the CPU 105, the data transmission circuit 102, the DMA circuit 103, and the data RAM 104 are in the operating state / stopped state in response to the state control signals S1-S5, respectively.
[0032]
<Operation>
Next, the operation of the IC card configured as described above will be described with reference to FIG. FIG. 2 is a diagram showing a flow of processing in the IC card shown in FIG. The following description will be divided into (1) data reception, (2) data writing / reading to / from the nonvolatile memory, and (3) data transmission.
[0033]
(1) When receiving data
First, it is assumed that the CPU 105 is in an operating state and the data transmission circuit 102 is in a stopped state. In this state, the CPU 105 gives a command signal CMD1 to the state control circuit 107. The command signal CMD1 is a command meaning “Make the data transmission circuit 102 in a receiving state”.
[0034]
Upon receiving the command signal CMD1, the state control circuit 107 gives an inactive state control signal S2 to the CPU 105. In response to the inactive state control signal S2, the CPU 105 stops its operation. The state control circuit 107 gives an active state control signal S3 to the data transmission circuit 102. In response to the active state control signal S3, the data transmission circuit 102 changes from the stopped state to the receiving state.
[0035]
The data transmission circuit 102 performs processing on the signal received by the antenna 101 and extracts 8-bit data d1. Further, the data transmission circuit 102 gives an interrupt signal C1 to the state control circuit 107. The interrupt signal C1 is a signal indicating a request “make the DMA circuit 103 in an operating state”.
[0036]
In response to the interrupt signal C 1, the state control circuit 107 gives an active state control signal S 4 to the DMA circuit 103. In response to the active state control signal S4, the DMA circuit 103 changes from the stopped state to the operating state. Then, the DMA circuit 103 controls the data RAM 104 to be in an operating state, and writes the 8-bit data d1 from the data transmission circuit 102 to the data RAM 104.
[0037]
When the writing is completed, the DMA circuit 103 and the data RAM 104 are stopped.
[0038]
The processing from the extraction of the 8-bit unit data d1 by the data transmission circuit 102 to the writing to the data RAM 104 by the DMA circuit 103 is repeated for each 8-bit unit data.
[0039]
When processing for all data is completed, that is, when reception processing is completed, the data transmission circuit 102 gives an interrupt signal C2 to the state control circuit 107. The interrupt signal C2 is a signal indicating a request “make the CPU 105 in an operating state”.
[0040]
In response to the interrupt signal C 2, the state control circuit 107 gives an active state control signal S 2 to the CPU 105. In response to the active state control signal S2, the CPU 105 returns from the stopped state to the operating state. The restored CPU 105 gives a command signal CMD2 to the state control circuit 107. The command signal CMD2 is a command that means “make the data transmission circuit 102 stop”.
[0041]
Upon receiving the command signal CMD2, the state control circuit 107 gives an inactive state control signal S3 to the data transmission circuit 102. In response to the inactive state control signal S3, the data transmission circuit 102 changes from the reception state to the stop state.
[0042]
(2) When writing / reading data to / from the non-volatile memory,
First, it is assumed that the CPU 105 is in an operating state and the nonvolatile memory 106 is in a stopped state. In this state, the CPU 105 gives a command signal CMD3 to the state control circuit 107. The command signal CMD3 is a command meaning “make the nonvolatile memory 106 in an operating state”.
[0043]
In response to the command signal CMD 3, the state control circuit 107 gives an active state control signal S 1 to the nonvolatile memory 106. In response to the active state control signal S1, the nonvolatile memory 106 changes from the stopped state to the operating state. Then, the CPU 105 writes / reads data d2 to / from the nonvolatile memory 106.
[0044]
When the writing / reading of the data d2 to / from the nonvolatile memory 106 is completed, the CPU 105 gives a command signal CMD4 to the state control circuit 107. The command signal CMD4 is a command meaning “make nonvolatile memory 106 stop”.
[0045]
Upon receiving the command signal CMD4, the state control circuit 107 gives an inactive state control signal S1 to the nonvolatile memory 106. In response to the inactive state control signal S1, the nonvolatile memory 106 stops operating.
[0046]
(3) When sending data
First, it is assumed that the CPU 105 is in an operating state and the data transmission circuit 102 is in a stopped state. At this time, the CPU 105 stores data to be transmitted in the data RAM 104. Then, the CPU 105 gives a command signal CMD5 to the state control circuit 107. The command signal CMD5 is a command meaning “Make the data transmission circuit 102 in a transmission state”.
[0047]
Upon receiving the command signal CMD5, the state control circuit 107 gives an inactive state control signal S2 to the CPU 105. In response to the inactive state control signal S2, the CPU 105 stops its operation. The state control circuit 107 gives an active state control signal S3 to the data transmission circuit 102. In response to the active state control signal S3, the data transmission circuit 102 changes from the stopped state to the transmitting state.
[0048]
The data transmission circuit 102 gives an interrupt signal C1 to the state control circuit 107. The interrupt signal C1 is a signal indicating a request “make the DMA circuit 103 in an operating state”.
[0049]
In response to the interrupt signal C 1, the state control circuit 107 gives an active state control signal S 4 to the DMA circuit 103. In response to the active state control signal S4, the DMA circuit 103 changes from the stopped state to the operating state. Then, the DMA circuit 103 controls the data RAM 104 to be in an operating state, reads the data d3 in 8-bit units from the data RAM 104, and transfers it to the data transmission circuit 102. When the transfer is completed, the DMA circuit 103 and the data RAM 104 are stopped.
[0050]
The data transmission circuit 102 processes the 8-bit data d3 from the DMA circuit 103 and transmits the processed data to the antenna 101.
[0051]
Processing from reading by the DMA circuit 103 to transmission by the data transmission circuit 102 is repeatedly performed for each 8-bit data.
[0052]
When the processing for all data to be transmitted is completed, that is, when the transmission processing is completed, the data transmission circuit 102 gives an interrupt signal C2 to the state control circuit 107. The interrupt signal C2 is a signal indicating a request “make the CPU 105 in an operating state”.
[0053]
In response to the interrupt signal C 2, the state control circuit 107 gives an active state control signal S 2 to the CPU 105. In response to the active state control signal S2, the CPU 105 returns from the stopped state to the operating state. The restored CPU 105 gives a command signal CMD2 to the state control circuit 107. The command signal CMD2 is a command that means “make the data transmission circuit 102 stop”.
[0054]
Upon receiving the command signal CMD2, the state control circuit 107 gives an inactive state control signal S3 to the data transmission circuit 102. In response to the inactive state control signal S3, the data transmission circuit 102 changes from the transmission state to the stop state.
[0055]
<About state transition>
FIG. 3 is a diagram showing state transitions of the CPU 105, nonvolatile memory 106, state control circuit 107, data RAM 104, DMA circuit 103, and data transmission circuit 102 shown in FIG. In FIG. 3, the period (1)-(3) corresponds to the period (1)-(3) shown in FIG. Further, “motion” means “operation state”, and “stop” means “stop state”.
[0056]
Referring to FIG. 3, CPU 105 and non-volatile memory 106 are in a stopped state while data transmission circuit 102 is in a receiving state and is processing a received signal.
[0057]
Further, the CPU 105 and the nonvolatile memory 106 are also stopped during the period in which the data transmission circuit 102 is in a transmission state and outputs a transmission signal.
[0058]
On the other hand, during a period in which the CPU 105 is in an operating state, the data transmission circuit 102 is stopped.
[0059]
As described above, the data transmission circuit 102, the CPU 105, and the nonvolatile memory 106 operate exclusively.
[0060]
The DMA circuit 103 is in an operating state during a data transfer period when the data transmission circuit 102 is in a reception state or a transmission state. The data RAM 104 is in an operating state during a period in which the data transmission circuit 102 is in a receiving state or a transmitting state and the DMA circuit 103 is in an operating state, and a period in which the CPU 105 is in an operating state. The state control circuit 107 is always in an operating state.
[0061]
The reception signal and the transmission signal are composed of an SOF (Start Of Frame), a data portion, and an EOF (End Of Frame), and comply with the regulations of ISO / IEC 144443-3.
[0062]
As described above, in the IC card according to the first embodiment, the period during which the data transmission circuit 102 is in the reception state and processes the reception signal and the period during which the data transmission circuit 102 is in the transmission state and outputs the transmission signal. The CPU 105 and the nonvolatile memory 106 are stopped. Therefore, it is possible to suppress the influence on the data transmission circuit 102 caused by the noise generated by the operation of the CPU 105 and the nonvolatile memory 106. Thereby, the reliability of the transmission / reception process by the data transmission circuit 102 can be improved. Similarly, even when one reader / writer reads / writes a plurality of IC cards at the same time, when the transmission circuit inside each IC card transmits / receives data to / from the outside, the nonvolatile memory inside each IC card Since the CPU and the CPU stop operating, mutual interference due to mutual noise generation can be prevented, and reliability in transmission / reception of a plurality of IC cards can be improved.
[0063]
(Second Embodiment)
<Configuration>
An IC card according to the second embodiment of the present invention includes a data transmission circuit 400 shown in FIG. 4 in place of the data transmission circuit 102 shown in FIG. Referring to FIG. 4, data transmission circuit 400 has the function of data transmission circuit 102 shown in FIG. 1, and further includes transmission / reception processing circuit 401 and data transfer timing generation circuit 402.
[0064]
The transmission / reception processing circuit 401 determines the state of a reception signal from an analog circuit unit (not shown) in the data transmission circuit 400 and a transmission signal to the analog circuit unit in accordance with the regulations of ISO / IEC144443-3, and indicates the state. Status information SMT is output.
[0065]
The data transfer timing generation circuit 402 includes status information SMT indicating that “the signal currently received by the data transmission circuit 400 is a stop bit period”, and “the signal currently transmitted by the data transmission circuit 400 is SOF. When the status information SMT indicating "H level (logic high level) period" and the status information SMT indicating "the signal currently transmitted by the data transmission circuit 400 is a stop bit period" are received, the status control is performed. An interrupt signal C3 is output to the circuit 107.
[0066]
<Operation>
Next, the operation of the IC card configured as described above will be described.
[0067]
As described above, data to be transmitted or received is composed of an SOF, a data part, and an EOF, and conforms to the provisions of ISO / IEC 14443-3. As shown in FIG. 5, the data portion conforms to the character format defined in ISO / IEC 14443-3. The character includes a start bit that is a first logic level, 8-bit data that is a second logic level, a stop bit that is a third logic level, and a protection time.
[0068]
Hereinafter, (a) when receiving data, and (b) when transmitting data, the description will be divided.
[0069]
(A) When receiving data
This corresponds to the case of (1) reception shown in FIG.
[0070]
First, when the data transmission circuit 102 is in a reception state, a reception signal is input to the transmission / reception processing circuit 401.
[0071]
The transmission / reception processing circuit 401 determines the state of the received signal in accordance with the provisions of ISO / IEC 144443-3, and outputs state information SMT indicating the state.
[0072]
Upon receiving the status information SMT from the transmission / reception processing circuit 401, the data transfer status control circuit 403 indicates that the status information SMT indicates that “the signal currently received by the data transmission circuit 400 is a stop bit period”. It is determined whether or not. As a result, when the status information SMT indicates that “the signal currently received by the data transmission circuit 400 is the stop bit period”, the interrupt signal C3 is output to the status control circuit 107. This corresponds to the process of giving the interrupt signal C1 in FIG.
[0073]
In response to the interrupt signal C 3, the state control circuit 107 gives an active state control signal S 4 to the DMA circuit 103. This corresponds to the case where the active state signal S4 is given in FIG.
[0074]
In response to the active state control signal S4, the DMA circuit 103 changes from the stopped state to the operating state. Then, the DMA circuit 103 controls the data RAM 104 to be in an operating state, and writes the 8-bit data d1 from the data transmission circuit 102 to the data RAM 104. When the transfer is completed, the DMA circuit 103 and the data RAM 104 are stopped.
[0075]
(B) When sending data
This corresponds to the case of (3) transmission shown in FIG.
[0076]
The transmission / reception processing circuit 401 receives a signal transmitted from the data transmission circuit 102. Then, the transmission / reception processing circuit 401 determines the state of the transmission signal in accordance with the regulations of ISO / IEC144443-3, and outputs state information SMT indicating the state.
[0077]
Upon receiving the state information SMT from the transmission / reception processing circuit 401, the data transfer state control circuit 403 indicates that the state information SMT is “the signal currently transmitted by the data transmission circuit 400 is in the SOF H level (logic high level) period. It is determined whether or not it indicates that “there is a signal that the data transmission circuit 400 is currently transmitting is a stop bit period”. As a result, when the state information SMT indicates one, an interrupt signal C3 is output to the state control circuit 107. This corresponds to the process of giving the interrupt signal C1 in FIG.
[0078]
In response to the interrupt signal C 3, the state control circuit 107 gives an active state control signal S 4 to the DMA circuit 103. This corresponds to the case where the active state signal S4 is given in FIG.
[0079]
In response to the active state control signal S4, the DMA circuit 103 changes from the stopped state to the operating state. Then, the DMA circuit 103 controls the data RAM 104 to be in an operating state, reads the data d3 in 8-bit units from the data RAM 104, and transfers it to the data transmission circuit 102. When the transfer is completed, the DMA circuit 103 and the data RAM 104 are stopped.
[0080]
FIG. 6 is a diagram illustrating timings of the reception signal, the transmission signal, and the interrupt signal C3. As shown in FIG. 6, the data transfer timing generation circuit 402 outputs an interrupt signal C3 in a period between a certain 8-bit data period and another 8-bit data period in the reception signal or transmission signal.
[0081]
As described above, in the second embodiment, since the transmission / reception processing circuit 401 and the data transfer timing generation circuit 402 are provided, there is a period in which a signal received or transmitted by the data transmission circuit 102 is 8-bit data. Data can be transferred by the DMA circuit 102 during a period between other 8-bit data periods. As a result, it is possible to prevent the signal transmitted / received by the data transmission circuit 102 from being garbled due to the influence of noise generated by the operation of the DMA circuit 102.
[0082]
(Third embodiment)
In the data transmission circuit 102 shown in FIG. 1, a signal received by the antenna 101 is processed. Recovery Digital data by analog circuit parts (not shown) Recovery As a result, a received signal as shown in FIG. 7 is obtained. As shown in FIG. 7, the received signal is composed of an SOF, a data portion, and an EOF, and is at a logic high level when the data transmission circuit 102 is in a state other than the reception state. Further, as shown in FIG. 8, the SOF configuration conforms to the configuration defined in ISO / IEC144443-3. The SOF has a first logic level falling, a second logic level 10 etu period Low (logical low level), a third logic level rising within 1 etu, and a fourth logic level. It is composed of a certain 2 to 3 etu period High (logic high level). Note that etu is a unit indicating time.
[0083]
However, the analog circuit unit is affected by noise generated by the operation of the CPU 105, the nonvolatile memory 106, and the like when the data transmission circuit 102 is in a state other than the reception state, and the received signal is received when the data transmission circuit 102 is in a state other than the reception state. May become a logic low level. As a result, there arises a disadvantage that the SOF cannot be correctly recognized in the logic circuit section provided at the subsequent stage of the analog circuit section. The IC card according to the third embodiment aims to solve such a problem.
[0084]
<Configuration>
The IC card according to the third embodiment of the present invention includes a data transmission circuit 700 shown in FIG. 9 instead of the data transmission circuit 102 shown in FIG. Referring to FIG. 9, data transmission circuit 700 has the function of data transmission circuit 102 shown in FIG. 1, and further includes a normal waveform storage circuit 701, an error prediction waveform storage circuit 702, and a received waveform detection circuit 703. A waveform pattern matching circuit 704.
[0085]
The normal waveform storage circuit 701 stores a waveform pattern of SOF in accordance with the regulations of ISO / IEC144443-3. The error prediction waveform storage circuit 702 stores an erroneous waveform pattern predicted in advance. For example, when the analog circuit unit is affected by noise generated by the operation of the CPU 105, the nonvolatile memory 106, and the like when the data transmission circuit 102 is in a state other than the reception state, the waveform pattern of the SOF of the reception signal is ISO / IEC14443. The waveform falls at a time earlier than the fall, which is the first logic level defined in -3. Such an erroneous waveform pattern expected in advance is stored. The reception waveform detection circuit 703 detects the SOF waveform pattern of the reception signal that is an output from the analog circuit unit. The waveform pattern matching circuit 704 uses either the waveform pattern stored in the normal waveform storage circuit 701 or the waveform pattern stored in the error prediction waveform storage circuit 702 as the SOF waveform pattern detected by the received waveform detection circuit 703. Determine whether they match. If it matches any of these, the waveform pattern of the SOF of the received signal is corrected to the waveform pattern stored in the normal waveform storage circuit 701.
[0086]
<Operation>
Next, the operation of the IC card configured as described above will be described with reference to FIG.
[0087]
A waveform pattern conforming to the regulations of ISO / IEC144443-3 is stored in the normal waveform storage circuit 701 in advance, and an expected incorrect waveform pattern is stored in the error prediction waveform storage circuit 702 in advance.
[0088]
In step ST1001, the reception waveform detection circuit 703 detects the SOF waveform pattern of the reception signal that is output from the analog circuit unit.
[0089]
Next, in step ST1002, the SOF waveform pattern of the received signal is collated with the waveform pattern stored in the normal waveform storage circuit 701 and the waveform pattern stored in the error prediction waveform storage circuit 702.
[0090]
Next, in step ST1003, it is determined whether or not the waveform pattern of the SOF of the received signal matches the waveform pattern stored in the normal waveform storage circuit 701 or the waveform pattern stored in the error prediction waveform storage circuit 702.
[0091]
If it is determined that they match any one, the process proceeds to step ST1004. In step ST1004, the SOF waveform pattern of the received signal is corrected to the waveform pattern stored in the normal waveform storage circuit 701.
[0092]
If it is determined that they do not match any of them, the process returns to step ST1001.
[0093]
As described above, according to the third embodiment, when a received signal includes an error that is predicted in advance, this can be corrected. As a result, it is possible to avoid the inconvenience that the SOF cannot be correctly recognized in the logic circuit section provided in the subsequent stage of the analog circuit section.
[0094]
Here, the number of expected error waveform storage circuits 702 is one, but a plurality of them may be provided. As a result, it is possible to correct more patterns of errors included in the received signal.
[0095]
(Fourth embodiment)
<Configuration>
The IC card according to the fourth embodiment of the present invention includes a data transmission circuit 1100 and a CPU 1110 shown in FIG. 11 instead of the data transmission circuit 102 and the CPU 105 shown in FIG.
[0096]
Referring to FIG. 11, data transmission circuit 1100 includes a transmission / reception circuit 1101 and a demodulation circuit 1102. The transmission / reception circuit 1101 transmits a signal received by the antenna 101 to the demodulation circuit 1102. The demodulation circuit 1102 converts the signal from the transmission / reception circuit 1101 into a digital signal. Recovery Adjust and output. The signal output from the demodulation circuit 1102 is the same as the received signal shown in FIG. A signal output from the demodulation circuit 1102 is processed by a logic circuit unit (not shown) in the subsequent stage and transferred by the DMA circuit 103. Further, the demodulation circuit 1102 sets the level of the output signal to a logic high level in response to the active preset signal PR.
[0097]
The CPU 1110 includes preset signal generation means 1111. The preset signal generator 1111 provides the demodulator circuit 1102 with a preset signal PR that is active for a predetermined period of time during which the data transmission circuit 1100 is in a state other than the reception state.
[0098]
<Operation>
As shown in FIG. 7, the signal output from the demodulation circuit 1102 is at a logic high level when the data transmission circuit 102 is in a state other than the reception state. However, when the data transmission circuit 102 is in a state other than the reception state, the demodulation circuit 1102 malfunctions due to noise caused by the operation of the CPU 105 and the nonvolatile memory 106 or performing transmission processing, as shown in FIG. In addition, the signal output from the demodulation circuit 1102 may become a logic low level. When the signal output from the demodulation circuit 1102 enters the reception state with the logic low level, the trailing edge of the SOF cannot be correctly recognized in the logic circuit portion provided in the subsequent stage.
[0099]
In the IC card according to the fourth embodiment, as shown in FIG. 12, the preset signal generator 1111 sends the preset signal PR active for a predetermined period to the demodulator circuit 1102 during the period when the data transmission circuit 1100 is in a state other than the reception state. give. In response to this active preset signal PR, the demodulation circuit 1102 sets the level of the output signal to a logic high level. Thereby, even if the signal output from the demodulation circuit 1102 becomes a logic low level, the signal output from the demodulation circuit 1102 can be prevented from entering the reception state with the logic low level. As a result, the falling edge of the SOF is correctly recognized in the logic circuit section provided in the subsequent stage.
[0100]
(Fifth embodiment)
<Configuration>
The IC card according to the fifth embodiment of the present invention is characterized in that a hold signal generating means 1301 shown in FIG. 13 is provided in place of the preset signal generating means 1111 shown in FIG.
[0101]
Referring to FIG. 13, hold signal generating means 1301 provides demodulator circuit 1102 with hold signal HL that is active during a period when data transmission circuit 1100 is in a state other than the reception state. In response to the active hold signal HL, the demodulation circuit 1102 sets the level of the output signal to a logic high level.
[0102]
<Operation>
In the IC card configured as described above, as shown in FIG. 14, the hold signal generating means 1301 provides the demodulating circuit 1102 with the hold signal HL that is active while the data transmission circuit 1100 is in a state other than the reception state. In response to the active hold signal HL, the demodulation circuit 1102 sets the level of the output signal to a logic high level. As a result, it is possible to prevent the signal output from the demodulation circuit 1102 from entering the reception state with the logic low level. As a result, the falling edge of the SOF is correctly recognized in the logic circuit portion provided in the subsequent stage.
[0103]
(Sixth embodiment)
FIG. 15 is a block diagram showing the configuration of the main part of an IC card according to the sixth embodiment of the present invention. Referring to FIG. 15, this IC card is characterized in that a resume circuit 1501 is provided in state control circuit 107. Other configurations are the same as those of the IC card shown in FIG.
[0104]
When the nonvolatile memory 106 changes from the operating state to the stopped state, the resume circuit 1501 stores the time during which the writing process is performed on the nonvolatile memory 106, the address and the data where the writing process has been performed.
[0105]
Next, the operation of the IC card configured as described above will be described with reference to FIG.
[0106]
When data is written to the nonvolatile memory 106, first, the CPU 105 gives a command signal CMD3 to the state control circuit 107. The command signal CMD3 is a command meaning “make the nonvolatile memory 106 in an operating state”.
[0107]
In response to the command signal CMD 3, the state control circuit 107 gives an active state control signal S 1 to the nonvolatile memory 106. In response to the active state control signal S1, the nonvolatile memory 106 changes from the stopped state to the operating state.
[0108]
On the other hand, the resume circuit 1501 starts counting time in response to the command signal CMD3.
[0109]
In order to completely write data to the nonvolatile memory 106, a voltage must be applied for a certain period of time. Here, it is assumed that a voltage needs to be applied for a period of 10 ms. The CPU 105 refers to the time indicated by the resume circuit 1501 after starting the writing process to the nonvolatile memory 106. When the time reaches 10 ms, it is determined that the data has been completely written. Then, the CPU 105 gives a command signal CMD4 to the state control circuit 107. The command signal CMD4 is a command meaning “make nonvolatile memory 106 stop”.
[0110]
Upon receiving the command signal CMD4, the state control circuit 107 gives an inactive state control signal S1 to the nonvolatile memory 106. In response to the inactive state control signal S1, the nonvolatile memory 106 stops operating.
[0111]
Here, processing when a transmission processing command is issued from the CPU 105 before the time indicated by the resume circuit 1501 reaches 10 ms after the writing processing to the nonvolatile memory 106 is started will be described.
[0112]
It is assumed that the CPU 105 gives the command signal CMD5 to the state control circuit 107 before the time indicated by the resume circuit 1501 reaches 10 ms, for example, 7 ms. The command signal CMD5 is a command meaning “Make the data transmission circuit 102 in a transmission state”.
[0113]
In response to the command signal CMD5, the resume circuit 107 indicates the state of the writing process at that time, that is, the address and data that have been subjected to the writing process, and the time required for the writing process so far (here, 7 ms). Remember.
[0114]
On the other hand, upon receiving the command signal CMD5, the state control circuit 107 gives an inactive state control signal S2 to the CPU 105. In response to the inactive state control signal S2, the CPU 105 stops its operation. The state control circuit 107 gives an active state control signal S3 to the data transmission circuit 102. In response to the active state control signal S3, the data transmission circuit 102 changes from the stopped state to the transmitting state. Thereafter, transmission processing is performed in the same manner as shown in FIG.
[0115]
When the transmission process is completed, the data transmission circuit 102 gives an interrupt signal C2 to the state control circuit 107. The interrupt signal C2 is a signal indicating a request “make the CPU 105 in an operating state”.
[0116]
In response to the interrupt signal C 2, the state control circuit 107 gives an active state control signal S 2 to the CPU 105. In response to the active state control signal S2, the CPU 105 returns from the stopped state to the operating state.
[0117]
The restored CPU 105 gives a command signal CMD2 to the state control circuit 107. The command signal CMD2 is a command that means “make the data transmission circuit 102 stop”. Upon receiving the command signal CMD2, the state control circuit 107 gives an inactive state control signal S3 to the data transmission circuit 102. In response to the inactive state control signal S3, the data transmission circuit 102 changes from the transmission state to the stop state.
[0118]
Further, the restored CPU 105 gives a command signal CMD3 to the state control circuit 107. The command signal CMD3 is a command meaning “make the nonvolatile memory 106 in an operating state”. When receiving the command signal CMD3, the state control circuit 107 provides an active state control signal S1. In response to the active state control signal S1, the nonvolatile memory 106 enters an operating state. The CPU 105 restarts the writing process from the state (address, data, time required for processing) stored in the resume circuit 1501. The resume circuit 1501 counts the time from the continuation of the stored time (here, 7 ms).
[0119]
When the time reaches 10 ms, the CPU 105 gives a command signal CMD4 to the state control circuit 107. The command signal CMD4 is a command meaning “make nonvolatile memory 106 stop”. Upon receiving the command signal CMD4, the state control circuit 107 gives an inactive state control signal S1 to the nonvolatile memory 106. In response to the inactive state control signal S1, the nonvolatile memory 106 stops operating.
[0120]
Even when a reception processing command is issued from the CPU 105 before the time indicated by the resume circuit 1501 reaches 10 ms after starting the writing process to the nonvolatile memory 106, the same processing as described above is performed. Is done.
[0121]
<Flowchart>
FIG. 17 is a flowchart showing a flow of a writing process to the nonvolatile memory by the IC card shown in FIG. Hereinafter, the flow of processing will be described with reference to FIG.
[0122]
First, in step ST1701, it is determined whether or not writing to the nonvolatile memory 106 is performed. In the case of performing the writing process, the process proceeds to step ST1701.
[0123]
Next, in step ST1702, it is determined whether or not the previous writing process has been completed. This is done by referring to the time stored in the resume circuit 1501. If the time stored in the resume circuit 1501 has not reached the time necessary for complete writing, it is determined that the previous writing has been interrupted, and the process proceeds to step ST1703.
[0124]
In step ST1703, the CPU 105 resumes the writing process from the state (address, data, time required for processing) stored in the resume circuit 1501. The resume circuit 1501 counts the time from the continuation of the stored time.
[0125]
On the other hand, if the time stored in the resume circuit 1501 has reached the time necessary for complete writing in step ST1702, it is determined that the previous writing has been completed, and the process goes to step ST1704. move on.
[0126]
In step ST1704, the CPU 105 starts the writing process from the beginning. The resume circuit 1501 counts time from one.
[0127]
Next, in step ST1705, when transmission / reception processing is started when the time counted by the resume circuit 1501 has not yet reached the time necessary for complete writing, the process proceeds to step ST1706.
[0128]
In step ST1706, the resume circuit 107 stores the state of the write process at that time, that is, the address, data, and the time required for the write process so far. Then, the process returns to step ST1701.
[0129]
On the other hand, if the transmission / reception process is not started in step ST1705, the process proceeds to step ST1707. In step ST1707, it is determined whether the time counted by the resume circuit 1501 has reached the time necessary for complete writing. If it has reached, the process proceeds to step ST1708 and the writing process is terminated.
[0130]
As described above, since the IC card according to the sixth embodiment of the present invention is provided with the resume circuit 1501, even if the writing process to the nonvolatile memory 106 is interrupted because the transmission / reception processing command is issued, the interrupt is interrupted. The writing process can be resumed from the state at the time.
[0131]
(Seventh embodiment)
FIG. 18 is a block diagram showing the configuration of the main part of an IC card according to the seventh embodiment of the present invention. Referring to FIG. 18, this IC card is characterized in that a time count circuit 1801 is provided in state control circuit 107. Other configurations are the same as those of the IC card shown in FIG.
[0132]
The time count circuit 1801 starts counting time in response to the command signals CMD1 and CMD5 from the CPU 105. The command signal CMD1 is a command meaning “Make the data transmission circuit 102 in a receiving state”. The command signal CMD5 is a command meaning “Make the data transmission circuit 102 in a transmission state”. In response to the interrupt signal C 2 from the data transmission circuit 102, the time count is stopped and the count value is output to the CPU 105.
[0133]
Next, the operation of the IC card configured as described above will be described.
[0134]
When the command signal CMD1 or CMD5 is supplied from the CPU 105 to the state control circuit 107, the time counting circuit 1801 starts counting time. In response to the command signals CMD1 and CMD5, the IC card performs reception processing or transmission processing.
[0135]
When the reception process or the transmission process is completed, the data transmission circuit 102 gives an interrupt signal C2 to the state control circuit 107. The interrupt signal C2 is a signal indicating a request “make the CPU 105 in an operating state”.
[0136]
In response to the interrupt signal C2, the time count circuit 1801 stops counting time and outputs the count value to the CPU 105.
[0137]
As shown in FIG. 7, when the data transmission circuit 102 is in a reception state or a transmission state, the CPU 105 is stopped. However, when the CPU 105 returns from the stopped state to the operating state, the CPU 105 needs to know the time during which it was in the stopped state (the system time required for reception and the system time required for transmission shown in FIG. 7). When the timer attached to the CPU 105 is used to know the time during which it was stopped, the CPU 105 operates at regular intervals when the data transmission circuit 102 is in the reception state or transmission state. Noise is generated by the operation of the CPU 105, and this noise may affect the data transmission circuit 102 in the reception state or transmission state.
[0138]
In the IC card shown in FIG. 18, since the time count circuit 1801 is provided, the CPU 105 can be completely stopped when the data transmission circuit 102 is in a reception state or a transmission state. As a result, the CPU 105 can be informed of the time during which the CPU 105 was stopped without generating noise due to the operation of the CPU 105.
[0139]
(Eighth embodiment)
FIG. 19 is a block diagram showing a configuration of a main part of an IC card according to the eighth embodiment of the present invention. Referring to FIG. 19, this IC card is characterized in that a time monitoring circuit 1901 is provided in state control circuit 107. Other configurations are the same as those of the IC card shown in FIG.
[0140]
The time monitoring circuit 1901 starts counting time in response to the command signal CMD1 from the CPU 105. The command signal CMD1 is a command meaning “Make the data transmission circuit 102 in a receiving state”. Then, the time monitoring circuit 1901 stops counting time and resets the count value in response to the interrupt signal C2 from the data transmission circuit 102. On the other hand, when the time count value reaches a predetermined value, that is, when the interrupt signal C2 is not given to the state control circuit 107 until the count value reaches the predetermined value, the time monitoring circuit 1901 times out. A signal TO is output to the CPU 105.
[0141]
Next, the operation of the IC card configured as described above will be described.
[0142]
When the command signal CMD1 is given from the CPU 105 to the state control circuit 107, the time monitoring circuit 1901 starts counting time. In response to the command signal CMD1, the data transmission circuit 102 enters a reception state.
[0143]
When the reception process is completed, the data transmission circuit 102 gives an interrupt signal C2 to the state control circuit 107. The interrupt signal C2 is a signal indicating a request “make the CPU 105 in an operating state”.
[0144]
In response to the interrupt signal C2, the time monitoring circuit 1901 stops counting the time and resets the count value.
[0145]
If the interrupt signal C2 is not given to the state control circuit 107 before the time count value by the time monitoring circuit 1901 reaches a predetermined value, the time monitoring circuit 1901 outputs a timeout signal TO to the CPU 105.
[0146]
In response to the timeout signal TO, the CPU 105 returns to the operating state and performs a timeout process.
[0147]
As described above, in the IC card according to the ninth embodiment, since the time monitoring circuit 1901 is provided, when the interrupt signal C2 is not given to the state control circuit 107 until the count value reaches a predetermined value, The CPU 105 can be returned from the stopped state to the operating state. As a result, it is possible to prevent the CPU 105 from being in the stopped state when the data transmission circuit 102 cannot receive the received data for a long time after the receiving state.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an IC card according to a first embodiment of the present invention.
2 is a diagram showing a flow of processing in the IC card shown in FIG. 1. FIG.
3 is a diagram showing state transitions of the CPU, nonvolatile memory, state control circuit, data RAM, DMA circuit, and data transmission circuit shown in FIG. 1;
FIG. 4 is a block diagram showing a configuration of a data transmission circuit in an IC card according to a second embodiment of the present invention.
FIG. 5 is a diagram showing a character format defined in ISO / IEC144443-3.
FIG. 6 is a diagram illustrating timings of a reception signal, a transmission signal, and an interrupt signal.
FIG. 7 is a diagram illustrating states of a reception signal, a transmission signal, a data transmission circuit, and a CPU.
FIG. 8 is a diagram showing a configuration of an SOF defined in ISO / IEC 144443-3.
FIG. 9 is a block diagram showing a configuration of a data transmission circuit in an IC card according to a third embodiment of the present invention.
FIG. 10 is a flowchart showing an operation of an IC card according to a third embodiment of the present invention.
FIG. 11 is a block diagram showing a configuration of a data transmission circuit and a CPU in an IC card according to a fourth embodiment of the present invention.
FIG. 12 is a diagram illustrating a relationship between a reception signal and a preset signal.
FIG. 13 is a block diagram showing a configuration of a data transmission circuit and a CPU in an IC card according to a fifth embodiment of the present invention.
FIG. 14 is a diagram illustrating a relationship between a reception signal and a hold signal.
FIG. 15 is a block diagram showing a configuration of a main part of an IC card according to a sixth embodiment of the present invention.
16 is a diagram for explaining the operation of the IC card shown in FIG.
17 is a flowchart showing a flow of a writing process to the nonvolatile memory by the IC card shown in FIG.
FIG. 18 is a block diagram showing a configuration of a main part of an IC card according to a seventh embodiment of the present invention.
FIG. 19 is a block diagram showing a configuration of a main part of an IC card according to an eighth embodiment of the present invention.

Claims (6)

A non-contact type IC card that sends and receives data to / from the outside without contact and receives power from the outside,
A transmission circuit for sending and receiving data to and from the outside;
Buffer memory,
A DMA circuit for transferring the data received by the transmission circuit to the buffer memory and transferring the data stored in the buffer memory to the transmission circuit;
Non-volatile memory;
A CPU for writing / reading data to / from the buffer memory and the nonvolatile memory;
A state control means for stopping the operation of the nonvolatile memory and the CPU when the transmission circuit is transmitting / receiving data to / from the outside ;
The data received by the transmission circuit has a frame configuration and a character configuration in accordance with ISO / IEC144443-3 regulations,
The transmission circuit is
Normal waveform storage means for storing a waveform pattern of SOF (Start OF Frame) defined by ISO / IEC144443-3;
An error prediction waveform storage means for storing a waveform pattern including an error predicted in advance for data received by the transmission circuit;
Waveform detection means for detecting a waveform pattern of data received by the transmission circuit;
When the waveform pattern detected by the waveform detection means matches the waveform pattern stored in the normal waveform storage means or the waveform pattern stored in the error prediction waveform storage means, the data received by the transmission circuit is An IC card comprising: matching means for correcting based on the normal waveform pattern . In the IC card according to claim 1,
The data received by the transmission circuit has a frame configuration and a character configuration in accordance with ISO / IEC144443-3 regulations,
The transmission circuit includes an analog circuit unit that demodulates and outputs digitally received data received from the outside,
The IC card further comprises preset signal generating means for providing the analog circuit unit with a preset signal active for a predetermined period of time other than a period in which the transmission circuit is receiving data,
In the IC card, the analog circuit unit outputs a logic high level in response to the active preset signal. In the IC card according to claim 1,
The data received by the transmission circuit has a frame configuration and a character configuration in accordance with ISO / IEC144443-3 regulations,
The transmission circuit includes an analog circuit unit that demodulates and outputs digitally received data received from the outside,
The IC card further comprises hold signal generating means for supplying the analog circuit unit a hold signal that is active for a period other than a period in which the transmission circuit is receiving data.
In the IC card, the analog circuit unit sets an output to a logic high level in a period other than a period in which the transmission circuit is receiving data in response to the active hold signal. In the IC card according to claim 1,
A resume circuit for storing a progress state of the writing process up to the point of interruption when the data writing process to the nonvolatile memory by the CPU is interrupted;
The CPU restarts the writing process to the nonvolatile memory based on the progress state stored in the resume circuit. In the IC card according to claim 1,
The state control circuit includes:
Time to start counting time in response to the CPU being stopped, stopping time counting in response to the next return of the CPU to the operating state, and outputting the count value to the CPU An IC card comprising a count circuit. In the IC card according to claim 1,
Time to start counting time in response to the CPU being stopped, and to output a timeout signal to the CPU when the CPU does not return to the operating state until the count value reaches a predetermined value A monitoring circuit;
The IC card, wherein the CPU enters an operating state in response to a time-out signal from the time monitoring circuit.

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