JP3775462B2 - Debug system and information storage medium - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a debugging system and an information storage medium used for the debugging system.
[0002]
[Background Art and Problems to be Solved by the Invention]
In recent years, there has been an increasing demand for microcomputers that are incorporated in electronic devices such as game devices, car navigation systems, printers, and portable information terminals, and that can realize advanced information processing. Such an embedded microcomputer is usually mounted on a user board called a target system. A software development support tool called ICE (In-Circuit Emulator) is widely used to support development of software for operating the target system.
[0003]
As such an ICE, an ICE called a CPU replacement type as shown in FIG. In this CPU replacement type ICE, the microcomputer 302 is removed from the target system 300 during debugging, and the probe 306 of the debugging tool 304 is connected instead. Then, the debugging tool 304 is made to emulate the operation of the removed microcomputer 302. Further, the debug tool 304 is caused to perform various processes necessary for acquiring trace information and debugging.
[0004]
However, in this CPU replacement type ICE, when the internal operating frequency of the microcomputer 302 increases, real-time tracing becomes difficult due to signal delay generated in the probe 306 and a buffer for storing trace information.
[0005]
In order to solve such problems, a system that enables real-time tracing on a mass-produced chip has been developed. At this time, in order to store information such as an address bus as trace information in the trace buffer in real time, several tens of dedicated terminals are required. Here, the number of such terminals is necessary only for debugging and unnecessary for the end user.
[0006]
Therefore, the present applicant has developed a system that outputs trace information for realizing real-time trace to four dedicated terminals, and enables real-time trace from this trace information.
[0007]
Specifically, CPU execution status information is output to 3 terminals every clock, and when an absolute branch is generated by an absolute branch instruction or the like, the branch destination PC value is serially output to 1 terminal in the following 27 clock cycles. An absolute branch instruction is an instruction whose branch destination address is determined by a register value or the like during execution of a program and cannot be determined from an instruction code. Therefore, when an absolute branch instruction is generated, the branch destination cannot be determined from the instruction code of the program, so that tracing can be performed by outputting the PC value of the branch destination.
[0008]
However, since the target system does not output the value of the program counter until an absolute branch occurs, there is a problem that the program counter value cannot be grasped during this time and trace information cannot be generated.
[0009]
In addition, in order to minimize the number of debugging terminals as much as possible, the target system under development by the present applicant does not distinguish between the case where an absolute branch occurs due to an absolute branch instruction and the case where an absolute branch occurs due to an interrupt. Status information indicating instruction execution was output. For this reason, in the case of status information of absolute branch instruction execution, there is a problem that it cannot be distinguished whether it is due to instruction execution or due to an interrupt.
[0010]
The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide a debugging system capable of generating real-time trace on a mass-produced chip with few terminals and generating trace information. And providing an information storage medium. More specifically, it is possible to provide a debugging system and an information storage medium capable of generating trace information even before the occurrence of an absolute branch, and to determine whether the status information of the absolute branch occurrence is due to execution of an absolute branch instruction or due to an interrupt. A debugging system and an information storage medium are provided.
[0011]
[Means for Solving the Problems]
The present invention provides status information for determining whether the execution state of the CPU belongs to normal instruction execution, absolute branch instruction execution, or relative branch instruction execution, and trace information of the target system that outputs the branch destination address of the absolute branch instruction Is executed by the means for receiving the status information from the target system and storing it in the memory without overwriting, the execution start address of the target system and the target CPU of the debug system. Trace information generating means for generating trace information before the occurrence of an absolute branch instruction based on information for grasping a machine language instruction sequence of the program.
[0012]
The information storage medium according to the present invention includes information for realizing the above means.
[0013]
Here, the information for grasping the machine language instruction string of the program executed by the target system may be a machine language instruction code string expressed in binary or hexadecimal notation, or a machine language instruction code string. An instruction code string represented by a mnemonic code may be used. It suffices that at least the machine language instruction sequence executed by the CPU of the target system can be grasped.
[0014]
In the present invention, status information received from the target system is stored in the trace memory without being overwritten. For this reason, particularly when range specification tracing or the like is not performed, status information from the start of execution is accumulated from the top of the trace memory. Therefore, the debug system can generate trace information after the start of accumulation in the memory and before the occurrence of the absolute branch instruction based on the execution start address of the target system and the contents of the program executed on the target system.
[0015]
According to the present invention, even when debugging a target system having a small number of debugging terminals, the trace information of the entire execution range can be obtained without being restricted by the fact that the trace information before execution of the absolute branch instruction cannot be generated. be able to.
[0016]
That is, since the debug system of the present invention can generate trace information similar to that of a normal ICE or the like even from a small amount of debug information, it is possible to reduce the number of debug terminals of the target system and contribute to the cost reduction of the target system. Also have.
[0017]
The execution start address and the contents of the program executed on the target system may be stored in the debug system in advance or may be acquired later.
[0018]
For example, when the execution start address of the target system is specified from the debug system and executed, it is preferable to hold the specified execution start address. Further, when an execution program is loaded from the debug system to the target system, it is preferable to keep the loaded program content in the debug system.
[0019]
The present invention provides status information for determining whether the CPU execution state belongs to normal instruction execution, absolute branch instruction execution, or relative branch instruction execution, and whether or not the trigger point is matched, and the branch destination address of the absolute branch instruction A debug system that outputs trace information of the target system that outputs the status information, the status information received from the target system and stored in the memory, and the status information stored in the memory match the trigger point Trace information for generating trace information before the occurrence of an absolute branch instruction based on the trigger point address of the debug system and the information for grasping the machine language instruction sequence of the program executed by the target Generating means.
[0020]
The information storage medium according to the present invention includes information for realizing the above means.
[0021]
Here, the information for grasping the machine language instruction sequence of the program executed by the target may be a machine language instruction code sequence expressed in binary or hexadecimal, or the machine language instruction code sequence may be mnemonic. An instruction code sequence expressed in code may be used. It is sufficient that at least the machine language instruction code sequence executed by the target machine can be grasped.
[0022]
There may be a plurality of trigger points. The trigger point is used for designating a range to be output, and it may be the case where the status information of the designated range is output. Further, regardless of the range specification, information on whether or not the trigger point is matched may be output.
[0023]
The status information stored in the memory includes information on whether or not the trigger point is matched. Therefore, based on the trigger point address of the debug system and the contents of the program executed in the target system, it is possible to generate trace information before the absolute branch instruction is generated after the start of accumulation in the memory.
[0024]
According to the present invention, even when debugging a target system having a small number of debugging terminals, the trace information of the entire execution range can be obtained without being restricted by the fact that the trace information before execution of the absolute branch instruction cannot be generated. be able to.
[0025]
That is, since the debug system of the present invention can generate trace information similar to that of a normal ICE or the like even from a small amount of debug information, it is possible to reduce the number of debug terminals of the target system and contribute to the cost reduction of the target system. Also have.
[0026]
The trigger point address and the contents of the program executed on the target system may be stored in the debug system in advance or may be acquired later.
[0027]
For example, in the case where the trigger point address of the target system is designated and executed from the debug system, it is preferable to retain the designated trigger point address. Further, when an execution program is loaded from the debug system to the target system, it is preferable to keep the loaded program contents in the debug system.
[0028]
The present invention outputs status information for determining whether the execution state of the CPU belongs to normal instruction execution, absolute branch generation, or relative branch instruction execution, and target system trace information that outputs the branch destination address of the absolute branch instruction. Means for receiving the status information from the target system and storing it in the memory, and when the status information stored in the memory indicates the occurrence of an absolute branch, the occurrence of the absolute branch is caused by the occurrence of an interrupt. Trace information generating means for generating trace information by discriminating whether or not the program is based on information for grasping a machine language instruction sequence of the program.
[0029]
The information storage medium according to the present invention includes information for realizing the above means.
[0030]
Here, the information for grasping the machine language instruction sequence of the program executed by the target may be a machine language instruction code sequence expressed in binary or hexadecimal, or the machine language instruction code sequence may be mnemonic. An instruction code sequence expressed in code may be used. It is sufficient that at least the machine language instruction code sequence executed by the target machine can be grasped.
[0031]
An absolute branch generally occurs when an absolute branch instruction is executed or an interrupt occurs. Here, an interrupt is a kind of program branch, but is not caused by a branch instruction, but is branched by a signal of a computer hardware. In the target system of the present invention, in order to reduce the number of terminals for debugging, status information on the occurrence of an absolute branch is output without distinguishing whether an absolute branch has occurred due to an interrupt or an absolute branch due to a branch instruction. ing.
[0032]
Therefore, it is difficult to determine whether an absolute branch instruction has been executed or an interrupt has occurred from only the status information and the absolute branch destination address, and it is difficult to generate trace information.
[0033]
However, according to the present invention, it is possible to generate trace information by automatically checking whether or not the machine language instruction string of the program corresponding to the status indicating execution of the absolute branch instruction is actually an absolute branch instruction, and performing the determination. Is possible.
[0034]
According to the present invention, even when a target system having a small number of debugging terminals is debugged, it is possible to generate trace information by distinguishing between an absolute branch instruction and the occurrence of an interrupt. That is, since the debug system of the present invention can generate trace information similar to that of a normal ICE or the like even from a small amount of debug information, it is possible to reduce the number of debug terminals of the target system and contribute to the cost reduction of the target system. Also have.
[0035]
Information for grasping a machine language instruction sequence of a program executed by the target system may be stored in the debug system in advance or may be acquired later.
[0036]
For example, when a program for execution is loaded from the debug system to the target system, it is preferable to keep the loaded program contents in the debug system.
[0037]
The debugging system of the present invention further includes program information storage means for storing in advance information for grasping a machine language instruction sequence of a program executed by the target, and the trace information generation means is stored in the program information storage means. Trace information is generated using information for grasping a machine language instruction sequence of the program.
[0038]
The information storage medium according to the present invention includes information for realizing the above means.
[0039]
According to the present invention, since it is not necessary to read the memory of the target system every time the trace information is generated, the trace information can be generated even during execution of the target system. In addition, the processing time for generating trace information can be greatly reduced.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0041]
1. Outline of Configuration of the Present Embodiment First, the configuration of the present embodiment will be described with reference to FIG.
[0042]
As shown in FIG. 2, the microcomputer 10 that is a target system to be debugged includes a CPU (Central Processing Unit) 12, an execution information output unit 14, and an internal memory 16.
[0043]
Here, the execution information output unit 16 outputs execution information for realizing a real-time trace to four dedicated terminals. Specifically, CPU instruction execution status information is output to 3 terminals (DST [2: 0]) every clock, and when a PC absolute branch execution occurs, the branch destination PC value (DPCO) is output in the following 27 clock cycles. Outputs serially to one terminal.
[0044]
The internal memory 16 stores a program executed by the target system.
[0045]
The debug system 20 according to this embodiment includes a debug tool 21 that is directly connected to a target microcomputer and a host computer 23 that is connected to the debug tool.
[0046]
The debug tool 21 includes an execution information acquisition unit 22 and a target memory writing unit 28, and the host computer 23 includes a program information storage unit 26, a trace information generation unit 27, and a program information writing unit 29.
[0047]
The execution information acquisition unit 22 stores 3-bit DST [2: 0] and DPCO representing a branch destination PC (program counter) value in the internal trace memory 24. When the trace range is designated, DST [2: 0] and DPCO in the range are stored in the trace memory.
[0048]
Since the branch destination PC is serially output bit by bit from the lower bits, if a new absolute branch occurs before all bits are output, only a part of the address information of the absolute branch destination can be received. .
[0049]
The target memory writing unit 28 has a function of loading a program into the internal memory 16 of the target system and rewriting a program in the memory of the target system, and is a microcomputer via a TXD / RXD line (bidirectional communication line). Data to be written to the internal memory 14 is transmitted.
[0050]
The program information storage unit 26 stores a machine language code string of the same program as the program stored in the internal memory 16 of the target system.
[0051]
When the trace information generation unit 27 receives a part of the absolute branch destination address from the target system, the trace information generation unit 27 is based on at least one of the information on the address area where the program executed by the target system exists and the status information received from the target system. A process for generating trace information by specifying a part other than a part of the absolute branch destination address is performed. Further, a candidate address group having a part of the received address information of the absolute branch destination as a lower bit is extracted, and specified by an array of status information received from the target system and a given candidate address included in the candidate address group Compared with the array of status information predicted from the machine language code string, the address information of the absolute branch destination is specified.
[0052]
Further, processing for generating trace information before the occurrence of the absolute branch instruction is performed based on the execution start address of the target system possessed by the debug system and the machine language code string of the program executed by the target CPU.
[0053]
If the status information stored in the memory indicates that it matches the trigger point, based on the trigger point address of the debug system and the machine language code string of the program executed by the target, Performs processing to generate trace information before the occurrence of an absolute branch instruction.
[0054]
If the status information stored in the memory indicates the occurrence of an absolute branch, the trace information is generated by determining whether the occurrence of the absolute branch is due to the occurrence of an interrupt based on the machine language code string of the program. Process.
[0055]
When generating trace information, a machine language code string of a program stored in the program information storage unit 26 is used.
[0056]
The program information writing unit 29 loads the same program as the program loaded into the memory of the target system into the program information storage unit 26 or reads out the program code stored in the memory of the target system to read the program information storage unit The program stored in the program information storage unit 26 is rewritten to have the same content as the program of the target system.
[0057]
2. Contents of Status Information Output by Target System FIG. 3 is a diagram showing the relationship between the output value of DST [2: 0] (hereinafter referred to as DST information) and the instruction execution state of the CPU. Here, the PC relative branch instruction is an instruction that branches to an address explicitly described in the program, and the branch destination can be determined from the instruction code. The PC absolute branch instruction is an instruction in which the branch destination address is determined by the register value during the execution of the program, and the branch destination cannot be determined from the instruction code.
[0058]
Therefore, in this embodiment, when a PC absolute branch instruction is generated, tracing is possible by outputting the PC value (DPCO) of the branch destination.
[0059]
That is, when the microprocessor executes instructions in the order of addresses (when the DST information is 000 or 100), it can be traced from the instruction code of the program because the program counter can be known to what extent. Also, when the microprocessor executes a PC relative branch instruction (when the DST information is 001 or 101), the branch destination can be known from the instruction code of the program, so that tracing is possible.
[0060]
However, when the microprocessor executes the PC absolute branch instruction (when the DST information is 010 or 110), the branch destination is not known from the instruction code of the program, and therefore tracing cannot be performed only with the DST information. In such a case, tracing is possible by outputting the PC value (DPCO) of the branch destination.
[0061]
3. Since the processing target system for specifying the branch destination address serially outputs the PC value to one terminal, if the absolute branch instruction is executed continuously or at intervals of several instructions, the information of the PC value is halfway. There was a problem that it was interrupted and could not be traced.
[0062]
Therefore, in the present embodiment, even when only a part of the PC value information can be obtained, the trace information generation unit 27 can specify the branch destination PC value of the absolute branch based on the map information and the DST information described later. Performs processing for specifying a branch destination address as described below.
[0063]
4A and 4B are diagrams for explaining extraction of a candidate address group for specifying an absolute branch destination address.
[0064]
Reference numeral 310 in FIG. 4A represents the PC value information obtained from the DPCO signal in hexadecimal. The PC value is output 27 bits one bit at a time from the lower bits. If a new absolute branch occurs during this period, the new absolute branch destination PC value is output there. Breaks there.
[0065]
310 is a state in which the PC value is interrupted by the information 312 for the lower 12 bits, and the upper bit information 314 and 316 is not obtained. In such a case, if the first 4 bits 316 (1 digit because it is a hexadecimal code) is set to 0, the number of PC values that are absolute branch destination candidates is 2 ¹⁶ = 65536 (see 320 in FIG. 4A). Therefore, it is difficult to specify the actual PC value.
[0066]
Therefore, in the present embodiment, as shown in FIG. 4B, map information 330 of the memory to which the CPU of the target system is connected is stored in the parameter file 340 of the debug system. The map information 330 is information relating to the address where the program exists. For example, the map information 330 includes RAM1, IROM, and RAM2 connected to the target CPU, and addresses 0-7FF in RAM1, 80000-80FFF in IROM, It shows that the program is stored at address 90000-9FFFF of RAM2.
[0067]
Assuming that the lower 12 bits of the PC value are at address 802 as in FIG. 4A, there are no candidates in RAM1, 80802 is a candidate in IROM, and 16 in 90802-9F802 are candidates in RAM2. Thus, the total number of candidates is 17 (see 340 in FIG. 4B).
[0068]
FIGS. 5A to 5C are diagrams for explaining processing for specifying an absolute branch destination address from a candidate group extracted from map information. FIG. 5A shows DST information 350 after execution of an absolute branch instruction stored in the trace memory 24.
[0069]
FIG. 5B is output when the instruction code 360 and subsequent instruction codes 360, one of the candidate groups specified by the map information, the instruction type 370 of the instruction code, and the instruction code are executed. The DST information 380 that is likely to be displayed.
[0070]
FIG. 5C is output when the instruction code 390 from address 90802, which is one of the candidate groups specified by the map information, the instruction type 400 of the instruction code, and the instruction code are executed. DST information 410 that may be present. For other candidate groups, a DST information sequence that is expected to be output is generated in the same manner as in FIGS. 5B and 5C, and the DST information 350 in the trace memory 24 in FIG. Do. If they are the same, the candidate is specified as the branch destination address. Here, since the DST information sequence output by the instruction execution after address 80802 in FIG. 5B matches the DST information 350 in the trace memory 34 in FIG. 5A, the address 80802 is specified as the branch destination address. .
[0071]
6, 7, and 8 are flowcharts illustrating an operation example of processing for specifying a branch destination address when an absolute branch occurs at a short interval and the program counter value does not output all bits from the DPCO.
[0072]
First, the overall flow of the incomplete PC value analysis process will be described with reference to FIG.
[0073]
At the start of incomplete PC value analysis processing, initial setting of candidate PC value (ulWorkPc) and number of candidates (ulExpectNum) is first performed (step S10).
[0074]
In loop A (steps S20 to S40), candidate PC search processing (step S30) using map information is performed for the number of memories for which map information is defined in the parameter file. For example, in FIG. 4B, the parameter file 340 defines the map information of three memories RAM1, IROM, and RAM2, and therefore the candidate PC value search process is performed three times. In this candidate PC value search process, the candidate PC value (ulWorkPc) and the number of candidates (ulExpectNum) are updated.
[0075]
When the loop A ends, it is determined whether or not the set number of candidates (ulExpectNum) is 1. If the number of candidates (ulExpectNum) = 1, it is determined that one PC value has been specified, the candidate PC value (ulWorkPc) updated in the candidate PC value specifying process is set as the address actually executed by the CPU, and the trace is performed. Data generation processing is performed (steps S50 and S60).
[0076]
Next, a detailed process example of the candidate PC search process using the map information (step S30 in FIG. 6) will be described with reference to FIG.
[0077]
The start address (ulMapTopAddr) obtained by shifting the start address of the memory defined by the map information to the right by the number of output bits of the DPCO signal is set. Also, the end address (ulMapBottomAddr) obtained by shifting the end address of the memory defined by the map information to the right by the number of output bits of the DPCO signal is set.
[0078]
For example, as described in FIGS. 4A and 4B, when the output of the DPCO signal is 12 bits (see 312 in FIG. 4A), the start address 90000 of the RAM 2 is shifted to the right by 12 bits. Set 9090 to the start address (ulMapTopAddr). Further, 0009F obtained by shifting the last address 9FFFF of the RAM 2 to the right by 12 bits is set as the end address (ulMapBottomAddr). Since the head address 90000 and the last address 9FFFF are expressed in hexadecimal, each digit represents a DPCO signal of 4 bits.
[0079]
Then, in loop B, the following processing is repeated from the start address (ulMapTopAddr) to the end address (ulMapBottomAddr) (steps S120 to S170). For example, in the case of FIG. 4B, it is repeated 16 times from 00990 to 0009F.
[0080]
First, a value obtained by adding the start address (ulMapTopAddr) to the left by the number of output bits of the DPCO signal and the PC value being output from the DPCO is set as the processing target PC value (ulPC) (step S130). ).
[0081]
Then, the processing target PC value (ulPC) is set to the work address (unWorkAddr) for extracting the instruction value after the processing target PC value (ulPC) on the instruction code (step S140).
[0082]
For example, in FIG. 4B, the first start address (ulMapTopAddr) is 00990. Therefore, if this is shifted to the left by 12 bits which is the number of output bits of the DPCO signal, 09000 is obtained. 090802, which is obtained by adding 00802 which is the PC value being output obtained from DPCO, is set as the processing target PC value (ulPC).
[0083]
Then, a PC value specifying process using the DST information is performed on the processing target PC value (ulPC) (step S150).
[0084]
In preparation for the next loop, the start address (ulMapTopAddr) is updated (step S160). In FIG. 4B, the start address (ulMapTopAddr) is updated to become 00091.
[0085]
Next, a detailed processing example of the PC value specifying process (step S150 in FIG. 7) using the DST information will be described with reference to FIG.
[0086]
In loop C, the following processing is repeated for the number of output bits of the DPCO signal (steps S210 to S250). In the present embodiment, since one bit of DPCO is output every clock, since the instruction is executed by the number of output bits of the DPCO signal after the absolute branch instruction is generated, the number of output bits of the DPCO signal. This is because DST information indicating the execution state of the subsequent instructions is stored in the trace memory.
[0087]
For example, in FIG. 4B, since the number of output bits of the DPCO signal is 12 bits, the processing from step S220 to S240 is repeated 12 times.
[0088]
First, the DST signal that will be output when the instruction code on the program indicated by the work address (unWorkAddr) is executed is substituted into the comparison target DST code (ucKindCode) (step S220). For example, in FIG. 5B, work address 1 (362) points to add, which is an instruction without branch, and therefore, DST information '000' that will be output when the instruction without branch is executed is compared with DST to be compared. Assign to code (ucKindCode).
[0089]
If the corresponding DST signal on the trace memory and the comparison target DST code do not coincide with each other (ucKindCode), the processing target PC value is determined not to be the absolute branch destination PC value to be obtained and the loop C is exited (step S230 ).
[0090]
If they match, the work address (unWorkAddr) is positioned at the next instruction code position in order to extract the next instruction code on the instruction code (step S240). α is an instruction size for shifting to the next instruction. For example, in FIG. 5B, when one instruction is 2 bytes, it is positioned from work address 1 (362) to work address 2 (364).
[0091]
When the loop C is executed by the number of output bits of the DPCO signal, the DST signal when the instruction code after the candidate PC value is executed and the DST signal stored in the trace memory all match. Assuming that the processing target PC value (ulPC) is the absolute branch destination address, the processing target PC value (ulPC) is set to the candidate PC value (ulWorkPc). The number of candidates (ulExpectNum) is incremented (step S260).
[0092]
4). Processing for realizing the trace function without stopping the target system In this embodiment, in order to generate trace information without stopping the execution of the target system, the machine language of the program stored in the internal memory of the target system An instruction sequence (hereinafter referred to as program information) is stored in the program information storage unit 26 of the host computer.
[0093]
In this way, for example, the comparison target DST code (ucKindCode) to be compared with the DST signal on the trace memory can be created from the program information stored in the program information storage unit 26. Therefore, since it is not necessary to read the internal memory 16 of the target system when generating the trace information, the trace information can be generated without stopping the execution of the target system.
[0094]
In addition, since it is not necessary to read the internal memory 16 of the target system, the processing time for generating trace information can be greatly shortened.
[0095]
In the present embodiment, the program information writing unit 29 performs the following processing in order to store the program information stored in the internal memory 16 of the target system and used for tracing in the program information storage unit 26 of the host computer. It is carried out.
[0096]
FIG. 9 is a flowchart for explaining an operation example when a program is loaded into the internal memory of the target system.
[0097]
In this embodiment, when a program is loaded into the internal memory of the target system, if the program is scheduled to be traced, the contents of the program loaded into the internal memory of the target system are written into the program information storage unit (steps S310 and S320). , S330).
[0098]
FIG. 10 is a flowchart for explaining an operation example when rewriting a program in the target system.
[0099]
In this embodiment, when a program in the internal memory of the target system is rewritten, if there is a plan to trace the program, the corresponding part of the program stored in the program information storage unit is rewritten with the same contents as the program of the target system. (Steps S410, S420, S430).
[0100]
FIG. 11 is a flowchart for explaining an operation example when the program is not loaded and is already in the internal memory of the target system.
[0101]
When tracing the program, the start address and end address of the memory in which the program is stored are specified from the map information (steps S510 and S520). Then, the contents specified by the start address and end address of the internal memory of the target system are read and written in the program information storage unit (step S530).
[0102]
5. Program Counter Analysis Processing Before Absolute Branch Instruction Generation FIG. 12 is a diagram for explaining program counter analysis processing before absolute branch instruction generation. FIG. 12 shows a state in which instructions i1, i2,... Are executed in the target system, and status information DST1 to DST12 is accumulated in the trace memory. In the present embodiment, since the target system does not output the program counter value until the absolute branch instruction is executed, the program counter value is not output until the instruction i9 is executed. Therefore, for the instructions i1 to i8 executed before the occurrence of the absolute branch, there is a problem that the execution position cannot be specified and the trace information cannot be created.
[0103]
Therefore, in the present embodiment, the following configuration is adopted in order to specify a program counter at the time of executing an instruction corresponding to the head status information DST1 accumulated in the trace memory.
[0104]
That is, when the range designation trace is not performed, for example, when the execution start position of the program is designated and executed, the execution start address is acquired by the debug system. Then, status information output from the target system is accumulated in a non-overwrite mode in which the trace memory is not overwritten.
[0105]
Here, when the range designation trace is not performed, the target system outputs DST information that is status information for all executed instructions. Therefore, the DST information DST1 accumulated at the head of the trace memory can be specified as the output of the instruction corresponding to the execution start address.
[0106]
In addition, the target system according to the present embodiment can set a start address and an end address as trigger addresses, and can perform a range designation trace that outputs only status information corresponding to instructions from the start address to the end address. At this time, the trigger address set in the target system is acquired in advance by the debug system.
[0107]
When performing such a range designation trace, the DST information DST1 accumulated at the head of the trace memory can be specified as being output by an instruction corresponding to the trigger address designated as the head address.
[0108]
FIG. 13 is a flowchart showing an operation example of processing for analyzing the program counter at the time of outputting the oldest data stored in the trace memory.
[0109]
When performing the range designation trace, the trigger address 1 which is the head address is set to the candidate PC (ulPC) (steps S610 and S620).
[0110]
When the range designation trace is not performed and the trace memory is not overwritten, the program counter value immediately before the trace start is set to the candidate PC (ulPC) (steps S630 and S640). Note that the address value of the instruction to be executed is set as the program counter value immediately before the start of tracing.
[0111]
Then, the trace information is generated using the candidate PC (ulPC) as the address value of the instruction corresponding to the oldest status information in the trace memory (step S650).
[0112]
6). Hardware Interrupt Determination Processing FIG. 14 is a diagram for explaining processing for determining whether status information indicating execution of an absolute branch instruction is due to instruction execution or hardware interrupt.
[0113]
When the status information stored in the trace memory indicates execution of an absolute branch instruction as indicated by 1410 in FIG. 14, it is due to execution of a normal absolute branch instruction or hardware interrupt. There may be.
[0114]
Therefore, in this embodiment, the status information is based on execution of a normal absolute branch instruction or hardware interrupt, as compared with the information in the machine language instruction sequence of the program stored in the program information storage unit. It is determined whether it exists.
[0115]
Assuming that the machine language instruction string of the instruction corresponding to the trace information stored in the trace memory is i1, i2,... I20 of 1420. If i3 is not an absolute branch instruction, it can be determined that the status information 1410 is not due to normal execution of an absolute branch instruction but is due to a hardware interrupt.
[0116]
FIG. 15 is a flowchart for explaining an operation example of processing for determining whether status information indicating execution of an absolute branch instruction is due to instruction execution or hardware interrupt.
[0117]
Loop A processing is performed for the number of DST information stored in the trace memory (steps S710 to S760).
[0118]
When the DST information indicates the execution of the absolute branch instruction, first, the address indicated by the program counter when the DST information is output is analyzed (steps S720 and S730). If the instruction code at the address indicated by the program counter as the analysis result is not an absolute branch instruction, it is set as a hardware interrupt occurrence location and registered in the data (steps S740 and S750).
[0119]
7). Configuration Example of Target System and Debug Tool FIG. 16 shows a detailed configuration example of the microcomputer and the debug system of this embodiment. As shown in FIG. 16, the microcomputer 1020 includes a CPU 1022, a BCU (bus control unit) 1026, an internal memory (internal ROM and internal RAM other than the mini monitor ROM 1042 and the mini monitor RAM 1044) 1028, a clock generation unit 1030, and a mini monitor unit 1040 (first monitor). 1 monitoring means) and an execution information output unit 1050.
[0120]
Here, the CPU 1022 executes various instructions and includes an internal register 1024. The internal registers 1024 include general-purpose registers R0 to R15, special registers SP (stack pointer register), AHR (higher-order register for product-sum result data), ALR (lower-order register for product-sum result data), and the like.
[0121]
The BCU 1026 controls the bus. For example, it is connected to a Harvard architecture bus 1031 connected to the CPU 1022, a bus 1032 connected to the internal memory 1028, an external bus 1033 connected to the external memory 1036, a mini monitor unit 1040, an execution information output unit 1050, and the like. The internal bus 1034 is controlled.
[0122]
The clock generation unit 1030 generates various clocks used in the microcomputer 1020. The clock generation unit 1030 also supplies a clock to an external debug tool 1060 via BCLK.
[0123]
The mini monitor unit 1040 includes a mini monitor ROM 1042, a mini monitor RAM 1044, a control register 1046, and an SIO 1048.
[0124]
Here, the mini monitor ROM 1042 stores a mini monitor program. In the present embodiment, this mini monitor program only processes simple and primitive commands such as GO, read, and write. For this reason, the memory capacity of the mini monitor ROM 42 can be suppressed to, for example, about 256 bytes, and the microcomputer 1020 can be reduced in size while having an on-chip debugging function.
[0125]
The contents of the internal register 1024 of the CPU 1022 are saved in the mini monitor RAM 1044 when shifting to the debug mode (when a break occurs in the user program). As a result, the execution of the user program can be restarted properly after the debug mode ends. In addition, reading of the contents of the internal register can be realized by a primitive read command etc. possessed by the mini monitor program.
[0126]
The control register 1046 is a register for controlling various debugging processes, and includes a step execution enable bit, a break enable bit, a break address bit, a trace enable bit, and the like. Various debugging processes are realized by the CPU 1022 operating according to the mini-monitor program writing data to each bit of the control register 1046 or reading data of each bit.
[0127]
The SIO 1048 is for transmitting and receiving data to and from the debug tool 1060 provided outside the microcomputer 1020. The SIO 1048 and the debug tool 1060 are connected by TXD / RXD (data transmission / reception line).
[0128]
The execution information output unit 1050 is for realizing a real-time trace function, and is a branch destination when a DST information (DST [2: 0]) that is status information indicating the execution state of the CPU and a PC absolute branch occurs. The PC (program counter) value (DPCO) is output as execution information to the outside through the dedicated four terminals.
[0129]
Between the execution information output unit 1050 and the debug tool 1060, three DST [2: 0] for outputting the status information of the instruction execution of the CPU 1022 and the PC (program counter) value of the absolute branch destination are serially 1 bit. They are connected by four lines, one DPCO that outputs them one by one.
[0130]
The debug tool 1060 includes a main monitor unit 1062 and an execution information acquisition unit 1064, and is connected to a host system 1066 realized by a personal computer or the like.
[0131]
The main monitor unit 106 performs processing for converting (decomposing) a debug command input from the host system 1066 into a primitive command. When the main monitor unit 1062 transmits data instructing execution of a primitive command to the mini monitor unit 1040, the mini monitor unit 1040 performs processing for executing the instructed primitive command.
[0132]
Further, the execution information acquisition unit 1064 stores the 3-bit DST [2: 0] and DPCO representing the branch destination PC (program counter) value in the internal trace memory 1104. When the trace range is designated, DST [2: 0] and DPCO in the range are stored in the trace memory.
[0133]
Next, in the present embodiment, a configuration for loading a program from the debug system into the internal memory of the microcomputer and rewriting information in the internal memory will be described.
[0134]
As shown in FIG. 17, in the present embodiment, the microcomputer 1020 includes a CPU (central processing unit) 1022 and a mini-monitor unit (first monitor means) 1040 that is a main part of the present embodiment. A main monitor unit (second monitor means) 1062 is provided outside the microcomputer 1020. Here, the main monitor unit 1062 performs processing for converting (decomposing) a debug command issued by, for example, the host computer 1066 into a primitive command. Further, the mini monitor unit 1040 transmits and receives data to and from the main monitor unit 1062. Then, the mini monitor unit 1040 determines a primitive command to be executed based on the received data from the main monitor unit 1062, and performs a process for executing the primitive command.
[0135]
Here, debug commands to be converted by the main monitor unit 1062 include program load, GO, step execution, memory write, memory read, internal register write, internal register read, breakpoint setting, breakpoint release, and the like. You can think of commands. The main monitor unit 1062 sends these various and complex debug commands to, for example, GO, write (write to a given address on the memory map in debug mode), read (from a given address on the memory map). (Read), etc., to convert to simple and primitive commands. In this way, the instruction code size of the mini monitor program that performs the processing of the mini monitor unit 1040 can be significantly reduced.
[0136]
As a result, a program can be loaded from the debug system to the internal memory of the microcomputer, and information in the internal memory can be rewritten. That is, when a program is loaded into a microcomputer as a target system or when a memory write is performed, these debug commands are issued from the host computer.
[0137]
8). Conversion to Primitive Command FIGS. 18A, 18B, 18C, and 18D schematically show processing for converting various debug commands into primitive commands.
[0138]
For example, as shown in FIG. 18A, a 12-byte program (ADD ..., SUB ..., AND ..., OR ..., XOR ..., LD.W ...) Assume that a debug command for loading at address 80010h is issued. In this case, the program load command includes write (80010h, ADD ..., SUB), write (80013h, AND ..., OR ...), write (80018h, XOR ..., LD.W ... .) Is converted into three primitive write commands. That is, the program load command is realized by the mini monitor program executing these three primitive write commands.
[0139]
Further, it is assumed that a debug command called a step execution command is issued as shown in FIG. Then, this step execution command is converted into a write command and a GO command to the step execution enable bit of the control register 1046 in FIG. That is, the mini monitor program executes the primitive write command and the GO command, thereby realizing a step execution command.
[0140]
Assume that a debug command called an internal register read command is issued as shown in FIG. Then, the internal register read command is converted into a read command from the mini monitor RAM 44 (a save destination of the contents of the internal register) on the memory map. That is, when the mini monitor program executes this primitive read command, the internal register read command is realized. The internal register write command, memory read command, and memory write command are also realized in the same manner.
[0141]
Assume that a debug command called a breakpoint setting command for setting a trigger address as a breakpoint is issued as shown in FIG. Then, this breakpoint setting command is converted into a write command to the break enable bit and break address bit of the control register 1046. That is, the breakpoint setting command is realized by the mini monitor program executing this primitive write command.
[0142]
As described above, in this embodiment, complicated and various debug commands are converted into primitive, simple read, write, and GO commands. Since the mini-monitor program only needs to execute these primitive read, write, and GO commands, the instruction code size of the mini-monitor program becomes very small. As a result, the memory capacity of the mini monitor ROM 1042 can be reduced, and an on-chip debugging function can be realized with a small hardware scale.
[0143]
9. Configuration Example of Debug Tool FIG. 19 shows a configuration example of the debug tool 1060.
[0144]
The CPU 1090 executes a program stored in the ROM 1108 and controls the entire debug tool 1060. The transmission / reception switching unit 1092 is for switching between transmission and reception of data. The clock control unit 1094 controls a clock supplied to the SCLK terminal of the CPU 1090, the address up counter 1100, and the trace memory 1104. BCLK from the microcomputer 1020 (SIO 1048) is input to the clock control unit 1094. The clock control unit 1094 includes a frequency detection circuit 1095 and a frequency dividing circuit 1096. The frequency detection circuit 1095 detects the frequency range to which the frequency of BCLK belongs, and outputs the result to the control register 1098. Further, the frequency dividing ratio in the frequency dividing circuit 1096 is controlled by the control register 1098. That is, the main monitor program (stored in the main monitor ROM 110) executed by the CPU 1090 reads the BCLK frequency range from the control register 1098. Then, the main monitor program determines an optimum frequency division ratio corresponding to this frequency range, and writes this frequency division ratio in the control register 1098. Then, the frequency dividing circuit 1096 divides BCLK by this frequency dividing ratio to generate SMC2, and outputs it to the SCLK terminal of the CPU 1090.
[0145]
The address up counter 1100 is for counting up the address of the trace memory. The selector 1102 selects either the line 1122 (address output from the address up counter 1100) or the line 1124 (address from the address bus 1120), and outputs data to the address terminal of the trace memory 1104. The selector 1106 selects either the line 1126 (DST [2: 0], DPCO which is the output of the execution information output unit 1050 in FIG. 16) or the line 1128 (data bus 1118), and the data terminal of the trace memory 1104 Output data to or retrieve data from the data terminal.
[0146]
The ROM 1108 includes a main monitor ROM 1110 (corresponding to the main monitor unit 1062 in FIG. 16), and the main monitor ROM 1110 stores a main monitor program. As described with reference to FIGS. 18A to 18D, the main monitor program performs processing for converting a debug command into a primitive command. The RAM 1112 serves as a work area for the CPU 1090.
[0147]
The RS232C interface 1114 and the parallel interface 1116 serve as interfaces with the host computer 1066 of FIG. 16, and debug commands from the host system 1066 are input to the CPU 1090 via these interfaces. The clock generation unit 1118 generates a clock for operating the CPU 1090 and the like.
[0148]
Next, the real-time trace processing in this embodiment will be briefly described. In the present embodiment, 3-bit DST [2: 0] representing the status information of instruction execution of the CPU 1022 in FIG. 16 and DPCO representing the branch destination PC value are stored in the trace memory 1104. Then, trace data is generated based on the data stored in the trace memory 1104 and the machine language instruction sequence information of the user program stored in the program information storage unit of the host computer 1066. By doing so, it is possible to realize a real-time trace function while reducing the number of connection lines between the microcomputer 1020 and the debug tool 1060.
[0149]
In the user program execution mode, the line 1122 is selected, and the output of the address up counter 1100 is input to the address terminal of the trace memory 1104 via the selector 1102. In addition, the line 1126 is selected, and DST [2: 0] and DPCO are input to the data terminal of the trace memory 1104 via the selector 1106. Here, in the address up counter 1100, first, a start address as shown in FIG. 20A is set by the CPU 1090 using the data bus 1118 and the address bus 1120. The ST / SP (start / stop) terminal of the address up counter 1100 is connected to the DST [2] line for specifying the trace range. Then, as shown in FIG. 20B, when the first pulse 130 is input to the DST [2] line, the address upcounting of the address upcounter 1100 starts. When the second pulse 132 is input to the DST [2] line, the address upcount of the address upcounter 1100 is stopped and the trace operation is stopped. In this way, data (DST [2: 0], DPCO) in a desired trace range can be stored in the trace memory 1104.
[0150]
On the other hand, when shifting from the user program execution mode to the debug mode, the line 1124 is selected, and the address from the address bus 1120 is input to the address terminal of the trace memory 1104 via the selector 1102. The line 1128 is selected, and data from the trace memory 1104 is output to the data bus 1118 via the selector 1106. As a result, the data (DST [2: 0], DPCO) stored in the trace memory 1104 can be read by the CPU 1090 (main monitor program) in the debug mode. Then, trace data can be generated based on the read data and the information of the machine language instruction sequence of the user program.
[0151]
In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.
[0152]
For example, although a case has been described with the present embodiment as an example where the means for realizing the functions of the debug system are provided separately in the debug tool and the host computer, the present invention is not limited thereto. A debugging system may be realized by providing means for realizing all functions in either the debugging tool or the host computer.
[0153]
In this embodiment, the case where the branch destination PC value is serially output bit by bit from the target system has been described as an example, but the present invention is not limited to this. A branch destination PC output terminal may be prepared for several bits and serially output several bits at a time.
[0154]
In the present embodiment, the case of performing range designation tracing with two trigger addresses has been described as an example, but the present invention is not limited to this. For example, one or three or more trigger points may be set, or a range may not be specified by the trigger point.
[0155]
Further, the configuration of the microcomputer and the debug tool is not limited to that described in the present embodiment, and various modifications can be made.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a CPU replacement type ICE.
FIG. 2 is a diagram for explaining a configuration of the present embodiment.
FIG. 3 is a diagram illustrating a relationship between an output value of DST [2: 0] and an instruction execution state of a CPU.
FIGS. 4A and 4B are diagrams for explaining extraction of a candidate address group for specifying an absolute branch destination address. FIGS.
FIGS. 5A to 5C are diagrams for explaining processing for specifying an absolute branch destination address from a candidate group extracted from map information. FIG.
FIG. 6 is a flowchart showing an operation example of processing for specifying a branch destination address when an absolute branch occurs at a short interval and the program counter value does not output all bits from the DPCO.
FIG. 7 is a flowchart showing an operation example of processing for specifying a branch destination address when an absolute branch occurs at a short interval and all bits of the program counter value are not output from the DPCO.
FIG. 8 is a flowchart showing an operation example of processing for specifying a branch destination address when an absolute branch occurs at a short interval and the program counter value does not output all bits from the DPCO.
FIG. 9 is a flowchart for explaining an operation example when a program is loaded into an internal memory of a target system.
FIG. 10 is a flowchart for explaining an operation example when rewriting a program code inside the target system;
FIG. 11 is a flowchart for explaining an operation example when the program is not loaded and is already in the internal memory of the target system.
FIG. 12 is a diagram for explaining a program counter analysis process before the occurrence of an absolute branch instruction.
FIG. 13 is a flowchart showing an operation example of processing for analyzing a program counter at the time of outputting the oldest data stored in the trace memory.
FIG. 14 is a diagram for describing processing for determining whether status information indicating absolute branch instruction execution is due to instruction execution or hardware interrupt;
FIG. 15 is a flowchart for explaining an operation example of processing for determining whether status information indicating absolute branch instruction execution is due to instruction execution or hardware interrupt;
FIG. 16 is a functional block diagram illustrating a configuration example of a microcomputer and a debugging system.
FIG. 17 is a diagram for explaining debug command execution processing in the present embodiment;
FIGS. 18A to 18D are diagrams for explaining processing for converting (decomposing) a debug command into a primitive command.
FIG. 19 is a functional block diagram illustrating a detailed configuration example of a debug tool.
FIG. 20 is a diagram illustrating a relationship between DST [2] and a trace range.
[Explanation of symbols]
10 Microcomputer 12 CPU (Central Processing Unit)
14 execution information output unit 16 internal memory 20 debug system 22 execution information acquisition unit 24 trace memory 26 program information storage unit 27 trace information generation unit 28 target memory writing unit 29 program information writing unit 1020 microcomputer 1022 CPU
1024 Internal register 1026 BCU
1028 Internal memory 1030 Clock generation unit 1036 External memory 1040 Mini monitor unit 1042 Mini monitor ROM
1044 Mini monitor RAM
1046 control register 1048 SIO
1050 Execution information output unit 1060 Debug tool 1062 Main monitor unit 1064 Execution information acquisition unit 1066 Host computer 1090 CPU
1092 Transmission / reception switching unit 1094 Clock control unit 1095 Frequency detection unit 1096 Frequency dividing circuit 1098 Control register 1100 Address up counter 1102 Selector 1104 Trace memory 1106 Selector 1108 ROM
1110 External monitor ROM
1112 RAM
1114 RS232C interface 1116 Parallel interface 1118 Clock generation unit

Claims (2)

Debug that outputs status information for determining whether the CPU execution status belongs to normal instruction execution, absolute branch instruction execution, or relative branch instruction execution, and target system trace information that outputs the branch destination address of the absolute branch instruction A system,
Means for storing in the storage unit information for grasping a machine language instruction sequence of a program executed by the target;
Storage means for receiving the status information from the target system and storing it in a memory;
It is determined whether or not the status information stored in the memory indicates execution of an absolute branch instruction. If the status information indicates execution of an absolute branch instruction, the address when the status information is output is analyzed and stored in the storage unit. Reads the information for grasping the machine language instruction string of the program executed by the target being executed, determines the instruction code of the analyzed address, and if the calculated instruction code is not an absolute branch instruction, the status information is interrupted Trace information generating means for generating trace information by judging that
The trace information generating means includes
When an absolute branch occurs first and instructions are subsequently executed in the order of addresses, the program counter is checked to determine how far the program counter has advanced from the branch destination address that was output during the previous absolute branch. Configured to parse,
The target system is configured to serially output the address information of the absolute branch destination by one or several bits, and when only a part of the address information of the previous absolute branch destination is received, For each candidate address included in the candidate address group in which a part of the address information is a lower bit, the machine language instruction sequence of the program after the candidate address is read from the program information storage unit, and the machine language instruction sequence of the read program is executed. The status information string that will be output if the error is generated is compared, the generated status information array is compared with the status information array stored in the memory after the absolute branch instruction, and the candidate matches If there is only one address, the candidate address is used as the address of the previous absolute branch destination. Debugging system characterized by analyzing the address from which the task information output. Debug that outputs status information for determining whether the CPU execution status belongs to normal instruction execution, absolute branch instruction execution, or relative branch instruction execution, and target system trace information that outputs the branch destination address of the absolute branch instruction A computer-readable information storage medium for controlling the system,
Means for storing in the storage unit information for grasping a machine language instruction sequence of a program executed by the target;
Storage means for receiving the status information from the target system and storing it in a memory;
It is determined whether or not the status information stored in the memory indicates execution of an absolute branch instruction. If the status information indicates execution of an absolute branch instruction, the address when the status information is output is analyzed and stored in the storage unit. Reads the information for grasping the machine language instruction string of the program executed by the target being executed, determines the instruction code of the analyzed address, and if the calculated instruction code is not an absolute branch instruction, the status information is interrupted A program for causing the computer to function as trace information generating means for generating trace information by judging that
The trace information generating means includes
When an absolute branch occurs first and instructions are subsequently executed in the order of addresses, the program counter is checked to determine how far the program counter has advanced from the branch destination address that was output during the previous absolute branch. Configured to parse,
The target system is configured to serially output the address information of the absolute branch destination by one or several bits, and when only a part of the address information of the previous absolute branch destination is received, For each candidate address included in the candidate address group in which a part of the address information is a lower bit, the machine language instruction sequence of the program after the candidate address is read from the program information storage unit, and the machine language instruction sequence of the read program is executed. The status information string that will be output if the error is generated is compared, the generated status information array is compared with the status information array stored in the memory after the absolute branch instruction, and the candidate matches If there is only one address, the candidate address is used as the address of the previous absolute branch destination. Information storage medium characterized by analyzing the address from which the task information output.

Images