JP3770007B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device on which a semiconductor element is mounted, and more particularly to a method for manufacturing a semiconductor device called a chip size package (CSP).
[0002]
[Prior art]
2. Description of the Related Art In recent years, due to miniaturization of electronic devices, semiconductor devices incorporated (mounted) in electronic devices are mounted at high density, and there is an increasing demand for miniaturization of semiconductor devices. As a technique that meets this requirement, a technique called a chip size package (hereinafter referred to as CSP) has been proposed.
The CSP can be approximately the same size as a semiconductor element (IC chip) incorporated therein, and can be said to be an effective technique for downsizing a semiconductor device.
Various structures and forms of CSPs have been proposed. Hereinafter, the CSP will be described with reference to the drawings schematically showing general CSP forms.
[0003]
As shown in FIG. 7, an electrode 73 (connection pad) made of aluminum or the like is formed on the semiconductor element 72 incorporated in the CSP 70. In the general semiconductor element 72, a passivation film 74 that exposes the electrode 73 is formed.
Here, when the CSP 70 is formed, a first insulating layer 75 made of an insulating resin or the like is formed on the semiconductor element 72 so as to expose the electrode 73. A wiring pattern 77 (wiring layer) made of a metal such as Cu connected to the electrode 73 is formed on the first insulating layer 75, and a metal post 79 made of copper or the like is disposed on the wiring pattern 77. is doing. In the example of FIG. 7, a metal barrier layer 76 is formed below the wiring pattern 77 in order to prevent a metal such as Cu from flowing out to the semiconductor element 72 side.
Next, a second insulating layer 78 is formed on the wiring pattern 77 and the first insulating layer 75 to expose the end face of the metal post 79. Further, sealing is performed so that the end face of the metal post 79 is exposed. Resin sealing is performed with the resin 80 to become CSP70.
[0004]
In order to improve heat dissipation of the semiconductor device, a heat sink material 82 for cooling may be attached to the back surface of the semiconductor element (the semiconductor element surface opposite to the surface on which the electrodes and the semiconductor integrated circuit are formed).
[0005]
A method for manufacturing a CSP having the above-described configuration will be described below with reference to the drawings. In the drawings described below, reference numerals are omitted for portions having the same name.
A plurality of semiconductor elements 72 are formed on the silicon (Si) wafer shown in FIG. 4A (an arrow line in the figure indicates one semiconductor element 72 region).
Each semiconductor element 72 is formed with an electrode 73 (connection pad) for electrical connection with the outside. Further, a passivation film 74 exposing the electrode 73 is formed on each semiconductor element 72 in advance.
[0006]
Next, in manufacturing the CSP, a first insulating layer 75 is formed on the semiconductor element 72 so as to expose the electrode 73 by using a photolithography method or the like (FIG. 4B).
Next, after the metal barrier layer 76 and the metal thin film layer 87 are stacked on the silicon wafer (FIG. 4C), the metal barrier layer 76 and the metal thin film layer 87 are patterned by a photoetching method or the like to obtain a predetermined pattern. A shaped wiring layer 77 is obtained (FIG. 4D).
[0007]
4D, an insulating resin or the like is used as a material, and a plating mask exposing a predetermined wiring layer 77 site is formed by photolithography or the like (FIG. 5A). Next, a metal post 79 is formed on the wiring layer 77 exposed from the plating mask by electroplating, and then the plating mask is peeled off (FIG. 5B).
Next, after removing the excess wiring layer 77 portion formed between the semiconductor elements 72 using a photoetching method or the like (FIG. 5C), the metal posts 79 are formed on the semiconductor elements 72 by a photolithography method or the like. A second insulating layer 78 exposing the front end surface is formed (FIG. 5D).
[0008]
Next, dicing is performed on the silicon wafer to divide the semiconductor element 72 into individual pieces (FIG. 5E). Next, each of the separated semiconductor elements 72 obtained in FIG. 5 (e) is bonded to a silicon wafer surface opposite to the surface on which the semiconductor elements 72 are formed, and then the separated semiconductor elements 72 are separated. The elements 72 are each oil-sealed with a sealing resin tree 80 using a mold (FIG. 6A). In the resin sealing, the resin sealing is performed so that the heat sink material 82 is exposed and the tip surface of the metal post 79 is exposed.
Next, the external connection terminals 81 are installed on the respective metal posts 79 to obtain the semiconductor device (CSP 70) shown in FIG. 6B and FIG.
[0009]
In the semiconductor device (CSP 70) obtained by the manufacturing process described above, the external connection terminal 81 is used for the electrical connection between the outside (for example, the mounting substrate) and the electrode 73 and the fixing between the outside and the semiconductor device. As the external connection terminals 81, solder (solder) balls or the like are used. A wiring layer 77 connected to the electrode 73 is formed on the first insulating layer 75, and the wiring layer 77 performs electrical connection between the electrode 73 and the metal post 79. The first insulating layer 75 and the second insulating layer 78 are electrically insulated, and stress generated by a difference in coefficient of thermal expansion between the semiconductor device and the mounting substrate after the semiconductor device is mounted is applied to the semiconductor device. When this occurs, it also has a function of relieving this stress, and this function is intended to prevent the semiconductor device from being cracked.
[0010]
In general, a heat sink material 82 is attached to the semiconductor element in order to improve heat dissipation of the semiconductor device (CSP).
[0011]
As described above, a silicon (Si) wafer in which a plurality of semiconductor elements 72 are formed on a plurality of surfaces is collectively formed until the second insulating layer 78 is formed, and then dicing is performed for each semiconductor element 72. By singulation, the CSP 70 can be approximately the same size as the semiconductor element 72.
[0012]
[Problems to be solved by the invention]
Here, it can be said that the above-described CSP manufacturing method has the following problems.
First, since a metal post is formed by electroplating after forming a wiring layer having a predetermined pattern, a plating power supply wiring for electroplating is required, and the CSP manufacturing process becomes complicated and uneconomical. It is a problem. This is because, in addition to the wiring layer for electrical connection between the electrode and the metal post, a plating power supply wiring for forming the metal post is separately required, and this plating power supply wiring becomes unnecessary after the metal post is formed. This is because it needs to be removed. That is, the manufacturing process becomes complicated and uneconomical because the plating power supply wiring that is unnecessary as the final product is formed.
[0013]
Further, since an extra area for forming the plating power supply wiring is required, the pattern design and pattern arrangement of the wiring layer are restricted.
Further, there are a plurality of metal post forming portions, and a plurality of plating power supply wirings are required. However, the lengths of the plating power supply wirings differ depending on the routing. For this reason, the height of the metal post formed by electroplating is likely to vary due to a difference in electrical resistance caused by a difference in length. In addition, a failure such as a metal post not being formed (plating is not attached) due to disconnection of the plating power supply wiring may occur, resulting in a poor electrical connection with the outside. It was also a factor that decreased.
[0014]
Furthermore, when the semiconductor element is encapsulated in a wafer state before being separated into pieces, the encapsulating resin, which is a protective layer of the semiconductor element, is thick on the top surface of the semiconductor element and thin on the side surface of the semiconductor element. Cheap. Therefore, after the semiconductor device is singulated, moisture absorption is likely to occur from the side surface portion of the semiconductor device, and the airtightness is insufficient, so that the reliability of the package becomes low.
By the way, the present inventors mounted a conventional semiconductor device (CSP) on a mounting substrate, and then changed the temperature of the mounting substrate to one cycle by changing the temperature from −40 ° C. to + 125 ° C. When the test was repeated a number of times, package cracks occurred in a relatively early period of 200 to 400 cycles.
[0015]
Further, in the conventional method of manufacturing a semiconductor device (CSP), since each individual semiconductor element is resin-sealed using a mold one by one, it takes time to manufacture and also costs manufacturing costs.
[0016]
The present invention has been made in view of the above-described problems. In the production of a semiconductor device (CSP), it is unnecessary to form a plating power supply wiring, and a semiconductor device (CSP) that does not require a mold for resin sealing. It is an object of the present invention to provide a manufacturing method, thereby providing a highly reliable semiconductor device (CSP) free from package cracks and poor electrical connection.
[0017]
[Means for Solving the Problems]
The inventors of the present invention have intensively studied to achieve the above-mentioned problems and have arrived at the present invention.
. That is, in claim 1, a step of forming a first insulating layer on the wafer surface on which a semiconductor element having an electrode is formed so as to expose the electrode, and the electrode on the surface on which the first insulating layer is formed Forming a metal thin film layer electrically connected to the metal thin film layer, forming a resist pattern for a plating mask on the metal thin film layer, and metal plating on a portion of the metal thin film layer exposed from the plating mask by electroplating. Forming a post; removing the resist pattern for the plating mask; patterning the metal thin film layer to form a wiring layer; covering the wiring layer and the first insulating layer; and A step of forming a second insulating layer that exposes the tip end face of the post, and plating the metal thin film layer during electroplating for forming the metal post And conductor In the step of forming the second insulating layer, after applying the photosensitive insulating resin by using a spin coating method, the insulating resin remaining on the front end surface of the metal post is removed by a photolithography method, whereby the second insulating layer is removed. The insulating layer is formed so as to cover the side surface of the metal post and to make the height of the second insulating layer excluding the portion covering the side surface of the metal post lower than the height of the metal post end surface. This is a method for manufacturing a semiconductor device.
[0019]
Further claims 2 In the claim, the semiconductor element is formed on a wafer formed by imposing a plurality of surfaces. 1 After the process of forming the second insulating layer is performed by the manufacturing method described above, the process of attaching the heat sink material for cooling to the back surface of the wafer and dicing from the second insulating layer forming surface side to the boundary between the wafer and the heat sink material Performing steps of separating the semiconductor elements into individual pieces, sealing the wafer including the semiconductor elements with a resin post so as to cover each of the separated semiconductor elements and to expose the tip surface of the metal post, and the semiconductor The semiconductor device manufacturing method includes at least a step of dicing and dicing including a heat sink material so as to leave a sealing resin on the side surface of the element.
[0020]
Furthermore, the claims 3 In the method, an external connection terminal having a stress relaxation function is disposed on the tip surface of the metal post before dicing into pieces including the heat sink material. 2 The manufacturing method of the semiconductor device described in the above.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
2 and 3 are drawings showing an example of an embodiment of a semiconductor device manufacturing method according to the present invention in the order of steps. FIG. 2A shows a semiconductor element 2 formed on a silicon (Si) wafer in a conventional manner (an arrow in FIG. 2A indicates a region of each semiconductor element 2). . Each semiconductor element 2 has an electrode 3 formed thereon, and a passivation film 4 is formed so as to expose the electrode 3.
[0022]
In the method for manufacturing a semiconductor device of the present invention, first, as shown in FIG. 2B, first insulation is performed so that the electrode 3 is exposed on the silicon wafer surface on which the semiconductor element 2 having the electrode 3 is formed. Layer 5 is formed.
[0023]
Next, as shown in FIG. 2C, a metal thin film layer 17 that is electrically connected to the electrode 3 formed on the semiconductor element 2 is formed on one surface on the surface on which the first insulating layer 5 is formed. Note that the metal thin film layer 17 may have a single-layer configuration of a good electrical conductor metal such as Cu (copper) or Ag (silver), and as shown in FIG. 2C, a metal such as Cr, TiW, or TiN. A multilayer structure in which a metal thin film layer 17 made of a good electrical conductor metal such as Cu (copper) or Ag (silver) is laminated on the barrier layer 6 may be used. Further, the means for forming the metal thin film layer 17 includes a sputtering method, a vacuum deposition method, an ion plating method, a CVD method, a sol-gel method, an electroless plating method, and the like, and may be appropriately selected.
[0024]
Next, a resist pattern serving as a plating mask at the time of electroplating is formed on the metal thin film layer 17 to expose the metal thin film layer 17 portion where the metal post is to be formed, and FIG. 2D is obtained.
Next, electroplating is performed using the metal thin film layer 17 as a plating power supply wiring. After the metal post 9 is formed on the metal thin film layer 17 exposed from the plating mask, the plating mask is peeled off to obtain FIG.
[0025]
Next, the metal thin film layer 17 and the metal barrier layer 6 formed on the entire surface of the silicon wafer are patterned by using a photoetching method or the like to form a wiring layer 7 having a predetermined pattern shape (FIG. 2F).
Ie , Place Before obtaining the wiring layer 7 having a fixed pattern shape, the metal thin film layer 17 uniformly formed on the entire surface is used as a conductor for plating power feeding.
[0026]
This eliminates the need for the formation of the plating power supply wiring and the removal of the plating power supply wiring, which are required in the conventional semiconductor device manufacturing method, and simplify the manufacturing process. It becomes possible.
In addition, since the metal thin film layer 17 serving as the plating power supply wiring is uniformly formed on the entire surface of the silicon wafer, disconnection of the plating power supply wiring is unlikely to occur, and the metal post 9 is not attached or the height of the metal post 9 varies. Thus, a highly reliable semiconductor device can be manufactured at low cost.
[0027]
Next, in the method for manufacturing a semiconductor device of the present invention, after forming the wiring layer 7 having a predetermined pattern shape shown in FIG. 2 (f), the wiring layer 7 and the first insulating layer 5 are covered, and A second insulating layer 8 exposing the tip surface of the metal post 9 is formed to obtain FIG.
[0028]
Here, as shown in FIG. 1 and FIG. 3A, the second insulating layer 8 is formed so that the surface of the second insulating layer 8 is lower than the tip end surface of the metal post 9 and in the vicinity of the tip end of the metal post 9. The metal post 9 is formed so as to cover the side surface.
That is, the structure is such that the adhesion between the second insulating layer 8 and the metal post 9 is prioritized below the tip of the metal post 9 (in the silicon wafer direction). As a result, the adhesion between the second insulating layer 8 and the metal post 9 is reinforced, and accordingly, the connection strength between the metal post 9 and the wiring pattern 7 is improved and the disconnection between the metal post 9 and the wiring pattern 7 is prevented. it can.
[0029]
Further, as will be described later, in the semiconductor device, resin sealing with a sealing resin is required, but when the surface of the second insulating layer 8 is equal to or higher than the height of the front end surface of the metal post 9, the second insulating layer The height of the surface of the sealing resin formed on 8 is higher than that of the metal post 9 tip. For this reason, even if an external connection terminal (for example, a solder ball) is arranged on the front end surface of the metal post 9 exposed from the opening of the sealing resin, it is obstructed by the sealing resin, and the external connection to the front end surface of the metal post 9 is performed. An electrical connection failure between the metal post 9 and the external connection terminal occurs, for example, a gap is formed between the terminal and the terminal.
[0030]
However, as shown in FIG. 3A, if the height of the second insulating layer 8 excluding the portion covering the side surface of the metal post 9 is made lower than the height of the tip surface of the metal post 9, the surface of the sealing resin and the metal Since the post 9 tip surface can be close and the sealing resin does not interfere, no gap is formed between the metal post 9 tip surface and the external connection terminal when the external connection terminal is provided, and the metal It is possible to prevent poor electrical connection between the post 9 and the external connection terminal. Further, by forming the second insulating layer 8 thin, the amount of the second insulating layer 8 using a relatively expensive material can be reduced, and the manufacturing cost of the semiconductor device can be reduced.
[0031]
Further, in order to form the second insulating layer 8 so that the height of the second insulating layer 8 is lower than the height of the metal post 9 tip surface except for the side surface in the vicinity of the tip portion of the metal post 9, the insulating resin is photosensitive. It is desirable to use a photolithography method in which unnecessary portions of the insulating resin are removed by coating, pattern exposure, development, and the like.
[0032]
The insulating resin used as the second insulating layer 8 may be applied by using a known coating means such as a spin coating method, a curtain coating method, a screen printing method, or a slit and spin coating method.
However, when it is considered that the height of the surface of the second insulating layer 8 is lower than the height of the tip surface of the metal post 9 except for the side surface in the vicinity of the tip portion of the metal post 9, the spin coating method is performed. desirable.
That is, if the insulating resin is applied by spin coating after the metal post 9 is formed, the excess insulating resin is removed out of the semiconductor element. For this reason, by appropriately setting the application conditions, the insulating resin can be applied with a film thickness thinner than the height of the tip surface of the metal post 9 in the region excluding the side surface portion in the vicinity of the tip portion of the metal post 9. The insulating resin can be applied also to the side surface in the vicinity of the tip end portion of the 9. The insulating resin remaining on the tip surface of the metal post 9 may be selectively removed by laser, dry etching, reverse sputtering or the like in addition to the photolithography method described above.
[0033]
Next, after forming the second insulating layer 8 as shown in FIG. 3A, in the method for manufacturing a semiconductor device of the present invention, the cooling heat sink material 12 is provided on the side opposite to the surface on which the semiconductor element is formed. Affix to the silicon wafer surface. In addition, as a material of the heat sink material 12 for cooling, metals, such as Ag, Cu, Al, or those with high thermal conductivity, such as these alloys, can be used. It is inexpensive and has high thermal conductivity. Next, dicing is performed after the cooling heat sink material 12 is pasted, so that a cut is made from the formation surface side of the second insulating layer 8 to the boundary between the silicon wafer and the heat sink material 12, and the silicon including the semiconductor element 2 is siliconized. The wafer is singulated to obtain FIG. At this time, each separated semiconductor element 2 is held and fixed on the cooling heat sink material 12 that has not been diced.
[0034]
Next, resin sealing with the sealing resin 10 is performed uniformly on the silicon wafer wafer so as to fill the gaps between the individual semiconductor elements 2 (cuts) and to expose the end surfaces of the metal posts 9, FIG. 3C is obtained. It is easy to remove the resin on the front surface of the metal post 9 after applying the sealing resin 10 uniformly on the entire surface of the silicon wafer including the front surface of the metal post 9 by spin coating. desirable. The removal of the resin on the front end surface of the metal post 9 is simple and desirable by using a photolithography method in which the sealing resin 10 is a photosensitive resin, and unnecessary portions are removed by coating, pattern exposure, development, and the like.
[0035]
Next, the external connection terminal 11 is disposed on the front end surface of the metal post 9 to obtain FIG. Next, the semiconductor element 2 is separated into individual pieces by dicing including the heat sink material 12 so as to leave the sealing resin 10 on the side surfaces of the semiconductor elements 2, and the semiconductor device (CSP 1) shown in FIGS. 1 and 3 (e). Get.
[0036]
In a semiconductor device typified by CSP1, resin sealing is required on the outer periphery of a semiconductor element in order to improve package reliability and mechanical strength.
As described above, in the conventional method of manufacturing a semiconductor device (CSP), after semiconductor elements are separated into pieces and completely separated and made independent, each semiconductor element 72 is resin-sealed one by one using a mold. It was.
For this reason, every time the shape of the semiconductor element 72 changes, in other words, a new mold is required for each type of semiconductor device. Making a mold is very expensive, and it can be said that making an expensive mold for each type of semiconductor device is uneconomical.
Further, in resin sealing using a mold, the sealing resin 80 is thick on the upper surface of the semiconductor element 72, the sealing resin 80 on the side surface of the semiconductor element 72 is easily formed thin, and the mechanical strength of the side surface of the semiconductor element 72 is increased. It was weak and lacked airtightness and was not reliable.
[0037]
However, in the method for manufacturing a semiconductor device of the present invention, a mold is not used for resin sealing.
That is, as shown in FIG. 3C, the space between the semiconductor elements 2 separated and held on the heat sink material 12 for cooling is filled (cut), and the tip surface of the metal post 9 is The resin sealing is performed uniformly with the sealing resin 10 on the silicon wafer so as to be exposed. Further, the final separation of the semiconductor elements 2 is performed by dicing including the cooling heat sink material 12 so as to leave the sealing resin 10 on the side surface of each semiconductor element 2.
[0038]
That is, in the method of manufacturing a semiconductor device of the present invention, each semiconductor element held and fixed on the heat sink material 12 for cooling is not subjected to resin sealing of individual semiconductor elements one by one using a mold. Resin sealing is performed on the elements 2 in a lump, and then the dicing is performed including the cooling heat sink material 12 to finally singulate. As a result, it is possible to reduce the manufacturing cost by eliminating the need to use an expensive metal mold for resin sealing, and it is also possible to reduce the time required for resin sealing.
In addition, since resin sealing is performed without using a mold, the adhesion between the semiconductor element and the sealing resin is improved, and the reliability and mechanical strength of the semiconductor device can be improved.
[0039]
Next, the external connection terminal 11 is disposed in the semiconductor device for fixing and electrical connection with the outside (for example, mounting substrate). In the manufacturing method of the present invention, the external connection terminal 11 is stressed. It is characterized by having a relaxation function.
[0040]
This point will be described.
When a semiconductor device is mounted on a mounting board or the like, a semiconductor element formed of silicon or the like (for example, a thermal expansion coefficient of about 3 ppm) and a mounting board (for example, a printed circuit board made of epoxy resin: a thermal expansion coefficient of about 40 to 200 ppm). However, stress (stress) generated by the difference in thermal expansion coefficient from the Tg point or more and exceeding 200 ppm is applied to the semiconductor device. This stress (stress) causes cracks and internal disconnections in the semiconductor device, reducing the reliability of the semiconductor device.
[0041]
However, in the method of manufacturing a semiconductor device according to the present invention, the external connection terminal 11 disposed on the metal post has a stress relaxation function, and stress caused by the difference in thermal expansion coefficient between the semiconductor device and the mounting substrate. (Stress) is relieved by the external connection terminal 11 having a stress relieving function, and it is possible to prevent the semiconductor device (CSP1) from being cracked or disconnected.
As an example of the external connection terminal 11 having a stress relaxation function, as shown in FIG. 8 or FIG. 9, a conductive material 16 is provided on the surface of a holding body 15 having a hollow portion opened to the outside. can give. FIG. 8 is a view of an example of the external connection terminal 11 having a stress relaxation function as viewed from the side surface (that is, a view as viewed from the side surface of the semiconductor device when the external connection terminal 11 is disposed in the semiconductor device). FIG. 9 is a view of a cross section taken along line AA ′ of FIG. 2 as viewed from above (when viewed from the mounting board side when mounted on the mounting board).
[0042]
Since the hollow holding body 15 has a flexible structure, even when the mounting substrate connected to the external connection terminal 11 repeatedly undergoes a considerable amount of thermal expansion and contraction, the generated stress (stress) can be absorbed and the stress can be reduced. Thereby, generation | occurrence | production of the crack in the interface of an insulating layer and sealing resin, and the external connection terminal 11 and the disconnection by a crack can be prevented.
The material of the holding body 15 is preferably engineer plastic having heat resistance. Here, the engineered plastic means a plastic having a heat resistance of 100 ° C. or higher, a strength of 49 MPa or higher, and a flexural modulus of 2.4 Gpa or higher.
Materials satisfying the above conditions include polyimide, polyamideimide, polyetherimide, thermoplastic polyimide, polyamide, polyacetal, polybutylene terephthalate, polyethylene terephthalate, polystyrene, syndiotactic polystyrene, polyphenylene sulfide, polyether ketone, liquid crystal polymer, polyether Examples include resins such as nitrile, fluororesin, polycarbonate, modified polyphenylene ether, polysulfone, polyethersulfone, and polyarylate. The material of the holder 15 may be a polymer alloy of the above engineer plastic.
[0043]
Next, the conductive material 16 must be fixed to the outside and be electrically connectable. As the conductive material 16 satisfying such conditions,
(1) Graphite, carbon or metal fine particle dispersion,
(2) Gold, silver, copper, aluminum, or nickel alone, or an alloy containing two or more of the above metals,
(3) Low melting point alloy mainly composed of tin or lead,
It is desirable to select from the above (1) to (3).
[0044]
Examples of the low melting point alloy include those using a metal such as mercury, gallium, or indium, but a solder (solder) alloy containing tin or lead as a main component is preferable from the viewpoint of manufacturing cost. As the solder alloy, eutectic solder or high melting point solder with an increased ratio of lead can be applied, and bismuth, cadmium, antimony, zinc, manganese, indium, tin, silver, etc. may be added as necessary. .
Also, as shown in the examples of FIGS. 8 and 9, an adhesive layer 27 is formed on the surface of the holding body 15 prior to disposing the conductive material 16 in order to improve the adhesion between the holding body 15 and the conductive material 16. May be formed.
[0045]
If the hollow portion of the holding body 15 is opened to the outside atmosphere, and the air (air) in the outside atmosphere can freely enter and leave the hollow portion, the moisture contained in the holding body 15 is transferred to the outside atmosphere. It can be released to prevent deterioration of the resin. Further, if the hollow portion of the holding body 15 is open to the external atmosphere, when heated during mounting, water vapor or expanded air in which the water in the holding body 15 is evaporated is released to the external atmosphere, and the holding body 15 Can be prevented from bursting. Furthermore, even if heat is applied to the semiconductor device after mounting, the moisture in the holding body 15 is released to the external atmosphere, so that the holding body 15 can be prevented from being ruptured or deteriorated.
[0046]
In addition, if the environment in which the semiconductor device (CSP1) is used has little heat change, and the stress generated between the semiconductor device and the mounting substrate is small, the shape of the holding body 15 does not have a hollow portion. It may be cylindrical.
[0047]
【Example】
Examples of the present invention will be described below.
<Example>
FIG. 2A shows a semiconductor element 2 obtained by a conventionally known means. The semiconductor element 2 has a silicon wafer as a base material, and an electrode 3 made of aluminum is formed. A passivation film 4 is formed on the semiconductor element 2 so as to expose the electrode 3. For convenience of explanation, FIG. 2A shows two semiconductor elements 2 out of a plurality of surfaces formed on a single silicon wafer.
[0048]
Next, after applying photosensitive polyimide (trade name “Paimel”, manufactured by Asahi Kasei Kogyo Co., Ltd.) on a silicon wafer, electrodes are formed on each semiconductor element 2 using a known photolithography method in which pattern exposure, development, and the like are performed. A first insulating layer 5 having a film thickness of about 10 μm exposing 3 was formed (FIG. 2B).
Next, a TiN layer (thickness: 200 nm) as the metal barrier layer 6 and a Cu layer (thickness: 500 nm) as the metal thin film layer 17 are collectively formed by sputtering on the surface side on which the first insulating layer 5 is formed. In this way, lamination was formed (FIG. 2C).
[0049]
Next, a photosensitive resist layer having a thickness of 20 μm is applied and formed on the metal thin film layer 17 by a spin coating method, and then the metal thin film layer 17 site where the metal post is formed is formed using a known photolithography method. An exposed plating mask was formed (FIG. 2D). Next, a metal post 9 made of Cu (copper) was formed on the metal thin film layer 17 exposed from the plating mask by electrolytic plating, and then the plating mask was peeled off (FIG. 2E). At this time, the metal thin film layer 17 was used as a conductor for plating power supply.
[0050]
Next, after forming a photosensitive resist layer having a film thickness of 1 μm by spin coating, the metal thin film layer 17 was patterned using a known photoetching method to form a wiring layer 7 having a predetermined pattern shape ( FIG. 2 (f)).
Next, after obtaining FIG. 2 (f), a photosensitive polyimide (manufactured by Asahi Kasei Kogyo Co., Ltd., trade name “Pimel”) is collectively applied to the surface side on which the wiring layer 7 is formed by a spin coating method. A photosensitive polyimide layer having a thickness of 10 μm was formed. Next, the photosensitive polyimide on the metal post 9 was removed by a known photolithography method to obtain a second insulating layer 8 (FIG. 3A).
[0051]
Next, a cooling heat sink material 12 having the same size as that of the silicon wafer was attached to the back surface of the silicon wafer opposite to the surface on which the semiconductor element 2 was formed. The material of the cooling heat sink material 12 was Cu (copper).
Next, dicing was performed at the boundaries between the semiconductor elements 2 to cut the semiconductor elements 2 into individual pieces. In addition, the cut | disconnection by dicing is put in the silicon wafer, and it does not put in the heat sink material 12 for cooling (FIG.3 (b)).
[0052]
Next, a sealing resin 10 having photosensitivity is applied to the silicon wafer surface so as to fill even the cuts formed by dicing by spin coating, and the resin is sealed, and then metal posts are formed by a known photolithography method. 9 The sealing resin 10 on the tip was removed (FIG. 3C).
Next, the external connection terminal 11 was placed on the metal post 9 (FIG. 3D).
The external connection terminal 11 used in this example has a stress relaxation function, and the conductive material 16 is formed on the surface of the hollow holding body 15 made of thermoplastic polyimide as shown in FIGS. The eutectic solder was formed as follows.
That is, first, a hollow thermoplastic polyimide tube having an inner diameter of 0.15 mm and a wall thickness of 50 μm was purchased in a long shape. Next, metallic chromium and copper were sequentially laminated on the tube surface (outer surface). Metal chromium and copper are used as the adhesive layer 27 when laminating conductive materials, and are formed by sputtering so that the metal chromium film thickness is 0.2 μm and the copper film thickness is 0.4 μm. Filmed. After forming the adhesive layer 17, eutectic solder having a thickness of about 20 μm was plated as the conductive material 16.
Next, after the eutectic solder was formed, each of the long thermoplastic polyimide tubes was cut to a length of about 0.3 mm to obtain the external connection terminals 11 used in this example, as shown in FIGS. .
[0053]
Next, as shown in FIG. 3D, after the external connection terminal 11 is placed, dicing including a heat sink material for cooling is finally performed so as to leave the sealing resin on the side surface of the semiconductor element 2. Thus, an independent semiconductor device (CSP1) was obtained (FIG. 3E).
[0054]
After mounting the semiconductor device (CSP1) obtained in the above embodiment on a printed circuit board, a thermal cycle test (−45 ° C. to + 125 ° C.) was performed on the printed circuit board. There were no defects such as cracks or internal disconnection.
[0055]
Although one embodiment of the present invention has been described above, the embodiment of the present invention is not limited to the above-described drawings and description, and various modifications may be made based on the spirit of the present invention. Needless to say.
[0056]
For example, the manufacturing conditions such as the material to be used and the thickness of the film to be formed may be appropriately set according to the specifications of the semiconductor device.
Further, as the external connection terminal having a stress relaxation function, a high melting point solder having a high Pb content or a solder ball having a multilayer structure with a ductile metal such as Cu may be used.
[0057]
【The invention's effect】
According to the method for manufacturing a semiconductor device of the present invention, it is not necessary to use an expensive metal mold for resin sealing. By using the method for manufacturing a semiconductor device of the present invention, the cost required for manufacturing the semiconductor device can be reduced. Can be reduced.
[0058]
Further, since the sealing resin can protect the outer periphery of the semiconductor element except for the upper surface of the metal post, it is excellent in airtightness and moisture resistance, and package cracks due to moisture absorption are less likely to occur. Furthermore, by providing the external connection terminal with a stress relaxation function, the stress (stress) caused by the difference in thermal expansion coefficient between the semiconductor device and the mounting substrate can be relaxed by the external connection terminal having the stress relaxation function. It is possible to prevent defects such as cracks and disconnections from occurring in the apparatus.
Further, by providing the cooling heat sink material on the back surface of the semiconductor element, a semiconductor device having excellent heat dissipation can be obtained.
[0059]
As described above, according to the semiconductor device manufacturing method of the present invention, a highly reliable semiconductor device (CSP) can be manufactured at low cost.
[0060]
[Brief description of the drawings]
FIG. 1 is an explanatory cross-sectional view schematically showing an example of a semiconductor device obtained by a method for manufacturing a semiconductor device of the present invention.
FIGS. 2A to 2F are cross-sectional explanatory views showing an embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.
FIGS. 3A to 3E are cross-sectional explanatory views showing an embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps. FIGS.
4A to 4D are cross-sectional explanatory views showing an example of a conventional method of manufacturing a semiconductor device in the order of steps.
FIGS. 5A to 5E are cross-sectional explanatory views showing an example of a conventional method of manufacturing a semiconductor device in the order of steps. FIGS.
6A to 6B are cross-sectional explanatory views showing an example of a conventional method of manufacturing a semiconductor device in the order of steps.
FIG. 7 is a cross-sectional explanatory view schematically showing an example of a semiconductor device obtained by a conventional method for manufacturing a semiconductor device.
FIG. 8 is an explanatory side view showing an example of an external connection terminal according to the present invention.
FIG. 9 is an explanatory cross-sectional view showing an example of an external connection terminal according to the present invention.
[Explanation of symbols]
1,70 CSP
2,72 Semiconductor element
3, 73 electrodes
4, 74 Passivation film
5, 75 First insulation layer
6, 76 Barrier layer
7, 77 Wiring layer
8, 78 Second insulation layer
9, 79 Metal post
10, 80 Sealing resin
11, 81 Terminal for external connection
12, 82 Heat sink material
15 Holder
16 Conductive material
17, 87 Metal thin film layer
27 Adhesive layer

Claims (3)

Forming a first insulating layer so as to expose the electrode on a wafer surface on which a semiconductor element having an electrode is formed; and a metal electrically connected to the electrode on a surface where the first insulating layer is formed A step of forming a thin film layer on one side, a step of forming a resist pattern for a plating mask on the metal thin film layer, a step of forming a metal post on a portion of the metal thin film layer exposed from the plating mask by electroplating, Removing the resist pattern for the plating mask, patterning the metal thin film layer to form a wiring layer, covering the wiring layer and the first insulating layer, and exposing the tip end surface of the metal post comprising at least a step of forming a second insulating layer, during the electroplating for the metal post forming, the metal thin film layer and the conductor for the plating feed, a second insulating layer In the step of forming, after coating a photosensitive insulating resin by spin coating, by removing the remaining insulating resin to the metal post distal end surface by photolithography, the second insulating layer, the metal post A method for manufacturing a semiconductor device, comprising: forming a second insulating layer so as to cover a side surface of the metal post and a height of a second insulating layer excluding a portion covering the side surface of the metal post to be lower than a height of a metal post front end surface .   A process of applying a cooling heat sink material to the back surface of the wafer after performing the second insulating layer forming process by the manufacturing method according to claim 1 on a wafer formed by imposing a plurality of semiconductor elements. And a step of dicing from the second insulating layer forming surface side to the boundary between the wafer and the heat sink material to divide the semiconductor elements, and to cover each of the separated semiconductor elements, and to the front surface of the metal post At least a step of resin-sealing a wafer including a semiconductor element so as to expose the semiconductor element, and a step of dicing and dicing including a heat sink material so as to leave a sealing resin on the side surface of the semiconductor element A method for manufacturing a semiconductor device.   3. The method of manufacturing a semiconductor device according to claim 2, wherein an external connection terminal having a stress relaxation function is provided on a tip surface of the metal post before dicing into pieces including the heat sink material. .

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