JP3764176B2 - Semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor device provided with an internal potential generation circuit.
In recent years, high speed has been promoted in semiconductor integrated circuit devices. In addition, lower power consumption has been promoted, and driving with a low power supply voltage has been pushed forward. Therefore, some semiconductor integrated circuit devices have an internal potential generation circuit for generating a high voltage necessary for driving the semiconductor integrated circuit device. By the way, if the generation of the high voltage is delayed with respect to the rise of the power supply voltage, there is a problem that the semiconductor integrated circuit device malfunctions during the delay. Therefore, it is necessary to speed up the increase of the high voltage in the internal potential generation circuit.
[0002]
[Prior art]
2. Description of the Related Art Some semiconductor integrated circuit devices require an internal potential that is higher or lower than a power supply voltage supplied for the operation. For example, in a DRAM (Dynamic RAM) or SRAM (Static RAM), the word line is set to a potential higher than the power supply voltage in order to prevent a decrease in the operation speed. Further, an EPROM (Erasable Programmable ROM) and an EEPROM (Electrically Erasable Programmable ROM) require a higher potential than the power supply voltage during a program operation. Therefore, some have an internal potential generation circuit that generates a high potential or a low potential from a power supply voltage.
[0003]
FIG. 4 is a block circuit diagram of the internal potential generation circuit. The internal potential generation circuit is a booster circuit, and includes an oscillation circuit 11, a pumping circuit 12, and an enhancement type N-channel MOS transistor (hereinafter referred to as NMOS transistor) 13. The oscillation circuit 11 is a ring oscillator circuit in which an odd number (three in FIG. 4) of inverter circuits 14 to 16 are connected in series and the output terminal of the inverter circuit 16 and the input terminal of the inverter circuit 14 are connected to each other. When the voltage Vcc is supplied, it oscillates based on the power supply voltage Vcc and outputs a rectangular wave pulse having a predetermined cycle.
[0004]
The pumping circuit 12 includes two enhancement type N-channel MOS transistors (hereinafter referred to as NMOS transistors) 17 and 18 and a capacitor 19. The gate and drain of the NMOS transistor 17 are connected to each other and to the high potential side power source Vcc. An NMOS transistor 18 having a gate and a drain connected to each other is connected to the source of the NMOS transistor 17. One end of a capacitor 19 is connected between the NMOS transistors 17 and 18, and the other end of the capacitor 19 is connected to the oscillation circuit 11. The source of the NMOS transistor 18 is connected to an internal circuit (not shown). The oscillation circuit 11 and the pumping circuit 12 constitute an internal potential generation circuit unit.
[0005]
When the high potential side power supply Vcc is input to the NMOS transistor 17, the potential of the node N1 between the NMOS transistors 17 and 18 becomes a potential that is lower than the high potential side power supply Vcc by the threshold voltage of the NMOS transistor 17. When a rectangular wave pulse from the oscillation circuit 11 is input, charges are accumulated in the capacitor 19 based on the rectangular wave pulse, and the potential at the node N1 is raised. That is, when the rectangular wave pulse rises from the L level to the H level, it rises from the potential of the node N1 toward the potential obtained by adding the H level potential of the rectangular wave pulse. Since the potential of the node N1 is lower than the high potential side power supply Vcc by the threshold voltage of the NMOS transistor 17, the boosted potential becomes higher than the high potential side power supply Vcc. Subsequently, when the rectangular wave pulse falls from the H level to the L level, the potential of the node N1 falls from a potential higher than the high potential side power source Vcc. Therefore, by controlling the rectangular wave pulse at a predetermined cycle, the potential of the node N1 is boosted to a potential higher than the high potential side power supply Vcc. When the boosted potential exceeds the threshold voltage of the NMOS transistor 18, the NMOS transistor 18 is turned on and is output to the internal circuit as the internal power supply voltage SVcc via the NMOS transistor 18. Accordingly, the internal power supply voltage SVcc becomes a potential that is lower than the potential of the node N1 by the threshold voltage of the NMOS transistor 18, and is output to the internal circuit with a delay as the NMOS transistor 18 is turned on.
[0006]
On the other hand, the gate and drain of the NMOS transistor 13 are connected to each other and to the high potential side power source Vcc, and the source is connected to the source of the NMOS transistor 18. The NMOS transistor 13 outputs an internal power supply voltage SVcc that rises based on the high potential side power supply Vcc to the internal circuit when the power is turned on, and prepares the operation of the internal circuit.
[0007]
That is, the NMOS transistor 13 makes the potential of the internal power supply voltage SVcc boosted by the pumping circuit 12 higher than 0 volts in advance when the pumping circuit 12 starts boosting. When the internal power supply voltage SVcc is to be boosted from 0 volts, the pumping circuit 12 takes time to reach a predetermined potential. When the internal power supply voltage SVcc is higher than 0 volts, the pumping circuit 12 takes time to boost the internal power voltage SVcc. Shortened. The operation thereof will be described in accordance with FIG.
[0008]
At startup of the semiconductor integrated circuit device, internal power supply voltage SVcc rises based on the rise of power supply voltage Vcc. That is, the semiconductor integrated circuit device is activated and remains at 0 volts until the power supply voltage Vcc exceeds the threshold voltage Vth of the NMOS transistor 13. When the power supply voltage Vcc exceeds the threshold voltage Vth of the NMOS transistor 13, the NMOS transistor 13 is turned on, and the internal power supply voltage SVcc is a potential (= Vcc−) which is lower than the power supply voltage Vcc by the threshold voltage Vth of the NMOS transistor 13. It rises at Vth).
[0009]
At this time, since the oscillation circuit 11 does not operate yet, a rectangular wave pulse is not output. Therefore, the internal power supply voltage SVcc rises at the potential of Vcc-Vth. In general, the current flowing through the drain of the NMOS transistor increases as the threshold voltage Vth increases. Accordingly, since the high-potential-side power supply Vcc has just exceeded its threshold voltage Vth, the NMOS transistor 13 has only a small amount of current flowing through its drain. Therefore, the current of the internal power supply voltage SVcc is small.
[0010]
Further, when the power supply voltage Vcc rises, the oscillation circuit 11 starts operating at point A in FIG. 5 and outputs a rectangular wave pulse. The pumping circuit 12 starts boosting based on the rectangular wave pulse, and the internal power supply voltage SVcc rises to a predetermined potential. The internal circuit operates based on the increased internal power supply voltage SVcc.
[0011]
[Problems to be solved by the invention]
However, the threshold voltage Vth of the NMOS transistor 13 may increase due to variations in the manufacturing process. The NMOS transistor 13 is not turned on unless the power supply voltage Vcc exceeds the increased threshold voltage Vth. Then, the potential of the internal power supply voltage SVcc at the point A becomes low, and the pumping circuit 12 boosts from the low potential. As a result, there is a problem that the time until the internal power supply voltage SVcc reaches a predetermined potential becomes long, and the internal circuit cannot operate accordingly.
[0012]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device including an internal potential generation circuit capable of quickly boosting the internal power supply voltage to a stable potential. is there.
[0013]
[Means for Solving the Problems]
FIG. 1 is a diagram illustrating the principle of the present invention. The semiconductor device includes a depletion type MOS transistor 1 and an internal potential generation circuit 2. Depletion Li Shon type MOS transistor 1 is Ru Tei provided between the power supply line of the supply voltage Vcc and the boost node. The internal potential generation circuit 2 sets the boosted node potential to a boosted voltage higher than the power supply voltage Vcc. Then, when the power is turned on, applies a power supply voltage V cc voltage equal to the gate of the depletion type MOS transistor 1.
[0014]
[Action]
Therefore, according to the present invention, the time until the boosted node by internal potential generation circuit 2 reaches the boosted voltage higher than the power supply voltage Vcc is shortened.
[0015]
【Example】
Hereinafter, an embodiment embodying the present invention will be described with reference to FIGS.
For convenience of explanation, the same components as those in FIG.
[0016]
As shown in FIG. 2, a depletion type N-channel MOS transistor (hereinafter referred to as a DpNMOS transistor) 21 is connected to the pumping circuit 12. The source of the DpNMOS transistor 21 is connected to the source of the pumping circuit 12NONMOS transistor 18, and the drain is connected to the high potential side power source Vcc. A power-on reset signal φ is input to the gate of the DpNMOS transistor 21. The power-on reset signal φ is used to prevent the malfunction of the semiconductor integrated circuit device by initializing the flip-flop circuit and latch circuit of the internal circuit when the power is turned on, and is generated by a power-on reset circuit (not shown). It has become.
[0017]
The DpNMOS transistor 21 is turned on when the threshold voltage V _TN is a negative value and the gate-source voltage V _GS is 0 volts. Therefore, when the power is turned on, the DpNMOS transistor 21 is on. As a result, the potential of the node N between the source of the DpNMOS transistor 21 and the pumping circuit 12, that is, between the source of the NMOS transistor 18 becomes the same potential as the high potential side power supply Vcc, and the node increases as the high potential side power supply Vcc rises. The potential of N also rises.
[0018]
The pumping circuit 12 inputs the potential of the node N, that is, the high potential side power supply Vcc. When the oscillation circuit 11 is not oscillating, the pumping circuit 12 outputs the potential of the node N as the internal power supply voltage SVcc. On the other hand, when the oscillation circuit 11 oscillates and outputs a rectangular wave pulse, the pumping circuit 12 receives the rectangular wave pulse, boosts the potential from the node N based on the rectangular wave pulse, The internal power supply voltage SVcc is output to the internal circuit.
[0019]
This and come, the gate-source voltage V _GS of DpNMOS transistor 21 becomes the potential difference of the internal power supply voltage SVcc for potential V.phi of the power-on reset signal φ inputted to the gate V1 (= Vφ-SVcc). When the potential V1 of the difference is smaller than the threshold voltage V _TN, DpNMOS transistor 21 is turned off. The potential of the high potential power source Vcc when the oscillation circuit 11 starts the oscillation operation is set to be equal to the potential of the high potential power source Vcc when the power-on reset signal φ falls. Therefore, when the power-on reset signal φ falls, the oscillation circuit 11 starts an oscillation operation. The threshold voltage V _GS of the DpNMOS transistor 21 is set equal to the potential of the high potential side power supply Vcc when the oscillation circuit 11 starts the oscillation operation.
[0020]
That is, when the power is turned on and the high-potential side power supply Vcc rises, the power-on reset signal φ rises in the same manner as the high-potential side power supply Vcc. The potential V1 (= Vφ−SVcc) of the difference between the voltages SVcc, that is, the gate-source voltage V _GS is 0 volt. Accordingly, the DpNMOS transistor 21 is turned on. When the power-on reset signal φ falls and the oscillation circuit 11 starts oscillating, the gate-source voltage V _GS of the DpNMOS transistor 21 becomes lower than the threshold value V _TN and the DpNMOS transistor 21 is turned off.
[0021]
Next, the operation of the internal potential generating circuit configured as described above will be described with reference to FIG.
Now, when an external power supply is supplied to a semiconductor integrated circuit device having an internal potential generation circuit, the high potential side power supply Vcc rises based on the external power supply. Further, the potential Vφ of the power-on reset signal φ also rises in the same manner as the high potential side power supply Vcc. At this time, since the DpNMOS transistor 21 is in the ON state, the potential of the node N rises similarly to the potential of the high potential side power supply Vcc. On the other hand, the oscillation circuit 11 does not oscillate and does not output a rectangular wave pulse because the high potential side power supply Vcc has not risen to the potential required for its operation. Therefore, the pumping circuit 12 outputs the input potential of the node N as the internal power supply voltage SVcc. Since the DpNMOS transistor 21 is on, the internal power supply voltage SVcc rises in the same manner as the high potential side power supply Vcc rises.
[0022]
When the high potential side power supply Vcc further rises and the power-on reset signal φ falls to a potential that falls, the oscillation circuit 11 starts an oscillation operation and outputs a rectangular wave pulse. The pumping circuit 12 inputs the rectangular wave pulse and starts a boosting operation. At this time, the internal power supply voltage SVcc rises together with the high potential side power supply Vcc. As a result, the time until the internal power supply voltage SVcc reaches a predetermined potential is shortened.
[0023]
At this time, the power-on reset signal φ input to the gate of the DpNMOS transistor 21 rises in the same manner as the high potential side power supply Vcc. Further, the source potential of the DpNMOS transistor 21 rises in the same manner as the high potential side power supply Vcc because the DpNMOS transistor 21 is in the ON state. As a result, the gate-source voltage V _GS of the DpNMOS transistor 21 becomes 0 volts. The drain current of the DpNMOS transistor 21 flows more when the gate-source voltage V _GS is higher, and decreases as it approaches the threshold voltage V _TN . Since the gate-source voltage V _{GS of} the DpNMOS transistor 21 is 0 volts, a large amount of current flows through the drain and is supplied to the pumping circuit 12. Since this current is supplied from the pumping circuit 12 to the internal circuit, a large amount of current of the internal power supply voltage SVcc flows.
[0024]
On the other hand, the power-on reset signal φ input to the gate of the DpNMOS transistor 21 falls, and the potential Vφ becomes 0 volts. Further, the internal power supply voltage SVcc, which is the source potential of the DpNMOS transistor 21, rises based on the rectangular wave pulse output from the oscillation circuit 11 since the oscillation circuit 11 starts an oscillation operation. As a result, the gate-source voltage V _GS of the DpNMOS transistor 21 becomes smaller than the threshold voltage V _TN . Accordingly, the DpNMOS transistor 21 is turned off. Then, since no current flows through the DpNMOS transistor 21, the DpNMOS transistor 21 does not become a load with respect to the internal power supply voltage SVcc.
[0025]
As described above, in this embodiment, the DpNMOS transistor 21 that is turned on when the high potential side power supply Vcc rises is connected to the pumping circuit 12 of the internal potential generation circuit, and the high potential side that rises through the DpNMOS transistor 21. The power supply Vcc was input. When the high potential side power supply Vcc further rises and the oscillation circuit 11 starts oscillating and outputs a rectangular wave pulse, the pumping circuit 12 generates a higher potential than the high potential side power supply Vcc based on the rectangular wave pulse. The high potential is output to the internal circuit as the internal power supply voltage SVcc.
[0026]
As a result, the internal power supply voltage SVcc can be quickly boosted to a stable potential.
The present invention may be carried out in the following modes in addition to the above embodiments.
[0027]
(1) In the above embodiment, instead of the power-on reset signal φ input to the gate of the DpNMOS transistor 21, the gate may be connected to the low potential side power source Vss. Off this time, DpNMOS transistor 21 when the voltage of the difference between the internal power supply voltage SVcc of low potential side power supply Vss and the source V2 (= Vss-SVcc) becomes a potential lower than the threshold voltage V _TN of DpNMOS transistor 21 It becomes a state. That is, since the high potential side power supply Vcc is 0 volt, the DpNMOS transistor 21 is turned off when the internal power supply voltage SVcc becomes larger than the absolute value | V _TN | of the threshold voltage.
[0028]
(2) inside the above embodiment has been applied to the internal potential generation circuit for generating an internal power supply voltage SVcc obtained by boosting the power supply voltage Vcc, for generating an internal step-down voltage V _BB obtained by reducing the low supply voltage V _EE than 0 volts You may apply to an electric potential generation circuit. In this case, carried by substituting DpNMOS transistor 13 to depletion Li Shon type P-channel MOS transistor. The internal step-down potential V _BB generated by the internal potential generation circuit is used as a well bias voltage applied to the well of the semiconductor substrate in order to secure the back gate voltage of the semiconductor integrated circuit device. With this configuration, the application of the well bias voltage can be accelerated.
[0029]
【The invention's effect】
As described above in detail, according to the present invention, there is an excellent effect that the internal power supply voltage can be quickly boosted to a stable potential.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is a block circuit diagram illustrating an internal potential generation circuit according to one embodiment.
FIG. 3 is a waveform diagram for explaining the operation of the internal potential generating circuit according to the embodiment;
FIG. 4 is a block circuit diagram illustrating a conventional internal potential generation circuit.
FIG. 5 is a waveform diagram for explaining the operation of a conventional internal potential generating circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Depletion type MOS transistor 2 Internal potential generation circuit part 11 Oscillation circuit 12 Pumping circuit Vcc Power supply voltage (high potential side power supply)
Vout Internal potential Va Voltage

Claims (3)

A depletion type MOS transistor provided between the power supply line of the power supply voltage and the boost node;
Semiconductor, characterized in that the potential of the boosting node and an internal potential generation circuit for boosting a potential higher than the power supply voltage, when the power is turned on to apply the power source voltage and voltage equal to the gate of the depletion type MOS transistor apparatus. The semiconductor device according to claim 1,
Wherein a given power-on reset signal to the gate of the front Kide Prin Shon type MOS transistor. A depletion type MOS transistor provided between the power supply line of the power supply voltage and the boosting node and having a gate connected to the ground potential ;
An internal potential generation circuit that boosts the potential of the boosting node to a potential higher than the power supply voltage .

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