JP3760022B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device technology, and particularly to a semiconductor memory device capable of reducing the area, specifically, simplifying a sub word driver and reducing the area while maintaining the advantages of the hierarchical word line system. It is related to effective technology.
[0002]
[Prior art]
For example, as a technique studied by the present inventor, a DRAM as an example of a semiconductor memory device employs a CMOS structure in order to increase the speed of the word driver itself, further improves the manufacturing yield of the word line itself, and reduces the wiring delay. In order to reduce the resistance, the so-called hierarchical word line method has been put into practical use instead of the so-called word line shunt method in which the resistance is lowered by lining the word line made of polysilicon or polycide layer of relatively high resistance with metal wiring. ing.
[0003]
In other words, the word line shunt system has been hampered by the increase in delay of thin and long aluminum wiring in response to the recent trend toward higher integration and larger capacity such as 64M bits and 256M bits. As a technique for drastically solving, a hierarchical word line system has been adopted. In this hierarchical word line system, the word lines are divided into multiple sub-word lines, and a set of row decoders and word drivers are shared by a plurality of sub-word lines, so that the metal wiring pitch (main word line, pre-decoder line) Is relaxed from the pitch of the memory cells, and the manufacturing yield of the metal wiring is increased.
[0004]
A technique related to a semiconductor memory device including such a hierarchical word line system is described in, for example, “Advanced Electronics I-9 VLSI Memory” P151 to P161 issued on November 5, 1994, published by Baifukan Co., Ltd. Technology.
[0005]
[Problems to be solved by the invention]
The inventor of the present invention pays attention to reducing the area while maintaining the advantages of the hierarchical word line system in the semiconductor memory device using the hierarchical word line system as described above, particularly about the structure of the sub word driver. investigated. The contents studied by the present inventor will be described below with reference to FIGS.
[0006]
FIG. 6 shows a word line structure in a hierarchical word line system. The main row decoder area 11, the main word driver area 12, the memory cell subarray 15, the sense amplifier area 16, the sub word driver area 17, and the intersection area 18 are shown. Etc. are shown. Main word line MWB (B is MW (true: true) inversion (bar) notation, and so on) and predecoder line FXB are formed of a metal wiring layer (for example, an aluminum layer), and sub word line SW is formed of a polysilicon or polycide layer. . Since the sub word line SW drives the transistor of the memory cell, the repetition pitch of the sub word line SW is as fine as the repetition pitch of the memory cell.
[0007]
For example, when the memory cell sub-array 15 of FIG. 6 is composed of 256 sub-word lines SW, the main word line MWB is 32, the predecoder line FXB is 8 and the sub-word driver performs a logical operation and 256 sub-word lines. Select one from SW. Since the metal wiring layer requires only 32 main word lines MWB and 8 predecoder lines FXB, the repetition pitch is relaxed to 256 / (32 + 8) = 6.4 times the repetition pitch of the memory cells. The sub word lines SW are alternately output from the sub word drivers on both sides of the memory cell sub array 15.
[0008]
Further, an FX driver is placed in the intersection region 18 between the sense amplifier region 16 and the sub word driver region 17, and an output of the predecoder line FX shaped from the input of the predecoder line FXB is generated and supplied to the sub word driver. In the intersection region 18, a control circuit (switch MOS transistor, etc.) for the sense amplifier group is also placed. In FIG. 6, M represents a metal wiring layer, represented by a metal 2 layer M2 and a metal 3 layer M3, and FG shown in FIG. 7 described later represents a gate layer of a MOS transistor.
[0009]
FIG. 7 shows the circuit configuration and operation waveforms of a typical subword driver. It consists of three transistors, a PMOS transistor MP1 and NMOS transistors MN1 and MN2, and has the disadvantage that the area becomes large. Fig. 7 (b) shows the operation waveform diagram. Here, VPP is an in-chip boost voltage that becomes a selection voltage of the word line.
[0010]
For example, when the main word line MWB is Low, the predecoder line FXB is Low, and the predecoder line FX is High, the sub word line SW is in a selected state of High level (VPP). The reason why the NMOS transistor MN2 is necessary is that when the main word line is selected and the predecoder line is not selected (MWB is Low, FXB is High, and FX is Low), the sub word line SW is fixed to the VSS level (0 V). is there. Without this NMOS transistor MN2, in this input state, the sub word line SW is not lowered below the threshold voltage Vth of the PMOS transistor MP1, and the potential easily rises even though it is not selected due to induction noise between signals. As a result, a leak current flows through the memory cell transistor, and the memory cell information is destroyed.
[0011]
As described above, the hierarchical word line method can improve the manufacturing yield by reducing the word line pitch (6.4 times in FIG. 6) as compared with the well-known word line shunt method, but the chip area is increased by a large number of sub word drivers. There is a disadvantage of becoming larger.
[0012]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of reducing the area of a sub word driver, which is the drawback, and further increasing the speed while maintaining the advantages of the hierarchical word line system.
[0013]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0014]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0015]
That is, the semiconductor memory device according to the present invention is applied to a semiconductor memory device having a hierarchical word line configuration, and the sub word driver is composed of one PMOS transistor (MP1) and one NMOS transistor (MN1). The low level of the main word line (MWB) is set to a negative voltage, and the output level of the sub word line (SW) is set to 0 V when not selected and set to the high level when selected.
[0016]
As a result, the number of sub-word drivers can be reduced from three to two MOS transistors, the sub-word drivers can be reduced, and the chip area can be reduced.
[0017]
In particular, the negative voltage Low level of the main word line can be the same voltage as the substrate voltage. As a result, the output voltage of the substrate voltage generation circuit can be used, so that it is not necessary to newly provide a special negative voltage generation circuit. As another result, the gate-source voltage of the PMOS transistor is increased by the negative voltage of the main word line, so that the load driving capability of the sub-word line is improved and the effect of speeding up can be expected.
[0018]
Further, the process of changing the main word line from the high level to the negative voltage low level is changed to 0V once and then to the negative voltage in two stages. As a result, high speed is achieved by using the negative voltage of the main word line, and most of the discharge current of the main word line is made to flow to 0 V, reducing the current supply burden of the negative voltage generation circuit and suppressing an increase in current consumption. Can do.
[0019]
In the semiconductor memory device according to the present invention, the predecoder line (FX) is directly arranged on the memory cell subarray, and the subword driver is directly driven from the FX driver near the main word driver. As a result, the load on the predecoder line can be reduced to increase the speed.
[0020]
Specifically, in the sub word driver, the gates of the PMOS transistor and the NMOS transistor are commonly connected to the main word line, the drain is commonly connected to the sub word line, the source of the PMOS transistor is the predecoder line, and the source of the NMOS transistor is 0V. They are connected to each other.
[0021]
At this time, the main word line is set to the negative first voltage and the positive second voltage, the predecoder line is set to the third voltage and the second voltage of 0 V, and the output level of the sub word line is the third voltage when not selected. The second voltage is selected at the time of selection.
[0022]
In particular, the semiconductor memory device is applied to a large capacity DRAM, for example, a DRAM of 64M, 256M or more, a synchronous DRAM, and the like.
[0023]
Therefore, according to the semiconductor memory device, the chip area is reduced by reducing the area of the sub-word driver, which is a bottleneck in improving the memory cell occupancy ratio such as DRAM and synchronous DRAM, which tend to increase in capacity. In addition, the negative voltage of the main word line, the improvement of the load driving capability of the sub-word line, and the load on the predecoder line can be reduced to achieve high speed.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the same members are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0025]
1A and 1B are a layout view and a partially enlarged view showing a semiconductor memory device according to an embodiment of the present invention, and FIGS. 2A and 2B show a sub word driver in the present embodiment. 3A and 3B are a circuit diagram and an operation waveform diagram showing a main word driver, a related main row decoder and an FXB driver, and FIGS. 4A and 4B are diagrams. FIG. 5 is a circuit diagram showing a negative voltage VBB generating circuit.
[0026]
First, the configuration of the semiconductor memory device of this embodiment will be described with reference to FIG.
[0027]
The semiconductor memory device of the present embodiment is, for example, a 64-Mbit or 256-Mbit DRAM using a hierarchical word line configuration. The memory chip 10 includes a main row decoder area 11, a main word driver area 12, a column decoder area. 13, peripheral circuit / bonding pad region 14, memory cell subarray 15, sense amplifier region 16, subword driver region 17, intersection region 18 and the like are formed on one semiconductor chip by a well-known semiconductor manufacturing technique. In FIG. 1, the horizontal direction is the row direction (word line direction), and the vertical direction is the column direction (bit line direction).
[0028]
In this DRAM, for example, as shown in FIG. 1, memory regions including memory cell subarrays 15 are divided and arranged on the left and right sides in the row direction of the memory chip 10 and on the upper and lower sides in the column direction. The memory areas arranged on the left side and the right side are arranged in pairs with the main row decoder area 11 arranged in the center via the main word driver area 12 corresponding to each memory area.
[0029]
In addition, column decoder regions 13 corresponding to the respective memory regions are disposed on the center side of the memory regions disposed on the upper side and the lower side. In addition, a row address buffer, a column address buffer, a predecoder, a timing generation circuit, a data input / output circuit, and the like are arranged as a peripheral circuit / bonding pad region 14 in the central portion, and a bonding pad for external connection is provided. It has been.
[0030]
In the memory region, a sense amplifier region 16 is arranged in the column direction of the memory cell sub-array 15 and a sub word driver region 17 is arranged in the row direction. An FX region is provided in the intersection region 18 between the sense amplifier region 16 and the sub word driver region 17. A driver and a control circuit (a switch MOS transistor, etc.) of a sense amplifier group are also arranged. With respect to the memory cell subarray 15, the word lines are in the row direction and the bit lines are in the column direction. It is obvious that the present invention can be used in the opposite arrangement.
[0031]
In the hierarchical word line configuration configured as described above, the sub word lines arranged in the row direction are outputs of the sub word driver, and the sub word driver has a pre-decoder line different from the main word line output from the main word driver. Input and perform logic operation. When a main word line as an input is selected and a pre-decoder line in the column direction is further selected, a specific sub word driver outputs a high level voltage to the sub word line, and all the sub word drivers connected to the sub word line The read operation and write operation of the memory cell are started.
[0032]
FIG. 2 is a circuit diagram and an operation waveform diagram of an example of the sub word driver in the embodiment of the present invention.
[0033]
In this embodiment, the sub-word driver is composed of two MOS transistors, one PMOS transistor MP1 and one NMOS transistor MN1. Further, the low level potential of the main word line MWB is a negative voltage.
[0034]
Specifically, the gates of the PMOS transistor MP1 and the NMOS transistor MN1 are commonly connected to the main word line MWB, the drains are commonly connected to the sub word line SW, and the source of the PMOS transistor MP1 is connected to the predecoder line FX. The source of the NMOS transistor MN1 is connected to 0V. In this case, the low level of the main word line MWB is a negative voltage, the high level is a voltage VPP, and the predecoder line FX is 0 V and the voltage VPP.
[0035]
For example, even when the main word line MWB is at a selected low level and the predecoder line FX is at a non-selected 0V, the sub word line SW is set to 0V by applying a negative voltage equal to or lower than − | Vth | to the gate of the PMOS transistor MP1. As described with reference to FIG. 7, the non-selection level does not rise above 0V. By simplifying this circuit, the area occupied by the sub-word driver can be reduced by about 15% (the length in the word line direction is reduced from 40 μm to 35 μm).
[0036]
As for the negative voltage of the main word line MWB, if the output voltage of the substrate bias generation circuit originally required for the DRAM is used, it is not necessary to provide a special negative voltage generation circuit. The accompanying effect of the present invention is that the gate-source voltage of the PMOS transistor MP1 is increased by the negative voltage of the main word line MWB, so that the load driving capability of the PMOS transistor MP1 with respect to the sub-word line SW is increased, and the effect of increasing the speed is also expected. it can.
[0037]
As a driving method of the predecoder line FX, as shown in FIG. 6, the predecoder line FXB is arranged on the memory cell subarray, a signal of the predecoder line FX shaped by the FX driver in the intersection region is generated, and the subword driver There are ways to supply. Alternatively, since the signal on the predecoder line FXB is no longer necessary for the sub word driver of FIG. 2, the FX driver on the intersection region with this is eliminated, and instead, the predecoder line FX is directly arranged on the memory cell subarray, and the main word driver The subword driver may be directly driven from a nearby FX driver.
[0038]
FIG. 3 is a circuit diagram and an operation waveform diagram of the main word driver, the related main row decoder, and FXB driver in the embodiment of the present invention.
[0039]
Here, VPP is an in-chip boost voltage that becomes a selection potential of the word line. VDD is an externally applied power supply voltage of 3.3 V or 5 V, for example. Depending on the type of DRAM, an internal step-down method may be used to reduce power consumption, and most peripheral circuits may be operated at a voltage VL lower than the voltage VDD. At that time, it is natural to apply a signal at the voltage VL level instead of the voltage VDD level.
[0040]
This main word driver has a negative voltage conversion unit surrounded by a broken line in addition to a normal level conversion circuit for converting a VPP amplitude precharge signal XDPHk, a VDD amplitude predecoder input AX3i, AX6j, and MSBk to a voltage VPP amplitude. is doing. A broken line portion is a circuit that supplies a negative voltage as a low potential of the main word line MWB.
[0041]
The feature of this circuit is that when the main word line MWB changes from the High (VPP) level to the Low level, first, until the voltage reaches 0 V, the inverter is composed of a PMOS transistor and an NMOS transistor on the left side in FIG. By the operation of the circuit shown by the broken line, the voltage is finally lowered to the level of the voltage VBB. This is because most of the discharge current of the main word line MWB is caused to flow to the voltage VSS, thereby reducing the burden on the negative voltage VBB generation circuit and suppressing an increase in current consumption.
[0042]
As is well known, since the negative voltage VBB generation circuit generates a negative voltage by a charge pumping operation, the energy efficiency is poor, and it is necessary to suppress the current flowing into the voltage VBB as much as possible. The PWELL voltage for forming the NMOS for pulling down the main word line MWB should be pulled to the voltage VBB as shown in the figure. In order to realize two kinds of NMOS PWELL voltages VBB and 0 V in the same chip, a triple well structure is required. This structure is also an essential structure in recent highly integrated DRAMs for other reasons (noise prevention, MOS performance enhancement, etc.), so it can be used.
[0043]
Assuming a 64-Mbit or 256-Mbit DRAM or a synchronous DRAM as in this embodiment, among the input signals of the main row decoder, XDPHk is the precharge signal of the decoder, and AX3i is the eight signals generated from A3 to A5. One of the predecoder signals, AX6j is one of the four predecoder signals made from A6 and A7, and MSBk is one of the 16 mat selection signals made from A8 to A11. The FXB driver generates a signal of the predecoder line FXB at the voltage VPP level from the address information of A0 to A2 and the mat selection information of MSBk. This does not require a negative voltage.
[0044]
Strictly speaking, in the sub-word driver of FIG. 7, the high level of the predecoder line FXB may be the level of the voltage VDD, but the high level of the predecoder line FX requires the level of the voltage VPP, and the voltage in a narrow crossing region. Since it is impossible to provide a level conversion circuit for the VPP, the level is converted to the level of the voltage VPP by an FXB driver having a sufficient area.
[0045]
FIG. 4 is a schematic diagram showing a plan layout for realizing the sub-word driver circuit of FIG. 2 and a cross-sectional structure diagram under the gate.
[0046]
This layout shows that eight sub-word lines SW0 to SW14 (even number) are output, but eight sub-word lines SW1 to SW15 (odd number) are alternately displayed from left and right adjacent sub-word drivers (not shown). Since they are wired, a total of 16 sub word lines SW0 to SW15 are arranged in the vertical dimension in this figure.
[0047]
The main word line MWB of the metal 2 layer M2 and the sub word line SW of the polycide layer run in the horizontal direction, and the predecoder line FX and the power supply lines (VPP, VSS) of the metal 3 layer M3 are placed in the vertical direction. The extraction of the source / drain in the sub word driver is performed by the metal 1 layer M1. If the bit line layer is used for inter-element connection, it is possible to use two layers of metal instead of three layers. The output of the sub word line SW at the left and right ends of the sub word driver is converted from the metal 1 layer M1 to the gate layer FG and sent to the memory cell sub array.
[0048]
FIG. 5 is a circuit diagram showing an example of a known negative voltage VBB generation circuit.
[0049]
The negative voltage VBB generation circuit generates a negative voltage by a charge pumping operation. Conventionally, this circuit is provided to apply to the substrate voltage in DRAM, but in this embodiment, it is also applied to the main word driver and used to generate a negative voltage on the main word line MWB as shown in FIG. . For this reason, the current supply capability of the negative voltage VBB generating circuit needs to be slightly strengthened as compared with the prior art. However, as described in FIG. 3, the current burden of the voltage VBB does not increase so much in the method of pulling down the main word line MWB in two stages.
[0050]
This negative voltage VBB generation circuit (FIG. 5) is obtained by connecting two CMOS charge pump circuits in parallel. For example, a low power pump circuit that always operates and a high-speed operation only when a large supply current is required. The circuit configuration is combined with a high power pump circuit. The high power pump circuit operates every time it is accessed from the outside of the chip (application of a low level of RASB), and can generate a large supply current commensurate with the magnitude of the current generated during access.
[0051]
Here, a typical operation mode of a DRAM, which is a read operation, a write operation, a refresh operation, and a high-speed column mode, will be briefly described.
[0052]
(1) Read operation
In this read operation, for example, in the address multiplex, the address signal is input in a time-sharing manner, so two synchronization signals of the row address strobe signal RASB and the column address strobe signal CASB are required. The period when RASB is at a high level is a period during which the row-related circuit is precharged. During this period, no memory operation is performed inside the chip. On the other hand, while CASB is at a high level, column-related circuits such as a data output buffer and a data input buffer are precharged, and during this period, reading and writing operations outside the chip are not performed.
[0053]
When RASB goes low, the row-related circuit is activated and the memory operation starts. Subsequently, when CASB becomes Low level, a read operation or a write operation starts, and data is exchanged with the outside of the chip. Thus, in the DRAM, the precharge period and the active period are alternately repeated. Normally, the RASB cycle time becomes the chip cycle time.
[0054]
The designation of the read operation is performed by setting the write control signal WEB to a high level before the falling edge of CASB and holding it until CASB rises. Once the data is output, it is held until CASB rises. There are three types of access time, and the time from when RASB and CASB fall to when data is output to the data output terminal is called RASB access time and CASB access time, respectively. The time from the start to the output of data is called the address access time.
[0055]
(2) Write operation
In this write operation, the relationship between the address signal and the RASB and CASB is the same as that in the read operation, and is therefore omitted. Also, the RASB and CASB timing standards such as the cycle time are exactly the same as the read operation. However, the write operation is designated by setting the write enable signal WEB to the Low level before the falling edge of CASB. During this cycle, the data output terminal is held in a high impedance (High-Z) state. There is also a specification of Read Modify Write operation in which the data once read out of the chip is changed outside and written to the same memory cell again while the RASB remains at the Low level.
[0056]
(3). Refresh operation
In this refresh operation, there are a refresh operation that is interrupted during a random access operation such as reading and writing, and a refresh operation that is performed only for holding stored information in the chip during a battery backup period. In the former, RASB only refresh and CBR (CASB before RASB) refresh are standard, and in the latter, self-refresh is standard. In addition, there is a hidden refresh that refreshes while outputting data.
[0057]
For example, in RASB only refresh, all memory cells in one row (word line) are refreshed simultaneously during one RASB cycle of the same timing standard as the read / write operation. However, the refresh address must be given from outside the chip by setting CASB to High level. Within a maximum refresh time period, word lines must be sequentially selected and refreshed by a combination of address signals.
[0058]
There are two types of refresh methods: centralized refresh and distributed refresh. Centralized refresh is a method in which refresh is repeated in the minimum cycle and memory access from outside the chip is not possible during this period, but memory access is accepted from outside without interrupting refresh during the remaining period. In the distributed refresh, one cycle of the refresh operation is equally distributed during the maximum refresh time. Actually, since distributed refresh is frequently used, one cycle of the refresh operation is a timing at which the cycle of the normal read / write operation is interrupted.
[0059]
In CBR refresh, CASB is set to Low level before RASB to determine internally that it is a refresh operation. By this determination pulse, an address is generated from the internal refresh address counter, and a word line is selected and refreshed. Therefore, it is not necessary to give an address signal from the outside.
[0060]
Further, in the self-refresh, after the end of a normal memory cycle, the RASB pulse width is set to, for example, 100 μs or more at the CBR timing. Internally, when this time is exceeded, a refresh operation using a refresh address counter and a refresh timer starts, and self-refreshing continues as long as both CASB and RASB are at a low level. The lower the refresh frequency, the lower the power consumption of the chip. This frequency is automatically adjusted by a timer that detects the temperature in the chip. It should be noted that a RASB precharge period is required when shifting from the self-refresh to the normal cycle.
[0061]
(4) .High-speed column access operation
In a system employing a cache memory, an image memory, or the like, in many cases, a row address is fixed and a column address is different, and many bits of a continuous column address are accessed. The column access mode utilizes structural features of the memory cell subarray that can be accessed in parallel. Since the multi-bit data of the column address can be processed at high speed, attention has recently been paid to the above-mentioned use.
[0062]
In this operation, first, a row (word) line is selected by a row address, and all memory cells on the word line are once read out to the respective data lines in a state amplified by a sense amplifier. Next, if the column address is sequentially changed so that the read information of a certain data line is taken out of the chip by the column address and then the information of the other data line is taken out by another column address, all the data on the word line Cell information can be extracted continuously, and this operation is fast.
[0063]
The access time in this case is the time from the input of the column address to the output of the data, that is, the address access time itself, and the operation time of the row-related circuit that takes a long time, for example, the driving time of the word line and the sense This is because there is no need to consider time. The cycle time is also faster by this amount.
[0064]
The write operation is also fast because the cell signal amplified data read to the data line is simply replaced with the write data supplied from the outside. After applying the write data voltage to all of the desired data lines, the word line is turned off to complete the write in the column access mode. As described above, various column access modes in which only the column address is switched while the row address remains the same have been proposed. Here, operation timings of typical high-speed page mode, nibble mode, and static column mode will be described.
[0065]
For example, at the read timing in the high-speed page mode, the column address selection is random and the cycle time is 40 ns, for example. Inside the chip, an ATD (Address Transition Detector) circuit precharges the main column circuits for each cycle, and the read data of the data line selected by the column address is controlled and output by the CASB near the data output buffer. . Due to standards such as address setup time and address hold time with CASB, there is a limit to speeding up the chip.
[0066]
At the nibble mode read timing, data is input / output, for example, in units of 4-bit shift registers. However, only the first bit in 4 bits can be specified at random using a 2-bit address signal. That is, the first bit is a normal read or write operation, but the subsequent 3 bits are continuously output only by the CASB clock pulse. It is not necessary to specify a column address except for the first bit.
[0067]
In this mode, four data latch circuits near the data output terminal and a ring counter type shift register with a 4-bit decoding function that receives the output are provided. Read data input in parallel from the four memory cell subarrays and temporarily stored in the four data latch circuits are converted in series by the shift register and continuously output to the outside in synchronization with CASB. Since this shift register is originally high speed, the nibble mode cycle is determined by the CASB cycle and is relatively fast, for example, 35 ns.
[0068]
Further, at the read timing of the static column mode, the column address is changed under the same row address, and the amplified data read to the data line is read / written. During the continuous cycle, CASB remains at the low level, and the address signal has no don't care portion. This is because the column address cannot be latched by CASB. The column address designation is random, and the cycle time is determined only by address switching. The column-related circuit is selected only by the operations of the ATD circuit and the column address buffer.
[0069]
As described above, the read operation, the write operation, the refresh operation, and the high-speed column access operation for the DRAM memory cells are performed. The DRAM is controlled by the rising / falling of the control signals of RASB, CASB, and WEB, whereas in the case of a synchronous DRAM, it is controlled by a command. This command is controlled by the chip select signals CSB, RASB, CASB, and WEB. Defined by combination.
[0070]
Therefore, according to the semiconductor memory device of the present embodiment, the sub word driver is composed of two MOS transistors of one PMOS transistor MP1 and one NMOS transistor MN1, and further the low level potential of the main word line MWB is set. By using a negative voltage, it is possible to reduce the chip area by reducing the size of the sub word driver in terms of layout, and it is possible to realize higher speed in terms of operation performance.
[0071]
In this embodiment, since the signal of the predecoder line FXB is unnecessary, instead, the predecoder line FX is directly arranged on the memory cell subarray, and the subword driver is directly driven from the FX driver near the main word driver. Higher speed can be realized by reducing the load on the predecoder line FXB.
[0072]
Further, the main word line MWB is discharged from the voltage VPP to 0 V, and then lowered to the level of the voltage VBB, so that most of the discharge current of the main word line MWB is caused to flow to the ground, thereby generating a negative voltage VBB generating circuit. Can be reduced, and an increase in current consumption can be suppressed.
[0073]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0074]
In the above description, the case where the invention made mainly by the present inventor is applied to a semiconductor memory device using DRAM, which is the technical field to which the present invention belongs, has been described. However, the present invention is not limited to this, and SRAM, RAM, ROM, PROM The present invention can also be widely applied to other semiconductor memory devices such as EPROM and EEPROM.
[0075]
【The invention's effect】
Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0076]
(1) Since the sub word driver is composed of two MOS transistors, the number of MOS transistors can be reduced, so that the sub word driver can be reduced. As a result, the chip area can be reduced in the chip layout.
[0077]
(2) By making the low level of the main word line a negative voltage, the output level of the sub word line is 0V when not selected, and the high level when selecting, the speed can be increased by utilizing the negative voltage of the main word line. It becomes. Furthermore, since the voltage between the gate and source of the PMOS transistor is increased by the negative voltage of the main word line, the load driving capability of the sub word line is increased and the effect of speeding up can be expected.
[0078]
(3) Since the output voltage of the substrate voltage generation circuit can be used by setting the low level of the main word line to the substrate voltage, it is not necessary to provide a new negative voltage generation circuit.
[0079]
(4) By changing the main word line from the high level to the low level in two steps from 0V to a negative voltage, most of the discharge current of the main word line flows to 0V. Therefore, it is possible to reduce the burden on the negative voltage generation circuit and suppress an increase in current consumption.
[0080]
(5) By placing the predecoder line directly on the memory cell subarray and driving the subword driver directly from the FX driver near the main word driver, it is possible to reduce the load on the predecoder line and increase the speed. It becomes.
[0081]
(6) According to the above (1) to (5), in a semiconductor memory device having a hierarchical word line structure such as a DRAM or a synchronous DRAM which tends to have a large capacity, the word line pitch of the hierarchical word line system can be increased. While maintaining the advantage that the manufacturing yield can be improved due to the relaxation, the sub word driver is reduced to suppress the increase of the chip area, the negative voltage of the main word line is used, the load driving capability of the sub word line is improved, the predecoder line It is possible to realize a high speed by reducing the load.
[Brief description of the drawings]
FIGS. 1A and 1B are a layout view and a partially enlarged view showing a semiconductor memory device according to an embodiment of the present invention.
FIGS. 2A and 2B are a circuit diagram and an operation waveform diagram showing a sub-word driver in an embodiment of the present invention.
FIGS. 3A and 3B are a circuit diagram and an operation waveform diagram showing a main word driver, a main row decoder and an FXB driver related to the main word driver in an embodiment of the present invention, respectively.
FIGS. 4A and 4B are a layout diagram and a cross-sectional view showing a sub-word driver in an embodiment of the present invention.
FIG. 5 is a circuit diagram showing a negative voltage VBB generation circuit according to an embodiment of the present invention.
6A and 6B are a layout diagram and a partially enlarged view showing a hierarchical word line configuration in a semiconductor memory device as a premise of the present invention.
7A and 7B are a circuit diagram and an operation waveform diagram showing a sub word driver in a semiconductor memory device as a premise of the present invention.
[Explanation of symbols]
10 memory chips
11 Main row decoder area
12 Main word driver area
13 Column decoder area
14 Peripheral circuit / bonding pad area
15 Memory cell subarray
16 sense amplifier area
17 Subword driver area
18 Intersection area
MWB main word line (inverted)
FXB predecoder line (inverted)
FX predecoder line
SW Sub word line

Claims (4)

A semiconductor memory device having a hierarchical word line configuration comprising a main word line and a sub word line,
The sub word driver is composed of one PMOS transistor and one NMOS transistor, the low level of the main word line is a negative voltage, and the output level of the sub word line is 0 V when not selected, and is high level when selected.
The process of changing the main word line from the high level to the low level due to the negative voltage is once changed to 0 V and then changed to the negative voltage through two steps.
The low level due to the negative voltage of the main word line is the substrate voltage,
The gates of the PMOS transistor and the NMOS transistor are commonly connected to the main word line, the drains of the PMOS transistor and the NMOS transistor are commonly connected to the sub word line, and the source of the PMOS transistor is a predecoder line. And the source of the NMOS transistor is connected to 0V,
The main word line is set to a negative first voltage and a positive second voltage, the predecoder line is set to a third voltage of 0V and the second voltage, and the output level of the sub word line is set to the third voltage when not selected. A semiconductor memory device, wherein the voltage is the second voltage when selected. A semiconductor memory device having a hierarchical word line configuration comprising a main word line and a sub word line,
The sub word driver is composed of one PMOS transistor and one NMOS transistor, the low level of the main word line is a negative voltage, and the output level of the sub word line is 0 V when not selected, and is high level when selected.
The process of changing the main word line from the high level to the low level due to the negative voltage is once changed to 0 V and then changed to the negative voltage through two steps.
The gates of the PMOS transistor and the NMOS transistor are commonly connected to the main word line, the drains of the PMOS transistor and the NMOS transistor are commonly connected to the sub word line, and the source of the PMOS transistor is a predecoder line. And the source of the NMOS transistor is connected to 0V,
The main word line is set to a negative first voltage and a positive second voltage, the predecoder line is set to a third voltage of 0V and the second voltage, and the output level of the sub word line is set to the third voltage when not selected. A semiconductor memory device, wherein the voltage is the second voltage when selected. The semiconductor memory device according to claim 1 , wherein
A semiconductor memory device, wherein the predecoder line is directly arranged on a memory cell subarray, and the subword driver is directly driven from an FX driver near a main word driver. A semiconductor memory device according to claim 1, wherein,
The semiconductor memory device is a large capacity DRAM.

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