JP3754197B2 - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit device Download PDFInfo
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- JP3754197B2 JP3754197B2 JP35391997A JP35391997A JP3754197B2 JP 3754197 B2 JP3754197 B2 JP 3754197B2 JP 35391997 A JP35391997 A JP 35391997A JP 35391997 A JP35391997 A JP 35391997A JP 3754197 B2 JP3754197 B2 JP 3754197B2
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- integrated circuit
- hybrid integrated
- circuit board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の属する技術分野】
本発明は混成集積回路装置に関するものである。
【従来の技術】
一般に、混成集積回路装置として採用される封止方法は、図5のように半導体素子等の回路素子1,2が実装された混成集積回路基板3の上に蓋をかぶせるような形状の手段、一般にはケース材4と呼ばれているものを採用して封止しているものがある。この構造は、箱状で中空構造であり、必要により中に樹脂が注入されている。
ここで1は、印刷抵抗、2は半導体チップである。またケース材4の一部、第1側面5の隣にケース材4の屋根になる部分には中空部の隣に開口部5が設けられ、そこに設けられた配線と外部リード6が半田を介して固着されている。ここで外部リード6は、基板と水平に延在されている。また外部リード6の固着部分は、一般にリード強度を増強させるために樹脂が封止されている。
また外部リード6を混成集積回路基板3から垂直に延在させたい場合、ケース材4と一体となり、上部に外部リード6の導出口7を有したる外部リード6の封止枠8は、第1側面5とは別に同様に基板端部に第2側面9を有する。図面では省略したが、もちろん混成集積回路基板の4側辺には、第1側面を含めて4枚の側面が当接し、これと屋根の部分に相当する上板10によりケース材が構成されている。
【発明が解決しようとする課題】
しかしながら、ケース材を使った封止構造は、前述したように混成集積回路基板3の側面11に当接させるため、ある厚みを有した当接面12を設けるため、紙面に対して左右、表裏に対応するケース材のサイズが大きくなるとともに、上板を有するため、混成集積回路装置の厚みも大きくなる。従って外形サイズが大きくなる問題があった。
一方、外部リード6を上方に延在させようとすると、ケース材4に図5や図6のような外部リードの導出口を形成するには、金型の加工、別のパーツとして用意するなど複雑になる問題もあった。しかもケース材に樹脂を注入しようとすると注入しずらい問題もあった。
【課題を解決するための手段】
本発明は上記の課題に鑑み成されたもので、第1に混成集積回路基板の上に載置され、素子を囲んだ枠部材と、枠部材と前記混成集積回路基板とで形成される空間に充填された樹脂とを有し、前記混成集積回路基板と当接する枠部材の当接面に、突出部を設け、この突出部に対応する前記混成集積回路基板に、前記突出部の係止部を形成することで解決するものである。
図1のように、基板の側面に対して内側に入る係止部により、枠部材の側面は、混成集積回路基板の側面と同一平面となり、また上面は省略されている。従って、枠部材の厚みの分、混成集積回路装置の厚み、左右のサイズが小さくなり、混成集積回路装置の小型化が実現できる。また混成集積回路基板と枠部材で樹脂注入用の箱を形成することになるが、係止部が形成されているため、その作業性も向上する。
第2に、混成集積回路基板と対面配置される枠部材の面に、外側全周に当接面を設け、この当接面の内側に、若干の隙間を有した離間面を設け、前記当接面から延在された突出部が、この突出部に対応する前記混成集積回路基板の係止部に係止され、前記離間面と混成集積回路基板との間に接着剤を設ける事で、第1の実施例の作用に加え、当接面への接着剤の塗布が部分的にしかできなかった場合で、接着が良好でなくても、枠部材全周にわたる離間面に樹脂が比較的厚く形成されるため、前記枠部材の接着性を補償でき、しかも枠部材に注入されるシリコン樹脂の漏洩を防止することができる。
第3に、前記混成集積回路基板として、金属基板を採用することで解決するものである。
特にモータ等の制御部は、小型で放熱性を必要とするので、混成集積回路基板として金属基板を採用することで、より小型・放熱性の優れた混成集積回路装置が実現できる。
第4に、前記混成集積回路基板の露出部に設けられたビス止め穴を介してビスが設けることで、混成集積回路基板がアース接地され、または外部機器と熱的に結合されることで解決するものである。
【発明の実施の形態】
以下で本発明の第1の実施形態に係る混成集積回路装置について図を参照しながら説明する。図1は、混成集積回路基板30と枠部材31の関係を示し、図2は、混成集積回路基板30に当接する枠部材31の当接面32と接着剤が設けられる離間面33を説明する斜視図である。図3は、混成集積回路装置34の平面図、図4は、図3のA−A線の断面図である。
先ず混成集積回路基板30は、一般には、プリント基板、セラミック基板または金属基板等の比較的強度のあるものが用いられる。つまり図4より明らかなように、混成集積回路装置として裏面が露出されるからである。またここで前記混成集積回路基板は、外部機器との熱的結合、或いはアース接地等が考慮され、金属基板が用いられ、特にその加工性よりアルミ基板が用いられる。
前記混成集積回路基板30は、IC回路が実現されるため、少なくともその表面は絶縁処理される。プリント基板等は元々絶縁基板であるため、絶縁処理は必要としないが、金属基板の場合は、必要とする。例えばAl基板の場合、表面が陽極酸化され酸化物が生成され、その上に更に絶縁性の優れた樹脂が全面に被着されている。但し耐圧を考慮しなければ、この金属酸化物は省略しても良い。また樹脂の材料としては、エポキシやイミド系等の樹脂である。またこの絶縁樹脂の代わりに樹脂シートが貼り合わされても良い。
そしてこの樹脂の上に例えばCuより成る導電パターン35が形成され、トランジスタやIC等の能動素子36、チップ抵抗、チップコンデンサ等の受動素子37が半田を介して実装され、所定の回路が実現されている。ここで一部半田を採用せず、銀ペースト等で電気的に接続されても良い。また前記半導体素子36がフェイスアップで実装される場合は、ボンデイングにより金属細線38を介して接続されている。更には、外部リード39が半田を介して接続されており封止樹脂40から外部に導出されている。
図3では、外部リード39の他に外部リード41も設けられているが図4では省略してある。特に外部リードは、枠部材31の中であれば、任意の位置に配置できる。またこれら外部リードを介して混成集積回路装置34の上方に例えばIC回路基板42が配置される。またIC回路基板42の間隔は、スペーサ43を使用し、例えばスペーサ43の中にネジ44が挿入されて固定される。
特に外部リードの形状をS字のような歪み吸収体を形成することによりIC基板と混成集積回路装置との間に発生する応力を吸収することができる。
本発明の特徴は、枠部材31である。特に屋根の部分に相当する部分がないため、その分混成集積回路装置の厚みを薄くすることができる。また図5、6のような従来構造では、枠体が混成集積回路基板の側辺に当接しているが、図4を見れば判るとおり、枠部材31の側辺と混成集積回路基板30の側辺がほぼ一致しているので、その分横のサイズも小さくできる。
また混成集積回路基板30と枠部材31の位置合わせのために、係止部(ツメ)45と係合部46を設けている。つまり混成集積回路基板30の上に枠部材31が設置され、この二つの構成により成る箱状の空間に封止樹脂40が注入されるが、係止部45が枠部材31のズレに対するストッパーとして作用し、作業性が向上する。
また第2に、混成集積回路基板30と対面配置される枠部材31の面に於いて、外側全周に当接面32が設けられ、この間に接着剤が塗られる。しかし部分的に接着剤が塗布されず、漏洩が考えられる。しかし枠部材全周にわたる離間面に樹脂が比較的厚く形成されるため、前記枠部材の接着性を補償でき、前記枠部材に注入されるシリコン樹脂の漏洩を防止することができる。
更には、混成集積回路基板30として、金属基板を採用するため、より小型・より放熱性の優れた混成集積回路装置が実現できる。しかも図3のように混成集積回路基板31の露出部47に設けられたビス止め穴48,49を介してビスが設けられ、混成集積回路基板をアース接地する事も可能であるし、または外部機器と熱的に結合する事も可能となる。
【発明の効果】
以上説明したように混成集積回路基板の上に載置され、素子を囲んだ枠部材と、枠部材と前記混成集積回路基板とで形成される空間に充填された樹脂とを有し、前記混成集積回路基板と当接する枠部材の当接面に、突出部を設け、この突出部に対応する前記混成集積回路基板に、前記突出部の係止部を形成することで混成集積回路装置の小型化が実現できる。また係止部が形成されているため、その作業性も向上する。
第2に、当接面の内側に、若干の隙間を有した離間面を設け、この離間面と混成集積回路基板との間に接着剤を設ける事で、枠部材全周にわたる離間面に樹脂が比較的厚く形成されるため、前記枠部材の接着性を補償でき、枠部材に注入されるシリコン樹脂の漏洩を防止することができる。
第3に、金属基板を採用することで小型で放熱性の優れた混成集積回路装置が実現できる。
第4に、前記混成集積回路基板の露出部に設けることで、混成集積回路基板のアース接地、または外部機器と熱的な結合が可能となる。
従って、モーター等の実装に要求される、小型・大電流・放熱性に優れた混成集積回路装置がを可能となる。
【図面の簡単な説明】
【図1】 本発明の混成集積回路装置に採用する枠部材と混成集積回路基板を説明する図である。
【図2】 図1の枠部材の係止部、当接面および離間面を説明する図である。
【図3】 本発明の混成集積回路装置の平面図である。
【図4】 図3のA-A線に対応する断面図である。
【図5】 従来の混成集積回路装置の断面図である。
【図6】 従来の混成集積回路装置の断面図である。
【符号の説明】
30 混成集積回路基板
31 枠部材
45 係止部
46 係合部BACKGROUND OF THE INVENTION
The present invention relates to a hybrid integrated circuit device.
[Prior art]
Generally, a sealing method employed as a hybrid integrated circuit device is a means having a shape that covers a hybrid
Here, 1 is a printing resistor, and 2 is a semiconductor chip. In addition, an
When it is desired to extend the
[Problems to be solved by the invention]
However, since the sealing structure using the case material is brought into contact with the
On the other hand, in order to extend the
[Means for Solving the Problems]
The present invention has been made in view of the above problems. First, a frame member is placed on the hybrid integrated circuit board and surrounds the element, and a space formed by the frame member and the hybrid integrated circuit board. A protrusion is provided on a contact surface of a frame member that contacts the hybrid integrated circuit board, and the protrusion is locked to the hybrid integrated circuit board corresponding to the protrusion. This is solved by forming the part.
As shown in FIG. 1, the side surface of the frame member is flush with the side surface of the hybrid integrated circuit board, and the upper surface is omitted because of the engaging portion that enters inside the side surface of the substrate. Accordingly, the thickness of the hybrid integrated circuit device and the left and right sizes are reduced by the thickness of the frame member, and the hybrid integrated circuit device can be downsized. Further, a resin injection box is formed by the hybrid integrated circuit board and the frame member, but the workability is improved because the locking portion is formed.
Second, a contact surface is provided on the entire outer periphery of the surface of the frame member that faces the hybrid integrated circuit board, and a separation surface having a slight gap is provided on the inner side of the contact surface. A protrusion extending from the contact surface is locked to the locking portion of the hybrid integrated circuit board corresponding to the protrusion, and an adhesive is provided between the separation surface and the hybrid integrated circuit board. In addition to the operation of the first embodiment, when the adhesive can only be partially applied to the contact surface, the resin is relatively free from the separation surface over the entire circumference of the frame member even if the adhesion is not good. Since it is formed thick, the adhesiveness of the frame member can be compensated, and leakage of silicon resin injected into the frame member can be prevented.
The third problem is solved by employing a metal substrate as the hybrid integrated circuit substrate.
In particular, since a control unit such as a motor is small and requires heat dissipation, a hybrid integrated circuit device that is more compact and has excellent heat dissipation can be realized by using a metal substrate as the hybrid integrated circuit substrate.
Fourth, the screw is provided through the screw fixing hole provided in the exposed portion of the hybrid integrated circuit board, so that the hybrid integrated circuit board is grounded or thermally coupled to an external device. To do.
DETAILED DESCRIPTION OF THE INVENTION
A hybrid integrated circuit device according to a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the relationship between the hybrid integrated
First, the hybrid integrated
Since the hybrid integrated
A
In FIG. 3, an
In particular, the stress generated between the IC substrate and the hybrid integrated circuit device can be absorbed by forming a strain absorber such as an S-shaped external lead.
A feature of the present invention is the
Further, a locking part (claw) 45 and an
Second, a
Furthermore, since a metal substrate is employed as the hybrid
【The invention's effect】
As described above, the frame member is placed on the hybrid integrated circuit board and surrounds the element, and the resin filled in the space formed by the frame member and the hybrid integrated circuit board is included, and the hybrid A projecting portion is provided on the abutting surface of the frame member that abuts on the integrated circuit substrate, and a locking portion of the projecting portion is formed on the hybrid integrated circuit substrate corresponding to the projecting portion, thereby reducing the size of the hybrid integrated circuit device. Can be realized. Moreover, since the latching | locking part is formed, the workability | operativity also improves.
Second, a separation surface having a slight gap is provided inside the contact surface, and an adhesive is provided between the separation surface and the hybrid integrated circuit board, so that the separation surface over the entire circumference of the frame member is resin. Therefore, the adhesiveness of the frame member can be compensated, and the leakage of the silicon resin injected into the frame member can be prevented.
Third, by adopting a metal substrate, a hybrid integrated circuit device having a small size and excellent heat dissipation can be realized.
Fourth, by providing at the exposed portion of the hybrid integrated circuit board, the hybrid integrated circuit board can be grounded or thermally coupled to an external device.
Accordingly, it is possible to provide a hybrid integrated circuit device that is required for mounting a motor or the like and is excellent in small size, large current, and heat dissipation.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a frame member and a hybrid integrated circuit board that are employed in a hybrid integrated circuit device of the present invention.
FIG. 2 is a diagram illustrating a locking portion, a contact surface, and a separation surface of the frame member of FIG.
FIG. 3 is a plan view of the hybrid integrated circuit device of the present invention.
4 is a cross-sectional view corresponding to the line AA in FIG. 3;
FIG. 5 is a cross-sectional view of a conventional hybrid integrated circuit device.
FIG. 6 is a cross-sectional view of a conventional hybrid integrated circuit device.
[Explanation of symbols]
30 Hybrid integrated
Claims (3)
前記素子を囲むように前記混成集積回路基板上に載置された枠部材と、
前記枠部材と前記混成集積回路基板とで形成される空間に充填された絶縁樹脂とを具備し、
前記枠部材には前記混成集積回路基板と当接する当接面が外側全周に設けられ、前記枠部材の前記当接面の内側全周には前記混成集積回路基板と離間する離間面が設けられ、
前記離間面と前記混成集積回路基板との間には接着剤が充填され、
前記枠部材を凹ませることで前記混成集積回路基板が露出され、露出する部分の前記混成集積回路基板の表面にビス穴を設け、このビス穴に設けられたビスを介して前記混成集積回路基板が接地されることを特徴とする混成集積回路装置。A conductive pattern is provided on at least a surface of which is insulated, and a hybrid integrated circuit board on which an element electrically connected to the conductive pattern is mounted, and is placed on the hybrid integrated circuit board so as to surround the element A frame member,
Comprising an insulating resin filled in a space formed by the frame member and the hybrid integrated circuit board;
The frame member is provided with a contact surface that contacts the hybrid integrated circuit board on the entire outer periphery, and a separation surface that is separated from the hybrid integrated circuit board is provided on the entire inner periphery of the contact surface of the frame member. And
An adhesive is filled between the spacing surface and the hybrid integrated circuit board,
The hybrid integrated circuit board is exposed by recessing the frame member, and a screw hole is provided on the surface of the exposed portion of the hybrid integrated circuit board, and the hybrid integrated circuit board is inserted through the screw provided in the screw hole. A hybrid integrated circuit device characterized in that is grounded.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35391997A JP3754197B2 (en) | 1997-12-22 | 1997-12-22 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35391997A JP3754197B2 (en) | 1997-12-22 | 1997-12-22 | Hybrid integrated circuit device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005261268A Division JP2005354118A (en) | 2005-09-08 | 2005-09-08 | Hybrid ic device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11186463A JPH11186463A (en) | 1999-07-09 |
JP3754197B2 true JP3754197B2 (en) | 2006-03-08 |
Family
ID=18434111
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP35391997A Expired - Lifetime JP3754197B2 (en) | 1997-12-22 | 1997-12-22 | Hybrid integrated circuit device |
Country Status (1)
Country | Link |
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JP (1) | JP3754197B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5285347B2 (en) * | 2008-07-30 | 2013-09-11 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Circuit equipment |
CN109716516B (en) * | 2016-09-20 | 2023-05-23 | 三菱电机株式会社 | Semiconductor device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61194754A (en) * | 1985-02-22 | 1986-08-29 | Toshiba Corp | Semiconductor device |
JP2593471B2 (en) * | 1987-03-11 | 1997-03-26 | 株式会社東芝 | Semiconductor device |
JPS6417455A (en) * | 1987-07-10 | 1989-01-20 | Mitsubishi Electric Corp | Semiconductor device |
JPH01319971A (en) * | 1988-06-22 | 1989-12-26 | Hitachi Ltd | Semiconductor device |
JPH02142166A (en) * | 1988-11-22 | 1990-05-31 | Mitsubishi Electric Corp | Semiconductor device |
JPH0677253U (en) * | 1993-03-30 | 1994-10-28 | 新電元工業株式会社 | Adhesive structure of metal substrate and case and electronic circuit device using the same |
-
1997
- 1997-12-22 JP JP35391997A patent/JP3754197B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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JPH11186463A (en) | 1999-07-09 |
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