JP3752029B2 - Line receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a line receiver that detects so-called crossing of a balanced signal and outputs the detected signal when transmitting a so-called balanced signal in a data transmission line, and in particular, an output for an offset generated between balanced signals. It relates to a product whose characteristics have been improved.
[0002]
[Prior art]
Conventionally, this type of line receiver is configured based on a differential amplifier circuit as shown in FIG. 3, for example, because it has a high gain and there is no leakage to the output signal due to the in-phase signal. Was used more often.
Here, with reference to FIG. 3, this circuit will be described in brief. This differential amplifier circuit is composed mainly of npn-type transistors 40 and 41, and includes two transistors 40 and 41. The emitters are connected to each other and connected to the current source 42, while the collectors are connected to the power supply voltage side via collector resistors 43 and 44, respectively.
In such a configuration, a so-called balanced signal having a phase difference of 180 degrees is applied to the bases of the npn transistors 40 and 41, and the differential voltage of the balanced signal becomes the amplification level of the differential amplifier circuit. It is amplified and output accordingly.
[0003]
[Problems to be solved by the invention]
By the way, in the differential amplifier circuit having such a configuration, there is a so-called linear operation region of ± VT with respect to a voltage at which the input signal is in a balanced state. This occurs due to the physical structure of the transistor. Usually, the VT is approximately 26 mV at room temperature.
Therefore, in the differential amplifier circuit described above, the difference voltage between the points where the balanced signals applied to the bases of the npn transistors 40 and 41 cross, that is, between so-called cross points (between adjacent cross points) is approximately 26 mV. If it became above, if it was detected that the balanced signal crossed so-called, the differential amplification output as a detection signal would be obtained.
In a line receiver using a differential amplifier circuit having such a configuration and function, for example, the so-called common voltage of the transmission path fluctuates due to the influence of the line length or the like, and an offset occurs between balanced signals on the receiving side. In this case, there is a problem that the reception signal output from the line receiver tends to become unstable.
[0004]
The present invention has been made in view of the above circumstances, and provides a line receiver capable of obtaining a relatively stable output signal unlike the conventional case even when an offset occurs between balanced signals.
Another object of the present invention is a line having a circuit configuration capable of setting a voltage difference between cross points of balanced signals as a condition for outputting an output signal to a desired value in a line receiver using a differential amplifier circuit. The object is to provide a receiver.
[0005]
[Means for Solving the Problems]
According to a first aspect of the present invention, a line receiver includes a first differential amplifier circuit that differentially amplifies a balanced signal and two transistors as a center, and a base of one transistor includes the first difference amplifier. the output voltage of the dynamic amplifier circuit, the base of the other transistor, the reference voltage is applied, and outputs an output voltage corresponding to the difference between the output voltage and the reference voltage of the first differential amplifier circuit a second differential amplifier circuit, wherein a reference voltage adjusting circuit for generating a hysteresis to the reference voltage of the second differential amplifier circuit, Ri name comprises a, the base of the other transistor, the emitter follower The emitter follower transistor is connected to the emitter follower transistor, where the power supply voltage is applied to the collector and the emitter is grounded via the constant current source. Is connected to the connection point of the resistor and the constant current source connected in series between the power supply voltage and the ground, and the output terminal of the reference voltage adjusting circuit is connected to the base. is there.
[0006]
In such a configuration, the second differential amplifier circuit performs differential amplification according to the difference between the reference voltage and the output voltage of the first differential amplifier circuit. The reference voltage is adjusted by the reference voltage adjustment circuit. Therefore, even in the first differential amplifier circuit, if the voltage gain of the first differential amplifier circuit is G with respect to the differential amplification of the balanced signal, 1 / G A magnitude hysteresis will occur. Therefore, the voltage difference between the cross-points of the balanced signal can be determined by appropriately selecting the hysteresis magnitude of the reference voltage in the second differential amplifier circuit by the reference voltage adjustment circuit and the voltage gain G of the first differential amplifier circuit. Therefore, a line receiver that can be set so as to obtain an output as a cross-point detection signal from the second differential amplifier circuit with a desired size or more is provided.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 and 2.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, the circuit configuration of the line receiver in the embodiment of the present invention will be described with reference to FIG.
The line receiver is roughly divided into a first differential amplifier circuit 1, a second differential amplifier circuit 2, and a reference voltage adjustment circuit 3. When the voltage difference between the cross points between the balanced signals applied to one differential amplifier circuit 1 exceeds a predetermined value, the differential amplified output of the balanced signal is output from the second differential amplifier circuit 2. It is what has become.
[0008]
The first differential amplifier circuit 1 is composed mainly of first and second npn-type transistors (indicated as “Q1” and “Q2” in FIG. 1 respectively) 5 and 6. The emitters of the second npn transistors 5 and 6 are connected to each other and grounded via the first constant current source 16, while the collectors of the first and second npn transistors 5 and 6 are connected to each other. The power supply voltage is applied through the first and second collector resistors 23 and 24, respectively. Furthermore, level adjusting resistors 25 and 26 are connected to the bases of the first and second npn transistors 5 and 6 in order to adjust the DC level of the input signal. A predetermined voltage by the constant voltage source 27 is applied through the via.
A balanced signal having a phase difference of 180 degrees and the same AC amplitude is applied to the base of the first npn-type transistor 5 and the base of the second npn-type transistor 6. When the voltage difference between the cross points exceeds a predetermined voltage (details will be described later), the potential difference between the bases of the first and second npn transistors 5 and 6 is multiplied by G (= g _m × R 1) and output. It has become so. Here, G is a voltage gain, g _m is a conductance of the first differential amplifier circuit 1, and R 1 is a resistance value of the first collector resistor 23.
[0009]
The output signal of the first differential amplifier circuit 1 is input to a second differential amplifier circuit 2 to be described later via an emitter follower by a fourth npn transistor (denoted as “Q4” in FIG. 1) 8. It has become so. That is, the base of the fourth npn-type transistor 8 is connected to the collector of the second npn-type transistor 6, while the power supply voltage V ⁺ is applied to the collector of the fourth npn-type transistor 8. ing. The emitter of the fourth npn-type transistor 8 is grounded via the fifth constant current source 20, and a fifth npn-type transistor (see FIG. 5) constituting the second differential amplifier circuit 2 described below. 1 is denoted as “Q5”) and a base of a seventh npn-type transistor (denoted as “Q7” in FIG. 1) 11 constituting a reference voltage adjusting circuit 3 described later. It operates as a circuit.
[0010]
The second differential amplifier circuit 2 is composed mainly of fifth and sixth npn transistors (referred to as “Q5” and “Q6” in FIG. 1) 9 and 10, respectively. And the emitters of the sixth npn transistors 9 and 10 are connected to each other and grounded via the second constant current source 17, while the collectors of the fifth and sixth npn transistors 9 and 10 are connected to the respective collectors. The power supply voltage V ⁺ is applied through the third and fourth collector resistors 28 and 29, respectively.
Further, an output voltage of a reference voltage adjusting circuit 3 to be described later is applied to the base of the sixth npn transistor 10 via an emitter follower by a ninth npn transistor (denoted as “Q9” in FIG. 1) 13. It has come to be.
That is, the base of the ninth npn transistor 13 is applied with the power supply voltage V ⁺ through the resistor 30 and is grounded through the seventh constant current source 22. Further, it is connected to the collector of a seventh npn transistor 11 constituting a reference voltage adjusting circuit 3 described later. On the other hand, the power supply voltage V ⁺ is applied to the collector of the ninth npn transistor 13. The emitter of the ninth npn-type transistor 13 is grounded via the sixth constant current source 21, and the base of the sixth npn-type transistor 10 and the eighth reference voltage adjusting circuit 3 are configured. Are connected to the base of an npn-type transistor (denoted as “Q8” in FIG. 1) 12 and operate as a so-called emitter follower circuit.
[0011]
The second differential amplifier circuit 2 is configured such that the signal applied to the base of the fifth npn-type transistor 9 depends on the magnitude of the base voltage of the sixth npn-type transistor 10 according to the magnitude of the second differential amplifier circuit 2. Amplified by the amplification factor of the differential amplifier circuit 2 and output as an output signal of the line receiver between the collectors of the fifth and sixth npn transistors 9 and 10 (details will be described later).
[0012]
The reference voltage adjusting circuit 3 includes a differential amplifier circuit mainly composed of seventh and eighth npn transistors (represented as “Q7” and “Q8” in FIG. 1) 11 and 12, respectively. Thus, the emitters of the seventh and eighth npn transistors 11 and 12 are connected to each other and grounded via the third constant current source 18, while the seventh and eighth npn transistors 11 and 12 On the collector side, a so-called current mirror circuit is connected as a load.
That is, the collector of the seventh npn transistor 11 includes the collector of the eleventh npn transistor (indicated as “Q11” in FIG. 1) 15, and the collector of the eighth npn transistor 12 includes the base and collector. Are connected to the collector of the tenth npn-type transistor 14, and the emitter of the eleventh npn-type transistor 15 is connected to the tenth npn via the first emitter resistor 31. A power supply voltage V ⁺ is applied to the emitter of the type transistor 14 via the second emitter resistor 32, and a so-called current mirror circuit is provided by the tenth and eleventh npn transistors 14 and 15. Is configured.
[0013]
The base of the seventh npn-type transistor 11 is connected to the emitter of the fourth npn-type transistor 8 together with the base of the fifth npn-type transistor 9 as described above. An output signal of the first differential amplifier circuit 1 is applied via an emitter follower by the npn transistor 8.
Further, as described above, the base of the eighth npn transistor 12 is connected to the emitter of the ninth npn transistor 13 together with the base of the sixth npn transistor 10, and the ninth npn transistor 13 As will be described later, the voltage on the base side of the ninth npn transistor 13 is applied via an emitter follower by the transistor 13.
The reference voltage adjusting circuit 3 has a function of changing the reference voltage applied to the base of the sixth npn transistor 10 constituting the second differential amplifier circuit 2 with a predetermined hysteresis width. (Details will be described later).
[0014]
Next, the operation in the above configuration will be described.
First, the general operation of this line receiver will be described. For example, the base of the first and second npn transistors 5 and 6 constituting the first differential amplifier circuit 1 is shown in FIG. As described above, a balanced signal in which each phase is in an opposite phase state is applied. As shown in the figure, this balanced signal has such a relationship that a crossing point, that is, a so-called cross point is generated, and the line receiver has a balanced signal between two adjacent cross points. Is output from the second differential amplifier circuit 2 having a significance as a detection signal that the balanced signal is crossed. .
[0015]
Next, when the voltage difference between the cross points of the balanced signals applied to the first differential amplifier circuit 1 exceeds any value, a signal is output from the second differential amplifier circuit 2. Let's explain what it is.
The output voltage of the first differential amplifier circuit 1 is applied to the base of the fifth npn-type transistor 9 constituting the second differential amplifier circuit 2 via the emitter follower by the fourth npn-type transistor 8; The differential amplification is performed in accordance with the comparison with the base voltage of the sixth npn transistor 10.
By the way, the base of the sixth npn transistor 10 is connected to the emitter of the ninth npn transistor 13 operating as an emitter follower together with the base of the eighth npn transistor 12. The base voltages of the eighth npn transistors 10 and 12 are determined according to the magnitude of the current flowing through the resistor 30.
[0016]
That is, when the base voltage of the seventh npn-type transistor 11 constituting the reference voltage adjusting circuit 3 is larger than the base voltage of the eighth npn-type transistor 12, the seventh npn-type transistor 11 is in a so-called conduction state. The eighth npn transistor 12 is in a so-called non-conductive state. Therefore, the collector current of any of the tenth and eleventh npn transistors 14 and 15 constituting the current mirror circuit does not flow out. Therefore, the current to flow into the collector of the seventh npn transistor 11, that is, the third The current substantially equal to the output current I ₃ of the constant current source 18 is supplied via the resistor 30.
After all, in this case, the current I _R1 flowing through the resistor 30 is under the condition that the output current I ₇ of the _seventh constant current source 22 is set larger than the output current I _{3 of} the third constant current source 18. _Therefore , I _R1 = I ₇ + I ₃ .
[0017]
On the other hand, when the base voltage of the seventh npn transistor 11 is lower than the base voltage of the eighth npn transistor 12, the seventh npn transistor 11 is turned off, The npn transistor 12 becomes conductive. A current substantially equal to the output current I ₃ of the third constant current source 18 is drawn to the collector of the eighth npn-type transistor 12 and flows from the tenth npn-type transistor 14, and thus the eleventh npn-type transistor 14. Although substantially the same current I3 flows out from the collector of the transistor 15, this current flows into the seventh constant current source 22 side because the seventh npn transistor 11 is non-conductive. .
Therefore, in this case, current I _R2 flowing through the resistor 30, the relation between the output current I ₃ of the seventh and the output current I ₇ of the constant current source 22 a third constant current source 18 is in a similar relationship to that described above Under these conditions, I _R2 = I ₇ −I ₃ .
Therefore, for the voltage drop in the resistor 30, if the value of the resistor 30 is Rb, VTH = I _R1 × Rb−I _R2 × Rb = {I ₇ + I ₃ − (I ₇ −I ₃ )} Rb = 2I ₃ Hysteresis represented by Rb occurs.
[0018]
Since the voltage drop in the resistor 30 appears at the base of the sixth npn-type transistor 10 constituting the second differential amplifier circuit 2 via the emitter follower by the ninth npn-type transistor 13, The differential amplifier circuit 2 performs differential amplification on the input signal applied to the base of the fifth npn type transistor 9 with the above hysteresis voltage V _TH . Further, the input signal applied to the base of the fifth npn-type transistor 9 constituting the second differential amplifier circuit 2 is applied via the first differential amplifier circuit 1. , the previous hysteresis shea scan becomes a to appear in the first input stage of the differential amplifier circuit 1, the magnitude of which, the previous hysteresis voltage V _TH = 2I ₃ Rb first differential amplifier circuit 1 The size is divided by the voltage gain.
[0019]
Therefore, the voltage gain of the first differential amplifier circuit 1 is set to an appropriate magnitude by selecting the bias current (the output current of the first constant current source 16) and the load resistor (the first collector resistor 23). In addition, the magnitude of the hysteresis voltage VTH in the second differential amplifier circuit 2 is set by appropriately selecting the output current of the resistor 30, the third and seventh constant current sources 18, 22, and The magnitude of the hysteresis voltage at the input stage of one differential amplifier circuit 1 can be set to a desired magnitude, and the magnitude of the hysteresis voltage has conventionally been In other words, it can be easily realized to be less than the limit value of 26 mV.
[0020]
Next, an example of the simulation result will be described with reference to FIG.
FIG. 2 shows a voltage gain G of the first differential amplifier circuit 1 of 20 times, a resistance value Rb of the resistor 30 of 10 kΩ, and an output current value I _{3 of} the third constant current source 18 in the circuit configuration example described above. The relationship between the balanced signal as the input signal and the output signal obtained from the second differential amplifier circuit 2 when 10 μA, the output current value I _{7 of} the seventh constant current source 22 is set to 50 μA, and VTH = 200 mV FIG.
FIG. 2A shows a balanced signal applied between the bases of the first and second npn transistors 5 and 6 constituting the first differential amplifier circuit 1, and between adjacent cross points. The voltage difference between the two signals is 9.8 mV.
FIG. 4B shows that even if the input voltage difference between adjacent cross points is 9.8 mV, which is lower than the conventional (26 mV), an output signal is output between the cross points. Yes.
[0021]
In the circuit configuration in the above-described embodiment, the npn type is used as the transistor. However, it is a matter of course that the same configuration can be achieved even if a pnp type transistor is used, and a transistor other than these bipolar transistors can be used. By making the bias and the like suitable for the transistor, a line receiver having the above-described operation can be realized with basically the same circuit configuration.
[0022]
【The invention's effect】
As described above, according to the present invention, in a line receiver using a differential amplifier circuit, a limit value for obtaining an output signal for detection of a crosspoint can be arbitrarily set. Since an arbitrary limit value smaller than the limit value can be set, it is possible to output a detection signal that is more stable and reliable than the conventional limit value, and to provide a more reliable line receiver. it can.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a circuit configuration example of a line receiver in an embodiment of the present invention.
2 is a characteristic diagram showing an example of a simulation result in the circuit shown in FIG. 1. FIG. 2 (a) shows a balanced signal as an input signal, and FIG. 2 (b) shows an output signal. It is shown.
FIG. 3 is a circuit diagram showing a circuit configuration example of a conventional line receiver.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... 1st differential amplifier circuit 2 ... 2nd differential amplifier circuit 3 ... Reference voltage adjustment circuit

Claims (2)

A first differential amplifier circuit for differentially amplifying the balanced signal;
The output voltage of the first differential amplifier circuit is applied to the base of one transistor, and the reference voltage is applied to the base of the other transistor, respectively . a second differential amplifier circuit for outputting an output voltage corresponding to the difference between the output voltage and the reference voltage of the differential amplifier circuit,
Ri Na comprises a, a reference voltage adjusting circuit for generating a hysteresis to said reference voltage in said second differential amplifier circuit,
The emitter of the emitter follower transistor is connected to the base of the other transistor. The emitter follower transistor has a power supply voltage applied to the collector, and the emitter is grounded via a constant current source. The connection point between the resistor and the constant current source connected in series between the power supply voltage and the ground is connected, and the output terminal of the reference voltage adjusting circuit is connected to the base. Line receiver characterized by. The reference voltage adjustment circuit includes a third differential amplifier circuit that is configured with two transistors as a center, and the base of one of the two transistors of the third differential amplifier circuit is included in the base of one of the two transistors. The output voltage of the first differential amplifier circuit is applied to the base of the other transistor, and the emitter voltage of the emitter follower transistor is applied to the two transistors of the third differential amplifier circuit. 2. The line receiver according to claim 1, wherein a current mirror circuit is connected as a load of the line receiver.

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