JP3748335B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device including an input circuit suitable for a semiconductor memory device having a high speed signal processing operation.
[0002]
In recent years, with further increase in the speed of semiconductor memory devices, an external clock signal with a reduced amplitude is input to the device, and the external clock signal is input as a complementary signal. Such a semiconductor memory device includes an input circuit that amplifies a complementary clock signal from the outside to an internal clock signal having an amplitude operable in the internal circuit. In this input circuit, it is desired to generate complementary clock signals that rise and fall at the same timing in order to improve the operation margin of the subsequent circuit.
[0003]
[Prior art]
FIG. 7 shows an example of the input unit 1 in a conventional semiconductor memory device. The input unit 1 includes three input circuits 2a to 2c, two latch circuits 3a and 3b, and an output circuit 4.
[0004]
The input circuit 2a receives an address signal A00 from the outside via the input pad 5a, and receives a reference voltage Vref from the outside via the input pad 5c. The input circuit 2a amplifies the external address signal A00 based on the reference voltage Vref, and outputs the amplified signal as the address signal a00z to the next latch circuit 3a.
[0005]
The latch circuit 3a receives the address signal a00z and the positive phase clock signal clkz. The latch circuit 3a latches the address signal a00z in response to the rising of the positive phase clock signal clkz, and outputs the latch signal as an internal address signal a00cz to the next stage circuit (not shown).
[0006]
A control signal RAS bar is input from the outside to the input circuit 2b via the input pad 5b, and a reference voltage Vref is input. The input circuit 2b amplifies the external control signal RAS bar based on the reference voltage Vref, and outputs the amplified signal as a control signal rasz to the next latch circuit 3b.
[0007]
The control signal rasz and the positive phase clock signal clkz are input to the latch circuit 3b. The latch circuit 3b latches the control signal rasz in response to the rising edge of the positive phase clock signal clkz, and outputs the latch signal as an internal control signal rascz to a next stage circuit (not shown).
[0008]
The positive phase clock signal clkz is generated by the input circuit 2c. That is, the input circuit 2c is supplied with the normal phase clock signal CLK from the outside via the input pad 5d and the external phase via the input pad 5e. The input circuit 2c amplifies the complementary clock signals CLK 1 and CLK bar from the outside, and outputs the amplified signals as complementary clock signals clkz and clkz bar to the latch circuits 3a and 3b and the output circuit 4 in the next stage.
[0009]
The input circuit 2c is a general differential amplifier circuit as shown in FIG. 8, and includes three NMOS transistors TN1 to TN3, two PMOS transistors TP1 and TP2, and two inverter circuits 6a and 6b. Consists of.
[0010]
The sources of the NMOS transistors TN1 and TN2 are connected to each other, and the sources are connected to the low potential side power source VSS via the NMOS transistor TN3. The high potential side power supply VCC is supplied to the gate of the NMOS transistor TN3. That is, the NMOS transistor TN3 operates as a constant current source.
[0011]
The drain of the NMOS transistor TN1 is connected to the high potential side power supply VCC through the PMOS transistor TP1. The drain of the NMOS transistor TN2 is connected to the high potential side power supply VCC through the PMOS transistor TP2. The PMOS transistors TP1 and TP2 constitute a current mirror circuit 7. That is, the gates of the PMOS transistors TP1 and TP2 are connected to each other, and the gates are connected to the drain of the PMOS transistor TP2.
[0012]
The normal phase clock signal CLK is input to the gate of the NMOS transistor TN1, and the negative phase clock signal CLK is input to the gate of the NMOS transistor TN2.
[0013]
A node N1 between the drain of the NMOS transistor TN1 and the drain of the PMOS transistor TP1 is a first output node, and the node N1 is connected to the input terminal of the inverter circuit 6a. The inverter circuit 6a outputs the amplified positive phase clock signal clkz from the output terminal.
[0014]
A node N2 between the drain of the NMOS transistor TN2 and the drain of the PMOS transistor TP2 is a second output node, and the node N2 is connected to the input terminal of the inverter circuit 6b. The inverter circuit 6b outputs the amplified anti-phase clock signal clkz bar from the output terminal.
[0015]
In such an input circuit 2c, when the external positive phase clock signal CLK rises and the external reverse phase clock signal CLK bar falls, the NMOS transistor TN1 is turned on and the NMOS transistor TN2 is turned off. Then, the potential of the node N1 decreases and the potential of the node N2 increases. Therefore, the inverter circuit 6a raises the normal phase clock signal clkz, and the inverter circuit 6b falls the reverse phase clock signal clkz bar.
[0016]
On the other hand, when the external positive phase clock signal CLK falls and the external reverse phase clock signal CLK bar rises, the NMOS transistor TN1 is turned off and the NMOS transistor TN2 is turned on. Then, the potential of the node N1 rises and the potential of the node N2 falls. Therefore, the inverter circuit 6a falls the normal phase clock signal clkz, and the inverter circuit 6b raises the negative phase clock signal clkz bar. Therefore, as shown in FIG. 10, the input circuit 2c generates the amplified in-phase complementary clock signals clkz and clkz bars based on the external complementary clock signals CLK and CLK bars, respectively.
[0017]
The output circuit 4 receives the complementary clock signals clkz and clkz and the data signals dataz and datax. The data signals dataz and datax are necessary for making the output pad 5f high impedance and setting the internal data signal DQ00 output from the output pad 5f to the H and L levels to trinize the internal data signal DQ00. 2 bit data.
[0018]
In FIG. 9, the detailed circuit configuration of the output circuit 4 is shown. The complementary clock signals clkz and clkz bar are input to the NOR circuit 4a. The output signal of the NOR circuit 4a is input to the transfer gates 4b and 4c as a gate control signal. On the other hand, the data signals dataz and datax are input to the latch circuits 4d and 4e via the transfer gates 4b and 4c, respectively. The output terminal of the latch circuit 4d is connected to the gate of the PMOS transistor TP3, and the output terminal of the latch circuit 4e is connected to the gate of the NMOS transistor TN4. The PMOS transistor TP3 and the NMOS transistor TN4 are connected in series between the power sources VCC and VSS, and the internal data signal DQ00 is output from the drain, that is, the node N3, through the output pad 5f.
[0019]
In such an output circuit 4, both transfer gates 4b and 4c are turned on in response to the rising of one of the clock signals clkz and clkz. Then, the data signals dataz and datax are latched by the latch circuits 4d and 4e, and inverted signals of the data signals dataz and datax are input to the gates of the MOS transistors TP3 and TN4.
[0020]
As shown in FIG. 10, when the data signals dataz and datax are at the L and H levels, both the MOS transistors TP3 and TN4 are in the off state, and the node N3, that is, the output pad 5f is in a high impedance state.
[0021]
Next, when the data signal dataz becomes H level and the clock signal clkz rises, the PMOS transistor TP3 is turned on and the H level internal data signal DQ00 is output.
[0022]
Next, when the data signals dataz and datax both become L level and the clock signal clkz bar rises, the PMOS transistor TP3 is turned off, the NMOS transistor is turned on, and the L level internal data signal DQ00 is output.
[0023]
Next, when the data signal datax becomes H level and the clock signal clkz rises, the NMOS transistor TN4 is turned off and the output pad 5f becomes high impedance. In this way, the output circuit 4 outputs the internal data signal DQ00 as shown in FIG. 10 in response to the rising of one of the clock signals clkz and clkz.
[0024]
[Problems to be solved by the invention]
However, in the input circuit 2c shown in FIG. 8, the NMOS transistor TN1 and the PMOS transistor TP1 are turned on and off in a complementary manner, whereas the NMOS transistor TN2 and the PMOS transistor TP2 are turned on and off in the same phase. That is, when the clock signal clkz rises, the NMOS transistor TN2 is turned on and the potential of the node N2 is lowered. However, when the potential of the node N2 is lowered, the PMOS transistor TP2 is turned on and the drain current is supplied to the node N2. Resulting in. On the other hand, when the clock signal clkz bar falls, the NMOS transistor TN2 is turned off and the potential of the node N2 rises. However, when the potential of the node N2 rises, the PMOS transistor TP2 is turned off, and the drain current to the node N2 increases. Stop supplying.
[0025]
Therefore, the amplitude of the potential at the node N2 becomes smaller than the amplitude of the potential at the node N1. As a result, a difference occurs in the operation speed of the inverter circuits 6a and 6b, and the edges of the clock signals clkz and clkz bar are relatively shifted. Then, in the output circuit 4 shown in FIG. 9, there is a possibility that the transfer timing of the transfer gates 4b and 4c is shifted and the internal data signal DQ00 of the wrong level is output.
[0026]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor integrated circuit device including a signal processing circuit that performs signal processing based on an internal complementary signal obtained by amplifying an external complementary signal. Another object of the present invention is to provide a semiconductor integrated circuit device that can prevent relative edge shifts of internal complementary signals during amplification and perform accurate signal processing.
[0027]
[Means for Solving the Problems]
According to the first aspect of the present invention, the input circuit includes a pair of transistors to which external complementary signals are respectively input, and a first positive phase signal is output from the output node based on the operation of each transistor. A differential amplifier circuit and a pair of transistors to which external complementary signals are respectively input, and based on the operation of each transistor, a second output of an internal negative phase signal whose phase is inverted from the internal positive phase signal from the output node The differential amplifier circuit. That is, the internal complementary signals are generated at the output nodes of the respective differential amplifier circuits. Accordingly, the relative edge shift of the internal complementary signals generated by the first and second differential amplifier circuits is prevented, and the signal processing circuit can perform accurate signal processing based on the internal complementary signals. it can.
[0028]
Further , a pseudo circuit is connected to at least one of the output terminals of the first and second differential amplifier circuits so that the loads of the circuits connected to the output terminal are equal. Therefore, this pseudo circuit makes the operating characteristics of the first and second differential amplifier circuits the same. As a result, the internal complementary signals generated by the first and second differential amplifier circuits are prevented from relatively shifting edges, and the signal processing circuit performs accurate signal processing based on the internal complementary signals. be able to.
[0029]
According to the second aspect of the present invention, the internal complementary signal generated by the input circuit is supplied only to the circuit including the signal processing circuit and operating with the complementary signal. As a result, the operating characteristics of the first and second differential amplifier circuits are the same. Accordingly, the internal complementary signals generated by the first and second differential amplifier circuits are prevented from being relatively shifted in edge, and the signal processing circuit can perform accurate signal processing based on the internal complementary signals. Can do.
[0030]
According to the third aspect of the present invention, the internal positive-phase signal is generated based on the external complementary signal with respect to the internal processing circuit. Alternatively, a third input circuit including a third differential amplifier circuit that supplies an internal reverse phase signal is provided. That is, an internal normal phase signal or an internal negative phase signal generated by the third input circuit is supplied to internal processing circuits other than the circuit operating with the complementary signal. That is, since the internal complementary signal generated by the input circuit is supplied only to the circuit including the signal processing circuit and operating with the complementary signal, the operating characteristics of the first and second differential amplifier circuits are the same. Accordingly, the internal complementary signals generated by the first and second differential amplifier circuits are prevented from being relatively shifted in edge, and the signal processing circuit can perform accurate signal processing based on the internal complementary signals. Can do.
[0031]
According to the invention described in claim 4 , the pseudo circuit is connected to at least one of the input pads to which the external complementary signal is input so that the load of the circuit connected to the input pad becomes equal. . Therefore, this pseudo circuit prevents the relative edge shift of the external complementary signal due to the load difference of the circuit connected to the input pad. As a result, the relative edge shift of the internal complementary signal generated by the first and second differential amplifier circuits based on the external complementary signal is reliably prevented, and the signal processing circuit is based on the internal complementary signal. And accurate signal processing can be performed.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. For convenience of explanation, the same reference numerals are given to the same components as those in the conventional example, and a part of the explanation is omitted.
[0033]
FIG. 1 shows an input unit 10a in the semiconductor memory device of this embodiment. The input unit 10a includes four input circuits 2a, 2b, 2d, and 2e, two latch circuits 3a and 3b, and an output circuit 4.
[0034]
The input circuit 2d receives a normal phase clock signal CLK from the outside via the input pad 5d, and receives a negative phase clock signal CLK from the outside via the input pad 5e. As shown in FIG. 2, the input circuit 2d includes two PMOS transistors TP1, TP2, three NMOS transistors TN3, and an inverter circuit 6a. A normal phase clock signal CLK is input to the gate of the NMOS transistor TN1, and a negative phase clock signal CLK is input to the gate of the NMOS transistor TN2. Then, the positive phase clock signal clkz amplified through the inverter circuit 6a is output from the node N1 which is the first output node.
[0035]
The input circuit 2e receives a normal phase clock signal CLK from the outside via the input pad 5d, and receives a reverse phase clock signal CLK bar from the outside via the input pad 5e. The input circuit 2e is configured similarly to the input circuit 2d shown in FIG. The negative phase clock signal CLK is input to the gate of the NMOS transistor TN1, and the normal phase clock signal CLK is input to the gate of the NMOS transistor TN2. Then, the amplified negative phase clock signal clkz bar is output from the node N1, which is the first output node, via the inverter circuit 6a.
[0036]
That is, in this embodiment, the input circuit 2d generates the positive phase clock signal clkz based on the positive phase clock signal CLK input from the outside, and the input circuit 2e is based on the negative phase clock signal CLK bar input from the outside. A negative phase clock signal clkz bar is generated. In addition, in each of the input circuits 2d and 2e, the node N1 is used as an output node. Therefore, the relative edge shift of the clock signals clkz and clkz bars output from the inverter circuit 6a of the input circuits 2d and 2e is prevented. As a result, in the output circuit 4 shown in FIG. 9 that operates with the clock signals clkz and clkz, it is possible to prevent the transfer gates 4b and 4c from being switched in conduction timing and non-conduction timing, and to generate an accurate internal data signal DQ00. Can be output.
[0037]
As described above, in the present embodiment, the following operational effects can be obtained.
(1) In the input circuit 2d, the normal phase clock signal CLK is input to the gate of the NMOS transistor TN1, and the negative phase clock signal CLK is input to the gate of the NMOS transistor TN2. On the other hand, in the input circuit 2e, the negative phase clock signal CLK is input to the gate of the NMOS transistor TN1, and the normal phase clock signal CLK is input to the gate of the NMOS transistor TN2. In this embodiment, complementary clock signals clkz and clkz bars amplified from the same node N1 via the inverter circuit 6a are output. Therefore, it is possible to prevent the shift of the relative edges of the clock signals clkz and clkz bars output from the input circuits 2d and 2e. As a result, in the output circuit 4 operating with the clock signals clkz and clkz bars, it is possible to prevent the transfer gates 4b and 4c from being switched between conduction and non-conduction, and output an accurate internal data signal DQ00. be able to.
[0038]
(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIG. For convenience of explanation, the same reference numerals are given to the same components as those of the first embodiment, and a part of the explanation is omitted.
[0039]
FIG. 3 shows the input unit 10b in the semiconductor memory device of this embodiment. The input unit 10b includes four input circuits 2a, 2b, 2d, 2e, two latch circuits 3a, 3b, an output circuit 4, and a dummy latch circuit 11 as a pseudo circuit.
[0040]
The dummy latch circuit 11 receives the reverse phase clock signal clkz bar from the input circuit 2e. The dummy latch circuit 11 is configured to be equivalent to a load obtained by adding the loads of the two latch circuits 3a and 3b, and is configured such that the loads viewed from the output terminals of the input circuits 2d and 2e are equal.
[0041]
Therefore, the operation characteristics of the input circuits 2d and 2e are the same, and the relative edge shift of each clock signal clkz and clkz bar is prevented. As a result, in the output circuit 4 shown in FIG. 9 that operates with the clock signals clkz and clkz, it is possible to prevent the transfer gates 4b and 4c from being switched in conduction timing and non-conduction timing, and to generate an accurate internal data signal DQ00. Can be output.
[0042]
(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIG. For convenience of explanation, the same reference numerals are given to the same components as those of the first embodiment, and a part of the explanation is omitted.
[0043]
FIG. 4 shows the input unit 10c in the semiconductor memory device of this embodiment. The input unit 10c includes five input circuits 2a, 2b, 2d, 2e, 2f, two latch circuits 3a, 3b, and an output circuit 4.
[0044]
The input circuit 2f is configured in the same manner as the input circuit 2d shown in FIGS. The input circuit 2f is supplied with the normal phase clock signal CLK from the outside via the input pad 5d, and is input with the reverse phase clock signal CLK bar from the outside via the input pad 5e. The input circuit 2f outputs the amplified positive phase clock signal clkz to the latch circuits 3a and 3b based on the external complementary clock signals CLK and CLK, respectively. That is, in this embodiment, the clock signals clkz and clkz bars generated by the input circuits 2d and 2e are output only to the output circuit 4 so that the loads viewed from the output terminals of the input circuits 2d and 2e are equal. It is configured.
[0045]
Therefore, the operation characteristics of the input circuits 2d and 2e are the same, and the relative edge shift of each clock signal clkz and clkz bar is prevented. As a result, in the output circuit 4 shown in FIG. 9 that operates with the clock signals clkz and clkz, it is possible to prevent the transfer gates 4b and 4c from being switched in conduction timing and non-conduction timing, and to generate an accurate internal data signal DQ00. Can be output.
[0046]
(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG. For convenience of explanation, the same reference numerals are given to the same components as those of the first embodiment, and a part of the explanation is omitted.
[0047]
FIG. 5 shows an input unit 10d in the semiconductor memory device of this embodiment. The input unit 10d includes five input circuits 2a, 2b, 2d, 2e, 2g, two latch circuits 3a, 3b, and an output circuit 4.
[0048]
The input circuit 2g is composed of a general differential amplifier circuit as shown in FIG. The input circuit 2g receives a normal phase clock signal CLK from the outside via the input pad 5d, and receives a reference voltage Vref from the outside via the input pad 5c. The input circuit 2g outputs the amplified positive phase clock signal clkz to the latch circuits 3a and 3b based on the positive phase clock signal CLK and the reference voltage Vref, respectively. That is, also in this embodiment, as in the third embodiment, the clock signals clkz and clkz bars generated by the input circuits 2d and 2e are output only to the output circuit 4, and the input circuits 2d and 2e are output. The loads viewed from the output terminals of the same are configured to be equal.
[0049]
Therefore, the operation characteristics of the input circuits 2d and 2e are the same, and the relative edge shift of each clock signal clkz and clkz bar is prevented. As a result, in the output circuit 4 shown in FIG. 9 that operates with the clock signals clkz and clkz, it is possible to prevent the transfer gates 4b and 4c from being switched in conduction timing and non-conduction timing, and to generate an accurate internal data signal DQ00. Can be output.
[0050]
(Fifth embodiment)
A fifth embodiment embodying the present invention will be described below with reference to FIG. For convenience of explanation, the same reference numerals are given to the same components as those in the fourth embodiment, and a part of the explanation is omitted.
[0051]
FIG. 6 shows an input unit 10e in the semiconductor memory device of this embodiment. The input unit 10e includes five input circuits 2a, 2b, 2d, 2e, and 2g, a dummy input circuit 12 as a pseudo circuit, two latch circuits 3a and 3b, and an output circuit 4.
[0052]
The dummy input circuit 12 receives a reverse phase clock signal CLK bar from the outside through the input pad 5e. The dummy input circuit 12 is configured to be equivalent to the load of the input circuit 2g, and is configured to have the same load as viewed from the input pads 5d and 5e. That is, in this embodiment, the load of an external clock signal generation circuit (not shown) that generates the clock signals CLK and CLK is equal.
[0053]
Therefore, the operating characteristics of the external clock signal generation circuit are the same, and the relative edge shift between the clock signals CLK 1 and CLK bar is prevented. This prevents the relative edge shift of the clock signals clkz and clkz bars generated by the input circuits 2d and 2e. As a result, in the output circuit 4 shown in FIG. 9 that operates with the clock signals clkz and clkz, it is possible to prevent the transfer gates 4b and 4c from being switched in conduction timing and non-conduction timing, and to generate an accurate internal data signal DQ00. Can be output.
[0054]
【The invention's effect】
As described above in detail, according to the present invention, in a semiconductor integrated circuit device including a signal processing circuit that performs signal processing based on an internal complementary signal obtained by amplifying an external complementary signal, Therefore, it is possible to provide a semiconductor integrated circuit device that can prevent an edge shift and perform accurate signal processing.
[Brief description of the drawings]
FIG. 1 is a block diagram of an input unit in a first embodiment.
FIG. 2 is a circuit diagram of an input circuit.
FIG. 3 is a block diagram of an input unit in the second embodiment.
FIG. 4 is a block diagram of an input unit in the third embodiment.
FIG. 5 is a block diagram of an input unit according to a fourth embodiment.
FIG. 6 is a block diagram of an input unit in the fifth embodiment.
FIG. 7 is a block diagram of an input unit in a conventional example.
FIG. 8 is a circuit diagram of an input circuit.
FIG. 9 is a circuit diagram of an output circuit.
FIG. 10 is an operation waveform diagram of the input unit.
[Explanation of symbols]
2d Input circuit 2e as a first differential amplifier circuit constituting an input circuit 2e Input circuit 4a as a second differential amplifier circuit constituting an input circuit 4 Output circuit as a signal processing circuit
CLK and CLK bars Complementary clock signals as external complementary signals
clkz, clkz bar Complementary clock signal N1 as internal complementary signal Node TN1, TN2 as output node NMOS transistor as transistor

Claims (4)

An input circuit for outputting an internal complementary signal composed of an internal positive phase signal and an internal reverse phase signal in response to the external complementary signal;
A semiconductor integrated circuit device comprising a signal processing circuit for performing signal processing based on the internal complementary signal,
The input circuit;
A first differential amplifier circuit including a pair of transistors to which the external complementary signals are respectively input, and outputting an internal positive phase signal from an output node based on the operation of each transistor;
A second differential amplifier including a pair of transistors to which the external complementary signals are respectively input, and outputting an internal negative-phase signal whose phase is inverted from that of the internal positive-phase signal from an output node based on the operation of each transistor A pseudo circuit is connected to at least one of the output terminals of the first and second differential amplifier circuits so that the load of the circuit connected to the output terminal is equal. A semiconductor integrated circuit device. An input circuit for outputting an internal complementary signal composed of an internal positive phase signal and an internal reverse phase signal in response to the external complementary signal;
A signal processing circuit for performing signal processing based on the internal complementary signal;
A semiconductor integrated circuit device comprising:
The input circuit;
A first differential amplifier circuit including a pair of transistors to which the external complementary signals are respectively input, and outputting an internal positive phase signal from an output node based on the operation of each transistor;
A second differential amplifier including a pair of transistors to which the external complementary signals are respectively input, and outputting an internal negative-phase signal whose phase is inverted from that of the internal positive-phase signal from an output node based on the operation of each transistor Circuit and
The semiconductor integrated circuit device is characterized in that the internal complementary signal generated by the input circuit is supplied only to a circuit including the signal processing circuit and operating with the complementary signal . The semiconductor integrated circuit device according to claim 2 ,
An internal processing circuit that operates on the internal positive phase signal or the internal negative phase signal;
A third input circuit comprising a third differential amplifier circuit for supplying the internal normal phase signal or the internal negative phase signal generated based on the external complementary signal to the internal processing circuit;
A semiconductor integrated circuit further comprising: An input circuit for outputting an internal complementary signal composed of an internal positive phase signal and an internal reverse phase signal in response to the external complementary signal;
A signal processing circuit for performing signal processing based on the internal complementary signal;
A semiconductor integrated circuit device comprising:
The input circuit;
A first differential amplifier circuit comprising a pair of transistors to which the external complementary signals are respectively input via input pads, and outputting an internal positive phase signal from an output node based on the operation of each transistor;
A pair of transistors to which the external complementary signals are input via input pads, respectively, and an internal negative phase signal whose phase is inverted from the internal positive phase signal is output from an output node based on the operation of each transistor; 2 differential amplifier circuits and
A semiconductor integrated circuit comprising: a pseudo circuit connected to at least one of the input pads so that a load of a circuit connected to the input pad is equal .

Images