JP3735375B2 - Multiprocessor system - Google Patents

Description

Technical field
The present invention relates to a multiprocessor system that includes a plurality of processors having a cache, detects a read request and a write request from a processor to a memory, and guarantees coherency between the memory and the cache, and is particularly suitable for memory access control for a shared memory. And a shared memory type multiprocessor system using the memory control chip.
Background art
In multiprocessor systems, it is essential to guarantee cache and memory coherency. In particular, when another processor issues a write to an address referenced by an arbitrary processor read, it is a problem to ensure that the written data is returned.
A conventional technique for the problem of cache coherency due to read and write competition will be described. A plurality of processors are connected to the memory control chip through a processor control line, a processor bus, and a coherent report line, respectively, and the memory control chip is connected to a memory through a memory bus and a memory control line.
Further, it is assumed that the latest data D ′ at address A exists in the cache of a certain processor, and the old data D exists in the memory. When another processor issues a read request to the memory for the address A and the previous processor issues a write request to the memory for the address A, in the prior art, the memory control chip refers to the read request and the write request. Address A conflict is detected, a retry read instruction signal is issued to the processor control line to the processor that issued the read request, and this processor issues a read request to address A again. The memory control chip invalidates the previously issued read request from the processor, and updates the contents of the memory address A to D ′ with priority on the write request. Thereafter, the memory control chip accepts the reissued read request and sends read data D ′ to the processor bus. Since the processor which issued the read request can receive the data D ′ for the address A, the coherency between the cache and the memory is guaranteed.
However, in such a conventional technique, when the processor that issued the read request receives the retry read request from the memory control chip, it is necessary to generate and issue the reference address A again. A buffer was needed to leave. In order to allow a plurality of read requests to be issued, information for identifying the lead to be retried is also required in the processor. Therefore, in the conventional technology, in order to suppress an increase in the amount of data due to the buffer, a read request that requires guarantee of memory and cache coherency is limited to one request for one processor, and a stage in which the processor cannot issue a read request is provided. Therefore, control has been performed to accept a retry read request between the stages. However, in this conventional technique, there is a period in which the processor cannot issue a read request, so that the memory read throughput of the system deteriorates and the performance deteriorates.
An object of the present invention is to improve the performance of a multiprocessor system by releasing a processor from a coherent guarantee operation.
Disclosure of the invention
In order to solve the above problem, the present invention provides a multiprocessor system that detects a match between reference addresses of a read request and a write request, a function that monitors the end of coherent reporting of a read request, A memory control chip having a function of determining that the write data of the write request is read data for the read request from a match detection result and a coherent report end result and a function of matching the read data and the write data are provided Is.
And if the read request is not activated in the memory, when the write request is issued before the coherent report of the read request is completed, the write operation is preferentially processed by detecting the conflict between the read request and the write request, Data with correct read operation can be read. Also, if a read request is activated in the memory, if a write request is issued before the coherent report of the read request is completed, the write operation is prioritized by detecting the conflict between the read request and the write request, and the read operation is performed. By invalidating and restarting the memory read with the same address and sending the read data to the bus, the data with the correct read request can be read.
As described above, the present invention guarantees the coherency of the memory and the cache in the memory control chip and the memory, thereby releasing the processor from the operation of the coherent guarantee and preventing the performance degradation of the multiprocessor system.
[Brief description of the drawings]
FIG. 1 is a block diagram of a preferred multiprocessor system according to the present invention.
FIG. 2 is an explanatory view of the conflict detection means in this multiprocessor system, FIG. 3 is another explanatory view of this conflict detection means, and FIG. 4 is an illustration of the conflict detection means of this conflict detection means. It is another explanatory view.
FIG. 5 is an explanatory diagram of the memory control means in the preferred multiprocessor system according to the present invention, FIG. 6 is an explanatory diagram of this memory control means, and FIG. 7 is another diagram of this memory control means. FIG. 8 is another explanatory view of this memory control means, FIG. 9 is still another explanatory view of this memory control means, and FIG. 10 is this memory control means. It is other explanatory drawing of.
FIG. 11 is an explanatory diagram of transmission control means in the preferred multiprocessor system according to the present invention, FIG. 12 is another explanatory diagram of this transmission control means, and FIG. 13 is an illustration of this transmission control means. It is another explanatory view.
FIG. 14 is an explanatory diagram of a retry read of a preferred multiprocessor system according to the present invention.
FIG. 15 is an explanatory diagram of the read buffer of the preferred multiprocessor system according to the present invention, and FIG. 16 is another explanatory diagram of the read buffer of the preferred multiprocessor system according to the present invention.
FIG. 17 is an explanatory diagram of a write buffer of a preferred multiprocessor system according to the present invention.
FIG. 18 is an explanatory diagram of a retry read buffer of a preferred multiprocessor system according to the present invention.
FIG. 19 is an explanatory diagram of a transmission buffer of a preferred multiprocessor system according to the present invention.
FIG. 20 is an explanatory diagram of the write priority processing of the preferred multiprocessor system according to the present invention.
FIG. 21 is an explanatory diagram of write priority processing and retry read of the preferred multiprocessor system according to the present invention.
FIG. 22 is an explanatory diagram of contention detection means in another preferred multiprocessor system according to the present invention.
FIG. 23 is another explanatory diagram of this competition detection means, and FIG. 24 is still another explanatory diagram of this competition detection means.
FIG. 25 is an explanatory view of a read buffer of another preferred multiprocessor system according to the present invention.
FIG. 26 is an explanatory diagram of another preferred multiprocessor system write buffer according to the present invention.
FIG. 27 is an explanatory diagram of a retry read buffer of another preferred multiprocessor system according to the present invention.
FIG. 28 is an explanatory diagram of a transmission buffer of another preferred multiprocessor system according to the present invention.
FIG. 29 is an explanatory diagram of a conflict between a plurality of read requests and one write request in another preferred multiprocessor system according to the present invention, and FIG. 30 is a conflict between the plurality of read requests and one write request. It is another explanatory drawing of.
FIG. 31 is an explanatory diagram of a conflict between a plurality of read requests and a plurality of write requests in another preferred multiprocessor system according to the present invention, and FIG. 32 is a conflict between the plurality of read requests and a plurality of write requests. It is another explanatory drawing of.
FIG. 33 is a block diagram of another preferred multiprocessor system according to the present invention.
FIG. 34 is an explanatory diagram of a write buffer in another preferred multiprocessor system according to the present invention, FIG. 35 is another explanatory diagram of this write buffer, and FIG. 36 is an example of this write buffer. It is another explanatory drawing of a buffer.
FIG. 37 is an explanatory diagram of a transmission buffer of another preferred multiprocessor system according to the present invention.
FIG. 38 is an explanatory diagram of the memory control means of another preferred multiprocessor system according to the present invention.
FIG. 39 is an explanatory diagram of a conflict between a plurality of read requests and a plurality of write requests in another preferred multiprocessor system according to the present invention, and FIG. 40 is a conflict between the plurality of read requests and a plurality of write requests. It is another explanatory drawing of.
FIG. 41 is a block diagram of still another preferred multiprocessor system according to the present invention.
FIG. 42 is an explanatory diagram of a read buffer of still another preferred multiprocessor system according to the present invention.
FIG. 43 is an explanatory diagram of the conflict between a plurality of read requests and a plurality of write requests in still another preferred multiprocessor system according to the present invention. FIG. 44 is a diagram illustrating the plurality of read requests and the plurality of write requests. It is another explanatory drawing of competition.
FIG. 45 is a block diagram of still another preferred multiprocessor system according to the present invention.
FIG. 46 is an explanatory view of a read buffer of still another preferred multiprocessor system according to the present invention.
FIG. 47 is an explanatory diagram of a contention detecting means of still another preferred multiprocessor system according to the present invention.
FIG. 48 is an explanatory diagram of a transmission buffer of still another preferred multiprocessor system according to the present invention.
FIG. 49 is an explanatory view of the transmission control means of still another preferred multiprocessor system according to the present invention.
FIG. 50 is an explanatory view of the conflict between a plurality of read requests and a plurality of write requests in still another preferred multiprocessor system according to the present invention, and FIG. 51 is a diagram of the plurality of read requests and the plurality of write requests. It is another explanatory drawing of competition.
FIG. 52 is an explanatory diagram of a multiprocessor system using a memory control chip according to the present invention.
FIG. 53 is a block diagram showing the structure of the conflict detection means in the multiprocessor system according to the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
One preferred embodiment of the present invention will be described with reference to FIG. In FIG. 1, 100, 101, 102 and 103 are cache memories (C), 104, 105, 106 and 107 are processors (P), 108, 109, 110 and 111 are cache coherent report signal lines, 112 is Bus arbiter signal line, 113 processor bus, 114 transmission control means, 115 coherent completion signal line, 116 retry read request signal line, 117 retry data valid signal line, 118 transmission completion signal line, 119 transmission data line , 120 is a sending buffer, 121 is a memory read data line, 122 is a write buffer, 123 is a write request signal line, 124 is a read buffer, 125 is a read request signal line, 126 is a read address line, and 127 is a request state Signal line 128 is competition detecting means, 129 is a write priority signal line, 13 Write approval signal line, 131 is a retry read buffer, 132 is a retry read address line, 133 is a memory control means, 134 is a memory control signal line, 135 is a memory address / data line, 136 is a transmission suppression signal line, and 137 is a read This is an approval signal line.
The present invention provides a means for detecting a match between a reference address of a read request issued from a processor of the system and a reference address of a write request issued from a processor of another system after the read request, and completion of coherent reporting of the read request. Have means for monitoring. These means are included in the competition detection means 128. A means for determining that the write data of the write request is the read data of the read from the coincidence detection result and the report end result is the transmission control means 114. The means for matching the read data with the write data is the retry read buffer 131, the memory control means 133, and the sending buffer 120.
The operation of each part in FIG. 1 will be described below. The read buffer 124 stores the read request issued to the processor bus 113, and outputs the stored read request to the memory control unit 133 through the read request signal line 125. Further, the read buffer 124 outputs the read address 126 and the request state 127 to the conflict detection unit 128. The request state 127 is a state indicating whether the entry in the read buffer 124 is valid and whether the read request is accepted by the memory control unit 133.
The conflict detection means 128 monitors the write request issued to the processor bus 113 and the coherent reports 108, 109, 110, and 111 from the processors 104, 105, 106, and 107, and the read address 126 output from the read buffer 124. And the address referred to by the write request and the arrival status of the coherent report, the outputs of the write priority signal 129, the coherent completion signal 115, and the transmission suppression signal 136 are controlled. The retry read buffer 131 stores the output 125 of the read buffer 124 received by the memory control unit 133, and the stored retry read address 132 is output to the memory control unit 133. The write buffer 122 stores a write request issued to the bus, and the stored write request is output to the memory control means 133 using the output 123. Based on the write priority signal 129 and the retry read request signal 116, the memory control means 133 accepts a request to be accepted among the output 125 of the read buffer, the output 123 of the write buffer, and the output 132 of the retry read buffer. Select to start the memory. When this activation depends on a read request or retry read, the memory control means 133 receives data 135 from the memory. The sending buffer 120 receives the data 121 from the memory control unit 133 and outputs the sending data 119 to the sending control unit 114. The transmission control unit 114 checks the coherent completion signal 115 and the transmission suppression signal 136 and determines whether to perform retry reading or to transmit to the processor bus 113 as it is.
Next, the operation of the conflict detection means 128 will be described with reference to FIGS. 2, 3, and 4. FIG. FIG. 2 defines the operation of the coherent completion signal 115. FIG. 3 defines the operation of the write priority signal 129. FIG. 4 defines the operation of the transmission inhibition signal 136.
The contention detection unit 128 turns on the coherent completion signal 115 when all of the read request coherent reports are output, and when the read request read data is transmitted from the transmission control unit 114 and the transmission completion signal 118 is turned on, the coherent completion is performed. The signal 115 is turned off.
In FIG. 2, 200 is a read request, and 201, 202, 203, and 204 are coherent reports for the read request 200. In FIG. 2, the contention detection means 128 turns on the coherent completion signal 115 because all the coherence of the read request 200 is reported at time 205. The contention detection unit 128 turns off the coherent completion signal 115 at time 207 because the transmission completion signal 118 is turned on at time 206.
If a write request having the same reference address as the reference address of the read request is issued before all the coherent reports for the read request are output, the conflict detection unit 128 turns the write priority signal 129 ON, and the write request is When the memory controller 133 accepts the write approval signal 130, the write priority signal 129 is turned OFF. In FIG. 3, 208 is a read request, 209 is a write request, 210, 211, 212, and 213 are coherent reports of the read request 208, 215 is a reference address of the read request 208, 219 is a read request, 220 is a write request, 210a , 211a, 212a, and 213a are coherent reports of the read request 219, and 215a is a reference address of the read request 219. The write request 209 has the same reference address as the read request 208. The write request 220 has the same reference address as the read request 219.
In FIG. 3, since the write request 209 is issued before the time 214 when all the coherent reports of the read request 208 are output, the contention detection unit 128 prioritizes writing at the next time 216 when the write request 209 is issued. The signal 129 is turned ON. Since the write approval signal 130 of the write request 209 is turned on at time 217, the conflict detection unit 128 turns off the write priority signal 129 at time 218. Since the write request 220 is issued after the time 221 when all the coherent reports of the read request 219 are output, the conflict detection unit 128 does not turn the write priority signal 130 ON.
The conflict detection unit 128 issues a write request having the same reference address as the reference address of the read request before all the coherent reports for the read request are output and after the read request is received by the memory control unit. Then, the transmission inhibition signal 136 is turned on. The conflict detection unit 128 turns the transmission inhibition signal 136 OFF when the retry read data of the read request is output from the memory control unit 133 and the retry data valid signal 117 is turned ON.
In FIG. 4, 222 is a read request, 223 is a write request, 229 is a read request, 230 is a write request, 233 is a reference address of the read request 222, and 234 is a reference address of the read request 229. The write request 223 has the same reference address as the read request 222. The write request 230 has the same reference address as the read request 229. In FIG. 4, the write request 223 is issued before the time 224 when all the coherent reports of the read request 222 are output. The write request 223 is issued after the time 225 when the read request 222 is accepted by the memory control means 133. For this reason, the conflict detection means 128 turns on the transmission suppression signal 136 at time 226. Since the retry data valid signal 117 is turned on at time 227, the conflict detection means 128 turns off the transmission suppression signal 136 at time 228. The write request 230 is issued before time 231 when all the coherent reports of the read request 229 are output. However, the write request 230 is issued before the time 232 when the read request 229 is accepted by the memory control means 133. For this reason, the conflict detection means 128 does not operate the transmission suppression signal 136.
Here, the configuration of the conflict detection means 128 will be described with reference to FIG. The conflict detection unit 128 includes an end monitoring unit 3600 that monitors the end of the coherent report, and an address match detection unit 3601 that detects a match between the addresses of the write request and the read request. The end monitoring means 3600 receives the coherent report signal lines 108, 109, 110, 111 and the transmission completion signal line 118 and outputs the coherent completion signal line 115. The operation of the coherent completion signal line 115 follows the definition of FIG. Address match detection means 3601 receives processor bus 113, read address line 126, request status signal line 127, write approval signal line 130, retry data valid signal line 117, coherent completion signal line 115, and write priority signal line 129, The transmission suppression signal line 136 is output. The operation of the write priority signal line 129 follows the definition of FIG. Further, the operation of the transmission suppression signal line 136 follows the definition of FIG.
Next, the operation of the memory control means 133 will be described with reference to FIG. When the write priority signal 129 and the retry read request signal 116 are OFF, the memory control unit 133 performs normal memory control if there is a write request or a read request. The memory control means 133 performs the following operation in addition to this normal memory control.
When the write priority signal 129 is ON, the memory control unit 133 gives priority to the memory write regardless of the state of the retry read request signal 116 if the address information 123 of the write request is valid. In addition, when the write priority signal 129 is OFF and the retry read request signal 116 is ON, the memory control unit 133 gives priority to retry reading if the retry read address information 132 is valid.
Next, the read request processing operation of the memory control means 133 will be described with reference to FIG. FIG. 6 defines the operations of the read approval signal 137, the memory control signal 134, the memory address / data 135, and the memory read data 121 during the read request processing. In FIG. 6, 300 is a read request, 302 is read control information, 303 is a reference address, and 304 is read data. If there is a read request when the read request can be processed, the memory control unit 133 accepts the read request and sets the read approval signal 137 to ON for one cycle. One cycle after the read approval signal 137 is turned ON, read control information is output to the memory control unit 134, and after one cycle, a reference address is output to the memory address / data 135. When the data read from the memory is output to the memory address / data 135, the memory control unit 133 outputs the read data to the memory read data 121 after one cycle. In FIG. 6, since the memory control means 133 accepts the read request 300 at time 301, the read approval signal 137 is turned ON at time 301. The memory control unit 133 outputs the read data 304 to the memory read data 121 at time 305 which is the next cycle output to the memory address / data 135.
Next, the write request processing operation of the memory control means 133 will be described with reference to FIG. FIG. 7 defines the operations of the write approval signal 130, the memory control signal 134, and the memory address / data 135 during the write request processing. In FIG. 7, 306 is a write request, 308 is write control information, 309 is a reference address, and 310 is write data. If there is a write request when the write request can be processed, the memory control unit 133 accepts the write request and turns on the write approval signal 130 for a period of one cycle. One cycle after the write approval signal 130 is turned ON, the write control information is output to the memory control signal 134, the reference address is written to the memory address / data 135 one cycle later, and the write data is written to the memory address / data 135 one cycle later. Is output. In FIG. 7, since the memory control means 133 accepts the write request 306 at time 307, the write approval signal 130 is turned ON at time 307.
Next, the read processing and write request contention processing operation of the memory control means 133 will be described with reference to FIG. FIG. 8 defines the operations of the read approval signal 137, the write approval signal 130, the memory control signal 134, the memory address / data 135, and the memory read data 121 during the read request / write request conflict processing operation. In FIG. 8, 311 is the read request, 313 is the write request, 314 is the read control information of the read request 311, 315 is the reference address of the read request 311, 318 is the read data of the read request 311, and 317 is the write request Write control information 313, 320 a reference address of the write request 313, and 321 write data of the write request 313. When the read request and the write request can be processed and the read request and the write request exist at the same time, the memory control means 133 accepts the read request first, and performs the read request processing operation defined in FIG. After the completion of the read request processing, the memory control means 133 accepts the write request and performs the write request processing operation defined in FIG.
In FIG. 8, the memory control means 133 accepts the read request 311 at the time 312 out of the read request 311 and the write request 313, so the read approval signal 137 is turned ON at the time 301. The memory control means 133 outputs the read data 318 to the memory read data 121 at time 316 which is the next cycle output to the memory address / data 135. Next, the memory control unit 313 turns on the write approval signal 130 at time 316 in order to accept the write request 313 at time 316 when the processing of the read request 311 ends.
Next, the read request, write request, and retry read contention processing operations of the memory control means 133 will be described with reference to FIG. FIG. 9 shows a read approval signal 137, a write approval signal 130, a memory control signal 134, a memory address / data 135, a memory read data 121, and a retry data valid signal 117 during a read request, write request, and retry read operation. Define the behavior. In FIG. 9, 322 is a read request, 324 is a write request, 326 is a retry read request, 329 is a read control information of the retry read request 326, 330 is a reference address of the retry read request 326, 331 is a read of the retry read request 326 The issued data, 332 is the read control information of the read request 322, 333 is the reference address of the read request 322, 334 is the read data of the read request 322, 335 is the write control information of the write request 324, and 336 is the write request Reference address 324 and 337 are write data of the write request 324. When the read request, the write request, and the retry read can be processed and the read request signal 116 indicating that there is a retry read is ON, the memory control unit 133 performs the retry. Accept lead with priority. The memory control means 133 outputs read control information to the memory control signal 134 based on the information of the retry address 132, and outputs a reference address to the memory address / data 135 one cycle later. When the data read from the memory is output to the memory address / data 135, the memory control means 133 turns on the retry data valid signal 117 one cycle later and outputs the read data to the memory read data 121 at the same time. To do. After the retry read process is completed, the memory control means 133 processes the read request and the write request in the order shown in FIG.
In FIG. 9, the memory control means 133 accepts the retry read request 326 at the time 338 among the read request 322, the write request 324, and the retry read request 326, so the read control information 329 is sent to the memory control signal 134 at the time 338. The reference address 330 is output to the memory address / data 135 in the next cycle. In response to the output of the read data 331 to the memory address / data 135, the memory control unit 133 turns on the retry data valid signal 117 at time 328 and outputs the read data 331 to the memory read data 121. The memory control means 133 accepts the read request 322 at time 323 after the retry read process is completed, and turns on the read approval signal 137. Further, the memory control means 133 accepts the write request 324 at time 325 after the end of the read process, and turns on the write approval signal 130.
Next, the read processing, write request, retry read, and write priority contention processing operation of the memory control means 133 will be described with reference to FIG. FIG. 10 shows a read approval signal 137, a write approval signal 130, a memory control signal 134, a memory address / data 135, a memory read data 121, and a retry data valid at the time of a read request, a write request, a retry read, and a write priority contention processing operation. The operation of the signal 117 is defined. In FIG. 10, 339 is a read request, 341 is a write request, 343 is a retry read request, 348 is read control information of the retry read request 343, 349 is a reference address of the retry read request 343, and 350 is a read of the retry read request 343. 351 is the read control information of the read request 339, 352 is the reference address of the read request 339, 353 is the read data of the read request 339, 345 is the write control information of the write request 341, 346 is the write request Reference address 341, 346 is write data of the write request 341. When the read request, the write request, and the retry read can be processed and the read request, the write request, and the retry read are present, and the write priority signal 129 that gives priority to writing is ON, the memory control unit 133 writes the write request. Priority is accepted. The memory control means 133 processes the write request in accordance with the rules of FIG. 7, and after the write processing, processes the retry read request in accordance with the rules of FIG. 9, and processes the read request in accordance with the rules of FIG. To do.
In FIG. 10, since the write priority signal 129 is ON among the read request 339, the write request 341, and the retry read request 343, the memory control means 133 turns the write approval signal 130 on for one cycle at time 342, and writes The request 341 is accepted. The memory control means 133 outputs the write control information 345 to the memory control signal 134 and outputs the reference address 346 and the write data 347 to the memory address / data 135 in the next two cycles. After processing the write request 341, the memory control means 133 accepts the retry read request 343 at time 354, so outputs the read control information 348 to the memory control signal 134 at time 354, and sets the reference address 349 to the memory address in the next cycle. / Output to data 135. In response to the output of the read data 350 to the memory address / data 135, the memory control unit 133 turns on the retry data valid signal 117 at time 344 and outputs the read data 350 to the memory read data 121. After the retry read is completed, the memory control means 133 accepts the read request 339 at time 340 and turns on the read approval signal 137.
Next, the operation of the sending control means 114 will be described with reference to the state transition diagram of FIG. When the coherent reports 108, 109, 110, 111 from the respective processors for the read request that caused the transmission have arrived for the transmission data 119 output from the transmission buffer 120 and the transmission data is correct, Define that the transmitted data is valid. Moreover, each transition condition in FIG. 11 is as follows.
(Condition 1): Transmission buffer 120 is invalid and
Coherent completion signal 115 is OFF.
(Condition 2) (Condition 6): The sending buffer 120 is valid, and
Coherent completion signal 115 is OFF.
(Condition 3) (Condition 7) (Condition 9): The sending buffer 120 is valid, and
The coherent completion signal 115 is ON, and
The transmission suppression signal 136 is OFF.
(Condition 4) (Condition 8) (Condition 11): The sending buffer 120 is valid, and
The coherent completion signal 115 is ON, and
The transmission inhibition signal 136 is ON.
(Condition 5) (Condition 10): The sending buffer 120 is invalid, and
Coherent completion signal 115 is ON.
(Condition 12): Retry data valid signal 117 is OFF.
(Condition 13): Retry data valid signal 117 is ON.
(Condition 14): Waiting for bus right.
(Condition 15): Obtain bus right.
The standby state 400 is a state waiting for the output from the transmission buffer 120 and the coherent completion signal 155 to be turned on. From the state 400, when data is output from the transmission buffer 120 and the coherent completion signal 115 remains OFF (condition 2), the transmission control unit 114 shifts to the coherent completion waiting state 401 until the coherent completion signal 115 is turned ON. Wait in state 401. From the state 400, when the coherent completion signal 115 is turned ON and no data is output from the transmission buffer 120 (condition 5), the transmission control unit 114 shifts to the transmission data output waiting state 402 until the transmission data is output. Wait in state 402. When the coherent completion signal 115 is turned ON from the state 400 and data is output from the transmission buffer 120 (condition 3), the transmission control unit 114 shifts to the data valid state 403 if the transmission suppression signal 136 is OFF. When the coherent completion signal 115 is turned ON from the state 401, the transmission control unit 114 shifts to the data valid state 403 if the transmission suppression signal 136 is OFF (condition 7). When the data is output from the transmission buffer 120 from the state 402, the transmission control unit 114 shifts to the data valid state 403 if the transmission inhibition signal 136 is OFF (condition 9). When the coherent completion signal 115 is turned ON from the state 400 and data is output from the transmission buffer 120, the transmission control unit 114 shifts to the retry read state 404 if the transmission suppression signal 136 is ON (condition 4). When the coherent completion signal 115 is turned ON from the state 401, the transmission control unit 114 shifts to the retry read state 404 if the transmission suppression signal 136 is ON (condition 8). When the transmission control unit 114 is in the state 402, if data is output from the transmission buffer 120 and the transmission suppression signal 136 is ON (condition 11), the transmission control unit 114 shifts to the retry read state 404. In the state 404, the transmission control means 114 turns the retry read request signal 116 ON. The transmission control means 114 waits in state 404 until retry data is output from the transmission buffer 120. When the retry data valid signal 117 is turned ON from the state 404 (condition 13), the transmission control unit 114 turns the retry read request signal 116 OFF and shifts to the data valid state 403. The transmission control means 114 waits in the data valid state 403 until the bus right can be acquired. When the bus right can be acquired (condition 15), the transmission completion signal 115 is turned ON and the state shifts to the standby state 400. The transmission control means 114 turns off the transmission completion signal 115 when the standby state 400 is entered.
Next, the operation of the sending control means 114 when retry reading is not performed will be described with reference to FIG. FIG. 12 defines the operations of the output 113 to the processor bus, the bus arbiter 112, and the transmission completion signal 118 when retry reading is not performed. In FIG. 12, reference numerals 405 and 406 denote transmission data. When the coherent completion signal 115 is ON and the transmission data 119 is not valid, the transmission control unit 114 waits until the transmission data 119 becomes valid. Further, when the coherent completion signal 115 is OFF and the transmission data 119 is valid, the transmission control unit 114 waits until the coherent completion signal 115 is turned ON. If the transmission data 119 is valid and the coherent completion signal 115 is ON, the transmission control unit 114 turns on the bus arbiter signal 112 and the transmission completion signal 118 and outputs the transmission data to the processor bus 113 in the next cycle.
In FIG. 12, although the transmission completion signal 115 is ON at time 407, since the transmission data 119 is not valid, the transmission control means 114 waits for the transmission data 405 to be output. Since the transmission data 405 is output at time 411, the transmission control unit 114 turns on the bus arbiter 112 and the transmission completion signal 118, and transmits the transmission data 405 to the processor bus 113 in the next cycle. Since the transmission completion signal 115 is ON at time 409 and the transmission data 119 is valid, the transmission control means 114 turns on the bus arbiter 112 and the transmission completion signal 118 and sends the transmission data 406 to the processor bus 113 in the next cycle. Send it out.
Next, the operation in the case of performing retry reading by the sending control means 114 will be described with reference to FIG. FIG. 13 defines the operations of the output 113 to the processor bus, the bus arbiter 112, the transmission completion signal 118, and the retry read request signal 116 when retry reading is performed. In FIG. 13, reference numerals 412 and 414 denote transmission data, and reference numerals 413 and 415 denote transmission data by retry read. When the coherent completion signal 115 is OFF or the transmission data 119 is invalid, the transmission control unit 114 waits until the coherent completion signal 115 is ON and the transmission data 119 becomes valid according to the definition of FIG. . If the coherent completion signal 115 is ON, the transmission data 119 is valid, and the transmission suppression signal 136 is OFF, the transmission control unit 114 performs processing according to the rules of FIG. The transmission control unit 114 turns the retry read request signal 116 ON when the coherent completion signal 115 is ON, the transmission data 119 is valid, and the transmission suppression signal 136 is ON. When the read data of the retry read is output from the memory control unit 133 and the retry data valid signal 117 is turned on, the conflict detection unit 128 turns off the transmission suppression signal 136. Since the transmission suppression signal 136 is turned OFF, the coherent completion signal 115 is ON, and the transmission data 119 is valid, the transmission control unit 114 performs processing according to the rules of FIG.
In FIG. 13, the transmission completion signal 115 is ON at time 416, but the transmission data 119 is invalid, so the transmission control means 114 waits for the transmission data 412 to be output. When the transmission data 412 is output, since the transmission suppression signal 136 is ON, the transmission control unit 114 sets the retry read request signal 116 to ON. Since the retry data valid signal 117 is turned on at time 417 and the transmission inhibition signal 136 is turned off at time 418, the transmission control means 114 turns on the transmission completion signal 118 and transmits the transmission data 413 by retry read in the next cycle. Is sent to the processor bus 113. When the transmission completion signal 115 is turned on at time 419, the transmission control unit 114 turns the retry read request signal 116 on because the transmission data 119 is valid and the transmission suppression signal 136 is on. Since the retry data valid signal 117 is turned on at time 420 and the transmission inhibition signal 136 is turned off at time 421, the transmission control unit 114 turns on the transmission completion signal 118 at time 421 and performs a retry read in the next cycle. Send data 415 is sent to the processor bus 113.
Next, an example of state transition of the sending control means 114 will be described with reference to FIG. Since the transmission data 119 is invalid at time 500 and the coherent completion signal 115 is also OFF, the state of the transmission control unit 114 is the standby state 400. Since the transmission data 506 is output from the transmission buffer 120 at time 501, the state of the transmission control unit 114 shifts from the standby state 400 to the coherent completion waiting state 401. At time 502, the coherent completion signal is turned on and the transmission suppression signal 136 is turned on, so that the state of the transmission control unit 114 shifts from the coherent completion waiting state 401 to the retry read state 404. Therefore, the retry read request signal 116 is turned ON at time 502. Since the retry data valid signal 117 is turned on at time 503, the state of the transmission control unit 114 shifts from the retry read state 404 to the data valid state 403 at time 504. Since the bus right is acquired at time 504, the transmission control means 114 turns on the transmission completion signal 118. At time 505, the state of the transmission control unit 114 shifts from the data valid state 403 to the standby state 400.
Next, the operation of the read buffer 124 will be described with reference to FIGS. 15 and 16 define the operations of the read request signal 125, the read address signal 126, and the request status signal 127. The read buffer 124 stores the read request output to the processor bus 113. The read buffer 124 outputs the stored read request to the memory control means 133 and the retry read buffer 131 using the read request signal 125. The read buffer 124 turns on the request state signal 127 until the stored read request is accepted by the memory control means 133. The read buffer 124 knows that the stored read request has been accepted by the memory control means 133 when the read approval signal 137 from the memory control means 133 is turned on, and turns off the request state signal 127 to read the read request signal. The request signal 125 is invalidated. The read buffer 124 outputs the read address signal 126 of the stored read request to the conflict detection means 128.
In FIG. 15, 2400 is a read request, and 2401 is the read address of the stored read request 2400. In FIG. 15, since the read request 2400 is stored in the read buffer 124 at time 2402, the read buffer 124 turns on the request status signal 127 from time 2402 and validates the read request signal 125. Since the read approval signal 137 is turned on at time 2403, the read buffer 124 turns off the request status signal 127 in the next cycle and invalidates the read request signal 125.
In FIG. 16, 2405 is a read request and 2406 is a read address of the stored read request 2405. In FIG. 16, since the read request 2405 is stored in the read buffer 124 at time 2407, the read buffer 124 turns on the request status signal 127 from time 2407 and validates the read request signal 125. Since the read approval signal 137 is turned on at time 2409, the read buffer 124 turns off the request state signal 127 in the next cycle and invalidates the read request signal 125.
Next, the operation of the write buffer 122 will be described with reference to FIG. FIG. 17 defines the operation of the write request signal 123. The write buffer 122 stores the write request output to the processor bus 113. The write buffer 122 outputs the stored write request to the memory control means 133 using the read request signal 123. The write buffer 122 knows that the stored write request has been accepted by the memory control signal 133 when the write approval signal 130 from the memory control means 133 is turned ON, and invalidates the write request signal 123. In FIG. 17, 2500 is a write request. In FIG. 17, at time 2501, the write request 2500 is stored in the write buffer 122, and the write request signal 123 becomes valid. Since the write approval signal 130 is turned ON at time 2502, the write buffer 122 invalidates the write request signal 123 in the next cycle.
Next, the operation of the retry read buffer 131 will be described with reference to FIG. FIG. 18 defines the operation of the retry read address line 132. The retry read buffer 131 stores a read request signal 125 when the read approval signal 137 is turned on and outputs it from the retry read address 132. The retry read buffer 131 invalidates the retry read address 132 when the transmission completion signal 118 is turned ON. In FIG. 18, 2600 is a read request. In FIG. 18, since the read approval signal 137 is turned ON at time 2601, the retry read buffer 131 stores the read request 2600 and outputs it from the retry read address 132. Since the transmission completion signal 118 is turned on at time 2602, the retry read buffer 131 invalidates the retry read address 132.
Next, the operation of the sending buffer 120 will be described with reference to FIG. FIG. 19 defines the operation of the transmission data line 119. The sending buffer 120 stores the data output to the memory read data 121 and outputs it from the sending data line 119. The sending buffer 120 stores the data of the memory read data 121 when the retry data valid signal 117 is turned on, and outputs it from the sending data line 119. The transmission buffer 120 disables the transmission data line 119 when the transmission completion signal 118 is turned ON.
In FIG. 19, 2700 and 2702 are transmission data, and 2703 is transmission data by retry read. In FIG. 19, since the transmission data 2700 is output to the memory read data 121, the transmission buffer 120 outputs the transmission data 2700 from the transmission data 119. Since the transmission completion signal 118 is turned ON at time 2701, the transmission buffer 120 invalidates the transmission data 119. Since the retry data valid signal 117 is turned ON at time 2705, the transmission buffer 120 changes the transmission data 2702 to the transmission data 119 and outputs the transmission data 2703. Since the transmission completion signal 118 is turned on at time 2704, the transmission buffer 120 invalidates the transmission data 119.
Next, in this preferred embodiment, the data sending operation when retry reading is not performed at the time of competition between reading and writing will be described with reference to FIG. The read request 600 is issued to the processor bus 113 at time 601 and the write request 602 is issued at time 603. The write request 602 has the same reference address as the read request 600. The coherent reports 108, 109, 110, and 111 for the read request 600 are completed at time 604. At time 603 when the write request 602 is issued, the coherent report has not been completed and the read request 600 has not been accepted, so the contention detection unit 128 turns the write priority signal 129 ON at time 605. Since the write priority signal 129 is ON, the memory control unit 133 accepts the write request 602 before the read request 600. Therefore, the data 600 read by the read request 600 becomes the data written by the write request 602. At time 608, since the data 607 is output from the transmission buffer 120 and the coherent completion signal 115 is also ON, the transmission control means 114 turns ON the transmission completion signal 118 at time 608, and the transmission control means 114 is at processor bus at time 609. Data 610 is sent to 113. Since the transmission completion signal 118 is ON, the conflict detection means 128 turns off the coherent completion signal 115. The send data 610 is the same as the data 606 and 607 and is data written by the write request 602. Thus, this embodiment guarantees cache and memory coherency.
Next, in this preferred embodiment, the data sending operation when retry reading is performed at the time of competition between read and write will be described with reference to FIG. The read request 700 is issued to the processor bus 113 at time 701 and the write request 702 is issued at time 703. The write request 702 has the same reference address as the read request 700. The coherent reports 108, 109, 110, and 111 for the read request 700 are completed at time 704. At time 703 when the write request 702 is issued, the coherent report has not been completed but acceptance of the read request has been completed. Therefore, the contention detection unit 128 turns on the write priority signal 129 at time 705, and at time 704. The transmission suppression signal 136 is turned ON. The transmission control unit 114 sets the retry read request signal 116 to ON because the coherent completion signal 115 and the transmission suppression signal 136 are ON at time 704 when the transmission data 706 is output from the transmission buffer 120. As a result, the memory control means 133 turns on the retry data valid signal 117 at time 708 and outputs data 707 by retry reading. Next, since the retry data valid signal 117 is ON, the transmission buffer 120 changes the output data from 706 to 707 at time 709, and the conflict detection means 128 turns the transmission inhibition signal 136 OFF. Since the transmission inhibition signal 136 is turned off, the transmission control unit 114 turns on the transmission completion signal 118 and transmits data 710 at time 711. The transmission data 710 is data written by the write request 702. Thus, this embodiment guarantees cache and memory coherency.
Next, another preferred embodiment of the present invention will be described. The read buffer 124 and the write buffer 122 are FIFOs, and each store a plurality of read requests and write requests. The conflict detection unit 128 detects a conflict between a plurality of read requests 126 stored in the read buffer and a write request issued to the processor bus 113 from the request status signal 127, and stores the conflict result. The conflict detection unit 128 outputs the stored result to the memory control unit 133 and the transmission control unit 114. The retry read buffer 131 is a FIFO, and stores a plurality of requests accepted by the memory control means 133 by the output of the read buffer 124. The sending buffer 120 is a FIFO buffer and stores a plurality of sending data 121.
The operation of the conflict detection means 128 will be described with reference to FIGS. 22, 23, and 24. FIG. FIG. 22 defines the operation of the coherent completion signal 115. The contention detection unit 128 monitors the coherent report for the read request issued to the processor bus 113, stores that all the reports are completed, and outputs it to the transmission control unit 114 by the coherent completion signal 115. When the transmission completion signal 118 indicating that the corresponding read request is processed by the transmission control unit 114 and transmitted to the processor bus 113 is turned ON, the storage of the coherent report completion of the corresponding read request is cleared, and the coherent completion signal Set 115 to OFF. Subsequently, the contention detection unit 128 outputs the coherent report status of the next read request to the coherent report completion signal 115.
In FIG. 22, 900, 901, 902, 903 are read requests, 904, 908, 912, 916 are coherent reports of the read request 900, 905, 909, 913, 917 are coherent reports of the read request 901, 906, 910, Reference numerals 914 and 918 are coherent reports for the read request 902, and reference numerals 907, 911, 915 and 919 are coherent reports for the read request 903.
In FIG. 22, since the coherent report of the read request 900 is completed when the coherent report 916 arrives, the contention detection unit 128 stores the completion of the coherent report of the read request 900 and outputs the coherent completion signal 115 at time 920. Turn it on. Since the coherent report of the read request 901 is completed when the coherent report 917 arrives, the conflict detection unit 128 stores the completion of the coherent report of the read request 901. Since the transmission completion signal 118 is turned on in response to the read request 900 at time 921, the conflict detection unit 128 turns off the coherent completion signal 115 in the next cycle. The contention detection unit 128 turns on the coherent completion signal 115 for the read request 901 at time 922 based on the coherent report completion information of the read request 901 already stored. Since the transmission completion signal 118 is turned ON in response to the read request 901 at time 922, the conflict detection means 128 turns off the coherent completion signal 115 in the next cycle. Since the coherent report of the read request 902 is completed when the coherent report 918 arrives, the conflict detection unit 128 stores the completion of the coherent report of the read request 902 and turns on the coherent completion signal 115 at time 924. Since the coherent report of the read request 903 is completed when the coherent report 919 arrives, the contention detection unit 128 stores the completion of the coherent report of the read request 903. Since the transmission completion signal 118 is turned on in response to the read request 902 at time 925, the conflict detection means 128 turns off the coherent completion signal 115 in the next cycle. The contention detection unit 128 turns on the coherent completion signal 115 for the read request 903 at time 926 based on the coherent report completion information of the read request 903 already stored. Since the transmission completion signal 118 is turned ON in response to the read request 903 at time 927, the conflict detection means 128 turns off the coherent completion signal 115 in the next cycle.
FIG. 23 defines the operation of the write priority signal 129. The conflict detection unit 128 monitors a write request issued to the processor bus 113 and detects a conflict for a read request that has already been issued and stored in the read buffer 124. The conflict detection unit 128 compares the reference address of the read request output to the read request address 126 with the reference address of the write request issued to the processor bus 113, and the reference address of the read request is the same as the reference address of the write request. If the coherent report for the read request is not completed, the write priority signal 129 is turned ON. The conflict detection means 128 stores the conflict information and the write request in association with each other. When the write request is accepted by the memory control unit 133 and the write approval signal 130 is turned on for the write request, the conflict detection unit 128 turns off the write priority signal 129 and conflicts with the stored write request. Clear information.
In FIG. 23, 928, 929, 930 and 931 are read requests, 932, 933, 934 and 935 are write requests, 936, 940, 944 and 948 are coherent reports of the read request 928, and 937, 941, 945 and 949 are The coherent report of the read request 929, 938, 942, 946, and 950 are the coherent reports of the read request 930, and 939, 943, 947, and 951 are the coherent reports of the read request 931. The write request 932 has the same reference address as the read request 928. The write request 933 and the write request 935 have the same reference address as the read request 930. The write request 934 has the same reference address as the read request 931.
In FIG. 23, the reference address of the write request 932 and the reference address of the read request 928 are the same, but since the issuance of the write request 932 is after the output of the last coherent report 944 of the read request 928, the conflict detection means 128 Does not operate the write priority signal 129. Since the issue of the write request 933 is before the completion of the coherent report of the read request 930, the conflict detection unit 128 stores the conflict information and turns on the write priority signal 129 at time 952. At time 952, the write approval signal 130 is turned ON for the write request 932, but since it is not for the write request 933, the conflict detection means 128 does not clear the conflict information of the write request 933, and the write priority signal Also, 129 is not turned off. Since the issuance of the write request 934 is before the completion of the coherent report of the read request 931, the conflict detection unit 128 stores the conflict information. Since the write approval signal 130 is turned ON for the write request 933 at time 953, the conflict detection unit 128 clears the conflict information of the write request 933 and turns the write priority signal 129 OFF. Since the contention means 128 stores contention information for the write request 934, the contention means 128 turns on the write priority signal 129 at time 954. Since the issue of the write request 935 is after the output of the last coherent report 950 of the read request 930, the conflict detection unit 128 does not store the conflict information. Since the write approval signal 130 is turned ON for the write request 934 at time 955, the conflict detection unit 128 clears the conflict information of the write request 934 and turns OFF the write priority signal 129. Since the write request 935 does not conflict with the read request, the conflict detection unit 128 turns the write priority signal 129 OFF after the next cycle of time 955.
FIG. 24 defines the operation of the transmission inhibition signal 136. The conflict detection unit 128 monitors a write request issued to the processor bus 113 and detects a conflict for a read request that has already been issued and stored in the read buffer 124. The conflict detection means 128 knows the acceptance status of the read request to the memory control means 133 from the request status signal 127. The conflict detection unit 128 compares the reference address of the read request output to the read request address 126 with the reference address of the write request issued to the processor bus 113, and the reference address of the read request is the same as the reference address of the write request. When the coherent report for the read request has not been completed and the acceptance of the read request to the memory control means 133 has been completed, information for sending out is transmitted in association with the read request. Store as control information. The contention detection unit 128 operates the transmission suppression signal 136 based on the transmission control information stored in association with the read request when the transmission by the read control is performed by the transmission control unit 114. The conflict detection unit 128 turns on the transmission suppression signal 136 when the transmission control information instructs to suppress transmission. In response to the read request, the transmission control unit 114 performs retry read, and the memory control unit 133 turns on the retry data valid signal 117, whereby the conflict detection unit 128 clears the conflict information stored in the read request. Then, the transmission inhibition signal 136 is turned off. When the transmission completion signal 118 is turned ON, the conflict detection unit 128 checks the transmission control information of the next read request and operates the transmission suppression signal 136.
In FIG. 24, 957, 958, 959, 960 are read requests, 961, 962, 963, 964 are write requests, 965, 969, 973, 977 are coherent reports of read requests 957, 966, 970, 974, 978 are Read request 958 coherent report, 967, 971, 975, 979 is read request 959 coherent report, 968, 972, 976, 980 is read request 960 coherent report, 986, 987, 988, 990, 991 is read request Accepted state. The write request 961 has the same reference address as the read request 957. The write request 962 and the write request 964 have the same reference address as the read request 959. The write request 963 has the same reference address as the read request 960. The request state 986 indicates a state in which only the entry storing the read request 957 in the read buffer 124 is valid and the entry is not yet accepted by the memory control unit 133. The request state 987 indicates a state in which the entry storing the read request 957 in the read buffer 124 and the entry storing the read request 958 are valid and these two entries are not yet accepted by the memory control unit 133. The request state 988 includes a state in which the entry storing the read request 958 and the entry storing the read request 959 in the read buffer 124 are valid, and these two entries are not yet received by the memory control unit 133. A state 957 is accepted by the memory control means 133. In the request state 989, the entry in which the read request 958 of the read buffer 124 is stored, the entry in which the read request 959 is stored, and the entry in which the read request 960 is stored are valid, and these three entries are still stored in the memory control unit 133. It shows a state where it is not accepted and a state where the read request 957 is accepted by the memory control means 133. The request state 990 includes a state where the entry storing the read request 959 of the read buffer 124 and the entry storing the read request 960 are valid, and these two entries are not yet accepted by the memory control unit 133, and the read request 957 and the read request 958 are shown in the state accepted by the memory control means 133. In the request state 991, the entry in the read buffer 124 in which the read request 960 is stored is valid and the entry is not yet accepted by the memory control means 133, and the read request 957, the read request 958, and the read request 959 are stored in the memory. The state accepted by the control means 133 is shown.
In FIG. 24, the reference address of the write request 961 and the reference address of the read request 957 are the same, and the read request 957 is already accepted by the memory control means 133, but the write request 961 is issued at the end of the read request 957. Since it is after the output of the coherent report 973, the conflict detection means 128 stores the transmission instruction as the transmission control information and turns off the transmission suppression signal 136. Since the issuance of the write request 962 is before the completion of the coherent report of the read request 959, and the read request 959 has already been received by the memory control unit 133, the contention detection unit 128 stores the transmission suppression as the transmission control information. Since the issuance of the write request 963 is before the completion of the coherent report of the read request 960 and the read request 960 has already been received by the memory control unit 133, the contention detection unit 128 stores the transmission suppression as the transmission control information. Since the transmission completion signal 118 is turned on in response to the read request 957 at time 994, the conflict detection unit 128 checks the transmission control information of the next read request 958. Since the transmission control information of the read request 958 is a transmission instruction, the conflict detection unit 128 keeps the transmission suppression signal 136 OFF. Since the transmission completion signal 118 is turned ON for the read request 958 at time 995, the conflict detection unit 128 checks the transmission control information of the next read request 959. Since the transmission control information of the read request 959 is transmission inhibition, the conflict detection unit 128 turns on the transmission inhibition signal 136 at time 992. Since the retry data valid signal 117 is turned on at time 996, the conflict detection unit 128 clears the conflict information of the read request 959 and turns off the transmission suppression signal 136. Since the transmission completion signal 118 is turned ON in response to the read request 959 at time 997, the conflict detection unit 128 checks the transmission control information of the next read request 960. Since the transmission control information of the read request 960 is transmission inhibition, the conflict detection unit 128 turns on the transmission inhibition signal 136 at time 993. Since the retry data valid signal 117 is turned on at time 998, the conflict detection unit 128 clears the conflict information of the read request 959 and turns off the transmission suppression signal 136.
Next, the operation of the read buffer 124 will be described with reference to FIG. FIG. 25 defines the operations of the read request signal 125 and the request status signal 127. The read buffer 124 stores a plurality of read requests output to the processor bus 113. The read buffer 124 outputs the stored read requests to the memory control unit 133 and the retry read buffer 131 using the read request signal 125 in the order in which the read requests are stored. The read buffer 124 notifies the contention detection unit 128 of the reception status of the stored read request to the memory control unit 133 by the request state signal 127. The read buffer 124 knows that the stored read request has been accepted by the memory control means 133 when the read approval signal 137 from the memory control means 133 is turned ON, and sends the read request signal 125 for one cycle. The read request stored next is invalidated and output to the read request signal 125.
In FIG. 25, 2800, 2801, 2802, 2803 are read requests, and 2804, 2805, 2806, 2807, 2808, 2809 are request states. The request state 2804 indicates a state in which only the entry storing the read request 2800 in the read buffer 124 is valid and the entry has not been accepted by the memory control unit 133 yet. The request state 2805 indicates a state where the entry storing the read request 2800 of the read buffer 124 and the entry storing the read request 2801 are valid and these two entries are not yet accepted by the memory control means 133. In the request state 2806, the entry storing the read request 2800 of the read buffer 124, the entry storing the read request 2801, and the entry storing the read request 2802 are valid, and these three entries are still in the memory control means 133. Indicates an unacceptable state. In the request state 2807, an entry in which the read request 2800 of the read buffer 124 is stored, an entry in which the read request 2801 is stored, an entry in which the read request 2802 is stored, and an entry in which the read request 2803 is stored are valid. One entry has not been accepted by the memory control means 133 yet. In the request state 2808, the entry storing the read request 2801 of the read buffer 124, the entry storing the read request 2802, and the entry storing the read request 2803 are valid, and these three entries are still in the memory control means 133. A state where it is not accepted and a state where the read request 2800 is accepted by the memory control means 133 are shown. The request state 2809 includes a state in which the entry storing the read request 2802 and the entry storing the read request 2803 of the read buffer 124 are valid, and these two entries are not yet accepted by the memory control unit 133. 2800 and a read request 2801 are received by the memory control means 133.
In FIG. 25, the read buffer 124 stores all read requests 2800, 2801, 2802, 2803. The read buffer 124 stores the read request 2800 and outputs the read request 2800 to the read request signal 125. Since the read approval signal 137 is turned ON at time 2813, the read buffer 124 invalidates the read request signal 125 in the next cycle and outputs the read request 2801 stored next to the read request 2800 to the read request signal 125. To do. Since the read approval signal 137 is turned ON at time 2814, the read buffer 124 invalidates the read request signal 125 in the next cycle and sets the read request 2802 stored next to the read request 2801 as the read request signal 125. Output.
Next, the operation of the write buffer 122 will be described with reference to FIG. FIG. 26 defines the operation of the write request signal 123. The write buffer 122 stores a plurality of write requests output to the processor bus 113. The write buffer 122 outputs the stored write request to the memory control means 133 using the write request signal 123. The write buffer 122 knows that the stored write request has been accepted by the memory control means 133 when the write approval signal 130 from the memory control means 133 is turned on, and the write request signal 123 is sent for one cycle. The invalidated write request is then output to the write request signal 123.
In FIG. 26, 2900, 2901, 2902 and 2903 are write requests. In FIG. 17, the write buffer 122 stores write requests 2900, 2901, 2902, 2903, and outputs a write request 2900 to the write request signal 123. Since the write approval signal 130 is turned ON at the time 2904, the write buffer 122 invalidates the write request signal 123 in the next cycle and outputs the write request 2901 stored next to the write request 2900 to the write request signal 123. To do. Since the write approval signal 130 is turned ON at time 2905, the write buffer 122 invalidates the write request signal 123 in the next cycle and outputs the write request 2902 stored next to the write request 2901 to the write request signal 123. To do.
Next, the operation of the retry read buffer 131 will be described with reference to FIG. FIG. 27 defines the operation of the retry read address line 132. The retry read buffer stores the read request signal 125 when the read approval signal 137 is turned on, and outputs it from the retry read address 132. The retry read buffer 131 invalidates the retry read address 132 for one cycle in response to the transmission completion signal 118 being turned ON, and then outputs the stored read request from the retry read address 132. In FIG. 27, 3000, 3001, and 3002 are read requests.
In FIG. 27, since the read approval signal 137 is turned on at time 3003, the retry read buffer 131 stores the read request 3000 and outputs the read request 3000 from the retry read address 132. Since the read approval signal 137 is turned on at time 3004, the retry read buffer 131 stores the read request 3001. Since the transmission completion signal 118 is turned ON at time 3006, the retry read buffer 131 outputs the read request 3001 after invalidating the retry read address 132 for the next one cycle. Since the read approval signal 137 is turned ON at time 3005, the retry read buffer 131 stores the read request 3002. Since the transmission completion signal 118 is turned ON at time 3007, the retry read buffer 131 invalidates the retry read address 132 for the next one cycle, and then outputs a read request 3002.
Next, the operation of the sending buffer 120 will be described with reference to FIG. FIG. 28 defines the operation of the transmission data line 119. The sending buffer 120 stores a plurality of data output to the memory read data 121 and outputs it from the sending data line 119. The sending buffer 120 stores the data of the memory read data 121 when the retry data valid signal 117 is turned on, and outputs it from the sending data line 119. When the transmission completion signal 118 is turned ON, the transmission buffer 120 invalidates the transmission data line 119 and outputs the data of the memory read data 121 stored next from the transmission data line 119.
In FIG. 28, 3100, 3101, 3102 and 3103 are transmission data, and 3104 is transmission data by retry read. In FIG. 28, since the transmission data 3100 is output to the memory read data 121, the transmission buffer 120 outputs the transmission data 3100 from the transmission data 119. Since the transmission completion signal 118 is turned on at time 3105, the transmission buffer 120 invalidates the transmission data 119 for one cycle, and outputs the stored transmission data 3101 from the transmission data line 119. Since the retry data valid signal 117 is turned on at time 3108, the transmission buffer 120 changes the transmission data 3101 of the transmission data line 119 and outputs the transmission data 3104. Since the transmission completion signal 118 is turned on at time 3106, the transmission buffer 120 invalidates the transmission data 119 for one cycle, and then outputs the stored transmission data 3102 from the transmission data line 119. Since the transmission completion signal 118 is turned on at time 3107, the transmission buffer 120 invalidates the transmission data 119 for one cycle, and then outputs the stored transmission data 3103 from the transmission data line 119.
With reference to FIG. 29 and FIG. 30 illustrating the temporally continuous signal regarding the coherency between the memory and the cache when a plurality of read requests and one write request conflict in another preferred embodiment. . The signal is continuous between the right end of FIG. 29 and the left end of FIG. Read requests 1000, 1002, and 1003 are issued to the bus 113 continuously from time 1001. At time 1005, a write request 1004 is issued. The reference address of the write request 1004 conflicts with the reference addresses of the read requests 1000 and 1003. As a result of conflict detection, the write priority signal 129 is turned ON at time 1006, and the write request approval signal 130 is turned ON at time 1007, so that the write priority signal 129 is turned OFF at time 1008. Read data corresponding to the read requests 1000, 1002, and 1003 is output from the memory control unit 133 continuously from time 1010. Since the coherent completion signal 115 and the transmission suppression signal 136 are turned on at time 1009, the transmission control unit 114 turns on the retry read request signal 116 at time 1009. The retry read address 132 is the reference address 1013 of the read request 1000. Since the write priority signal 129 is ON at time 1009, the memory control unit 133 prioritizes writing of the write request 1004 over retry reading.
Since the write priority signal 129 is turned off at time 1008, the memory control unit 133 turns on the retry data valid signal 117 at time 1014 and outputs data 1015 by retry reading. The transmission buffer 120 replaces the transmission data from 1012 to the retry read data 1017. Since the retry data valid signal 117 is turned on, the conflict detection means 128 turns off the transmission suppression signal 136 at time 1016. Since the transmission suppression signal 136 is turned off, the transmission control unit 114 turns on the transmission completion signal 118 at time 1016 and transmits the transmission data 1017 to the bus 113 as data 1019 at time 1018. Upon receiving the transmission completion signal 118, the contention detection means 128 clears the coherent completion signal 115, and the retry read buffer 131 outputs the reference address of the read request 1002. Since the coherent completion signal 115 of the read request 1002 is ON and the transmission suppression signal 136 is OFF at time 1021, the transmission control unit 114 sets the transmission completion signal 118 to ON, and sends the transmission data 1020 to the bus 113 at time 1023. Send out as Since the transmission completion signal 118 is turned on, the conflict detection means 128 turns off the coherent completion signal 115 at time 1023. At time 1025, the coherent completion signal 115 and the transmission suppression signal 136 of the read request 1003 are output. In response to this, the transmission control means 114 turns the retry request signal 116 ON. The retry read buffer 131 outputs the reference address 1026 of the read request 1003 as the retry read address.
The memory control unit 133 executes retry reading with the reference address of the read request 1003 and outputs retry data 1032 at time 1027. Since the retry data valid signal 117 is ON, the transmission buffer 120 changes the output from the data 1024 to the data 1028, and the conflict detection means 128 turns the transmission suppression signal 136 OFF. Since the transmission suppression signal 136 is turned off at time 1029, the transmission control unit 114 turns on the transmission completion signal 118 and outputs the data 1028 to the bus 113 as data 1031 at time 1030. Since the data 1015 and 1032 read by the retry read are both data written by the write request 1004, the coherent memory and cache can be guaranteed.
With reference to FIG. 31 and FIG. 32, the temporally continuous signals will be described for memory and cache coherency when a plurality of read requests and a plurality of write requests compete in another preferred embodiment. . The signal is continuous between the right end of FIG. 31 and the left end of FIG. Read requests 1100, 1102, and 1103 are issued to the bus 113 continuously from time 1101. A write request 1108 is issued at time 1105 and a write request 1108 is issued at time 1107. The reference address of the write request 1104 conflicts with the read request 1103, and the reference address of the write request 1108 conflicts with the reference address of the read request 1100. As a result of the conflict detection, the write priority signal 129 is turned on at time 1106 and the write approval signal 130 is turned on at time 1109, so that the write priority signal 129 is turned off at time 1110. Read data 1113, 1114, and 1115 corresponding to the read requests 1100, 1102, and 1103 are output from the memory control unit 133 continuously from time 1112. Since the coherent completion signal 115 and the transmission suppression signal 136 are turned on at time 1111, the transmission control unit 114 turns on the retry read request signal 116 at time 1117. The retry read address 132 is the reference address 1118 of the read request 1100. Since the write priority signal 129 is ON at time 1117, the memory control unit 133 prioritizes writing of the write request 1104 over retry reading. Although the one-cycle write priority signal 129 is turned OFF at time 1110, the memory control means 133 does not accept the request in the next cycle in which the write is accepted, so the retry read request is waited and the write request 1108 is prioritized.
Since the write approval signal 130 is issued at time 1119 and the write priority signal 129 is turned off at time 1120, the memory control unit 133 accepts the retry read request, turns on the retry data valid signal 117 at time 1122, and performs the retry read. Data 1123 is output. The sending buffer 120 replaces the sending data with the retry read data 1127 from 1116. Since the retry data valid signal 117 is turned on, the contention detection unit 128 turns off the transmission suppression signal 136 at time 1124. Since the transmission suppression signal 136 is turned off, the transmission control unit 114 turns on the transmission completion signal 118 at time 1124 and transmits the transmission data 1127 to the bus 113 as data 1126 at time 1125. Upon receiving the transmission completion signal 118, the contention detection means 128 clears the coherent completion signal 115, and the retry read buffer 131 outputs the reference address 1130 of the read request 1102. At time 1129, since the coherent completion signal 115 of the read request 1102 is ON and the transmission suppression signal 136 is OFF, the transmission control unit 114 sets the transmission completion signal 118 ON, and the transmission data 1128 is set as data 1132 on the bus at time 1131. Send it out. Since the transmission completion signal 118 is turned on, the conflict detection means 128 turns off the coherent completion signal 115 at time 1131. At time 1134, the coherent completion signal 115 and the transmission suppression signal 136 of the read request 1103 are output. In response to this, the transmission control means 114 turns the retry read request signal 116 ON. The retry read buffer 131 outputs the reference address 1133 of the read request 1103 as the retry read address.
The memory control unit 133 executes retry reading with the reference address of the read request 1103, and outputs retry data 1137 at time 1135. Since the retry data valid signal 117 is ON, the output buffer 120 changes the output from the data 1136 to the data 1139, and the conflict detection means 128 turns the transmission suppression signal 136 OFF. Since the transmission suppression signal 136 is turned off at time 1138, the transmission control unit 114 turns on the transmission completion signal 118 and outputs data 1139 as data 1141 to the bus 113 at time 1140. Since the data 1123 and 1137 read by the retry read are data written by the write request 1108 and the write request 1104, respectively, the coherency of the memory and the cache can be guaranteed.
FIG. 33 shows another preferred embodiment of the present invention. This embodiment corresponds to bringing data from the write buffer 122 when retry read is necessary due to competition between the read request and the write request. In addition to the function of storing a plurality of write requests issued to the bus 113, the write buffer 122 has a write request having a reference address that matches the address 132 output from the retry read buffer 131 by the retry read request 116. Are output to the transmission buffer 120. The transmission buffer 120 has a function of outputting the output 123 of the write buffer to the transmission data 119 when the retry data valid signal 117 is turned on, in addition to the function of storing the transmission data output from the memory control unit 133. Have. When the retry read request signal 116 is ON, the memory control unit 133 does not accept other than a write request whose write priority signal 129 is ON.
Next, the operation of the write buffer 122 will be described with reference to FIG. 34, FIG. 35, and FIG. FIG. 34 defines the operation of the write request signal 123. 35 and 36 define the operations of the write request signal 123 and the retry data valid signal 117. The write buffer 122 stores a plurality of write requests output to the processor bus 113. When the retry read request signal 116 is OFF or the write priority signal 129 is ON, the write buffer 122 outputs the stored write request to the memory control means 133 using the write request signal 123. The write buffer 122 knows that the stored write request has been accepted by the memory control means 133 when the write approval signal 130 from the memory control means 133 is turned on, and the write request signal 123 is sent for one cycle. The invalidated write request is then output to the write request signal 123. When the retry read request signal 116 is ON and the write priority signal 129 is OFF, the write buffer 122 turns the retry data valid signal 117 ON to match the retry read address 132 from all stored write requests. Write data of a write request having a reference address to be output to the write request line 123. In FIG. 34, when the retry read request signal 116 is OFF or the write priority signal 129 is ON, 1300, 1301, 1302, and 1303 are write requests.
In FIG. 34, the write buffer 122 stores the write request 1300 and outputs it to the write request signal 123. At time 1304, since the write approval signal 130 is turned ON, the write buffer 122 invalidates the write request signal 123 in the next cycle, and the write request 1301 stored next to the write request 1300 is used as the write request signal 123. Output. At time 1305, since the write approval signal 130 is turned ON, the write buffer 122 invalidates the write request signal 123 in the next cycle, and the write request 1302 stored next to the write request 1301 is used as the write request signal 123. Output. At time 1306, since the write approval signal 130 is turned ON, the write buffer 122 invalidates the write request signal 123 in the next cycle, and the write request 1303 stored next to the write request 1302 is used as the write request signal 123. Output. Since the write approval signal 130 is turned on at time 1307, the write buffer 122 invalidates the write request signal 123 in the next cycle.
In FIG. 35, 1308, 1309, 1310, and 1311 are write requests, and 1316 is a retry read reference address. The reference address of the write request 1308 is the same as the reference address 1316 of the retry read. In FIG. 35, the write buffer 122 stores the write request 1308, outputs the write request 1308 to the write request signal 123 according to the rules of FIG. 34, and receives the write request signal 130 ON at time 1312 in response to the write request. A write request 1309 is output to the signal 123. Since the retry read request signal 116 is turned ON at time 1314, the write buffer 122 outputs a write request 1308 with a reference address that matches the reference address 1316 output to the retry read address 132 to the write request signal 123. The write buffer 122 turns on the retry data valid signal 117 at time 1315, invalidates the write request signal 123 for one cycle, and outputs the write request 1309 again. Thereafter, the write buffer 122 outputs a write request 1310 to the write request signal 123 in response to the write approval signal 130 at time 1313 being turned on in accordance with the rules of FIG.
In FIG. 36, 1317, 1318, 1319 and 1320 are write requests, and 1326 is a retry read reference address. The reference address of the write request 1317 is the same as the reference address 1326 of the retry read. In FIG. 36, the write buffer 122 processes the write request 1317 in accordance with the rules of FIG. 34 and outputs a write request 1318 to the write request signal 123. Since the write priority signal 129 is ON at time 1324, the write buffer 122 processes the write request 1318 in accordance with the rules of FIG. When the write approval signal 130 at time 1322 is turned ON, the write priority signal 129 is turned OFF. Since the write priority signal 129 is OFF and the retry read request signal 116 is ON, the write buffer 122 has the same reference address as the reference address 1326 output to the retry read address 132 in accordance with the rules of FIG. A write request 1317 is output to the write request signal 123. The write buffer 122 turns on the retry data valid signal 117 at time 1325 and outputs a write request 1319 to the write request signal 123 in accordance with the rules of FIG. The write buffer 122 processes the write requests 1319 and 1320 in accordance with the rules of FIG.
Next, the operation of the sending buffer 120 will be described with reference to FIG. FIG. 37 defines the operation of the transmission data line 119. The sending buffer 120 stores a plurality of data output to the memory read data 121 and outputs it from the sending data line 119. The sending buffer 120 stores the data of the write request signal line 123 when the retry data valid signal 117 is turned ON, and outputs it from the sending data line 119. When the transmission completion signal 118 is turned ON, the transmission buffer 120 invalidates the transmission data line 119 and outputs the next stored data from the transmission data line 119. In FIG. 37, 1400, 1401, 1402, and 1403 are send data, and 1409 is write data for a write request stored in the write buffer 122. In FIG. 37, since the transmission data 1400 is output to the memory read data 121, the transmission buffer 120 outputs the transmission data 1400 from the transmission data 119. Since the transmission completion signal 118 is turned ON at time 1404, the transmission buffer 120 invalidates the transmission data 119 for one cycle, and outputs the stored transmission data 1401 from the transmission data line 119. Since the retry data valid signal 117 is turned on at time 1408, the transmission buffer 120 changes the transmission data 1401 of the transmission data line 119 and outputs the transmission data 1409. Since the transmission completion signal 118 is turned on at time 1405, the transmission buffer 120 invalidates the transmission data 119 for one cycle, and then outputs the stored transmission data 1402 from the transmission data line 119. Since the transmission completion signal 118 is turned on at time 1406, the transmission buffer 120 invalidates the transmission data 119 for one cycle, and then outputs the stored transmission data 1403 from the transmission data line 119. Since the transmission completion signal 118 is turned on at time 1407, the transmission buffer 120 invalidates the transmission data 119 for one cycle.
Next, the operation of the memory control means 133 will be described with reference to FIG. The read request processing operation, the write request processing operation, and the read request and write request contention processing operation are the same as those of the memory control means 133, and are shown in FIG. 6, FIG. 7, and FIG. When the write priority signal 129 is OFF and the retry read request signal 116 is ON, the memory control unit 133 accepts neither a read request nor a write request. 38, 3200 is a read request, 3202 is a write request, 3203 is write data for retry read, 3208 is write control data, 3209 is read control data, 3210 is write address, 3211 is write data, and 3212 is read address. , 3213 are read data for reading. In FIG. 38, the retry read request signal 116 is ON at time 3205, but since the write priority signal 129 is ON, the memory control means 133 accepts the write request 3202. The acceptance of the write request conforms to the rules of FIG. Since the write priority signal 129 is OFF and the retry read valid signal 116 is ON after the write request is received, the memory control unit 133 receives neither the content of the write request signal line 123 nor the read request signal line 125. Since the retry read request signal 116 is turned OFF at time 3207, the memory control means 133 accepts the read request 3200 in accordance with the rules of FIG.
See FIG. 39 and FIG. 40, which illustrate temporally continuous signals for memory and cache coherency when a plurality of read requests and a plurality of write requests compete in another preferred embodiment of the present invention. To explain. The signal is continuous between the right end of FIG. 39 and the left end of FIG. Read requests 1500, 1502, and 1503 are issued to the bus 113 continuously from time 1501. A write request 1504 is issued at time 1505 and a write request 1508 is issued at time 1507. The reference address of the write request 1504 conflicts with the read request 1503, and the reference address of the write request 1508 conflicts with the reference address of the read request 1500. As a result of the conflict detection, the write priority signal 129 is turned ON at time 1506, and the write approval signal 130 is turned ON at time 1509, so that the write priority signal 129 is turned OFF at time 1510. Read data 1513, 1514, 1515 corresponding to the read requests 1500, 1502, 1503 are continuously output from the memory control means 133 from time 1512. Since the coherent completion signal 115 and the transmission suppression signal 136 are turned on at time 1511, the transmission control unit 114 turns on the retry read request signal 116 at time 1517. The retry read address 132 is the reference address 1518 of the read request 1500. Since the write priority signal 129 is ON at time 1517, the memory control unit 133 prioritizes writing of the write request 1504 over retry read, and the write buffer 122 uses the stored information 1542 of the write request 1504. Output. At time 1510, the write priority signal 129 is turned OFF for one cycle, but the memory control means 133 does not accept the request in the next cycle after accepting the request, so the retry read request is awaited, and writing of the write request 1508 is prioritized. The In the next cycle when the write buffer 122 also receives the approval signal, the output 132 is not validated, so a retry read request is awaited and the stored information 1543 of the write request 1508 is output. Since the write approval signal 130 is issued at time 1519 and the write priority signal 129 is turned off at time 1520, the memory control means 133 receives a retry read request and does not accept a normal read request or write request. The write buffer 122 performs a retry read operation because the write priority signal 129 is OFF and the retry read request signal 116 is ON at time 1521, and data of the write request 1508 that sets the retry read address 1518 as a reference address at time 1521. 1544 is output to the output 123. The transmission buffer 120 replaces the transmission data with the retry read data 1527 from 1518. Since the retry data valid signal 116 is turned on, the conflict detection means 128 turns off the transmission suppression signal 136 at time 1524. Since the transmission suppression signal 136 is turned off, the transmission control unit 114 turns on the transmission completion signal 118 at time 1524 and transmits the transmission data 1527 as data 1526 to the bus 113 at time 1525. Upon receiving the transmission completion signal 118, the contention detection means 128 clears the coherent completion signal 115, and the retry read buffer 131 outputs the reference address 1530 of the read request 1502. At time 1529, since the coherent completion signal 115 of the read request 1502 is ON and the transmission suppression signal 136 is OFF, the transmission control unit 114 sets the transmission completion signal 118 ON, and sends the transmission data 1528 to the bus 113 at time 1531. Send out as Since the transmission completion signal 118 is turned on, the conflict detection means 128 turns off the coherent completion signal 115 at time 1531. At time 1534, the coherent completion signal 115 of the read request 1503 and the transmission suppression signal 136 are output. In response to this, the transmission control means 114 turns the retry read request signal 116 ON. The retry read buffer 131 outputs the reference address 1533 of the read request 1503 as the retry read address. The memory control means 133 receives a retry read request and does not accept a normal read request or write request. The write buffer 122 performs a retry read operation because the write priority signal 129 is OFF and the retry read request signal 116 is ON at time 1534, and the data of the write request 1504 using the retry read address 1533 as a reference address at time 1534. 1545 is output to the output 123. Since the retry data valid signal 117 is ON, the transmission buffer 120 changes the output from the data 1536 to the data 1539, and the conflict detection means 128 turns the transmission suppression signal 136 OFF. Since the transmission suppression signal 136 is turned off at time 1538, the transmission control unit 114 turns on the transmission completion signal 118 and outputs data 1539 as data 1541 to the bus 113 at time 1540. Since the data 1523 and 1537 read by retry read are data written by the write request 1508 and the write request 1504, respectively, the coherency of the memory and the cache can be guaranteed.
FIG. 41 shows still another preferred embodiment of the present invention. This embodiment corresponds to the case where the retry read address is brought from the read buffer 124 when the retry read is necessary due to the conflict between the read request and the write request. The read buffer 124 has a function of outputting a retry read address to the output 132 in addition to a function of storing a plurality of read requests issued to the bus 113.
The operation of the read buffer 124 will be described with reference to FIG. FIG. 42 defines the operation of the retry read address 132. The read request signal 125, the read address 126, and the request status signal 127 operate according to the rules of FIG. The read buffer 124 stores a plurality of read requests output to the processor bus 113. The read buffer 124 outputs the stored read requests to the memory control unit 133 using the read request signal 125 and the retry read address line 132 in the order in which they are stored. The read buffer 124 notifies the contention detection unit 128 of the reception status of the stored read request to the memory control unit 133 by the request state signal 127. The read buffer 124 knows that the stored read request has been accepted by the memory control means 133 when the read approval signal 137 from the memory control means 133 is turned ON, and sends the read request signal 125 for one cycle. The read request stored next is invalidated and output to the read request signal 125. The read buffer 124 knows that the transmission for the stored read request is completed when the transmission completion signal 118 from the transmission control means 114 is turned ON, invalidates the retry read address 132 for one cycle, Is output to the retry read address 132.
In FIG. 42, 1700, 1701, 1702, and 1703 are read requests. In FIG. 42, since the read approval signal 137 is turned ON at time 1704, the read buffer 124 outputs a read request 1701 to the read request signal 125 instead of the read request 1700. Since the read approval signal 137 is turned on at time 1705, the read buffer 124 outputs a read request 1702 to the read request signal 125 instead of the read request 1701. Since the transmission completion signal 118 is turned on at time 1706, the read buffer 124 invalidates the retry read address signal 132 for one cycle, and outputs a read request 1701 to the retry read address signal 132 instead of the read request 1700.
FIG. 43 and FIG. 44 illustrate temporally continuous signals regarding memory and cache coherency when a plurality of read requests and a plurality of write requests conflict in another preferred embodiment of the present invention. The description will be given with reference. The signal is continuous between the right end of FIG. 43 and the left end of FIG. Read requests 1800, 1802, and 1803 are issued to the bus 113 continuously from time 1801. At time 1842, a read request 1843 is issued. A write request 1808 is issued at time 1805 and a write request 1808 is issued at time 1807. The reference address of the write request 1804 conflicts with the read request 1803, and the reference address of the write request 1808 conflicts with the reference address of the read request 1800. As a result of the conflict detection, the write priority signal 129 is turned on at time 1806, and the write approval signal 130 is turned on at time 1809, so that the write priority signal 129 is turned off at time 1810. Read data 1813, 1814, and 1818 corresponding to the read requests 1800, 1802, and 1803 are continuously output from the memory control unit 133 from time 1812. Since the coherent completion signal 115 and the transmission suppression signal 136 are turned on at time 1811, the transmission control unit 114 turns on the retry read request signal 116 at time 1817. The read buffer 124 outputs the reference address 1848 of the read request 1800 to the retry read address 132. Since the write priority signal 129 is ON at time 1817, the memory control unit 133 prioritizes writing of the write request 1804 over retry reading. Although the one-cycle write priority signal 129 is turned OFF at time 1810, the memory control means 133 does not accept the request in the next cycle in which the request is received, so the retry read request is waited for, and writing of the write request 1808 is prioritized. Since the write approval signal 130 is issued at time 1819 and the write priority signal 129 is turned off at time 1820, the memory control unit 133 accepts the retry read request at the reference address 1848 of the read request 1800, and at time 1821 the retry data valid signal. 117 is turned ON and retry data 1823 is output. The transmission buffer 120 replaces the transmission data from the data 1818 to the retry read data 1827. Since the retry data valid signal 117 is turned on, the conflict detection means 128 turns off the transmission suppression signal 136 at time 1824. Since the transmission suppression signal 136 is turned OFF, the transmission control unit 114 turns the transmission completion signal 118 ON at time 1824 and transmits transmission data 1827 to the bus 113 as data 1826 at time 1825. Upon receiving the transmission completion signal 118, the conflict detection means 128 clears the coherent completion signal 115, and the read buffer 124 outputs the reference address 1830 of the read request 1802 to the retry read address 132. At time 1829, since the coherent completion signal 115 of the read request 1802 is ON and the transmission suppression signal 136 is OFF, the transmission control unit 114 sets the transmission completion signal 118 ON, and sends the transmission data 1828 to the bus 113 at time 1831. Send out as Since the transmission completion signal 118 is turned on, the conflict detection means 128 turns off the coherent completion signal 115 at time 1831. Since the transmission completion signal 118 is turned ON at time 1824, the read buffer 124 outputs the reference address 1833 of the read request 1803 to the retry read address 132. The memory control means 133 outputs the read data 1850 of the read request 1843 at time 1849. At time 1834, the coherent completion signal 115 of the read request 1803 and the transmission suppression signal 136 are output. In response to this, the transmission control means 114 turns the retry read request signal 116 ON. The memory control unit 133 receives a retry read request at the reference address 1833 of the read request 1803, turns on the retry data valid signal 117 at time 1835, and outputs the retry data 1837. The transmission buffer 120 changes the output from the data 1836 to the data 1839, and the conflict detection means 128 turns off the transmission suppression signal 136. Since the transmission inhibition signal 136 is turned off at time 1838, the transmission control unit 114 turns on the transmission completion signal 118 and outputs data 1839 as data 1841 to the bus 113 at time 1840. At time 1840, the transmission buffer 120 outputs read data 1851 of the read request 1843. Since the data 1823 and 1837 read by retry read are data written by the write request 1808 and the write request 1804, respectively, the coherency of the memory and the cache can be guaranteed.
FIG. 45 shows still another preferred embodiment of the present invention. This embodiment corresponds to a case in which a read request is output to the memory control means 133 after the completion of the cache report. In addition to the function of storing a plurality of read requests issued to the bus 113, the read buffer 124 receives a coherent completion signal 115 and outputs a read request to the output 125. When the memory control unit 133 accepts the read request, the memory control unit 133 outputs a read approval signal 137 to the conflict detection unit 128. Upon receiving the read approval signal 137, the conflict detection means 128 clears the coherent completion signal 115. The sending control unit 114 sends the output of the sending buffer 120 to the bus 113.
Next, the operation of the read buffer 124 will be described with reference to FIG. FIG. 46 defines the operation of the read request signal 125. The operation of the read address 126 follows the definition of FIG. The read buffer 124 stores a plurality of read requests output to the processor bus 113. When the coherent completion signal 115 is turned ON, the read buffer 124 uses the read request signal 125 in the order in which the stored read requests are stored, and outputs them to the memory control means 133. The read buffer 124 knows that the stored read request has been accepted by the memory control means 133 when the read approval signal 137 from the memory control means 133 is turned ON, and sends the read request signal 125 for one cycle. The read request stored next is invalidated and output to the read request signal 125. In FIG. 46, 2000, 2001, 2002 and 2003 are read requests. In FIG. 46, since the coherent completion signal 115 is turned ON at time 2007, the read buffer 124 outputs the read request 2000 stored first in the read request signal 125 in the next cycle. Since the read approval signal 137 is turned on at time 2106, the read buffer 124 invalidates the read request signal 125. Since the coherent completion signal 115 is turned on at time 2008, the read buffer 124 outputs the read request 2001 stored after the read request 2000 to the read request signal 125.
The operation of the conflict detection means 128 will be described with reference to FIG. FIG. 47 defines the operation of the coherent completion signal 115. The operation of the write priority signal 129 follows the definition of FIG. The contention detection means 128 monitors the coherent report for the read request issued to the processor bus 113, stores that all the reports are completed, and outputs it to the read buffer 124 by the coherent completion signal 115. When the read approval signal 137 indicating that the corresponding read request is accepted by the memory control unit 133 is turned ON, the storage of the coherent report completion of the corresponding read request is cleared, and the coherent completion signal 115 is turned OFF. Subsequently, the contention detection unit 128 outputs a coherent report state of the next read request to the coherent completion signal 115. 47, 3300, 3301, 3302, and 3303 are read requests, 3304, 3308, 3312, and 3316 are coherent reports of the read request 3300, 3305, 3309, 3313, and 3317 are coherent reports of the read request 3301, 3306, 3310, 3314 and 3318 are coherent reports of the read request 3302, and 3307, 3311, 3315 and 3319 are coherent reports of the read request 3303. In FIG. 47, since the coherent report of the read request 3300 is completed when the coherent report 3316 arrives, the contention detection unit 128 stores the completion of the coherent report of the read request 3300 and outputs the coherent completion signal 115 at time 3320. Turn it on. Since the coherent report of the read request 3301 is completed when the coherent report 3317 arrives, the conflict detection unit 128 stores the completion of the coherent report of the read request 3301. Since the read approval signal 137 is turned ON for the read request 900 at time 3324, the conflict detection unit 128 turns OFF the coherent completion signal 115 in the next cycle. The contention detection unit 128 turns on the coherent completion signal 115 for the read request 3301 at time 3321 based on the coherent report completion information of the read request 3301 already stored. Since the read approval signal 137 is turned on in response to the read request 3301 at time 3321, the conflict detection unit 128 turns off the coherent completion signal 115 in the next cycle. Since the coherent report of the read request 3302 is completed when the coherent report 3318 arrives, the conflict detection unit 128 stores the completion of the coherent report of the read request 3302 and turns on the coherent completion signal 115 at time 3322. Since the coherent report of the read request 3303 is completed when the coherent report 3319 arrives, the conflict detection unit 128 stores the completion of the coherent report of the read request 3303. Since the read approval signal 137 is turned on in response to the read request 3302 at time 3326, the conflict detection unit 128 turns off the coherent completion signal 115 in the next cycle. The contention detection unit 128 turns on the coherent completion signal 115 for the read request 3303 at time 3323 based on the coherent report completion information of the read request 3303 already stored. Since the read approval signal 137 is turned on in response to the read request 3303 at time 3327, the conflict detection unit 128 turns off the coherent completion signal 115 in the next cycle.
Next, the memory control means 133 will be described. The memory control unit 133 processes a read request or a write request output from the read buffer 124 and the write buffer 122, and outputs a transmission data to the memory read data line 121 in the case of a read request. When the write priority signal 129 is ON, the memory control unit 133 receives the write request with priority. The operations of the read approval signal 137, the memory control signal 134, the memory address / data 135, and the memory read data 121 during the read request processing are in accordance with the rules of FIG. The operations of the write approval signal 130, the memory control signal 134, and the memory address / data 135 during the write request processing are in accordance with the rules of FIG. The operations of the read approval signal 137, the write approval signal 130, the memory control signal 134, the memory address / data 135, and the memory read data 121 during the read request / write request conflict processing operation are in accordance with the rules of FIG.
Next, the operation of the sending buffer 120 will be described with reference to FIG. FIG. 48 defines the operation of the transmission data line 119. The sending buffer 120 stores a plurality of data output to the memory read data 121 and outputs it from the sending data line 119. When the transmission completion signal 118 is turned ON, the transmission buffer 120 invalidates the transmission data line 119 and outputs the data of the memory read data 121 stored next from the transmission data line 119. In FIG. 48, 3400, 3401, 3402 and 3403 are transmission data. In FIG. 48, since the transmission data 3100 is output to the memory read data 121, the transmission buffer 120 outputs the transmission data 3100 from the transmission data 119. Since the transmission completion signal 118 is turned ON at time 3404, the transmission buffer 120 invalidates the transmission data 119 for one cycle, and outputs the transmission data 3401 stored next to the transmission data 3400 from the transmission data line 119. Since the transmission completion signal 118 is turned ON at time 3405, the transmission buffer 120 invalidates the transmission data 119 for one cycle, and outputs the transmission data 3402 stored next to the transmission data 3401 from the transmission data line 119. Since the transmission completion signal 118 is turned ON at time 3406, the transmission buffer 120 invalidates the transmission data 119 for one cycle, and outputs the transmission data 3403 stored next to the transmission data 3402 from the transmission data line 119.
Next, the operation of the sending control means 114 will be described with reference to FIG. FIG. 49 defines the operations of the output 113 to the processor bus, the bus arbiter 112, and the transmission completion signal 118. In FIG. 49, reference numerals 3500 and 3501 denote transmission data. When the sending data 119 is not valid, the sending control means waits until the sending data 119 becomes valid. If the transmission data 119 is valid, the transmission control unit 114 turns on the bus arbiter signal 112 and the transmission completion signal 118 and outputs the transmission data to the processor bus 113 in the next cycle. In FIG. 49, since the transmission data 119 is valid at time 3502, the transmission control means 114 turns on the bus arbiter 112 and the transmission completion signal 118, and transmits the transmission data 3500 to the processor bus 113 in the next cycle. Since the transmission data 119 is valid at time 3503, the transmission control unit 128 turns on the bus arbiter 112 and the transmission completion signal 118, and transmits the transmission data 3501 to the processor bus 113 in the next cycle.
With reference to FIG. 50 and FIG. 51, the temporally continuous signals for the coherency of the memory and the cache when a plurality of read requests and a plurality of write requests compete in this further preferred embodiment will be described. To do. The signal is continuous between the right end of FIG. 50 and the left end of FIG. Read requests 2100, 2102, and 2103 are issued to the bus 113 continuously from time 2101. A write request 2104 is issued at time 2105 and a write request 2108 is issued at time 2107. The reference address of the write request 2104 conflicts with the read request 2103, and the reference address of the write request 2108 conflicts with the reference address of the read request 2100. As a result of conflict detection, the write priority signal 129 is turned ON at time 2106, and the write approval signal 130 is turned ON at time 2109, so that the write priority signal 129 is turned OFF at time 2110. Since the coherent completion signal 115 is turned on at time 2111, the read buffer 124 outputs the address 2118 of the read request 2100. Since the memory control means 133 does not accept the request in the next cycle after accepting the request, the write priority is given from the time 2106 to the time 2120, the write requests 2104 and 2108 are accepted, and the read request 2100 is at the time 2122 after the time 2120. Accept. The conflict detection unit 128 receives the read approval signal 137 and clears the coherent completion signal 115 at time 2121. As a result, the read request address becomes invalid. Since the coherent completion signal 115 is turned ON at time 2123, the read buffer 124 outputs the address 2124 of the read request 2102. In response to the read approval signal 137 being turned ON at time 2125, the conflict detection unit 128 clears the coherent completion signal 115 in the next cycle. As a result, the read request address becomes invalid. Since the coherent completion signal 115 is turned ON at time 2127, the read buffer 124 outputs the address 2126 of the read request 2103. In response to the read approval signal 137 being turned ON at time 2128, the conflict detection unit 128 clears the coherent completion signal in the next cycle. The read data of the read requests 2100, 2102, and 2103 are output to the read data 121 continuously from the time 2112, and the read data of the read request 2100 output to the send data 119 at the time 2129 are output to the bus 113 at the time 2136. The Similarly, read data 2114, 2115, and send data 2231, 2132 of the read requests 2102 and 2103 are continuously output to the read data 121 and the send data 119, and are output to the bus 113 as 2134 and 2135, respectively. Since the data 2133 and 2135 read by the read requests 2100 and 2103 are data written by the write request 2108 and the write request 2104, respectively, the coherency between the memory and the cache can be guaranteed.
Next, a preferred embodiment of a multiprocessor system constituted by a memory control chip using the present invention will be described with reference to FIG. The processor 2200 has a cache 2211, and a plurality of the processors 2200 are connected by a memory control chip 2203 through a processor bus 2201, a control line 2202, and a coherent report signal line 2204. The memory control chip 2203 detects a conflict between a read request and a write request issued by the processor, and uses the internal buffer of the memory control chip or the memory 2205 as a buffer to guarantee memory and cache coherency. The memory control chip is connected by a memory 2205, a memory bus 2206, and a control line 2207, and controls reading and writing of the memory. The memory control chip is connected to each I / O 2210, the system bus 2208, and a control line 2209 to read and write requests for I / O from the processor, and DMA read and write requests to the memory from the I / O. To control.
Industrial applicability
As described above, according to the multiprocessor system of the present invention, the memory control chip detects a read request and a write request from the processor to the memory, and guarantees the coherency of the memory and the cache. The processor can issue other requests without being bound by issued requests, and is suitable for use in a system that requires high performance.

Claims (2)

In a multiprocessor system in which a plurality of processors and a main memory are connected via a memory control chip,
The processor confirms whether or not the cache memory and the latest data at the address of the read request output from another processor exist in the cache memory, and when there is, the write request output to the main memory of the data ends. Means for outputting a coherent report indicating whether or not
The memory control chip detects a match between a reference address of a read request issued from the processor and a reference address of a write request issued from another processor later than the read request;
Monitoring means for monitoring a coherent report output by the processor in response to the read request, and determining that coherent for the read request has been completed when all of the processors output a coherent report;
If the detection means detects an address match, and the monitoring means does not detect coherent completion for the read request for which the detection means detects an address match, the address match is used as read data for the read request. Determination means for determining that the write data of the requested write should be used;
Storage means for storing the address of the read request that activated the main memory;
Restart means for restarting the main memory at the address of the read request stored in the storage means;
An exchange means for exchanging data obtained by restarting the main memory and data obtained by normal activation;
When it is determined by the determination means that the write data of the write request with the matching address should be used as the read data of the read request, the data obtained by the restart by the replacement means and the data obtained by the normal activation A multiprocessor system characterized by exchanging data. The multiprocessor system of claim 1, wherein
If the determination means determines that the write data of the write request with the matching address should be used as the read data of the read request, the write request to the main memory is given priority over other read requests. The multiprocessor system is characterized in that execution of the main memory from the restarting means is performed prior to other read requests.

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