JP3733582B2 - EL display device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an improvement in an EL (electro luminescence) display device, and more particularly to an EL display device that prevents light emission of non-selected pixels due to current leakage.
[0002]
[Prior art]
The structure of the EL display device will be described with reference to FIG. FIG. 1 is an explanatory diagram schematically illustrating an EL device with a cross-sectional view. Broadly speaking, a substrate 1, an integrated circuit layer 2 on which a circuit for controlling light emission of a pixel is formed, and an EL light emitting pixel are arranged in a matrix. The display pixel forming layer 3 is formed.
[0003]
The substrate 1 is a transparent glass substrate that transmits light from the light emitting layer. The integrated circuit formation layer 2 is integrated with a selection circuit composed of a switch circuit S group for lighting each pixel at a designated arrangement position (address). The display pixel formation layer 3 is formed by patterning an ITO film on the integrated circuit formation layer 2, and a plurality of transparent pixel electrodes (anodes) 34 arranged in a matrix, and the pixel electrode 34 and the integrated circuit formation layer. 2, a light-emitting layer 32 formed by depositing an organic EL on the hole-transport layer 31, and a cathode 33 formed on the light-emitting layer 32. Has been.
[0004]
In such a configuration, the output of the decoder (not shown), for example, closing the switch circuit S _n of the selection circuit. Thereby, the power supply E is applied to the pixel electrode 34, and the current I _a flows from the pixel electrode 34 toward the cathode 33. The organic EL light emitting layer 32 between the pixel electrode 34 and the cathode 33 emits light. The light generated in the light emitting layer 32 passes through the transparent pixel electrode 34, the integrated circuit forming layer 2, and the glass substrate 1 and is emitted to the outside. In addition, a voltage necessary for light emission is not applied between the pixel electrode 34 and the cathode 32 to which the non-closed switch circuit Sn _{+ 1} is connected, and the light emitting layer 32 sandwiched between them does not emit light. In this way, a two-dimensional image is formed by individually controlling the light emission of each pixel arranged in a matrix.
[0005]
[Problems to be solved by the invention]
However, in the EL display device configured as described above, the light emitting layer 32 is not formed as an independent region for each pixel. Emitting layer 32 has a high resistance, since the hole transport layer 31 is a low resistance, flows to the adjacent pixels a part of the drive current I _a of the light emitting pixel is off as leakage current i _0. As a result, the potential of some of the pixel electrodes 34 increases, and there is a problem that (weak) light emission occurs from a pixel portion that should originally be non-light-emitting (off). This causes a decrease in contrast and blurring of the outline.
[0006]
Therefore, an object of the present invention is to provide an EL display device in which pixels that should not emit light by light emission of adjacent pixels do not emit light.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, an EL display device of the present invention is a progressive scanning EL display device in which a plurality of pixels are arranged in a matrix and the pixel columns of each row are sequentially driven.
The pixels are arranged in a plurality of regions defined by a plurality of scanning lines extending in one direction parallel to each other and a plurality of data lines intersecting with the extending direction of each scanning line,
The pixel region includes an EL light-emitting element having one end connected to the first power source, one of the source / drain regions serving as a first data line, and the other region serving as a second through a capacitor. A first transistor of one conductivity type whose gate is connected to the first scanning line, a power source, one of the source / drain regions as the second scanning line, and the other region as the EL light emitting element. A second transistor of one conductivity type whose gate is connected to the other region of the first transistor, and one of the source / drain regions to the second power source and the other A region is formed at the other end of the EL light emitting element, and a third transistor of another conductivity type is formed, the gate of which is connected to the other region of the first transistor.
[0008]
Further, the second scan line is a scan line of an adjacent pixel columns, said second and third transistors comprising operate complementary to each other.
[0009]
With such a structure, a circuit for forcibly clamping the potential of the EL light emitting element that should not emit light to a non-light emitting level can be formed in the pixel region with a small number of elements and wirings. Thereby, it becomes possible to improve the aperture efficiency of the pixel.
[0010]
Preferably, each of the pixels includes a plurality of scanning lines extending in one direction parallel to each other, a plurality of data lines orthogonal to the extending direction of each scanning line, the plurality of scanning lines, and the plurality of data. The display information is updated for each row, arranged in a matrix in a plurality of regions defined by the lines, and a data line to which the pixel column of the previous row is connected is used as a potential application bus line .
[0011]
In this way, in an EL display that performs a line scanning display, the scanning lines other than the selected scanning line have a non-emission (extinguishment) control signal, so that the scanning line is before or after the selected scanning line. A scanning line in a row can be used as a clamp potential. As a result, the bus wiring can be reduced, the pixel electrode area can be increased, and the aperture efficiency is improved. Yield can be improved by reducing the wiring.
[0012]
Embodiment
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram for explaining a reference example related to the embodiment of the present invention.
[0013]
In the figure, an EL display device includes a substrate 1, an integrated circuit layer 2 on which a circuit for controlling light emission of pixels is formed, and a display pixel formation layer 3 formed by two-dimensionally arranging EL light emitting pixels in a matrix. . The substrate 1 is a transparent glass substrate that transmits light from the light emitting layer. Further, the integrated circuit formation layer 2 integrates a selection circuit composed of a switch circuit S group for lighting each pixel at a designated arrangement position (address). The display pixel formation layer 3 is formed by patterning an ITO film on the integrated circuit formation layer 2, and includes a plurality of transparent pixel electrodes (anodes) 34 arranged in a matrix, and the pixel electrodes 34 and the integrated circuit. A hole transport layer 31 deposited on the formation layer; a light emitting layer 32 formed by depositing an organic EL on the hole transport layer 31; and a cathode 33 formed on the light emitting layer 32. , Is composed of. Thus, one pixel of the display pixel formation layer 3 formed in a stacked manner corresponds to a unit display pixel.
[0014]
The switch circuit S that operates each display pixel of the integrated circuit forming layer 2 that controls the light emission of the display pixel is complementary to a normally open contact that relays a signal when operating and a normally closed contact that relays a signal when not operating. A complementary switch circuit that generates an output is used. For example, a high voltage V _H is supplied as a first potential sufficient to activate the light emitting layer from the power supply circuit to the normally open contact side of each complementary switch circuit. For example, a low voltage _VL is supplied to the normally closed contact side as a potential sufficient to deactivate the light emitting layer from the power supply circuit. A pixel to emit light is selected by a decoder (not shown), and a control signal is supplied to the corresponding one or more complementary switch circuits. The complementary switch circuit supplied with the control signal switches the output to the normally open contact side, selects the high voltage V _H that activates the light emitting layer, and supplies it to the pixel electrode. Thereby, the selected display pixel emits light. Further, in the pixel that is not selected, the complementary switch circuit maintains the relay at the level of the normally closed contact side, and supplies the pixel electrode with a low voltage V _L that deactivates the light emitting layer. Therefore, the potential (or voltage) of the pixel electrode of the display pixel that is not selected is forcibly set to _VL, and the floating state of the potential of the pixel electrode is avoided. Thereby, the current flowing through the hole transport layer 3 having a relatively low resistance can be controlled. Further, light emission due to current leakage from the pixel electrode is suppressed. As a result of reducing the influence of the light emitting pixels on the non-light emitting pixels, the pixels can be arranged closer to each other, and the pixel density can be increased. The normally open contact side circuit of the complementary switch circuit corresponds to a selection circuit that causes the unit display pixel to emit light, and the normally closed contact side circuit corresponds to a light emission suppression circuit that does not cause the unit display pixel to emit light. Note that it is not necessary to use the complementary switch circuit as long as the equivalent function is exhibited.
[0015]
FIG. 2 shows a configuration example of the complementary switch circuit S for one pixel. In the figure, transistors Q _{1 to} Q ₄ are N-type TFTs. A high potential bus line B _H and a low potential bus line B _L are arranged in the vertical direction on the left side of FIG. Data lines x _n and / x _n to which complementary signals are supplied are arranged in the upper right and lower directions, and scanning lines y _n are arranged in the lower left and right directions. The data lines x _n and / x _n and the scanning line y _n are driven by a decoder (not shown). In the figure, _one of the source / drain regions of the transistor Q ₁ is connected to the anode (pixel electrode) A of the EL light emitting element. The other is connected to the high potential bus line _BH . One of the source / drain regions of the transistor Q ₂ is connected to the anode A of the EL light emitting element. The other is connected to the low potential bus line _BL . A capacitor C ₁ and a transistor Q ₃ for holding the potential are connected in series between the high potential bus line B _H and the data line x _n . A connection point between the capacitor C ₁ and the transistor Q ₃ is connected to the gate of the transistor Q ₁ . A capacitor C ₂ and a transistor Q ₄ for holding the potential are connected in series between the low potential bus line _BL and the data line / x _n . The connection point between the capacitor C ₂ and the transistor Q ₄ is connected to the gate of the transistor Q ₂ . The gates of the transistors Q ₃ and Q ₄ are connected to the scan line y _n.
[0016]
In such a configuration, in the case where the light emitting elements EL _n of the selected sequence, the decoder scan line y _n of the selected row is set to "H" level to turn on the transistors Q _3, Q ₄ . Further, the data lines x _n and / x _n are set to the “H” level for making the transistor Q ₁ conductive and the “L” level for making the transistor Q ₂ non-conductive. When the scanning line y _n becomes “H” level, the transistors Q ₃ and Q ₄ are both turned on. Thereby, the capacitors C ₁ and C ₂ are charged by the potentials of the data lines x _n and / x _n , respectively, and the corresponding potential is held until the next scanning (writing). Further, the gates of the transistors Q ₁ and Q ₂ are set to “H” level and “L” level, respectively. Transistor Q ₁ is turned, the electric potential V _H on the high potential bus line B _H is applied to the anode A, and supplies the operating current. Transistor Q ₂ are non-conductive, relay to the anode A of the potential V _L on the low potential bus line B _L is interrupted. The light emitting element EL _n by the high voltage V _H is applied to the pixel electrode from the high potential bus line B _H to the light emitting element EL _n emits light.
[0017]
On the other hand, when the light emitting elements EL _n in the selected row are not caused to emit light, the decoder sets the data lines x _n and / x _n to the “L” level that makes the transistors non-conductive and the “H” level that makes the transistors conductive Set. Since the scanning line y _n is at “H” level, the transistors Q ₃ and Q ₄ are both conducting. Thereby, potential holding capacitors C ₁ and C _2, respectively "L" level is set to "H" level, is retained until the next scanning (writing). Further, the gates of the transistors Q ₁ and Q ₂ are set to “L” level and “H” level, respectively. The transistor Q ₁ becomes non-conductive, and the supply of the drive current to the anode A by the potential V _H of the high potential bus line B _H is stopped. On the other hand, the transistor Q ₂ is turned, the potential V _L on the low potential bus line B _L is relayed to the anode A. The potential of the anode A is clamped to the potential _VL of the low potential bus line maintained at a constant potential. No light is emitted when a low voltage V _L is applied to the light emitting element EL _n . In the above-described embodiment, each transistor is configured as an N type, but may be configured as a P type.
[0018]
FIG. 3 shows an integrated circuit pattern of the complementary switch circuit shown in FIG. In the figure, A is an anode (pixel electrode) of the EL light emitting element. Since the functional element portion is denoted by the same reference numerals as those in FIG. Connections between the wiring films are made by contact holes.
[0019]
FIG. 4 shows an example in which the switch circuit shown in FIG. 2 is composed of complementary TFT transistors using an N-type TFT (Q ₁₁ ) and a P-type TFT (Q ₁₂ ). By using the complementary TFT, the data line signal / x _n , the capacitor C ₂ and the transistor Q ₄ shown in FIG. 2 become unnecessary.
[0020]
Stated The operation of this circuit, when the "H" level signal is applied to the scanning lines y _n, transistor Q ₁₃ is an N-type TFT becomes conductive. Thereby, the signal level of the data line x _n is charged capacitor C ₁₁ of the potential holding, it is held until the next scan. Further, the “H” level of the data line x _n turns on the transistor Q ₁₁ and turns off the transistor Q ₁₂ . The pixel electrode A of the EL light emitting element is clamped at a low level, and light emission is blocked.
[0021]
On the other hand, when the scanning line y _n is at “H” level and the data line x _n is at “L” level (or negative level), the transistor Q ₁₁ is turned off and the transistor Q ₁₂ is turned on. As a result, the level clamp is released, and a high level V _H is applied from the high potential bus line B _H to the pixel electrode A of the EL light emitting element, and a drive current flows to emit light.
[0022]
FIG. 5 is an embodiment of the present invention, and shows an example of a switch circuit that does not require the low potential bus line _BL described in FIG. Other configurations are the same as those in FIG. That in this example, when updating the screen display in sequential scanning, when the scanning line y _n are accessed, the scanning lines y _n-1 of the previous row is non-access ( "L" level) We are using. One of the drain / source regions of the transistor Q ₁₁ is connected to the scanning line yn ₋₁ and the other is connected to the anode A of the light emitting element.
[0023]
FIG. 6 shows an integrated circuit pattern of the switch circuit of FIG. The same components are denoted by the same reference numerals, and description thereof is omitted. Compared to the wiring pattern shown in FIG. 3, the number of bus lines is reduced, and the area of the anode (pixel electrode) A of the EL light emitting element can be increased. In addition, the pixel density can be increased.
[0024]
According to the above-described embodiment, light emission due to current leakage can be suppressed, so that the pixels can be arranged closer to each other, and the density of the pixels can be increased. Further, by utilizing the scanning line of the adjacent pixel as the clamp potential, the wiring is reduced, the area of the pixel electrode can be increased, and the aperture efficiency is improved.
[0025]
Note that the present invention can be applied not only to an organic EL display device but also to a light emitting device using a general organic semiconductor film when preventing current leakage from an adjacent pixel electrode.
[0026]
【The invention's effect】
As described above, according to the display device of the present invention, since the potential of the pixel electrode of the non-display pixel is level clamped to a predetermined potential, light emission due to current leakage from the adjacent pixel electrode is suppressed.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram illustrating a display device according to a reference example of the present invention.
FIG. 2 is a circuit diagram illustrating a configuration example of a switch circuit.
FIG. 3 is an explanatory diagram showing an integrated circuit pattern of the switch circuit shown in FIG. 2;
FIG. 4 is a circuit diagram showing a configuration example of another switch circuit using complementary TFTs.
5 is a circuit diagram showing an example of a switch circuit in which a part of the switch circuit of FIG. 4 is changed according to an embodiment of the present invention .
6 is an explanatory diagram showing an integrated circuit pattern of the switch circuit shown in FIG. 5. FIG.
FIG. 7 is an explanatory diagram for explaining a defect of an EL light emitting display device.

Claims (3)

A sequential scanning EL display device in which a plurality of pixels are arranged in a matrix and the pixel columns in each row are sequentially driven,
  The pixels are arranged in a plurality of regions defined by a plurality of scanning lines extending in one direction parallel to each other and a plurality of data lines intersecting the extending direction of each scanning line,
  In the pixel area,
  An EL light emitting element having one end connected to the first power source;
  One of the source / drain regions is connected to the first data line, the other region is connected to the second power source via the capacitor, and the first conductivity type first gate is connected to the first scanning line. A transistor,
  One conductivity type in which one of the source / drain regions is connected to the second scanning line, the other region is connected to the other end of the EL light emitting element, and the gate is connected to the other region of the first transistor. A second transistor;
  One of the source / drain regions is connected to the second power source, the other region is connected to the other end of the EL light emitting element, and the gate is connected to the other region of the first transistor. A third transistor is formed;
  An EL display device. The EL display device according to claim 1, wherein the second scanning line is a scanning line of an adjacent pixel column . The EL display device according to claim 1, wherein the second and third transistors operate complementarily to each other .

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