JP3732908B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit capable of performing electrostatic breakdown protection on an integrated circuit incorporating a plurality of resistance elements while preventing fluctuations in the ratio of resistance values between the resistance elements.
[0002]
[Prior art]
In general, when a resistance element is incorporated as a passive element incorporated in an integrated circuit, a diffusion region having a desired impurity concentration is formed and a specific resistance of the diffusion region is used. When a resistive element is used as a single circuit, the accuracy is not required. However, when using a voltage dividing resistor as a circuit, the resistance ratio between the resistive elements is not the absolute value of each resistive element. May be considered important.
[0003]
For example, in a circuit such as a divided power supply for LCD shown in FIG. 5, resistors 1 to 4 are arranged in series between the power supply potential VCC and the ground potential GND, and further a voltage dividing resistor R between the resistors 2 and 3. 2R, 3R, 4R, 8R are arranged. Note that the numbers of the voltage dividing resistors R to 8R indicate multiples. For example, the voltage dividing resistor 4R has a resistance value four times that of the voltage dividing resistor R by connecting four resistors corresponding to the voltage dividing resistor R in series. Show that you have. The values of the resistors 1 to 4 have the same value as the voltage dividing resistor R.
[0004]
Since this circuit is equivalent to a total of 22 resistors, for example, when the power supply potential VCC is 22V, the voltage across each resistor is 1V. Therefore, a desired output voltage is generated at the output terminals V1 to V4 of the operational amplifiers OP1, OP2, OP3, and OP4 depending on how the input terminals R × 1 to R × 6 of the voltage dividing resistors R to 8R are short-circuited. It is like that.
[0005]
At this time, if the ratio of the resistance values of the resistors 1 to 4 is deviated, even if the output potential of a certain output terminal is fixed to the design value, the output potential of other output terminals deviates from the design value, and all output terminals are It becomes impossible to match the design value. For this reason, the resistance ratio of the resistors 1 to 4 must be strictly designed and managed.
Further, an IC that can set the output voltage obtained from the user side to an arbitrary value is easier to design an electronic device incorporating the IC. Therefore, not only the input terminals R × 1 to R × 6 but also all the other input terminals R1 to R4 and IN1 to IN4 are led to the external connection pads, for example, external resistors between the input terminals outside the IC. There has been a demand for doubling the combination of output voltages obtained by inserting or shorting.
[0006]
On the other hand, in the design of a semiconductor integrated circuit, an element for preventing electrostatic breakdown as shown in FIGS. 6A and 6B is to be inserted in order to protect internal elements from disturbance noise from external connection pads. is there. This electrostatic breakdown preventing element includes a protection diode 6 connected between the pad 5 and the ground potential GND, and a limiting resistor 8 connected between the pad 5 and the internal circuit 7. When the following potential is applied, the protective diode is turned on to release the current, and when a potential equal to or higher than the power supply potential VCC is applied to the pad 6, the limiting resistor 8 is applied as shown in FIG. The structure is such that the parasitic protection diode 11 composed of the P type diffusion region 9 and the N type epitaxial layer 10 constituting the structure is turned on to allow current to escape to the power supply potential VCC applied to the epitaxial layer 10.
[0007]
However, in the structure of FIG. 6B, since the power supply potential VCC is applied to the epitaxial layer 10, a depletion layer is generated between the diffusion region 9 and the epitaxial layer 10 due to the potential difference with the potential applied to the pad 5. Since the depletion layer narrows the effective cross-sectional area of the diffusion region 9, this means that the resistance value of the limiting resistor 8 varies depending on the potential applied to the pad 5. If such a limiting resistor 8 is connected in series to a resistance element that requires the accuracy of the resistance ratio, a factor that deviates the balance of the resistance value is added, so that it cannot be connected.
[0008]
[Problems to be solved by the invention]
As described above, when connecting a resistance element that requires accuracy of resistance value balance to an external connection pad, it is difficult to connect an electrostatic breakdown protection element.
Also, providing the external connection terminals corresponding to the number of resistance elements, and providing the electrostatic breakdown protection elements shown in FIG. 6 for each of them, requires a large number of pads 5 that require a large area of, for example, 200 × 200 μm. Since the individual islands are formed separately, and each island is required to have a relatively large area, there is a disadvantage that the chip size increases and the cost increases.
[0009]
[Means for Solving the Problems]
The present invention has been made in view of such a conventional problem. By forming a PNPN thyristor on an island in which a resistance element is formed, and connecting the thyristor element between a pad and a ground potential, The present invention provides a semiconductor integrated circuit that can release a current even when noise exceeding a power supply potential is superimposed on a pad and does not disturb the balance of resistance values.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a sectional view showing a semiconductor integrated circuit device according to the present invention.
In FIG. 1, 21 is a P-type silicon semiconductor chip, 22 is a pad for external connection formed in the peripheral portion of the semiconductor chip, and 23 is a circuit for forming active and passive circuit elements to achieve a desired circuit function. A block 24 is a number of resistance elements for constituting the voltage dividing circuit of FIG. The resistance elements 24 are densely arranged near the center of the semiconductor chip 21 and are arranged in parallel with each other in the same size. Further, both ends of the resistance element 24 are connected to the corresponding pads 22 or internal circuits by electrode wirings (not shown). Thus, by arranging the resistance elements together in the central portion of the semiconductor chip 21, the resistance value variation due to mechanical stress applied to the chip is minimized.
[0011]
2A is an enlarged plan view of a part of the resistance element, and FIG. Note that the resistance elements shown in the figure correspond to the resistors 1 and 2 in the circuit diagram of FIG.
In this figure, 25 is a P-type silicon semiconductor substrate, 26 is a P + type isolation region penetrating an N-type epitaxial layer formed on the substrate 25, 27 is an island junction-separated by the isolation region 26, and 28 is a selection. This is a P-type diffusion region formed on the surface of the island 27 by diffusion, and the diffusion region 28 constitutes the resistance element 24. 29 is an N + type channel stopper region surrounding the diffusion region 28, 30 is a P type diffusion region for forming a thyristor, and 31 is an N + type for forming a thyristor formed on the surface of the P type diffusion region 30. It is a diffusion region.
[0012]
The channel stopper region 29 is formed on the surface of the island 27 between the diffusion region 28 and the isolation region 26, and is disposed so as to surround the P type diffusion region 30 as well as surrounding the diffusion region 28. However, a part of the P-type diffusion region 30 is extended with a thin line width (30a in the figure) and overlapped with the separation region, and a portion where the portion 30a extending with the thin line width crosses the channel stopper region 29 is cut. is doing.
[0013]
One end of the diffusion region 28 is connected to an external connection pad 32a serving as an input terminal by an electrode wiring 33a, and the other end is connected to a pad 32b serving as an internal circuit and another input terminal by an electrode wiring 33b. A part of the channel region 29 near the other end is expanded, and an electrode 33a connected to the one end extends on the oxide film 34 and contacts the expanded portion. Thus, the island 27 is biased by the potential on the high potential side of the resistance element 24. By biasing at the high potential side in this way, the shape and size of the depletion layer formed at the PN junction between the island 27 and the diffusion region 28 are made constant in each resistance element 24 regardless of the input voltage. It is possible to prevent the balance of resistance values from being lost. The electrode 33a connected to one end is also extended on the oxide film 34 to at least the outside of the channel region 29 and the upper part of the P-type diffusion region 30 to form a field electrode 33c. In the field electrode 33c, the electrode wiring crosses the upper part of the diffusion region 28, and the depletion layer of the diffusion region is changed by the potential of the electrode wiring, thereby preventing the resistance value from shifting. Further, the channel region 29 prevents the p-type channel generated at the interface between the island 27 and the oxide film 34 from reaching the isolation region 26, and the resistance value is reduced by the current flowing through the diffusion region 28 leaking through the channel. Preventing changes.
[0014]
The ground potential GND is applied to the N + type diffusion region 31 by the electrode wiring 33d. The ground potential GND is also applied to the isolation region 26 and the semiconductor substrate 25 by electrode wiring (not shown).
When viewed from one of the pads 32a, a resistance element composed of the P-type diffusion region 28 is connected to the pad 32a, and a thyristor element SCR is connected to the ground potential. The thyristor element SCR includes a PNP transistor TR1 composed of P in the P-type diffusion region 28, N in the island 27, P in the P-type diffusion region 30, and N in the island 27, P in the P-type diffusion region 30, and N + type. It is configured by a combination with NPN transistor TR2 made of N in diffusion region 31. Further, the EB bias resistor r1 of the PNP transistor TR1 is formed by extending the channel region 20, and the EB bias resistor r2 of the NPN transistor TR2 is formed by the portion 30a extended with a thin line width of the P-type diffusion region 30. Forming.
[0015]
When a surge voltage lower than the ground potential GND is applied to one pad 32a, a protection diode 6 (not shown) formed of an independent island near or directly below the pad 32a is turned on to protect the internal circuit. The protection diode 6 is configured with the N-type region of the island 27 as a cathode and the isolation region 26 and the P-type region of the substrate 25 as an anode. This structure and operation are the same as those of the conventional example shown in FIG.
[0016]
When a surge voltage higher than the power supply potential VCC is applied to one pad 32a, first, the PNP transistor Tr1 is turned on by the potential difference generated by the resistor r1, the collector current supplies the base current of the NPN transistor TR2, and the minute resistance r2 The NPN transistor TR2 is turned on by the potential difference generated by the thyristor element SCR, the thyristor element SCR is turned on, and a surge current flows from the N + diffusion region 31 to the ground potential GND through the electrode. The turn-on potential can be set to a desired value depending on the distance between the P-type diffusion region 28 and the P-type diffusion region 30. The turn-on voltage must be smaller than the reverse breakdown voltage (about 100V) of the diode formed by the island 27 and the isolation region 26, and is set to about 50V. At this time, unless the portion 30a of the P-type diffusion region 30 extending with a narrow line width, that is, the resistance of the P-type diffusion region 3 is fixed by the resistor r2, the NPN transistor TR2 is simply obtained by the collector current of the PNP transistor TR1. Is turned on, and the potential at which leakage begins becomes unstable. Therefore, an inconvenience arises as an electrostatic breakdown protection operation that is desired to be turned on when a certain voltage or more is applied.
[0017]
When a surge voltage lower than the ground potential GND is applied to the other pad 32b, a protection diode 6 (not shown) formed of an independent island near or directly below the pad 32b is turned on to protect the internal circuit. This operation is the same as that in FIG.
When a surge voltage higher than the power supply potential VCC is applied to the other pad 32b, as shown in FIG. 3, the PN diode 35 having the P-type diffusion region 28 at the other end as the anode and the island 27 as the cathode is turned on. Then, a base current is supplied to the PNP transistor TR1 to turn on the thyristor element SCR. After the turn-on, a current is supplied through the resistance component 36 of the P-type diffusion region 28. Further, when the other pad 32b is short-circuited to one pad 32a of the adjacent resistance element, the protection operation by the operation of FIG.
[0018]
FIG. 4 shows a second embodiment of the present invention. The same parts are denoted by the same reference numerals and description thereof is omitted. The difference lies in that a P + type region 37 having a diffusion depth deeper than that of the P type diffusion regions 28 and 30 is formed in the portion that becomes the emitter / collector of the PNP transistor TR1.
The P-type diffusion region 28 is preferably a relatively shallow diffusion region in order to obtain a highly accurate resistance element. On the other hand, in order to secure a current capacity when the thyristor element SCR is turned on, it is preferable that the opposing area of the P-type diffusion region 28 and the P-type diffusion region 30 is large.
The N + channel stopper region 29 between the P-type diffusion region 28 and the P-type diffusion region 30 also has the meaning of preventing the PNP transistor TR1 from turning on in a steady state and generating a leakage current. This means that the current amplification factor of the PNP transistor TR1 is lowered at the same time and the turn-on current of the thyristor element SCR is suppressed.
[0019]
Therefore, in the present embodiment, as shown in the drawing, a P + type diffusion region 35 deeper than the N + channel stopper region 29 (deeper than the emitter diffusion) is provided in the contact portion with the electrode, and by increasing the facing area in the depth direction, The current capacity of the thyristor element SCR is ensured. Since the portion formed at the same time is a portion in contact with the electrode wiring 33a, the arrangement of the deep diffusion region also has an effect of preventing the breakdown voltage deterioration due to the aluminum spike of the aluminum electrode.
[0020]
Thus, in the structure of the present invention, since the thyristor element SCR is formed in the same island 27 as the resistance element 24, it is possible to achieve both prevention of fluctuations in the resistance value of the resistance element 24 and protection of electrostatic breakdown. It is possible to do. In addition, since the electrostatic breakdown protection elements are formed on the same island 27, the chip size can be reduced as compared with the case where they are formed on individual islands. Furthermore, even if applied to one of the pads 32a and the other pad 32b, one thyristor element SCR can cope with it, so that there is a further effect of reducing the chip size.
[0021]
【The invention's effect】
As described above, according to the present invention, there is an advantage that the electrostatic breakdown protection element can be incorporated without increasing the variation factor of the resistance value of the resistance element 24. In addition, since the electrostatic breakdown protection element can be formed in the same island as the resistance element 24, there is an advantage that the chip size can be reduced.
[0022]
Further, even when both ends of the resistance element 24 are connected to the pad, the single thyristor element SCR can cope with it, so that the chip size can be further reduced.
[Brief description of the drawings]
FIG. 1 is a plan view for explaining a semiconductor integrated circuit device of the present invention.
2A is an enlarged plan view of a main part of FIG. 1, and FIG. 2B is a cross-sectional view thereof.
FIG. 3 is an enlarged cross-sectional view of a main part of FIG.
FIG. 4 is a cross-sectional view for explaining a second embodiment of the present invention.
FIG. 5 is a circuit diagram for explaining a conventional example.
FIG. 6 is a cross-sectional view for explaining a conventional example.

Claims (5)

An N- type epitaxial layer formed on a P- type semiconductor substrate;
A P- type isolation region that penetrates the epitaxial layer to form a plurality of islands;
A P- type resistance region formed on the surface of the island;
Means for applying a potential at one end of the resistance region to the island ;
An N- type channel stopper region formed on the surface of the island so as to surround the periphery of the resistance region;
Means for connecting the other end of the resistance region to an external connection terminal ;
A P- type diffusion region formed on the surface of the island apart from the resistance region;
An N type diffusion region formed on the surface of the P type diffusion region;
An electrode wiring provided on the N-type diffusion region;
Anda extending portion of the front Symbol P type you overlap the separation region is extended from the P-type diffusion region, said one end said a higher potential than the other end of the resistor region A semiconductor integrated circuit , wherein the island is biased by a potential of a portion and a ground potential is applied to the N-type diffusion region . 2. The semiconductor integrated circuit according to claim 1, wherein an N- type channel stopper region surrounds the resistance region.   2. The semiconductor integrated circuit according to claim 1, wherein a field electrode is provided on an island between the resistance region and the channel stopper region, and a potential on the high potential side of the resistance region is applied to the field electrode.   2. The semiconductor integrated circuit according to claim 1, wherein a plurality of islands in which the resistance region is formed are provided side by side. 5. The semiconductor integrated circuit according to claim 4 , wherein the island in which the resistance region is formed is arranged in a concentrated manner at the center of the semiconductor chip.

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