JP3732046B2 - Crystal oscillator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a crystal oscillator in an industrial technical field, and more particularly to a crystal oscillator that prevents malfunction of a device due to self-excited oscillation (parasitic oscillation) of a buffer amplifier at the time of startup.
[0002]
[Prior art]
BACKGROUND OF THE INVENTION Crystal oscillators are widely used in various electronic devices including communication devices as a frequency and time reference source. For example, in a mobile phone, it is used as a local oscillator that obtains an intermediate frequency. In recent years, not only an intermediate frequency is obtained but also used as a synchronization signal.
[0003]
(Example of Prior Art) FIG. 5 is a circuit diagram of a crystal oscillator for explaining a conventional example.
The crystal oscillator includes an oscillation circuit 1 and a buffer amplifier 2. The oscillation circuit 1 includes a Colpitts oscillation circuit 1 (not shown) having a crystal resonator 3 as an L component. The buffer amplifier 2 is composed of a complementary connection MOS-FET 4 (referred to as a CMOS inverter) (ab), which is a two-stage coupling, both of which are inverter type. In the first stage, a feedback resistor 5 is provided to set an operating voltage. Further, a coupling capacitor 6 is provided between the oscillation circuit 1 and the buffer amplifier 2 so as to be connected at a high frequency. These are integrated (IC) integrally on a silicon substrate (not shown) except for the crystal unit 3. Reference numeral 16 denotes a coupling capacitor with an external circuit.
[0004]
[Problems to be solved by the invention]
(Problems of the prior art) However, in the crystal oscillator configured as described above, since the oscillation circuit 1 uses the crystal resonator 3, the rise is relatively slow until the oscillation frequency (steady output) is reached after the power is turned on. (About 1.5-2.2msec). Therefore, when the power is turned on, there is a problem that the buffer amplifier 2 operates first and causes self-excited oscillation. In this case, there is a risk of adversely affecting other circuits such as a synchronous circuit.
[0005]
When the oscillation output is equal to or higher than the reference level (approximately 10% or more of the normal output), the operation of the buffer amplifier 2 is stabilized and no self-excited oscillation occurs.
[0006]
(Object of the Invention) An object of the present invention is to provide a crystal oscillator that suppresses self-excited oscillation at the time of rising of a buffer amplifier and obtains a stable oscillation frequency immediately after startup.
[0007]
[Means for Solving the Problems]
The present invention relates to a crystal oscillation circuit which is driven by the same power source in which a buffer amplifier is connected to the oscillation circuit and both of which have a voltage of 0 to 1, and the rising of the buffer amplifier is set at the input stage of the buffer amplifier. delaying the rise of the oscillation circuit, comprising a start delay circuit comprising a pulse generating circuit and voltage drop below circuit, said pulse generating circuit includes a capacitor charged when the power is turned on and connected to the power source, of the capacitor The first FET that generates the power supply voltage only during a charging time, the voltage drop circuit includes a second FET connected to the first FET, and the second FET is a buffer amplifier according to the power supply voltage from the first FET. The operating voltage of the input stage is shifted from a reference value that is ½ of the power supply voltage, and the output voltage of the buffer amplifier is set to the 0 or 1 level. A structure stopping the amplification function of the power-on as.
[0008]
[Action]
In the present invention, the operation at the time of rising of the buffer amplifier is delayed. Therefore, during that period, the oscillation output becomes equal to or higher than the reference level at which the buffer amplifier operates normally. Therefore, since the oscillation output exceeding the reference level is input during the delay operation of the buffer amplifier, the self-excited oscillation at the rising time and thereafter is suppressed. It will be described in detail with the action by one embodiment of the present invention.
[0009]
【Example】
1 and 2 are diagrams for explaining one embodiment of the present invention. FIG. 1 is a circuit diagram of a crystal oscillator and FIG. 2 is a time chart. In addition, the same number is attached | subjected to the same part as a prior art example figure, and the description is abbreviate | omitted or abbreviate | omitted.
As described above, the crystal oscillator includes a buffer amplifier 2 composed of a two-stage coupled CMOS inverter 4 (ab) connected to the Colpitts oscillation circuit 1 having the crystal resonator 3 as an L component by a coupling capacitor 6 at a high frequency. Provided and configured. These are integrated.
[0010]
In this embodiment, a startup delay circuit 7 is provided at the input stage of the buffer amplifier 2. The startup delay circuit 7 includes a pulse generation circuit 8 and a voltage drop circuit 9. The pulse generation circuit 8 connects a constant current source 10 and a grounded capacitor 11 connected in series to a power source Vcc. The middle point of the constant current source 10 and the capacitor 11 is connected to the gate of the first FET 12 whose drain and source are connected between the power source Vcc and the ground. A load resistor 13 is provided on the drain side.
[0011]
The voltage drop circuit 9 connects the output (drain) of the pulse generation circuit 8 to the gate of the second FET 14 whose drain and source are connected between the input stage of the buffer amplifier 2 and the ground. A high frequency blocking resistor 15 is provided on the drain side of the second FET 14.
[0012]
In such a case, when the power source Vcc is turned on, the capacitor 11 of the pulse generation circuit 8 is first charged as shown in FIG. 2 (a). When the potential of the capacitor 11 exceeds the forward voltage drop (threshold voltage) of the first FET 12, the gate of the first FET 12 opens and a drain current is generated. Therefore, the power supply voltage (suppressed pulse P) is generated at the drain output only during the charging time of the capacitor 11 (FIG. 2B).
[0013]
When the suppression pulse P is applied to the gate of the second FET 14 of the voltage drop circuit 9, the second FET 14 operates to generate a drain current from the input stage of the buffer amplifier 2. Therefore, the voltage of the input stage (FET gate) of the buffer amplifier 2 drops, and the operating voltage shifts from the reference value (usually 1/2 of the power supply voltage) Vs to the lower Vs ′. (FIG. 3) That is, the operating point is shifted from the linear region (inclined amplification region) to the non-amplification region (flat portion, 1 level, HIGH level). FIG. 3 is an input (Vi) -output (Vo) characteristic diagram of the CMOS inverter.
[0014]
For this reason, the buffer amplifier 2 does not operate (does not have an amplification function) while the suppression pulse P (about 1 msec) is applied after the power is turned on. Therefore, self-excited oscillation due to noise after power on does not occur. On the other hand, the oscillation circuit 1 operates when the power is turned on, and the oscillation output becomes equal to or higher than the reference level during the application of the suppression pulse P to the buffer amplifier 2 (FIG. 2 (c)). The reference level is, for example, 10% or more of the normal time when the buffer amplifier 2 operates normally.
[0015]
Further, after the suppression pulse P disappears, a normal operating voltage is applied to the buffer amplifier 2. Then, the buffer amplifier 2 receives an oscillation output (frequency) that has reached the reference level or higher, and amplifies it (FIG. 2 (d)). Note that the self-excited oscillation does not occur in the buffer amplifier 2 due to the input of the oscillation output reaching the stable region. Further, since the oscillation circuit 1 and the voltage drop circuit 9 are cut off at a high frequency by the high frequency blocking resistor 15, the level of the oscillation output is prevented from being lowered.
[0016]
For this reason, when the power is turned on, there is no high-frequency output from the buffer amplifier 2 by the start delay circuit 7 (suppression pulse P), and a stable oscillation amplification output can be obtained as the suppression pulse P disappears. Therefore, during the application of the suppression pulse P, there is no output due to the self-excited oscillation of the buffer amplifier 2, and this prevents the influence on other circuits such as a synchronous circuit. Then, the start-up is delayed and a stable oscillation output can be obtained from the beginning of the delay.
[0017]
[Other matters]
In the above embodiment, the operating voltage of the buffer amplifier 2 (4a) is shifted from the reference value Vs to Vs ′ below by the suppression pulse P and set to 1 level (HIGH level). It is the same even if it moves to Vs ″ upward and is set to 0 level (LOW level).
[0018]
In this case, for example, as shown in FIG. 4, the drive delay circuit 7 is composed of the pulse generator 8 and the voltage raising circuit 19 described above. The voltage raising circuit 19 includes a third FET 17 and a fourth FET 18 and performs a switching operation by the suppression pulse P from the pulse generator 8 to set the operating voltage of the buffer amplifier 2 to Vs ″ (0 level) higher than the reference value Vs. . Reference numeral 20 denotes a load resistance.
[0019]
Further, the drive delay circuit 7 is formed of the pulse generation circuit 8 and the voltage drop circuit 9 or the voltage rise circuit 19. However, the drive delay circuit 7 is not limited to this. What is necessary is just to be in the state of 0.
[0020]
The buffer amplifier 2 is not limited to a CMOS inverter but may be an amplifier such as a MOSFET or a bipolar transistor.
[0021]
【The invention's effect】
The present invention relates to a crystal oscillation circuit which is driven by the same power source in which a buffer amplifier is connected to the oscillation circuit and both of which have a voltage of 0 to 1, and the rising of the buffer amplifier is set at the input stage of the buffer amplifier. An activation delay circuit comprising a pulse generation circuit and a voltage drop circuit that delays the rise of the oscillation circuit; the pulse generation circuit being connected to the power supply and charged when the power is turned on; and charging of the capacitor The first FET for generating the power supply voltage only for a time, the voltage drop circuit comprises a second FET connected to the first FET, and the second FET is input to the buffer amplification register by the power supply voltage from the first FET. The operating voltage of the stage is shifted from a reference value that is ½ of the power supply voltage, and the output voltage of the buffer amplifier is set to the 0 or 1 level. Since the amplification function of the power-on it is stopped as can provide a crystal oscillator to obtain a stable oscillation frequency immediately after starting.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a crystal oscillator for explaining an embodiment of the present invention.
FIG. 2 is a time chart illustrating the operation and effect of an embodiment of the present invention.
FIG. 3 is an input-output characteristic diagram of a CMOS inverter for explaining the operation and effect of one embodiment of the present invention.
FIG. 4 is a circuit diagram of a crystal oscillator for explaining another embodiment of the present invention.
FIG. 5 is a circuit diagram of a crystal oscillator for explaining a conventional example.
[Explanation of symbols]
1 oscillator circuit, 2 buffer amplifier, 3 crystal oscillator, 4 CMOS inverter, 5 feedback resistor, 6, 16 coupling capacitor, 7 delay drive circuit, 8 pulse generator, 9 voltage drop circuit, 10 constant current source, 11 capacitor, 12, 14, 17, 18 FET, 13, 20 Load resistance, 15 High frequency blocking resistance, 19 Voltage rise circuit.

Claims (1)

In a crystal oscillation circuit that is driven by the same power source in which a buffer amplifier is connected to the oscillation circuit and both are at a voltage of 0 to 1 level ,
Wherein the input stage of the buffer amplifier, the rise of the buffer amplifier Ru delayed than the rise of the oscillation circuit, comprising a start delay circuit comprising a pulse generating circuit and a voltage drop circuit,
The pulse generation circuit comprises a capacitor connected to the power supply and charged when the power is turned on, and a first FET that generates the power supply voltage only during the charging time of the capacitor,
The voltage drop circuit is composed of a second FET connected to the first FET, and the second FET makes the operating voltage of the input stage of the buffer amplifier a half of the power supply voltage by the power supply voltage from the first FET. A crystal oscillation circuit characterized in that it is shifted from a reference value, and the amplification function at power-on is stopped by setting the output voltage of the buffer amplifier to the 0 or 1 level .

Images