JP3716523B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having fine contacts.
[0002]
[Prior art]
As seen in recent VLSI and the like, with the progress of higher integration and higher performance of semiconductor devices, fine processing of semiconductor devices has become an indispensable condition. In order to finely process a semiconductor device, for example, the gate width of a gate electrode of a transistor or the area occupied by a capacitor in a DRAM or the like is reduced, while the wiring portion is required to be finely processed as well.
[0003]
Among them, self-alignment contact technology that can eliminate the design margin on the mask for alignment of the contact hole process has attracted attention, and has been activated especially in generations after the 0.25 μm rule. To put it to practical use, it must be said that there are still many problems, such as the need to clear a highly difficult etching technique that stops etching on thin Si ₃ N ₄ . Therefore, a conventionally known method has been attempted in which a layer serving as a mask for opening a contact hole is formed on the inner wall of the contact hole in the shape of a sidewall and the diameter of the contact hole is narrowed. .
[0004]
Hereinafter, a method of narrowing and opening the contact hole will be described with reference to the drawings.
[0005]
FIG. 4G is a cross-sectional view of the semiconductor device manufactured by the above manufacturing method. A semiconductor element such as a transistor or a diffusion layer (not shown) is provided on the semiconductor substrate 10, and the insulating film 20 covers the upper layer of the semiconductor substrate 10. A contact hole reaching the semiconductor substrate 10 is opened in the insulating film 20, and a buried wiring layer 33 including a sidewall-like second conductive layer 31 a and a third conductive layer 32 is embedded in the contact hole.
[0006]
Below, the manufacturing method of said semiconductor device is demonstrated. First, as shown in FIG. 3A, after forming semiconductor elements such as transistors and diffusion layers (not shown) on the silicon semiconductor substrate 10, these elements are covered and, for example, silicon oxide is formed by a method such as atmospheric pressure CVD. Then, the insulating film 20 is formed by planarizing by reflow or etch back. On the upper layer, for example, polysilicon is deposited to a thickness of 300 nm by a low pressure CVD method to form the first conductive layer 30. A resist film R is patterned on the first conductive layer to have a diameter of, for example, 0.32 μm.
[0007]
Next, as shown in FIG. 3B, etching such as RIE (reactive ion etching) is performed using the resist R as a mask to penetrate the first conductive layer 30 and open above the insulating film 20. The first contact hole CH1 is opened.
[0008]
Next, as shown in FIG. 3C, for example, polysilicon is deposited over the entire surface of the first conductive layer 30 and the first contact hole CH1 by a low pressure CVD method to deposit 100 nm, and the second conductive layer 31 is formed. Form.
[0009]
Next, as shown in FIG. 3D, etching such as RIE is performed, the second conductive layer 31 is etched so as to leave the side wall portion of the first contact hole, and the side wall-like second conductive layer 31a. Form.
[0010]
Next, as shown in FIG. 4E, a second contact hole CH2 that penetrates the insulating film 20 and exposes the semiconductor substrate 10 is opened by, for example, an ECR type plasma etching apparatus. At this time, the opening diameter of the second contact hole CH2 is, for example, about 0.1 μm, and a fine contact hole can be formed by narrowing the diameter of the etching mask by forming the sidewall-like second conductive layer 31a.
[0011]
Next, as shown in FIG. 4F, for example, polysilicon is embedded in the second contact hole CH2 by a low pressure CVD method, and the first conductive layer 30 and the sidewall-like second conductive layer 31a are covered. The third conductive layer 32 is formed by depositing 300 nm.
[0012]
Next, as shown in FIG. 4G, the entire surface is etched back by etching such as RIE, for example, and the conductive layer outside the contact hole is removed to form a sidewall-like first in the second contact hole CH2. A buried wiring layer 33 composed of the second conductive layer 31 a and the third conductive layer 32 is formed. In the above process, the polysilicon used for the first conductive layer 30, the second conductive layer 31, and the third conductive layer 32 is provided with conductivity by containing, for example, an n-type impurity.
[0013]
According to the above method, unlike the above-described self-aligned contact, a new process such as a high selectivity ratio with respect to Si ₃ N ₄ is unnecessary, and the conventional approach of carefully clearing the microloading effect is applied. As a result, it is possible to achieve contact holes with a very fine and high aspect ratio of about 0.1 μmφ.
[0014]
[Problems to be solved by the invention]
However, when forming the buried wiring layer of the contact hole using this technique, as shown in FIG. 4G, the plug loss becomes large in the etch back of the buried wiring layer 33, so that the upper layer is flattened or the stack contact is formed. There is a problem of adversely affecting the formation of the wiring and greatly reducing the reliability of the wiring. If the over-etching amount is reduced to suppress this plug loss, there is a problem that the conductive layer material that causes a short circuit is left in the portion other than the contact hole opening due to the etching uniformity problem. .
[0015]
As an etching method, there is a method of confirming the end point of etching by observing the emission of plasma, but in the case of etch back of the buried wiring layer, the effect of suppressing plug loss is hardly obtained, and The problem remains unsolved.
[0016]
The present invention has been made in view of the above-mentioned problems. Therefore, the object of the present invention is to form a sidewall on the inner wall of the contact hole and to narrow the diameter of the contact hole to form a buried wiring layer. And a method of manufacturing a semiconductor device having a buried wiring layer in which plug loss is suppressed and a conductive layer material that causes a short circuit is not left in a portion other than a contact hole opening portion. It is.
[0017]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a semiconductor substrate, a step of forming a first conductive layer on the insulating film, and the first conductive layer. And a step of opening the first contact hole, and an inner wall of the first contact hole made of the same semiconductor as the first conductive layer, containing conductive impurities having a concentration different from that of the first conductive layer, Forming a sidewall-like second conductive layer whose etching rate in the etching process is slower than that of the first conductive layer; and forming a second contact hole in the insulating film using the second conductive layer as a mask And the first conductive layer, the upper layer of the second conductive layer, and the second contact hole are made of the same semiconductor as the first conductive layer and contain conductive impurities having a concentration different from that of the first conductive layer. to etch Forming a third conductive layer having an etching rate slower than that of the first conductive layer, etching the first conductive layer, the second conductive layer, and the third conductive layer to form the first contact hole. And a step of etching away the conductive layer outside the second contact hole.
[0018]
In the semiconductor device manufacturing method, the first conductive layer outside the contact hole has a higher etching rate than the second conductive layer and the third conductive layer in which the contact hole is buried. When etching back to remove the contact hole, the upper region of the contact hole has only the second conductive layer and the third conductive layer, so that the etching rate is slow, and still remains even when the region outside the contact hole is etched away first. ing. Therefore, even if the over-etching is sufficiently performed so as not to leave a conductive layer material that causes a short circuit in a portion other than the contact hole opening portion, the plug loss is not deteriorated.
[0019]
In addition, it is possible to perform over-etching when the second conductive layer is formed into a sidewall shape. As a result, the second conductive layer has a slower etching rate than the first conductive layer, so The tip portion of the second conductive layer can be protruded higher than the surface of the first conductive layer, and in the subsequent step of depositing the third conductive layer, it is deposited in a shape protruding convexly in the region above the contact hole. It becomes possible. Since the film thickness of the upper region of the contact hole is thick, the subsequent etching is performed so that the upper portion of the contact hole remains, and plug loss can be further suppressed.
[0020]
Preferably, in the method for manufacturing a semiconductor device, after the second conductive layer is formed in a sidewall shape, the end portion of the second conductive layer in the sidewall shape is formed over the surface of the first conductive layer by overetching. Protrude high. As a result, in the step of depositing the third conductive layer, it is possible to deposit in a shape protruding convexly in the region above the contact hole, and plug loss can be suppressed.
[0021]
The method of manufacturing a semiconductor device, preferably, contain an n-type impurity concentration lower than the previous SL first conductive layer on the second conductive layer and the third conductive layer, or the first conductive layer A higher concentration of p-type impurities is contained in the second conductive layer and the third conductive layer.
[0022]
Introducing impurities into a semiconductor such as polysilicon to impart conductivity and using it as a conductor for wiring is generally performed, but by changing the concentration of impurities in the conductor at that time, The etching rate can also be changed. For example, when an n-type impurity (for example, P) is introduced into polysilicon, the etching rate increases as the concentration in the polysilicon increases. Conversely, when p-type impurities (for example, BF ₂ ) are introduced into polysilicon, the higher the concentration in the polysilicon, the slower the etching rate.
[0023]
In the method for manufacturing a semiconductor device, preferably, the second conductive layer and the third conductive layer are formed of a material having the same etching rate, and more preferably, the second conductive layer The third conductive layer contains conductive impurities having the same concentration. By using the materials having the same etching rate for the second conductive layer and the third conductive layer, the center portion of the buried wiring layer may be removed during the etch-back process for forming the buried wiring layer in the contact hole, It becomes possible to prevent the part from falling off. In order to obtain the same etching rate, it can be realized by containing conductive impurities having the same concentration.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 2G shows a cross-sectional view of the semiconductor device manufactured by the semiconductor device manufacturing method of this embodiment. A semiconductor element such as a transistor or a diffusion layer (not shown) is provided on the semiconductor substrate 10, and the insulating film 20 covers the upper layer of the semiconductor substrate 10. A contact hole reaching the semiconductor substrate 10 is opened in the insulating film 20, and a buried wiring layer 33 including a sidewall-like second conductive layer 31 a and a third conductive layer 32 is embedded in the contact hole.
[0025]
In such a semiconductor device, the plug loss of the buried wiring layer formed in the contact hole is suppressed, and the conductive layer material is not left in the portion other than the opening portion of the contact hole, and the fine contact that ensures the reliability of the wiring. A semiconductor device having a hole.
[0026]
A method for manufacturing the semiconductor device according to the present embodiment will be described below. First, as shown in FIG. 1A, after forming semiconductor elements such as transistors and diffusion layers (not shown) on a silicon semiconductor substrate 10, these elements are covered and, for example, silicon oxide is applied by atmospheric pressure CVD or the like. The insulating film 20 was formed by planarizing by reflow or etch back. On the upper layer, for example, polysilicon is deposited to a thickness of 300 nm by a low pressure CVD method to form the first conductive layer 30. Here, as the polysilicon for the first conductive layer 30, an n-type impurity was contained to impart conductivity. A resist film R was patterned on the first conductive layer to have a diameter of, for example, 0.32 μm.
[0027]
Next, as shown in FIG. 1B, etching such as RIE (reactive ion etching) is performed using the resist R as a mask to penetrate the first conductive layer 30 and open above the insulating film 20. A first contact hole CH1 was opened.
[0028]
Next, as shown in FIG. 1C, for example, polysilicon is deposited over the entire surface of the first conductive layer 30 and the first contact hole CH1 by a low pressure CVD method to deposit 100 nm, and the second conductive layer 31 is formed. Formed. Here, as the polysilicon for the second conductive layer 31, the n-type impurity concentration was set lower than that of the polysilicon of the first conductive layer 30. Thereby, the etching rate of the second conductive layer 31 can be made smaller than that of the first conductive layer 30.
[0029]
Next, as shown in FIG. 1D, etching such as RIE is performed, and the conductive layer 30 and the second conductive layer 31 are first etched to leave the side wall portion of the first contact hole. A second conductive layer 31a having a shape was formed. At this time, since the first conductive layer 30 has an etching rate larger than that of the second conductive layer 31, the first conductive layer 30 is formed by performing over-etching after the second conductive layer 31 is formed into a sidewall shape. As a result, the surface of the second conductive layer 31a having a sidewall shape protruded into a protruding shape.
[0030]
Next, as shown in FIG. 2E, a second contact hole CH2 that penetrates the insulating film 20 and exposes the semiconductor substrate 10 is opened by, for example, an ECR type plasma etching apparatus. At this time, the opening diameter of the second contact hole CH2 was about 0.1 μm, and a fine contact hole could be formed by narrowing the diameter of the etching mask by forming the sidewall-like second conductive layer 31a.
[0031]
Next, as shown in FIG. 2F, for example, polysilicon is filled in the second contact hole CH2 by a low pressure CVD method, and the first conductive layer 30 and the sidewall-like second conductive layer 31a are covered. The third conductive layer 32 was formed by depositing 300 nm. At this time, since the tip end portion of the sidewall-like second conductive layer 31a protrudes higher than the surface of the first conductive layer 30, the third conductive layer 32 protrudes in the region above the contact hole. Deposited in a protruding shape. Here, as the polysilicon for the third conductive layer 32, the same polysilicon as the polysilicon of the second conductive layer 31 in which the n-type impurity concentration is set lower than that of the polysilicon of the first conductive layer 30 is used. Thereby, the etching rate of the third conductive layer 32 can be made smaller than that of the first conductive layer 30.
[0032]
Next, as shown in FIG. 2G, the entire surface is etched back by etching such as RIE, for example, and the conductive layer outside the contact hole is removed to form a sidewall-shaped first in the second contact hole CH2. An embedded wiring layer 33 composed of the second conductive layer 31a and the third conductive layer 32 was formed. Here, the first conductive layer 30 has a convex shape in which the etching rate is higher than that of the second conductive layer 31a and the third conductive layer 32 in a sidewall shape, and the film thickness is increased above the contact hole. The first conductive layer 30 other than the contact hole opening is completely removed by etching, and even if the overetching is sufficiently performed so that there remains no etching residue of the conductive layer material causing a short circuit, the contact hole opening Etching is performed so that the upper part of the part remains, and plug loss is suppressed. In addition, due to etching characteristics such as RIE, the shoulder portion of the third conductive layer 32 protruding above the contact hole and the protruding tip portion of the sidewall-like second conductive layer 31a are easily etched. The formed buried wiring layer 33 has suppressed plug loss.
[0033]
As described above, as shown in FIG. 2G, plug loss is suppressed, and a conductive layer material is not left in a portion other than the contact hole opening portion, and a fine contact hole that ensures wiring reliability is formed. We were able to.
[0034]
The present invention can be applied to any semiconductor device having a contact hole, such as a MOS transistor semiconductor device, a bipolar semiconductor device, or an A / D converter. It is possible to provide bonding with a fine and highly reliable contact to a semiconductor device whose device has been miniaturized and reduced.
[0035]
The present invention is not limited to the above embodiment. For example, in the step of opening the first contact hole, the first conductive layer 30 is penetrated and etched to the upper side of the insulating film 20 to provide the opening portion. May be stopped when the surface of the insulating film 20 is exposed by penetrating the first conductive layer 30, or may be stopped before penetrating the first conductive layer 30. The impurity contained in the conductive layer may be p-type instead of n-type. However, in that case, the etching rate is lower when the p-type impurity concentration is higher. The first to third conductive layers may each have a multilayer structure. In addition, various changes can be made without departing from the scope of the present invention.
[0036]
【The invention's effect】
According to the present invention, a plug loss is suppressed by using a method of forming a buried wiring layer by forming a sidewall on the inner wall of a contact hole and opening the contact hole with a reduced diameter, and other than the contact hole opening portion. A semiconductor device having a buried wiring layer in which no conductive layer material that causes a short circuit is left in this portion can be manufactured.
[Brief description of the drawings]
FIGS. 1A and 1B are cross-sectional views showing a manufacturing process of a method for manufacturing a semiconductor device according to the present invention, wherein (a) up to a resist film forming process, (b) up to a first contact hole opening process; ) Shows the process up to the formation of the second conductive layer, and (d) shows the process up to the process of forming the sidewall-like second conductive layer.
FIGS. 2A and 2B show a process continued from FIG. 1, wherein FIG. 2E shows a process for forming a second contact hole, FIG. 2F shows a process for forming a third conductive layer, and FIG. The etching process is shown.
FIGS. 3A and 3B are cross-sectional views showing a manufacturing process of a conventional method for manufacturing a semiconductor device, where FIG. 3A shows a process up to a resist film formation process, and FIG. 3B shows a process up to the opening process of a first contact hole; ) Shows the process up to the formation of the second conductive layer, and (d) shows the process up to the process of forming the sidewall-like second conductive layer.
4 shows a process following FIG. 3, in which (e) shows the process until the second contact hole is formed, (f) shows the process until the formation of the third conductive layer, and (g) shows the embedded wiring layer. The etching process is shown.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 20 ... Insulating film, 30 ... 1st conductive layer, 31, 31a ... 2nd conductive layer, 32 ... 3rd conductive layer, 33 ... Embedded wiring layer, R ... Resist, CH1, CH2 ... Contact hole

Claims (6)

Forming an insulating film on the semiconductor substrate;
Forming a first conductive layer on the insulating film;
Opening a first contact hole in the first conductive layer;
The inner wall of the first contact hole is made of the same semiconductor as the first conductive layer, contains conductive impurities having a concentration different from that of the first conductive layer, and the etching rate in the etching process is higher than that of the first conductive layer. Forming a second sidewall-like second conductive layer,
Opening a second contact hole in the insulating film using the second conductive layer as a mask;
The upper layer of the first conductive layer and the second conductive layer and the second contact hole are made of the same semiconductor as the first conductive layer and contain conductive impurities having a concentration different from that of the first conductive layer. A step of forming a third conductive layer whose etching rate in the etching step is slower than that of the first conductive layer;
Etching the first conductive layer, the second conductive layer, and the third conductive layer to etch away the first contact hole and the conductive layer outside the second contact hole. . The method for manufacturing a semiconductor device according to claim 1, wherein after the second conductive layer is formed in a sidewall shape, the tip of the second conductive layer in the sidewall shape is protruded higher than the surface of the first conductive layer by overetching. . The process according to claim 1, the semiconductor device according to contain the first lower concentration than the conductive layer n-type impurity into the second conductive layer and the third conductive layer. The process according to claim 1, the semiconductor device according to contain the high concentration p-type impurity than the first conductive layer on the second conductive layer and the third conductive layer. The method according to claim 1, wherein forming the third conductive layer and the second conductive layer of a material having an etching rate of the same speed. The second conductive layer and the third conductive layer contain conductive impurities having the same concentration.
A method for manufacturing a semiconductor device according to claim 1.

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