JP3709034B2 - Boundary scan compatible integrated circuit design support device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a design support apparatus for a boundary scan compatible integrated circuit.
[0002]
[Prior art]
Conventionally, PCB (Printed Circuit Board) inspection has been mainly performed by an in-circuit test method. In the inspection by the in-circuit test method, a test pad for contacting a probe pin for a tester is provided on each signal line formed on a PCB (hereinafter simply referred to as “board”), and probing directly from the tester. The input value of each IC (integrated circuit) mounted on the board is controlled and the output value is observed.
[0003]
However, recently, the mounting density of components on the board has increased and the number of pins of each component package has increased, and as a result, probing in the in-circuit test method has become very difficult. Therefore, as a test method that replaces the in-circuit test method, a “board test method using a boundary scan” has been proposed by a JTAG (Joint Test Action Groupe) composed of LSI (large scale integrated circuit) vendors. (Institute of Electrical and Electronics Engineers), standardized as IEEE1149.1.
[0004]
In the board test method using boundary scan, a scan chain consisting of boundary scan registers (called “boundary scan chain”) is incorporated in each IC on the board so that the boundary scan chain can be shifted from the outside of the IC. To. The boundary scan register in the IC can load a signal value to be received from the input pad, or can directly set the value held in the boundary scan register to the output pad. According to such a configuration, the boundary scan register incorporated in the IC functions as a test pad in the above in-circuit test method. Therefore, according to the board test method based on the boundary scan, it is possible to carry out a failure inspection such as a short circuit or an open signal line on the board without physically contacting the probe pins.
[0005]
The contents of the boundary scan chain (hereinafter referred to as “BS chain”) incorporated in each IC on the board are controlled and observed from the tester via a test access port (hereinafter referred to as “TAP”) during the board test. A test pattern for testing the board under test using such a mechanism is generated by a board test ATPG (Automatic Test Pattern Generator). When generating a test pattern by this board test ATPG, a BSDL (Boundary Scan Description Language) file is required for each IC. This BSDL file describes the configuration of the BS chain of the boundary scan register in the IC, and serves as a substitute for the internal model of the IC when generating a test pattern by the board test ATPG. Specifically, information on device pins of IC packages, that is, external terminals (input and output types, port names and pin number correspondences, etc.), executable board scan instruction names and instruction codes, and The connection order of the boundary scan registers and the port names of the device pins controlled and observed by each boundary scan register are described. Such a BSDL file is created and provided by an IC manufacturer.
[0006]
[Problems to be solved by the invention]
However, at present, the BSDL file is mostly created manually, so the reliability of the provided BSDL file is low, the description of the connection order of the boundary scan registers is incorrect, and it corresponds to each boundary scan register There are many simple mistakes such as a description of the port name of the device pin to be wrong. For this reason, the board tester engineer spends a lot of time correcting errors in the description in the BSDL. On the other hand, some CAD (Computer Aided Design) tools for LSI design have a function of automatically creating a BSDL file by automatically inserting a boundary scan into a design target IC. However, since this BSDL file does not include the device pin information of the IC package, it is necessary to manually modify the BSDL file to use it in the board test ATPG. As a result, the BSDL file There is a risk of errors.
[0007]
In addition, in an IC in which a BS chain is incorporated, the connection order of the BS chain may not match the arrangement of device pins in the IC package, and wiring efficiency in the layout may deteriorate. In this case, the cost of the IC greatly increases due to the incorporation of the BS chain.
[0008]
Therefore, in the present invention, a design of an integrated circuit corresponding to a boundary scan capable of incorporating a BS chain into an IC and automatically creating a BSDL file corresponding to such a BS chain so that the wiring efficiency in the layout does not deteriorate. An object is to provide a support device.
[0009]
[Means for Solving the Problems]
In a first design support apparatus according to the present invention made to solve the above problems, in a design support apparatus for an integrated circuit corresponding to a boundary scan,
First storage means for storing logical connection information indicating a configuration of the integrated circuit as a logic circuit;
Second storage means for storing a test instruction description file describing an instruction name and an instruction code of an instruction of a board test that can be executed by a boundary scan chain incorporated in the integrated circuit;
Third storage means for storing a boundary scan cell information file describing the functions and terminals of each of the boundary scan cells constituting the boundary scan chain;
Fourth storage means for storing package terminal data including information indicating the port name and pin number of each external terminal of the integrated circuit;
The order of the pin numbers in which the connection order of the boundary scan chain is indicated by the package terminal data To correspond to the pin arrangement of each external terminal of the integrated circuit Boundary scan chain optimization means for changing the logical connection information and outputting the changed logical connection information;
The connection relation of the boundary scan chain is examined using the logical connection information after being changed by the boundary scan chain optimization means, and the test instruction description file, the boundary scan cancel information file, and the package terminal data are referred to The information indicating the port name and pin number of the external terminal of the integrated circuit, the information indicating the instruction name and instruction code of the board test instruction executable in the boundary scan chain, and the boundary scan chain are configured. The information indicating the boundary scan chain connection order is extracted together with the port name for the input or output pad at the previous stage or the next stage of the boundary scan and the function name of the boundary scan cancel. And BSDL file creation means, and outputs the extracted information as a file written in BSDL format,
It is set as the structure provided with.
[0010]
In the second design support apparatus according to the present invention, in the first design support apparatus,
The connection order of the boundary scan chain indicated by the logical connection information after being changed by the boundary scan chain optimization means, and the port for the input or output pad of the previous stage or the next stage of each boundary scan cell constituting the boundary scan chain And a test pattern generating means for generating a test pattern for inspecting a boundary scan mechanism in the integrated circuit based on the name.
[0011]
【The invention's effect】
According to the first design support apparatus of the present invention, the boundary scan chain optimizing means causes the boundary scan chain connection order to be the pin number order indicated by the package terminal data. In order to correspond to the pin arrangement of each external terminal of the IC Since the logical connection information of the IC is changed, the wiring efficiency is improved in the layout of the IC in which the boundary scan chain is incorporated. In addition, even when the IC package is changed and the arrangement of the external terminals is changed, the design support apparatus makes it easy to obtain the logical connection information of the IC in which the connection order of the boundary scan chain matches the arrangement of the external terminals. can get. As a result, an increase in cost due to the incorporation of the boundary scan chain into the IC can be suppressed. Furthermore, according to the present design support device, the BSDL file is automatically created by the BSDL file creation means in consideration of the information on the external terminals of the IC. Become. Thereby, the work efficiency in the board test by the boundary scan method is improved.
[0012]
According to the second design support apparatus of the present invention, the test pattern creating means generates a test pattern for inspecting the boundary scan mechanism incorporated in the IC. By using this, the board is assembled. Prior to the inspection, the boundary scan chain can be inspected with the IC alone. Further, when this test pattern is used for logic verification at the IC design stage, it is effective in reducing the cost by avoiding mask revision.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
<1 Overall Configuration of Embodiment>
FIG. 2 is a schematic block diagram showing a hardware configuration of a design support apparatus (hereinafter simply referred to as “design support apparatus”) for a boundary scan compatible IC according to an embodiment of the present invention. The hardware of the design support apparatus is a computer system such as a workstation, and has a configuration in which a processor (CPU) 101, a memory 102, and an input / output controller 103 are connected to a bus. Are connected to a display device 104 such as a CRT display, an external storage device 105 such as a hard disk device, and an input device 106 such as a keyboard and a mouse. When the CPU 101 executes a predetermined program stored in the memory 102, the BSDL file creation function necessary for generating the test pattern by the ATPG for the board test of the boundary scan method and the wiring efficiency in the layout are poor. Functions for supporting the development of the boundary scan compatible IC, such as a function for incorporating the BS chain into the IC, are realized.
[0014]
FIG. 1 is a functional block diagram conceptually showing the configuration of the present design support apparatus. As shown in this figure, this design support apparatus conceptually has logical connection information, a boundary scan information file, package terminal data, and a test instruction indicating the configuration of a logic circuit of an IC for which a BSDL file is created. First to fourth storage units 11 to 14 for storing description files, BS chain optimization unit 22, BSDL file creation unit 24, test pattern creation unit 26, and logical connection of ICs after BS chain optimization It is comprised from the 5th-7th storage parts 31-33 for each storing information (it mentions later for details), a BSDL file, and a test pattern. Among these, the first to seventh storage units 11 to 14, 31 to 33 are realized by the external storage device 105, and the other functional blocks 22, 24, and 26 are realized by predetermined programs stored in the memory 102. .
[0015]
The design support apparatus having the above configuration includes predetermined information about each IC mounted on the board to be tested, that is, logical connection information of the IC stored in each of the first to fourth storage units 11 to 14, and a boundary list. A cancel information file (hereinafter referred to as “BS cell information file”), package terminal data, and a test instruction description file are read, and using these, the logical connection of the IC in which the BS chain connection sequence is optimized Generation of information, creation of a BSDL file, and generation of a test pattern for inspecting a boundary scan mechanism using a BS chain are performed. The contents of the IC logical connection information, BS cell information file, package terminal data, and test instruction description file as input data are as follows.
[0016]
The logical connection information of the IC is connection information indicating the configuration of the IC as a logical circuit mounted on the board, and is obtained as a result of the logical design of the IC. This logical connection information may be described in a hardware description language such as Verilog-HDL or VHDL. The design support apparatus reads the logical connection information of the IC from the first storage unit 11 and creates a database on the memory 102 with a predetermined data structure.
[0017]
The BS cell information file includes i) terminal information such as scan-in that is input of the boundary scan cell (hereinafter referred to as “BS cell”) constituting the BS chain and scan-out that is output of the BS cell, and ii) each BS cell. The BS cell is placed next to the input I / O pad and inputs a signal from the outside, or is placed before the output I / O pad and outputs the signal to the outside. Etc. (hereinafter, a name indicating such a function is referred to as “function name”). This BS cell information file is created by an IC designer using an editor, for example. FIG. 3 shows an example of this BS cell information file. The present design support apparatus reads such a BS cell information file from the second storage unit 12, creates a database on the memory 102, and stores the BS cell information file linked to the logical connection information on the memory 102. FIG. 4 shows an example of a data structure for making the contents of the BS cell information file into a database on the memory 102 in this way. In this example, one structure 201 is prepared for each BS cell constituting the BS chain. Each structure 201 is indicated by a pointer included in data indicating connection information of logic circuits in the IC, and holds information indicating connection relations between BS cells in the BS chain (by this structure). The information held is also a part of the logical connection information. Hereinafter, this structure is referred to as “BS chain information structure”). That is, each BS chain information structure 201 indicates the chain connection order which is a numerical value indicating the connection order of the BS chain, and the BS cell at the next stage, together with the port name and pin number (device pin number) of the external terminal of the IC. Holding a pointer. Also, a structure 202 for holding BS cell information including a BS cell name, a scan-in terminal name, a scan-out terminal name, and a function name is prepared (hereinafter referred to as “BS cell”). Each BS chain information structure 201 also holds a pointer that points to the corresponding BS cell information structure 202. The structures 201 and 202 can be realized by “structures” in C language, for example.
[0018]
The package terminal data is a list of IC external terminal numbers (device pin numbers), port names, and types (input pins or output pins). FIG. 5 shows an example of package terminal data. For example, such package terminal data can be output as a file from a package terminal table editing device for editing a pad layout diagram and a terminal table.
[0019]
The test instruction description file is a list of instruction names and instruction codes of instructions that can be used in the target IC among the board test instructions by the boundary scan method. For example, the IC designer uses an editor to edit the test instruction description file. Created. In this test instruction description file, an instruction standardized as the standard IEEE 1149.1, such as a BYPASS instruction and an EXTEST instruction, can be described. In addition to this, a user-defined instruction can also be described. FIG. 6 shows an example of the test instruction description file.
[0020]
Next, the BS chain optimization unit 22, the BSDL file creation unit 24, and the test pattern creation unit 26, which are functional blocks constituting the design support apparatus, will be described.
The BS chain optimization unit 22 reads the logical connection information of the IC from the first storage unit 11, the BS cell information file from the second storage unit 12, and the package terminal data from the third storage unit 13. Based on the information, in order to optimize the BS chain connection order so that an efficient layout can be made, the IC logical connection information is corrected, and the corrected IC logical connection information is referred to as “BS chain optimized logical connection information. To the fifth storage unit 31.
[0021]
The BSDL file creation unit 24 reads the test instruction description file 14 from the fourth storage unit 14 and the logical connection information after the BS chain optimization obtained by the BS chain optimization unit 22 (this includes BS cell information). And a package terminal data, a BSDL file for the IC is created and output to the sixth storage unit 32.
[0022]
The test pattern creation unit 26 checks the boundary scan mechanism realized by the BS chain incorporated in the IC based on the logical connection information after the BS chain optimization obtained on the memory 102 by the BS chain optimization unit 22. The test pattern is output to the seventh storage unit 33.
[0023]
<Operation of 2 embodiment>
According to the standard IEEE1149.1, the BS chain can be shifted via a TAP (test access port) from outside the IC. The scan-in port name is “TDI” and the scan-out port name. Is defined as “TDO”. The BS cell is basically inserted in the next stage of the input I / O pad and the previous stage of the output I / O pad. These BS cells are connected to each other to form the BS chain. The entrance of this BS chain is the port TDI, and the exit is the port TDO. In this case, the connection order is counted in order from the one close to TDO, and the count value is a numerical value indicating “chain connection order” (see FIG. 4).
[0024]
FIG. 7A shows a configuration example of such a BS chain. In the following, the logical connection information, BS cell information file, package terminal data, and test command description file for the IC in which the BS chain of this configuration is incorporated are stored in advance in the first to fourth storage units 11 to 14, respectively. As an example, the operation of the design support apparatus will be described. According to the standard IEEE1149.1, in addition to the test clock port (TCK) and the mode select port (TMS), a TAP controller, an instruction register, and a BYPASS register are required in the IC. In FIG. Only the TDI, TDO, I / O pad, and BS cell that are the minimum necessary for the description of the embodiment are shown.
[0025]
In this design support apparatus, first, the BS chain optimization unit 22 reads the logical connection information, the BS cell information file, and the package terminal data of the IC corresponding to the example of FIG. 7A as described above. Thereby, the logical connection information of the IC and the BS cell information are linked to form a database on the memory 102. The format of the data structure for creating this database is as shown in FIG. 4, and the data structure shown in FIG. 8 is generated for FIG. 7A. In FIG. 8, P1, P2, and P3 are addresses (pointers) of the BS chain information structure 201. By linking these BS chain information structures 201 in the connection order of the BS chains, a one-way list is obtained. (Hereinafter referred to as “BS chain list”) is formed. P01 and P02 are addresses (pointers) of the BS cell information structure 202 in which information regarding each BS cell constituting the BS chain is held.
[0026]
In the example of FIG. 7A, when the port names of the external terminals of the IC are arranged in the order of connection of the BS cells corresponding to the I / O pads connected to the external terminals, B → C → A. Although it can be considered to indicate the connection order, this connection order is not consistent with the arrangement of the device pins (external terminals) of the IC. However, considering the wiring efficiency in the layout for the IC, it is desirable that the connection order of the BS cells follows the arrangement of the device pins of the package to which the I / O pad is connected.
[0027]
<2.1 BS chain optimization>
Therefore, the BS chain optimizing unit 22 in this design support apparatus changes the BS chain connection order so as to match the arrangement of the device pins of the package, that is, the arrangement of the external terminals of the IC, and the logic of the IC reflecting this change. The connection information is output as a file to the fifth storage unit 31 as logical connection information after BS chain optimization. Hereinafter, the BS chain rearrangement procedure (BS chain connection order change procedure) by the BS chain optimizing unit 22 will be described using the BS chain of FIG. 7A as an example.
[0028]
FIG. 9 is a flowchart showing a BS chain rearrangement procedure by the BS chain optimizing unit 22. As shown in this figure, first, in step S10, the link of the BS chain list formed by linking each BS chain information structure 201 is released. This means that the connection between the scan-in terminal and the scan-out terminal of adjacent BS cells in the BS chain is disconnected.
[0029]
Next, in step S20, a queue is created, and as shown in FIG. 10A, a pointer to each BS chain information structure 201 is stored in the queue. In step S30, a package is created for the pointer stored in the queue. Sorting by device pin number. As a result, the pointers in the queue are arranged in the order of the device pin numbers as shown in FIG. By the way, the device pin number corresponds to the value counted in the arrangement order of the device pins in the package. Therefore, by this sorting, the pointers to the BS chain information structures 201 are stored in the queue in the order corresponding to the arrangement of the device pins in the package. In FIG. 10, “head” indicates the head of the queue, and “tail” indicates the tail of the queue. In addition, alphabets and numerical values in parentheses described below the pointers P1 to P3 are a port name for an I / O pad connected to a BS cell corresponding to the BS chain information structure 201 pointed to by the pointer, and Each device pin number is shown.
[0030]
After performing the sorting as described above, in step S40, one pointer is taken out from the head of the queue, and a null value “as a pointer to the BS cell at the next stage is stored in the BS chain information structure 201 corresponding to the taken out pointer. “NULL” is set. This means that the BS cell corresponding to the pointer taken out from the queue is the first BS cell in the BS chain after the connection order is changed. Accordingly, the scan-out port so of the BS chain is connected to the scan-out terminal so of the leading BS cell. Thereafter, in steps S50 to S80, pointers are taken out one by one from the head of the queue, the pointer (prev) taken out from the queue immediately before is pointed to the BS chain information structure 201 pointed to by the pointer, and the pointer to the BS cell at the next stage. Set as. This means that the scan-out terminal so of the BS cell corresponding to the pointer newly taken out from the queue is connected to the scan-in terminal si of the BS cell corresponding to the pointer taken out from the queue immediately before.
[0031]
In this manner, pointers are extracted one by one from the head of the queue, and the BS chain information structure 201 is linked. When there are no more pointers stored in the queue, the process proceeds to step S90. At this time, the BS cell corresponding to the last pointer taken out from the queue is the last BS cell in the BS chain after the connection order is changed. Accordingly, the scan-in terminal si of the BS cell corresponding to the pointer is connected to the scan-in port TDI of the BS chain.
[0032]
The data structure shown in FIG. 8 is changed to the data structure shown in FIG. 11 by the above processing executed by the BS chain optimizing unit 22. This means that the BS chain having the configuration shown in FIG. 7A has been changed to the configuration shown in FIG. 7B. After executing the BS chain rearrangement procedure as described above, the BS chain optimizing unit 22 obtains the logical connection information (see FIG. 11) corresponding to the configuration of FIG. 7B after the BS chain optimization. The information is output to the fifth storage unit 31 as the logical connection information of the IC. As can be seen from FIG. 7B, since the BS chain connection order after the change corresponds to the arrangement of the device pins of the package, the IC chain based on the logical connection information of the IC after the BS chain optimization Wiring efficiency is improved in the layout.
[0033]
<2.2 Creation of BSDL file>
In the present design support apparatus, the BSDL file creation unit 24 next refers to the data structure of FIG. 11 after the rearrangement of the BS chain, thereby determining the BS chain after changing the connection order (hereinafter referred to as “optimized BS chain”). Scan to check the connection information of the optimized BS chain, and create a BSDL file by referring to the test instruction description file, the BS cell information file and the package terminal data.
[0034]
The BSDL file is composed of three parts. The first part is a list in which device pin numbers and port names of packages are listed, and information necessary for creating this list can be obtained from package terminal data (FIG. 5). The second part is a list in which the instruction names and instruction codes of the board test instructions are listed, and information necessary for creating this list can be obtained from the test instruction description file (FIG. 6). The third part is the function name (“input”, “output”, etc.) of the I / O pad at the previous stage or the next stage of the BS cell in order from the port TDO to the port TDI for each BS cell constituting the BS chain. The list enumerated together with the information necessary for creating this list can be obtained by scanning the BS chain with reference to the data structure of FIG. 11 and examining the connection information of the BS chain. In the data structure of FIG. 11, since each BS chain information structure 201 is linked by the address pointer in the order of connection of the BS chain, the BS chain can be easily scanned by following this link by the address pointer. . Furthermore, in this data structure, since the BS cell information structure 202 is linked to the BS chain information structure 201, the function name of the BS cell can be easily obtained.
[0035]
After obtaining the information necessary for creating the list corresponding to the first to third parts as described above, the BSDL file creation unit 24 stores the information in the sixth storage unit 32 according to the BSDL format. Output. 12 shows the logical connection information of the IC after the BS chain optimization corresponding to FIG. 7B, the BS cell information file shown in FIG. 3, the package terminal data shown in FIG. 5, and the FIG. The BSDL file created from the test instruction description file is shown. In the BSDL file shown in FIG. 12, description 301 corresponds to the first part, description 302 corresponds to the second part, and description 303 corresponds to the third part.
[0036]
<2.3 Creation of test pattern for inspection of boundary scan mechanism>
In this design support apparatus, next, the test pattern creation unit 26 creates a test pattern for inspecting the boundary scan mechanism incorporated in the IC. Here, the IC is produced based on the logical connection information of the IC after the BS chain optimization. In the data structure of FIG. 11, each BS chain information structure 201 is linked by the address pointer in the order of connection of the BS chain, and it is easy to refer to the port name of each device pin. If the test pattern given to the input port) and the scan-in data given to the BS chain (data as the test pattern inputted from the port TDI) are determined, the expected value for this is obvious. For example, in the EXTEST instruction, a signal value (hereinafter referred to as “parallel input”) given to an input port (input device pin) of an IC is captured (captured), and a signal value to be output from an output port (output device pin) of the IC ( Updater (update) (hereinafter referred to as “parallel output”) is performed using the BS chain. For this reason, the expected value of scan-out data (data output from the port TDO) for parallel input and the expected value of parallel output for scan-in data are self-evident.
[0037]
Therefore, the test pattern creating unit 26 obtains the parallel input and the expected value of the scan-out data corresponding thereto, and the expected value of the scan-in data and the parallel output corresponding thereto, and outputs them to the seventh storage unit 33 according to the test pattern format. To do. FIG. 13 shows a part of the test pattern for inspecting the boundary scan mechanism using the BS chain shown in FIG. 7B as an example of the test pattern created in this way. In FIG. 13, in order to clarify the attribute of the signal value, the input signal value is represented by “1” and “0”, and the output signal value is represented by “H” and “L”. In the example shown in FIG. 13, serial input / output is performed in cycles 1 to 3 and 5 to 7, and parallel input / output is performed in cycles 4 and 8.
[0038]
According to this design support apparatus, as described above, the logical connection information of the IC after the BS chain optimization for the IC mounted on the board, the BSDL file, and the test pattern for inspection of the boundary scan mechanism are automatically created. . Then, an IC in which a BS chain is incorporated is produced using this logical connection information, a test pattern is generated by the board test ATPG using this BSDL file, and a boundary scan mechanism inside the IC is created using this test pattern. Inspection is performed.
[0039]
<3 effects>
According to the design support apparatus of the above-described embodiment, the BS chain optimization unit 22 is changed so that the BS chain connection order is in the device pin number order (FIGS. 10 and 11), and a new one corresponding to the change is made. The logical connection information of the IC after the BS chain optimization is output as the logical connection information, and the IC is manufactured based on this information. Therefore, in the IC to be manufactured, the BS chain connection order corresponds to the arrangement of the device pins of the package (see FIG. 7B), so that the wiring efficiency in the layout of the IC is improved. Even when the IC package is changed and the device pin arrangement is changed, the design support apparatus of this embodiment can easily provide the logical connection information after the BS chain optimization corresponding to the changed device pin arrangement. can get.
[0040]
Further, according to the design support apparatus of the present embodiment, the BSDL file creation unit 24 checks the connection information of the BS chain, and automatically creates a BSDL file in which device pin information is added using package terminal data. Therefore, unlike the conventional case, manual correction of the BSDL file is not necessary.
[0041]
Furthermore, according to the design support apparatus of the present embodiment, a test pattern for inspecting the boundary scan mechanism inside the IC is generated in the test pattern creation unit 26. By using this, a board is assembled. The boundary scan mechanism can be inspected before using the IC alone.
[Brief description of the drawings]
FIG. 1 is a functional block diagram showing a configuration of a design support apparatus for a boundary scan compatible IC according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a hardware configuration of a design support apparatus for a boundary scan compatible IC according to the embodiment;
FIG. 3 is a diagram showing an example of a BS cell information file.
FIG. 4 is a diagram showing an example of a data structure for linking the contents of a BS cell information file with the logical connection information of an IC and creating a database on a memory.
FIG. 5 is a diagram showing an example of package terminal data.
FIG. 6 is a diagram showing an example of a test instruction description file.
7A is a diagram showing a configuration of a BS chain before the connection order is changed, and FIG. 7B is a diagram showing a configuration of the BS chain after the connection order is changed.
FIG. 8 is a diagram showing a data structure corresponding to a BS chain before the connection order is changed.
FIG. 9 is a flowchart showing a procedure for rearranging BS chains.
FIG. 10 is a diagram showing queues used for rearranging BS chains.
FIG. 11 is a view showing a data structure corresponding to a BS chain after the connection order is changed.
FIG. 12 is a diagram showing the contents of a BSDL file.
FIG. 13 is a diagram showing an example of a test pattern for a BS chain.
[Explanation of symbols]
11 ... 1st storage part (storage part of logic connection information of IC)
12 ... 2nd storage part (storage part of BS cell)
13 ... 3rd storage part (storage part of package terminal data)
14 ... Fourth storage section (storage section for test instruction description file)
22… BS chain optimization department
24 ... BSDL file creation part
26 ... Test pattern creation section
31 ... 5th storage part (storage part of logical connection information of IC after BS chain optimization)
32 ... 6th storage part (storage part of BSDL file)
33 ... Seventh storage section (storage section for test pattern for inspection of boundary scan mechanism)

Claims (3)

In the design support device for the integrated circuit corresponding to the boundary scan,
First storage means for storing logical connection information indicating a configuration of the integrated circuit as a logic circuit;
Second storage means for storing a test instruction description file describing an instruction name and an instruction code of an instruction of a board test that can be executed by a boundary scan chain incorporated in the integrated circuit;
Third storage means for storing a boundary scan cell information file describing the functions and terminals of each of the boundary scan cells constituting the boundary scan chain;
Fourth storage means for storing package terminal data including information indicating the port name and pin number of each external terminal of the integrated circuit;
The logical connection information is changed so that the connection order of the boundary scan chain corresponds to the pin arrangement of each external terminal of the integrated circuit in the order of the pin numbers indicated by the package terminal data. Boundary scan chain optimization means for outputting connection information;
The connection relation of the boundary scan chain is examined using the logical connection information after being changed by the boundary scan chain optimization means, and the test instruction description file, the boundary scan cancel information file, and the package terminal data are referred to The information indicating the port name and pin number of the external terminal of the integrated circuit, the information indicating the instruction name and instruction code of the board test instruction executable in the boundary scan chain, and the boundary scan chain are configured. The information indicating the boundary scan chain connection order is extracted together with the port name for the input or output pad at the previous stage or the next stage of the boundary scan and the function name of the boundary scan cancel. And BSDL file creation means, and outputs the extracted information as a file written in BSDL format,
A design support apparatus comprising: The design support apparatus according to claim 1,
The connection order of the boundary scan chain indicated by the logical connection information after being changed by the boundary scan chain optimization means, and the port for the input or output pad of the previous stage or the next stage of each boundary scan cell constituting the boundary scan chain A design support apparatus further comprising test pattern generation means for generating a test pattern for inspecting a boundary scan mechanism in the integrated circuit based on a name. Design support comprising a first storage means, a second storage means, a third storage means, and a fourth storage means, and supporting the design of the boundary scan compatible integrated circuit using the design support device for the boundary scan compatible integrated circuit In the method
Storing logical connection information indicating a configuration of the integrated circuit as a logic circuit in the first storage means;
Storing a test instruction description file describing an instruction name and an instruction code of a board test instruction that can be executed by a boundary scan chain incorporated in the integrated circuit in the second storage means;
Storing a boundary scan cell information file describing the functions and terminals of each of the boundary scan cells constituting the boundary scan chain in the third storage unit;
Storing package terminal data including information indicating the port name and pin number of each external terminal of the integrated circuit in the fourth storage means;
The logical connection information is changed so that the connection order of the boundary scan chain corresponds to the pin arrangement of each external terminal of the integrated circuit in the order of the pin numbers indicated by the package terminal data. Outputting connection information;
The connection relationship of the boundary scan chain is checked using the logical connection information after the change, and the test instruction description file and the boundary scan cell information Information indicating the port name and pin number of the external terminal of the integrated circuit by referring to the file and the package terminal data, information indicating the instruction name and instruction code of the board test instruction executable in the boundary scan chain And information indicating each boundary scan cell constituting the boundary scan chain in the order of connection of the boundary scan chain together with a port name and a function name of the boundary scan cell for the input or output pad at the previous stage or the next stage of the boundary scan cell And a process of outputting the extracted information as a file described in the BSDL format.

Images