JP3695996B2 - Complementary source follower circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a complementary source follower circuit capable of operating at a low power supply voltage.
[0002]
[Prior art]
Conventionally, a circuit shown in FIG. 7 is known as a complementary source follower circuit. FIG. 7 shows an example in the case of being configured by CMOS technology. In the figure, the conductances of the N-type FET 103 and the P-type FET 104 change according to the voltage level of the signal input from the input terminal 101. The flowing current changes, and the voltage (output voltage) of the output terminal 102 changes. Such a complementary source follower circuit is widely used as a buffer in digital circuits and analog circuits mainly for the purpose of output impedance conversion and signal level conversion. If not required the level conversion of the signal, when the input voltage V _in becomes half of the power supply voltage V _DD, so that the output voltage V _out is equal to the input voltage V _in, N type FET and a P-type Adjust the current driving force of the FET. FIG. 8 shows an example of input / output characteristics in this case. However, since the threshold voltages of the N-type FET and the P-type FET generally have finite positive and negative values, the influence of the threshold voltage cannot be ignored particularly in an analog circuit and a low-voltage power supply. The combined conductance of the CMOS circuit viewed from the output terminal side is near the boundary where the load current shifts from the N-type to the P-type, that is, in the vicinity of the threshold voltage, the input / output signal characteristics exhibit nonlinearity. In the surrounding area, the current driving force is extremely reduced. For this reason, as shown in FIG. 8, the result shows a non-linear characteristic in the vicinity of ½ of the power supply voltage V _DD , and this non-linear characteristic causes distortion of various transmission waveforms.
[0003]
In order to solve such a problem of distortion, a method of reducing the distortion with a circuit as shown in FIG. 9 has been proposed. That is, the diode 105 and the diode 106 are inserted in series between the gates of the N-type FET 103 and the P-type FET 104, and an offset is given to the input voltage at the gates of both FETs to input to the N-type FET and the P-type FET, respectively. Thus, the non-linear region appearing in FIG. 8 is compensated. However, the power supply voltage for which this method is effective has a lower limit. For example, when a silicon diode is used as the diodes 105 and 106, it cannot be used at a power supply voltage of 1 V or less. For this reason, this method cannot be applied when the power supply voltage is lowered for the purpose of reducing power consumption.
[0004]
[Problems to be solved by the invention]
The complementary MOSFET configuration is widely used in digital LSIs because it consumes less power and is relatively easy to manufacture as an integrated circuit. However, when considering application to analog circuits, it is low as described above. In the complementary circuit of voltage operation, particularly the conventionally known complementary source follower circuit in the present invention, there is no circuit that realizes a circuit with low distortion near 1 V or less and with little distortion. An object of the present invention is to provide a source follower circuit in which such non-linearity does not occur even in the low power supply voltage operation as described above.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has the following configuration.
[0006]
That is,
In claim 1, the gate terminals of the N-type FET and the P-type FET are connected, the drain terminal of the N-type FET is connected to a power supply terminal having a high potential, and the drain terminal of the P-type FET has a low potential. A complementary source follower circuit in which source terminals of the N-type FET and the P-type FET are connected, the gate terminal is an input terminal, and the source terminal is an output terminal, voltage between the high potential and the low potential is not less 1V or less, the upper Symbol N-type FET has a negative threshold voltage, and the P-type FET has a positive threshold voltage, the N-type FET The absolute values of the threshold voltage and the threshold voltage of the P-type FET are smaller than the applied power supply voltage, and the complementary source follower circuit is such that the change in the output voltage is substantially equal to the change in the input voltage.
[0007]
According to a second aspect of the present invention, the impurity concentration of the channel portion of the N-type FET and the P-type FET constituting the complementary source follower according to the first aspect is set to 10 ¹⁵ cm ⁻³ or less.
[0008]
According to a third aspect of the present invention, the FET constituting the complementary source follower circuit according to the first or second aspect is a complementary source follower circuit having a configuration formed on an SOI substrate.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The configuration of the complementary source follower circuit of the present invention will be specifically described below with reference to the drawings.
[0010]
FIG. 1 is a diagram showing a schematic circuit configuration of a complementary source follower circuit according to a first embodiment of the present invention. As shown in FIG. 1, one of the source / drain terminals of the N-type FET 10 is connected to the power supply terminal 12, and one of the source / drain terminals of the P-type FET 11 is connected to the ground terminal 13. And the other one of the source and drain terminals of both FETs of the P-type FET are connected to each other, and at the same time, this connection point is connected to the output terminal 15, and the gates of both FETs are also connected to each other and connected to the input terminal 14. Yes. By combining complementary MOSFETs in this way, the operations of the N-type and P-type FETs are as shown in FIG. FIG. 2A shows a state in which the current I ₁ is balanced when the input voltage is V ₁ and the output voltage is V _out . At this time, the sum of V _N1 and | V _tN | which is an extrapolation of the current curve of the N-type FET to zero current is equal to V _out, and the curve of the current I _P of the P-type FET is _out of zero current. There is a relationship in which the difference between the inserted point V _P1 and V _dd + | V _tP | is equal to (V _dd −V _out ). Here, V _tN and V _tP represent threshold voltages of N-type and P-type FETs. Assuming that the input voltage increases from V ₁ to V ₂ , as shown in FIG. 2A, an imbalance occurs between I _N (V2) and I _P (V2), and V _out cancels this. It moves to. As a result, as shown in FIG. 2B, I _N2 and I _P2 in which the current curve has changed due to the effect of ΔV _out which is a change in V _out appear. Here, as can be seen from FIG. 2, ΔV _out is always substantially equal to the change in input voltage (V ₂ −V ₁ ). As a result, the input / output characteristics of the complementary source follower circuit according to the present invention are linear. The appearing non-linear region can be eliminated. Thereby, even an input signal with a low amplitude can be transmitted reliably, and an output signal with little distortion can be obtained even with an input with a large amplitude. However, in this case, when the potential of the input terminal is about ½ of the power supply voltage _Vdd , both the N-type FET and the P-type FET are in an on state, and current flows through both FETs, thereby causing the power supply Since a leakage current called a through current flows between the terminal 12 and the ground terminal 13, there is a problem that power consumption partially increases in this voltage region. However, if the power supply voltage is 1 V or less, the amount of current is small and the power consumption is small.
[0011]
FIG. 3 shows a cross-sectional view of an integrated circuit according to the second embodiment of the present invention. In FIG. 3, connection portions between elements are not shown, but the circuit configuration is the same as that in FIG. The N-type FET 20 and the P-type FET 21 have a MOSFET structure, and the impurity concentration of the channel region 22 is set to 10 ¹⁵ cm ⁻³ or less. Here, reference numeral 23 denotes a region for forming gate electrodes of the N-type FET and the P-type FET, which is formed as an n ⁺ region for the N-type and a p ⁺ region for the P-type. Reference numeral 24 denotes a region formed to be used as a source / drain electrode of each FET. Reference numeral 25 denotes an element isolation region for insulating and separating the N-type FET and the P-type FET in FIG. It is. With such a configuration, a MOSFET with a low threshold voltage that forms the complementary source follower circuit using the same gate electrode, gate insulating film, etc. as the MOSFET used in a normal CMOS circuit is connected to the CMOS circuit. It can be manufactured on the same substrate. Further, if the impurity concentration is set to 10 ¹⁵ cm ⁻³ or less, the input / output characteristics shown in FIG. 2 can be obtained for any impurity species corresponding to the FET conductivity type (N-type or P-type). . That is, the channel regions 22 of the N-type FET 20 and the P-type FET 21 used in the complementary source follower circuit may be configured with the same impurity and the same concentration. Since it can be formed simultaneously, the manufacturing process becomes easy. Further, when manufacturing using a silicon wafer having the above-mentioned impurity concentration (10 ¹⁵ cm ⁻³ or less), a desired amount of impurities is impregnated only in the channel region of a MOSFET constituting a normal CMOS circuit. Since the complementary source follower circuit FET can be formed only by not selectively impregnating the channel region of the complementary source follower configuration MOSFET, it can be manufactured more easily.
[0012]
FIG. 4 shows a cross-sectional view of an integrated circuit according to a third embodiment of the present invention. The connection portion between elements is not shown, but the circuit configuration is the same as FIG. As shown in FIG. 4, the N-type FET 30 and the P-type FET 31 have an SOI (Si1 on-Insulator) structure formed on a buried insulating layer 36 formed on a silicon substrate 37. The impurity concentration of the channel region 32 of the N-type FET 30 and the channel region 33 of the P-type FET 31 is set to 10 ¹⁵ cm ⁻³ or less as described in the second embodiment. By adopting such a configuration, the same effects as those of the second embodiment can be obtained, and the impurity concentration of the channel region 32 of the N-type FET 30 and the channel region 33 of the P-type FET 31 is low. The SOI structure can prevent the punch-through caused, that is, the breakdown voltage drop between the source / drain electrodes 35 formed on both sides of the channel portion 32 or 33 formed under the gate electrode 34 of each FET. It is possible to contribute to improving the performance of the FET, such as shortening the length and improving the high frequency characteristics.
[0013]
FIG. 5 is a cross-sectional view of an integrated circuit according to the fourth embodiment of the present invention. The connection portion between elements is not shown, but the circuit configuration is a complementary circuit having the same configuration as FIG. Two sets are configured on the same substrate. The channel regions of the N-type FET 38 and the P-type FET 39 for the complementary source follower configuration may be configured to have opposite conductivity types to the channel regions of the normal CMOS circuit configuration N-type FET 40 and the P-type FET 41, respectively. Good. That is, the channel region of the N-type FET 40 normally uses a P-type material, whereas the channel region of the N-type FET 38 uses an n ⁻ material and similarly uses a p ⁻ material for the channel region of the P-type FET 39. ing. Even if the complementary source follower circuit is configured using the MOSFET having such a structure, the threshold voltage of the N-type FET 38 is negative and the threshold voltage of the P-type FET 39 is positive, so that it is the same as in the second embodiment. The effect is obtained. At this time, the channel impurity concentrations of the N-type FET 38 and the P-type FET 41, and the P-type FET 39 and the N-type FET 40 may be equalized, whereby the respective regions can be formed simultaneously, thereby facilitating the manufacturing process.
[0014]
FIG. 6 shows a cross-sectional view of an integrated circuit according to a fifth embodiment of the present invention. The connection portion between elements is not shown, but the circuit configuration is the same as FIG. A complementary source follower is formed using an N-type FET 42 with a buried channel structure and a P-type FET 43 with a buried channel structure. Even in this case, a complementary source follower circuit having the above-described effect can be formed without adding any process to the normal CMOS manufacturing process. Also, the complementary source follower circuit FETs configured as shown in FIGS. 4, 5, and 6 can be used in any combination on the same wafer according to conditions such as power supply voltage used and input level. In this case as well, no additional steps are required.
[0015]
As described above, the complementary source follower circuit according to the present invention does not have non-linearity in the input / output characteristics even when the input voltage is in the vicinity of ½ of the power supply voltage. However, the transfer characteristic is not deteriorated. Therefore, a complementary source follower circuit that can operate even when the power supply voltage is lowered can be realized.
[0016]
Further, the channel portions of the N-type FET and the P-type FET are simultaneously formed by setting the impurity concentration of the channel portions of the N-type and P-type FETs constituting the complementary source follower to 10 ¹⁵ cm ⁻³ or less. And the manufacturing process is simplified.
[0017]
Further, by forming the FET constituting the complementary source follower circuit on the SOI substrate, even when the gate length is shortened and the high-speed performance is improved, good characteristics of the complementary source follower circuit can be obtained. it can.
[0018]
【The invention's effect】
As described above, according to the present invention, by setting the threshold voltage to a depletion type, the effect of the non-linear region at a low voltage can be substantially canceled, and even when the power supply voltage is 1 V or less. A complementary source follower circuit capable of operation with less distortion can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a complementary source follower according to a first embodiment of the present invention.
FIG. 2 is an input / output characteristic diagram of the complementary source follower circuit according to the first embodiment of the present invention.
FIG. 3 is a sectional view showing a schematic configuration of a complementary source follower circuit according to a second embodiment of the present invention;
FIG. 4 is a cross-sectional view showing a schematic configuration of a complementary source follower circuit according to a third embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a schematic configuration of a complementary source follower circuit according to a fourth embodiment of the present invention.
FIG. 6 is a sectional view showing a schematic configuration of a complementary source follower circuit according to a fifth embodiment of the present invention.
FIG. 7 is a complementary source follower circuit diagram constructed according to the prior art.
FIG. 8 is an input / output characteristic diagram of a complementary source follower circuit configured by a conventional technique.
FIG. 9 is another complementary source follower circuit diagram configured in accordance with the prior art.
[Explanation of symbols]
10: N-type FET 11: P-type FET
12: Power supply terminal 13: Ground terminal 14: Input terminal 15: Output terminal 20: N-type FET 21: P-type FET
22: Channel region 23: Gate electrode 24: Source / drain region 25: Element isolation region 30: N-type FET 31: P-type FET
32: Channel region 33: Channel region 34: Gate electrode 35: Source / drain region 36: Buried insulating layer 37: Silicon substrate 38: N-type FET 39: P-type FET
40: N-type FET 41: P-type FET
42: buried channel NFET
43: buried channel type PFET
101: Input terminal 102: Output terminal 102: Output terminal 103: N-type FET
104: P-type FET 105: Diode 106: Diode 107: Power supply terminal 108 Ground terminal

Claims (3)

The gate terminals of the N-type FET and P-type FET are connected,
A drain terminal of the N-type FET is connected to a power supply terminal having a high potential;
A drain terminal of the P-type FET is connected to a power supply terminal having a low potential;
Source terminals of the N-type FET and the P-type FET are connected,
A complementary source follower circuit in which the gate terminal is an input terminal and the source terminal is an output terminal;
A potential difference between the high potential and the low potential is 1 V or less ;
The N-type FET has a negative threshold voltage, and the P-type FET has a positive threshold voltage;
The absolute value of the threshold voltage and the threshold voltage of the P-type FET of the N-type FET is Ri smaller der than the applied power supply voltage,
A complementary source follower circuit characterized in that a change in output voltage is substantially equal to a change in input voltage . The complementary source follower circuit according to claim 1, wherein the impurity concentration of the channel portion of the N-type FET and the P-type FET constituting the complementary source follower according to claim 1 is 10 ¹⁵ cm ^-3 or less. The FET constituting the complementary source follower circuit according to claim 1 or 2 is:
A complementary source follower circuit formed on an SOI substrate.

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