JP3676030B2 - Polishing pad dressing method and semiconductor device manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a chemical mechanical polishing (CMP) process used for planarization of an inter-brow insulating film or an insulating film embedded in a trench in a multilayer wiring process, and in particular, at the same time as dressing a polishing pad surface deteriorated after polishing. And a method of dressing a polishing pad using the dresser.
[0002]
[Prior art]
Conventionally, a CMP method used in a semiconductor device is used when flattening a thin film such as an insulating film or a metal film formed on a semiconductor wafer by CVD or the like.
The CMP method is a method of flattening a thin film on the surface of a semiconductor wafer by impregnating a polishing pad containing abrasive particles called slurry into a polishing pad and polishing the semiconductor wafer on a rotating polishing disk (polishing). When this method is used, if the wafer is polished continuously, the surface of the polishing pad becomes rough and deteriorates. Conventionally, a surface treatment called dressing is performed as a method for recovering the rough surface.
In a CMP method used for manufacturing a semiconductor device, polishing is performed with an abrasive interposed between a polishing pad and a semiconductor wafer. Various materials are used for the polishing pad used for polishing. One commonly used is a foamed polyurethane pad. This polishing pad has a structure in which many fine pores exist on the cloth surface, and polishing is performed while holding an abrasive therein.
[0003]
[Problems to be solved by the invention]
As described above, when the CMP method is applied to a semiconductor device manufacturing method or the like, when a semiconductor wafer is continuously used, reaction products and abrasive particles are gradually compressed and confined inside the pores. If polishing is performed in this state, the polishing rate and the uniformity of polishing will be reduced.
In addition, when foamed polyurethane is used for a polishing pad, an initial process called conditioning that slightly roughens the surface at the start of use of the polishing pad is required. A stable polishing rate and uniform polishing cannot be obtained unless the surface is roughened by this treatment.
It has been found that the deterioration of the polishing pad appears more prominently when a highly viscous substance such as a polymeric surfactant other than abrasive particles or a polysaccharide is added to the abrasive. The use of this deteriorated polishing pad has been highlighted as a major problem in reducing the yield in the CMP process of a semiconductor device wafer in which fine patterns are densely packed.
[0004]
  Conventionally, a pad dressing process called dressing has been performed in order to remove clogged foreign substances and scrape rough surfaces. This dressing usually uses a diamond dresser in which diamond particles are embedded with resin or electrodeposited. The diamond dresser scrapes and removes the surface layer of the foamed polyurethane pad, so that the foreign matter can be completely removed. However, the polishing pad returns to the initial surface state. In other words, conditioning must be performed after dressing so that the surface of the polishing pad can be polished. At present, productivity reduction in this process is a big problem.
  The present invention has been made under such circumstances, and is a CMP method.SuchWhen polishing the surface of a semiconductor wafer by using a dresser that can dress the polishing pad surface that has deteriorated after polishing and at the same time condition the polishing pad, it is possible to increase the life of the polishing pad and stabilize the polishing rate A polishing pad dressing method and a semiconductor device manufacturing method using the polishing pad obtained by the method are provided.
[0005]
[Means for Solving the Problems]
The present invention is suitable for dressing by this CMP method.In addition to the traditional diamond dressing,A ceramic dresser using ceramics made of SiC, SiN, alumina, silica or the like is used.
  Impurities such as abrasives clogged inside the pores of the polishing pad can be easily removed, and the foamed film with a rough surface can be removed. Further, the surface of the regenerated polishing pad is almost the same as that after the conditioning, and the next polishing can be performed without performing the conditioning. Further, the life of the polishing pad can be extended and the polishing rate can be stabilized.
[0006]
  The polishing pad dressing method of the present invention comprises:A step of dressing a surface of a used polishing pad with a diamond dresser, a step of dressing a surface of the polishing pad treated with the diamond dresser with a ceramic dresser, and an abrasive containing abrasive particles of a semiconductor wafer. Polishing at least one semiconductor wafer while polishing the semiconductor wafer with the polishing pad while hanging on the polishing surface; and polishing the surface of the polishing pad deteriorated by polishing the at least one semiconductor wafer. And a step of dressing using the ceramic dresser.
[0008]
  A method of manufacturing a semiconductor device according to the present invention is claimed.A step of attaching a polishing pad dressed by the dressing method according to any one of claims 1 to 5 to a polishing disc of a polishing apparatus, and a semiconductor wafer while polishing the polishing agent on the polishing surface of the semiconductor wafer while applying an abrasive containing polishing particles. Polishing the polishing film on the surface with the polishing pad, polishing the polishing film on the surface of the plurality of semiconductor wafers using the polishing pad, and polishing the polishing film on the surface of the plurality of semiconductor wafers. And a step of dressing the surface of the polishing pad deteriorated by the above using a ceramic dresser.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The present invention relates to a wafer processing step in manufacturing a semiconductor device. FIG. 1 is a schematic view of a semiconductor manufacturing apparatus that uses a CMP apparatus (polishing apparatus) to perform a series of sequences from polishing to in-line cleaning on a semiconductor wafer. The semiconductor manufacturing apparatus 50 is divided into a polishing area 51 and a wafer cleaning area 52. In addition, a wafer supply unit 53 for supplying a semiconductor wafer into the apparatus and a semiconductor wafer processed in the apparatus are received and made outside. And a receiving portion 54 to be carried out. In the polishing region 51, a semiconductor wafer such as silicon is polished by a polishing pad (not shown) attached on a polishing board 17 (also referred to as a turntable) of the polishing apparatus. At the time of polishing, a polishing agent, pure water, an additive or the like, which is called slurry, is supplied to the polishing pad. The semiconductor wafer polished by the polishing pad is temporarily stored in the wafer reversing unit 55 in the wafer cleaning region 52 from the wafer supply unit 53 and is supplied to the polishing pad of the polishing board 17 from here.
[0011]
The polished semiconductor wafer is returned to the wafer reversing unit 55, processed from here by the brushing unit 56, further washed and dried by the rinse / drying unit 57, and conveyed to the wafer receiving unit 54. The semiconductor wafer is transferred from the wafer receiving unit 54 for the next process. The polishing pad deteriorates as many semiconductor wafers are processed, resulting in poor polishing characteristics. Therefore, the characteristics of the polishing pad with deteriorated characteristics are recovered by dressing or conditioning.
[0012]
Next, a polishing apparatus used in the semiconductor manufacturing apparatus of FIG. 1 will be described with reference to FIG. FIG. 2 is a schematic cross-sectional view of a CMP polishing apparatus used in the semiconductor manufacturing apparatus of FIG. A polishing disc receiver 15 is disposed on the base 11 via a bearing 13. A polishing disk 17 is attached on the polishing receiver 15. A polishing pad 19 for polishing the semiconductor wafer is attached on the polishing board 17. In order to rotate the polishing receiver 15 and the polishing disc 17, a drive shaft 21 is connected to the central portion thereof. The drive shaft 21 is rotated by a motor 23 via a rotating belt 25. On the other hand, the semiconductor wafer 20 is adsorbed by an adsorbing plate 33 provided with a template 29 and an adsorbing cloth 31 using a vacuum or the like so as to come to a position facing the polishing pad 19. The suction disk 33 is connected to the drive shaft 35. The drive shaft 35 is rotated by a motor 37 via gears 39 and 41. The drive shaft 35 is fixed to the drive base 43 with respect to the vertical movement.
[0013]
With such a structure, the drive base 43 moves up and down as the cylinder 45 moves up and down, whereby the semiconductor wafer 20 fixed to the suction plate 33 is pressed against the polishing pad 19 or separated from the polishing pad 19. . A polishing agent according to the purpose is allowed to flow between the semiconductor wafer 20 and the polishing pad 19, thereby polishing the semiconductor wafer 20.
Although not shown in the drawings, the semiconductor wafer can be moved in the XY direction (horizontal direction) by another drive system during polishing.
For example, when a polysilicon film embedded in a trench is polished using a silicon oxide film as a stopper film, polishing is performed using the following sequence. The type of slurry used varies depending on the type of film to be polished on the semiconductor wafer, such as a polysilicon film.
[0014]
(1) From the mixing valve, a slurry having a high polishing rate of the oxide film is supplied in order to remove the natural oxide film on the polysilicon film.
(2) After removing the natural oxide film, in order to polish the polysilicon film, the slurry having a high polishing rate is supplied to the silicon oxide film after the supply of the slurry used in (1) is stopped. As this material, for example, an organic amine-based colloidal silica slurry is used. As the polishing proceeds, the oxide film stopper is exposed and the polishing is completed.
(3) When the oxide film is exposed, the supply of the polysilicon film polishing slurry is stopped and a surfactant for treating the wafer surface is added.
(4) Stop supplying the surfactant, rinse with ultrapure water, and transport the semiconductor wafer to the cleaning process.
(5) Dressing the surface of the polishing pad to remove the slurry clogged in the polishing pad.
When this process is repeated, the surface of the polishing pad deteriorates and cannot be recovered with a ceramic dresser alone. Therefore, the pad surface is scraped off with a diamond dresser or the like having a sharp surface.
(6) The pad after using this diamond dresser is in a pre-break-in state and returns to the same surface state as a new one.
[0015]
Conventionally, the CMP process was resumed after processing 6 to 10 or more dummy silicon wafers (about 10 minutes / sheet) in this state to acclimatize the polishing pad surface. However, the ceramic dresser of the present invention was replaced with a diamond dresser. The surface state equivalent to the processing of several tens of silicon dummy wafers can be obtained only by using for several minutes after dressing.
FIG. 3 is a characteristic diagram for explaining the effect of the dressing / conditioning of the present invention while comparing the conventional examples. In the present invention and the prior art, the dressing / conditioning processing of the polishing pad (virgin pad) before use is shown. It shows how they differ. The vertical axis represents the polishing pad processing time (min (min) / 1 sheet). Conventionally, polishing is performed by performing silicon dummy dressing (conditioning) and diamond dressing, but in the present invention, polishing is performed by performing diamond dressing and ceramic dressing. The dressing processing time is only about 10 min / 1 sheet in the present invention, whereas the conventional dressing processing time is 70 min / 1 sheet. By performing soft dressing with a ceramic dresser in this way, the polishing pad can be conditioned in a short time and without a silicon dummy wafer.
[0016]
FIG. 4 is a characteristic diagram for explaining the operational effects of the present invention and conventional dressing / conditioning during continuous processing. As shown in the figure, the processing time is shortened to ½ compared with the prior art.
Next, a first embodiment according to the dressing method of the polishing pad will be described with reference to FIG. In this embodiment, the dressing for the polishing pad in the initial state will be described. FIG. 5 is a time chart of polishing and dressing. Since the polishing pad which is not yet used in the initial state formed from foamed polyurethane is in a rough surface state after performing diamond dressing, it is necessary to perform a so-called conditioning called a conditioning. The ceramic dresser according to the present invention can perform dressing also as conditioning.
First, an unused polishing pad is dressed with a ceramic dresser (ceramic dressing). For example, 1 to 6 silicon wafers are polished using this polishing pad. This ceramic dressing / polishing is repeated several times. Thereafter, the polishing pad is again subjected to ceramic dressing, and then 1 to 6 silicon wafers are polished.
[0017]
Next, this polishing pad is dressed with a diamond dresser (diamond dressing) (a). Next, the polishing pad is dressed with a ceramic dresser (ceramic dressing) (b). One or more silicon wafers are polished using this polishing pad (c). This ceramic dressing / polishing (b / c) is repeated a plurality of times. Thereafter, the polishing pad is again subjected to ceramic dressing (d), and then one or more silicon wafers are polished (e). This a process thru | or e process is made into a series of processes (A), and this A process is performed at least once or more.
The above is the polishing / dressing sequence when an unused polishing pad is used. Next, a second embodiment of the dressing method for the polishing pad will be described with reference to FIG. This embodiment is a method of dressing a polishing pad with degraded performance by repeating polishing.
[0018]
First, a polishing pad with degraded performance is dressed with a diamond dresser (diamond dressing). Next, the polishing pad is dressed with a ceramic dresser (ceramic dressing). One or more silicon wafers are polished using this polishing pad. This ceramic dressing / polishing process is repeated several times. Thereafter, ceramic dressing is performed again on the polishing pad, and then one or more silicon wafers are polished. This series of steps (A in FIG. 5) is performed at least once.
Next, the dresser used in the embodiment of the present invention will be described with reference to FIGS. All the figures are cross-sectional views of the dresser. The ceramic dresser 22 shown in FIG. 7A is made of a ceramic obtained by firing alumina, silicon nitride, silicon carbide or the like at a high temperature. For example, the ceramic dresser 22 is a disk-shaped body, and the first main surface is a dressing for dressing a polishing pad. A surface 221 is formed. When at least one step is formed on the dressing surface, the polishing efficiency increases. The step is about 20 to 30 nm. The ceramic dresser 22 is operated by a support arm 222 attached to the main surface opposite to the dressing surface 221.
[0019]
The diamond dresser 24 shown in FIG. 7B is, for example, a disk-shaped body in which diamond particles 243 are dispersed in a resin or the like, and the sharp tips of the diamond particles 243 are exposed on the dressing surface 241. The diamond dresser 24 is operated by a support arm 242 attached to the surface opposite to the dressing surface 241. Without using a resin, diamond particles can be dispersed in a disk-like body formed by Ni electrodeposition. The dresser of FIG. 8 is a disk-shaped body used in place of the diamond dresser of FIG. In the dresser of FIG. 8A, a thin film 271 of silicon nitride or silicon carbide having a thickness of about 5 to 40 μm is formed on the surface of a silicon nitride (SiN) substrate having a thickness of about 5 to 10 mm by ECR / CVD. The surface on which this thin film is formed is the dressing surface. The dresser 27 is operated by a support arm 272 attached to a surface opposite to the dressing surface. In the dresser 28 of FIG. 8B, a thin film 281 of silicon nitride or silicon carbide having a thickness of about 5 to 40 μm is formed on the surface of a carbon nitride (SiC) substrate having a thickness of about 5 to 10 mm by ECR / CVD. The surface on which this thin film is formed is the dressing surface.
[0020]
The dresser 28 is operated by a support arm 282 attached to a surface opposite to the dressing surface.
The above dressing method is alternately performed in the dressing apparatus shown in FIG. 2 in the order of dressing → polishing → dressing →.
Next, a third embodiment relating to a dressing method using the dressing apparatus will be described with reference to FIGS. Each figure is a plan view of the main part of the dressing apparatus shown in FIG. The polishing pad 19 is mounted on a polishing board 17 that rotates at 100 rpm. The number of rotations of the polishing board 17 during polishing is usually 20 to 200 rpm, and the processing pressure is 50 to 500 g / cm.²It is. Especially 350g / cm²Is appropriate. As shown in FIG. 9, polishing is performed by pressing the silicon wafer 20 against the rotating polishing pad 19 with a predetermined processing pressure. The polishing pad 18 is dressed while pressing the ceramic dresser 22 so as to follow the locus of the silicon wafer 20 during polishing. Since polishing and dressing are repeated for each silicon wafer, the life of the polishing pad is prolonged and the manufacturing time of the semiconductor device is shortened.
[0021]
Next, the state of the polishing pad to which the dressing of the present invention is applied will be described with reference to FIGS. FIG. 11 is a polishing pad before use, and FIGS. 12 to 14 are enlarged surface views and cross-sectional views of the polishing pad after dressing. As shown in FIG. 11, the surface of the polishing pad made of foamed polyurethane and the foamed layer (pore layer) in the cross section are alive and are formed substantially uniformly. When one or more semiconductor wafers are polished using the polishing pad of FIG. 11, reaction products and abrasive particles are compressed and confined inside the foam layer, and the foam layer is clogged as shown by the oblique lines in the figure. In many cases, there is no room for abrasives during polishing, making them unsuitable for polishing. In the prior art shown in FIG. 13, the polishing pad is restored to the same state as the virgin pad over time. FIG. 14 shows a state after dressing the polishing pad shown in FIG. 12 with a ceramic dresser. It is sufficiently repaired as shown in the figure by short-time treatment using only a ceramic dresser.
[0022]
Next, a fourth embodiment will be described with reference to FIGS.
Conventionally, there has been known a polishing method capable of suppressing dishing by polishing using a foaming polyurethane-based polishing pad and polishing using a polishing liquid in which a hydrophilic polysaccharide that forms a film on a silicon surface is added to an abrasive. It has been.
FIG. 15 is a perspective view showing a part of a polishing apparatus used in this polishing method. Similar to the polishing apparatus of FIG. 2, this polishing apparatus has a rotating polishing disc 17 having a polishing pad 19 attached to the surface thereof. Above the polishing pad 19, an adsorbing plate 33 rotated by a drive shaft 35 while fixing a silicon wafer, an abrasive supply nozzle 30, and an additive supply nozzle 32 are arranged. For example, the silicon wafer attached to the suction disk 33 is rotated while pressing the polishing surface on which the polysilicon film is formed against the polishing pad 19. At this time, the abrasive and the additive from the nozzle 30 are simultaneously dropped onto the polishing pad 19 from the nozzle 30. The abrasive is an alkaline solution containing abrasive particles such as silica. The alkaline solution is a material that chemically etches silicon made of, for example, an organic amine.
[0023]
Examples of the additive include celluloses such as hydroxyethyl cellulose, flurrane, pyrrolidone and the like. The additive is suitably about 1 to 10 wt% with respect to the abrasive. Examples of solvents that dissolve hydrophilic polysaccharides include ammonia and triethanolamine.
16 and 17 are cross-sectional views of a semiconductor substrate showing a state in which a polishing target film of a semiconductor substrate such as silicon is polished using a polishing pad.
The polishing agent 34 to which hydroxyethyl cellulose is added as an additive enters the recess of the polysilicon film 3 formed on the silicon oxide film 2 on the semiconductor substrate 1 and polishes the polysilicon film 3. At that time, hydroxyethyl cellulose adheres to the surface of the polysilicon film 3 having irregularities, and a coating 36 is formed. The coating 36 is mechanically polished and removed from the convex portion by the polishing pad 19 and abrasive particles in the abrasive. As a result, only the convex portion of the polysilicon film 3 is exposed. The exposed polysilicon film is mechanically polished by the polishing pad 19 and polishing particles, and at the same time is chemically etched by an alkaline solution. On the other hand, the coating film 36 formed in the recess remains as it is and covers the recess of the polysilicon film 3. The coating 36 covering the recesses protects the recesses from chemical etching with an alkaline solution.
[0024]
In this embodiment, every time a single silicon wafer is polished, dressing is performed on the silicon wafer using a ceramic dresser that is a feature of the present invention. Any of the dressers shown in FIG. 7 may be used.
Next, the operation of this embodiment will be described with reference to the characteristic diagram shown in FIG.
Since the polishing pad is habituated using a ceramic dresser every time the wafer is processed, the stability of the polishing characteristics can be maintained. Dressing with a ceramic dresser can suppress dishing more than using a diamond dresser, and can suppress dust adsorption to a semiconductor wafer due to dust generation from a polishing pad, compared to a process without dressing (FIG. 18A). In addition, the life of the polishing pad can be extended and the rate can be stabilized. Further, it is possible to start up the polishing pad after the polishing pad is replaced (FIG. 18B).
The additive for forming a film on the silicon surface used in this example is not limited to hydrophilic polysaccharides. Any material that prevents excessive polishing is acceptable. For example, a material that oxidizes the silicon surface may be used.
[0025]
Next, referring to FIG. 19 and FIG. 20, the SiO 2 on the wafer surface by the polishing method using the polishing apparatus shown in FIG. 2 as the fifth embodiment.₂A film planarization process will be described. First, Si is formed on the semiconductor substrate 1 by CVD or the like._ThreeN_FourA film 7 is formed (FIG. 19A). Next, patterning is performed to form Si._ThreeN_FourThe film 7 and a predetermined portion of the semiconductor substrate 1 are etched to form a groove 8 there (FIG. 19B). And Si_ThreeN_FourSiO on the film 7 and in the groove 8₂The film 5 is laminated by the CVD method (FIG. 20A). Subsequently, SiO is obtained by CMP.₂Si film 5 is polished to form a stopper film_ThreeN_FourWhen the exposure of the film 7 is detected, SiO₂By finishing the polishing of the film 5, SiO into the groove 8 is obtained.₂The filling of the film 5 is completed and the surface of the semiconductor substrate 1 is planarized (FIG. 20B).
After this polishing is performed on one or more silicon wafers, dressing, which is a feature of the present invention, is performed on the polishing pad. The polishing pad deteriorated by polishing the silicon wafer is recovered in a short time.
[0026]
Recently, CMP technology has been used in the manufacturing process of highly integrated devices. Next, a manufacturing process for a highly integrated device according to the sixth embodiment will be described with reference to FIG. FIG. 21 is a manufacturing process sectional view of the semiconductor device applied to the trench element isolation process. The surface of the semiconductor substrate 1 is thermally oxidized to make SiO₂After forming the film 2, Si serving as a stopper film for polishing_ThreeN_FourThe film 7 is made of this SiO₂It is formed on the film by the CVD method. Next, Si in the element isolation formation region is patterned by lithography._ThreeN_FourFilm 7 and SiO₂A part of the film 2 and the semiconductor substrate 1 is removed to form a groove 9. Subsequently, the surface of the semiconductor substrate 1 in the groove 9 is oxidized, and boron is ion-implanted into the bottom of the groove 9 to form a channel cut region 10. Next, Si_ThreeN_FourA polysilicon film 3 is formed on the film 7 and in the groove 9 by the CVD method (FIG. 21A). SiO instead of polysilicon film₂May be used. Next, the polysilicon film 3 on the surface of the semiconductor substrate 1 is made Si._ThreeN_FourPolishing is performed until the film 7 is exposed (FIG. 21B). Under the polishing conditions at this time, Si is compared with the polysilicon film._ThreeN_FourSince the polishing rate of the film 7 is as small as about 1/10 to 1/200, Si is used._ThreeN_FourPolishing can be stopped by the film 7, and the polysilicon film 3 is embedded only in the groove.
[0027]
As described above, the stopper film for polishing is selected to have a lower posing rate than the film to be polished, and the polishing can be terminated when the stopper film is exposed by specifying the polishing time.
After this polishing is performed on one or more silicon wafers, dressing, which is a feature of the present invention, is performed on the polishing pad. The polishing pad deteriorated by polishing the silicon wafer is recovered in a short period of time.
Next, with reference to FIGS. 22 and 23, a polishing method used in the case where the metal wiring according to the seventh embodiment is embedded in the groove of the insulating film will be described.
SiO 2 formed by CVD on the semiconductor substrate 1₂Film 5 and plasma SiO₂The film 12 is continuously formed (FIG. 22A). Subsequently, plasma SiO₂The film 12 is patterned to form a groove 14 at a predetermined location (FIG. 22B). Groove 14 and plasma SiO₂A Cu film 16 is laminated on the entire surface of the film 12 (FIG. 22C). Plasma SiO₂The Cu film 16 is polished using the film 12 as a stopper film. Plasma SiO₂When the polishing of the Cu film 16 is finished at the stage where the film 12 is exposed, the Cu film 14 is embedded only in the groove portion 14 and a Cu embedded wiring is formed (FIG. 23A).
[0028]
By this polishing, the surface of the semiconductor substrate 1 is flattened, and then the second-layer plasma SiO₂Formation of the film 18 is facilitated (FIG. 23B). The planarization by the CMP method facilitates formation of the second and third electrode wirings (not shown).
After this polishing is performed on one or more silicon wafers, dressing, which is a feature of the present invention, is performed on the polishing pad. The polishing pad deteriorated by polishing the silicon wafer is recovered in a short period of time.
[0029]
【The invention's effect】
  According to the present invention, (1) the reaction product and abrasive particles clogged inside the pores (foamed layer) of the polishing pad can be removed by compressing and confining impurities and the surface. It is possible to remove the deteriorated foam layer. (2) The surface of the regenerated polishing pad is almost the same as the condition after conditioning, and the next polishing can be performed without conditioning. (3) A stable polishing rate and polishing uniformity can be obtained by performing the ceramic dresser of the present invention after polishing or simultaneously with polishing. Further, (4) the life of the polishing pad and the stability of the polishing rate can be maintained.
[Brief description of the drawings]
FIG. 1 is a block diagram of a semiconductor manufacturing apparatus including a polishing apparatus according to the present invention.
2 is a cross-sectional view of a polishing apparatus used in the semiconductor manufacturing apparatus of FIG.
FIG. 3 is a characteristic diagram illustrating polishing / dressing processing according to the present invention.
FIG. 4 is a characteristic diagram illustrating polishing / dressing processing according to the present invention.
FIG. 5 is a flowchart illustrating dressing processing according to the present invention.
FIG. 6 is a flowchart illustrating dressing processing according to the present invention.
FIG. 7 is a cross-sectional view of a dresser used in the dressing process of the present invention.
FIG. 8 is a cross-sectional view of a dresser used in the dressing process of the present invention.
FIG. 9 is a plan view of a polishing apparatus for explaining a polishing method of the present invention.
FIG. 10 is a plan view of a polishing apparatus for explaining the polishing method of the present invention.
FIGS. 11A and 11B are a cross-sectional view and a plan view of a polishing pad enlarged to explain a state of a polishing pad for polishing a semiconductor wafer. FIGS.
FIGS. 12A and 12B are a cross-sectional view and a plan view of a polishing pad enlarged to explain a state of a polishing pad for polishing a semiconductor wafer. FIGS.
FIGS. 13A and 13B are a cross-sectional view and a plan view of a polishing pad enlarged to explain a state of a polishing pad for polishing a semiconductor wafer. FIGS.
14A and 14B are a cross-sectional view and a plan view of a polishing pad enlarged to explain a state of a polishing pad for polishing a semiconductor wafer.
FIG. 15 is a partial perspective view of the polishing apparatus of the present invention.
16 is a cross-sectional view of a polishing pad and a semiconductor wafer of the polishing apparatus shown in FIG.
17 is a cross-sectional view of a polishing pad and a semiconductor wafer of the polishing apparatus shown in FIG.
FIG. 18 is a characteristic diagram for explaining the operation of the polishing method of FIG. 15;
FIG. 19 is a cross-sectional view of a manufacturing process of a semiconductor device of the invention.
20 is a cross-sectional view of a manufacturing process of a semiconductor device of the invention. FIG.
FIG. 21 is a manufacturing process cross-sectional view of the semiconductor device of the invention.
22 is a cross-sectional view of a manufacturing process of a semiconductor device of the invention. FIG.
FIG. 23 is a manufacturing process cross-sectional view of the semiconductor device of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2, 5, 12, 18 ... SiO₂film,
3 ... polysilicon film, 4, 8, 9, 14 ... groove,
6 ... Etch back resist, 7 ... Si_ThreeN_Fourfilm,
10 ... channel cut region, 11 ... stand,
13 ... Bearing, 15 ... Polishing disc holder,
16 ... Cu film, 17 ... polishing disc, 19 ... polishing pad,
20 ... semiconductor wafer 21, 26, 35 ... drive shaft,
22 ... Ceramic dresser, 23, 37 ... Motor,
24 ... Diamond dresser, 25 ... Rotating belt,
27, 28 ... Dresser, 29 ... Template,
30 ... Nozzle for supplying abrasive, 31 ... Adsorbent cloth,
32 ... Nozzle for additive supply, 33 ... Adsorption plate,
34 ... Abrasive, 36 ... Coating, 39, 41 ... Gear,
43 ... Drive base, 45 ... Cylinder,
50 ... Semiconductor manufacturing equipment, 51 ... Polishing region,
52 ... Wafer cleaning area,
53 ... Wafer supply unit, 54 ... Wafer receiving unit,
55 ... Wafer reversing part, 56 ... Wafer brushing part,
57 ... Wafer rinse and fitting part,
222, 242, 272, 282 ... Dresser support arms.

Claims (6)

Dressing the surface of a used polishing pad with a diamond dresser;
Dressing the surface of the polishing pad treated with the diamond dresser using a ceramic dresser;
Polishing at least one semiconductor wafer by polishing the semiconductor wafer with the polishing pad while applying an abrasive containing abrasive particles to the polishing surface of the semiconductor wafer;
Dressing the surface of the polishing pad deteriorated by polishing the at least one semiconductor wafer using the ceramic dresser.   2. The method of claim 1, further comprising the step of dressing the deteriorated polishing pad regenerated by the ceramic dresser with a ceramic dresser again after being deteriorated by polishing the at least one semiconductor wafer. A method for dressing a polishing pad according to claim 1. 3. The method of dressing a polishing pad according to claim 2, wherein the polishing pad that has been subjected to the dressing process using a ceramic dresser again and again is dressed with a diamond dresser.   4. The polishing pad dressing method according to claim 3, wherein the polishing pad dressed with the diamond dresser is regenerated by dressing with a ceramic dresser before being used for polishing.   5. The polishing pad dressing method according to claim 1, wherein at least one step is formed on the surface of the ceramic dresser. Attaching the polishing pad dressed by the dressing method according to any one of claims 1 to 5 to a polishing disk of a polishing apparatus;
Polishing a polishing film on the surface of the semiconductor wafer with the polishing pad while applying an abrasive containing abrasive particles to the polishing surface of the semiconductor wafer;
Polishing a polishing target film on a plurality of semiconductor wafer surfaces using the polishing pad;
And a step of dressing the surface of the polishing pad deteriorated by polishing the polishing film on the surface of the plurality of semiconductor wafers using a ceramic dresser.

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