JP3660186B2 - Semiconductor device - Google Patents

Description

となる。主半導体素子ＱＡ及び基準半導体素子ＱＢのドレイン〜ソース間電圧をそれぞれＶ_ＤＳＡ及びＶ_ＤＳＢとすると、
Ｖ_ＤＳＢ＝Ｒ_ｏｎＢ×Ｉ_ＤＢ
＝３０［Ω］×５［ｍＡ］＝０．１５［Ｖ］…（５）
Ｖ_ＤＳＡ＝Ｒ_ｏｎＡ×Ｉ_ＤＡ＝３０［ｍΩ］×Ｉ_ＤＡ…（６）
Ｖ_ＤＳＡ−Ｖ_ＤＳＢ＝３０［ｍΩ］（Ｉ_ＤＡ−５［Ａ］） …（７）
となる。Ｉ_ＤＡ＝５［Ａ］のときＶ_ＤＳＢ＝Ｖ_ＤＳＡとなり、Ｉ_ＤＡ＜５［Ａ］ではＶ_ＤＳＡ＜Ｖ_ＤＳＢとなり、Ｉ_ＤＡ＞５［Ａ］ではＶ_ＤＳＡ＞Ｖ_ＤＳＢとなる。
【０００８】
電源電圧ＶＢを基準にして比較器ＣＭＰ１の（＋）及び（−）入力端子電圧を考える。ＣＭＰ１の（−）入力端子には基準半導体素子ＱＢのドレイン〜ソース間電圧Ｖ_ＤＳＢが加えられる。一方、ＣＭＰ１の（＋）入力端子には主半導体素子ＱＡのドレイン〜ソース間電圧を抵抗Ｒ１とＲ２で分圧した電圧が加えられる。即ち抵抗Ｒ１の電圧降下をＶＲ１とすると、
Ｖ_Ｒ１＝Ｖ_ＤＳＡ×（Ｒ１／（Ｒ１＋Ｒ２）） …（８）
で決定される電圧Ｖ_Ｒ１がＣＭＰ１の（＋）入力端子に加えられる。Ｖ_Ｒ１＝Ｖ_ＤＳＢとなるＶ_ＤＳＡをＶ_{ＤＳＡｔｈ}とすると、
Ｖ_ＤＳＢ＝Ｖ_{ＤＳＡｔｈ}×（Ｒ１／（Ｒ１＋Ｒ２）） …（９）
Ｖ_{ＤＳＡｔｈ}−Ｖ_ＤＳＢ＝（Ｒ２／Ｒ１）×Ｖ_ＤＳＢ…（１０）
となる。この例では（１）式より、Ｉ_ＤＡ＝５［Ａ］のときにＶ_ＤＳＡ＝Ｖ_ＤＳＢとなり、（８）式よりＶ_ＤＳＡ＞Ｖ_Ｒ１となるから、この状態ではＶ_Ｒ１＜Ｖ_ＤＳＢとなる。
【０００９】
Ｖ_Ｒ１＜Ｖ_ＤＳＢのときＣＭＰ１の出力は“Ｈ”となり駆動回路１１１内のソーストランジスタＱ５がオンし、シンクトランジスタＱ６がオフして主半導体素子ＱＡ及び基準半導体素子ＱＢのゲートにはチャージポンプ電圧ＶＰが印加され、主半導体素子ＱＡ及び基準半導体素子ＱＢはオンする。
【００１０】
Ｖ_ＤＳＡがＶ_ＤＳＢより大きくなり、（１０）式で示されるＶ_{ＤＳＡｔｈ}より大きくなるとＶ_Ｒ１＞Ｖ_ＤＳＢとなる。このとき、Ｉ_ＤＡは５［Ａ］より大きくなっているので、いわゆる過電流の状態にある。ＣＭＰ１の出力は“Ｌ”となり、駆動回路１１１内のソーストランジスタＱ５はオフし、シンクトランジスタＱ６がオンして主半導体素子ＱＡ及び基準半導体素子ＱＢのゲート回路が接地されるので、主半導体素子ＱＡ及び基準半導体素子ＱＢはオフ動作に入る。オフ動作に入るとＶ_ＤＳＡ及びＶ_ＤＳＢは増大し、Ｉ_ＤＡ及びＩ_ＤＢは減少する。そのためＶ_ＤＳＡとＶ_ＤＳＢの差が少なくなり、一方、（１０）式から判るように、Ｖ_ＤＳＢが大きくなるにつれて、Ｖ_{ＤＳＡｔｈ}−Ｖ_ＤＳＢはどんどん大きくなる。従って、Ｖ_ＤＳＡ及びＶ_ＤＳＢが大きくなるにつれて、Ｖ_Ｒ１＜Ｖ_ＤＳＢが再度成立し、ＣＭＰ１の出力は“Ｈ”となり、主半導体素子ＱＡ及び基準半導体素子ＱＢはオンする。即ち、過電流の状態では主半導体素子ＱＡ及び基準半導体素子ＱＢはオン／オフ動作を行うことになる。オン／オフ動作が継続すると素子に内蔵した温度センサによる過熱遮断機能により主半導体素子ＱＡを遮断する。或いは、オン／オフ継続時間をタイマーで計測することにより、主半導体素子ＱＡを遮断する。このようにして図５に示す電力供給装置は主半導体素子ＱＡを流れる負荷電流が所定値以下であれば、オン動作を継続して負荷に電力を供給し、所定値を超える過電流が流れると一定時間後に主半導体素子ＱＡを遮断して過電流による配線及び電力供給装置自身の焼損を防止している。
【００１１】
【発明が解決しようとする課題】
しかしながら、従来の電源供給装置にあっては、電流検出を行うために、主半導体素子ＱＡのソース電位と基準半導体素子ＱＢのソース電位を比較器ＣＭＰ１で比較している。比較器ＣＭＰ１の（＋）及び（−）入力端子には、主半導体素子ＱＡ及び基準半導体素子ＱＢのソース電位が入力されるが、主半導体素子ＱＡ及び基準半導体素子ＱＢのソース電位は電源電圧ＶＢの範囲で変化する。主半導体素子ＱＡのソース電位については負荷電流が流れる配線のインダクタンスにより電源電圧範囲ＶＢを超えて変化することも起こり得る。従って、ＣＭＰ１及びこのＣＭＰ１の（＋）、（−）入力端子は、電源電圧ＶＢ以上の耐圧を有するものでなければならない。一方、自動車の電源系は現状では１２Ｖ系が主体で、その場合には電源電圧ＶＢの最大値は１８Ｖ程度を考えていれば良い。しかし、最近では負荷電流による電力損失を低減するため、電源電圧の昇圧が検討され、４２Ｖ系の電源が具体的に検討され初めている。この場合には、主半導体素子ＱＡ及び基準半導体素子ＱＢとその駆動回路は４２Ｖ電源系に必要な耐圧まで耐圧を向上させねばならない。
【００１２】
このとき従来の方式では比較器ＣＭＰ１についても同様に耐圧アップが必要となる。比較器ＣＭＰ１等の制御回路はＣＭＯＳプロセス又はＢｉＣＭＯＳプロセスで製造されるが、素子構造の高耐圧化や、これに伴うプロセスの改善が必要となる。高耐圧化の手法は、同じ耐圧を有する素子の数を増やす方法や、ゲート絶縁膜の厚さを厚くする、ガードリングやフィールドプレートを形成する等により、素子そのものの耐圧を向上させる等の手法がある。しかし、素子の数を増やす方法では、チップ面積の増大、プロセス工程の複雑化等が必要となり、部品コストの増大をもたらす。高耐圧化のために、ゲート絶縁膜の厚さを厚くすれば、素子の変換コンダクタンスｇ_ｍ等の性能（電気的特性）は低下する。又高耐圧の環境下で素子を使用することは、素子の信頼性低下の要因にもなる。
【００１３】
電源電圧が高電圧化されても、制御回路は従来の耐圧の素子を使用することが出来れば、部品コストの増大を防ぐことが出来、又素子の信頼性確保の面からも好ましいことである。
【００１４】
本発明の目的は、上記従来の問題点や事情を解決することにあり、電源電圧が従来の１２Ｖ系から、例えば４２Ｖ系のような高電圧電源系に移行した場合でも、第１及び第２の半導体素子の半導体素子の第２の主電極間の電位を比較する比較器として、従来の１２Ｖ系の素子を使用することが可能な半導体装置を提供することである。
【００１５】
本発明の他の目的は、制御回路に用いている比較器の高耐圧化を不要とし、高耐圧化に伴うコストアップを回避することが出来る半導体装置を提供することである。
【００１６】
本発明の更に他の目的は、制御回路に用いている比較器の高電圧環境下での使用を避けることによる信頼性の向上が可能になる半導体装置を提供することである。
【００１７】
【課題を解決するための手段】
本発明の第１の特徴は、直流電源に接続した第１の主電極、負荷に接続した第２の主電極及び制御電極とを有する第１の半導体素子と、第１の半導体素子の第１の主電極に接続した第１の主電極、基準回路に接続した第２の主電極及び第１の半導体素子の制御電極に接続した制御電極とを有する第２の半導体素子と、高位電源端子と低位電源端子とを具備し、第１の半導体素子の第２の主電極に第１の入力端子を接続し、第２の半導体素子の第２の主電極に第２の入力端子を接続した比較器と、この比較器の出力に応じて、第１及び第２の半導体素子の制御電極にそれぞれ制御電圧を供給する駆動回路と、第１の入力端子と低位電源端子間に接続した第１のダイオードと、第２の入力端子と低位電源端子間に抵抗を介して接続した第２のダイオードとから少なくともなる半導体装置であることである。そして、基準回路で決まる所定電流値を上回る過電流が第１の半導体素子を流れたときは、第１の半導体素子をオン／オフ制御して電流振動を生成し、この電流振動により、第１の半導体素子の導通状態を遮断する。ここで、「基準回路」とは、基準抵抗の他に、定電流源、抵抗と定電流源との並列回路等の種々の回路が含まれる。そして、高位電源端子は系の電源電圧に保持され、高位電源端子と低位電源端子との間の電圧は系の電源電圧より小さい電圧に保持されている。又、第１及び第２の半導体素子としては、ＭＯＳ電界効果トランジスタ（ＦＥＴ）、ＭＯＳ静電誘導トランジスタ（ＳＩＴ）等のＭＯＳトランジスタ、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）等の絶縁ゲート型パワーデバイスが使用可能である。或いはエミッタ・スイッチド・サイリスタ（ＥＳＴ）等の種々のＭＯＳ複合型デバイスでもかまわない。これらの半導体素子はｎチャネル型でもｐチャネル型でもかまわない。又「第１の主電極」とは、ＩＧＢＴにおいてはエミッタ電極又はコレクタ電極のいずれか一方、ＭＯＳトランジスタ等の絶縁ゲート型トランジスタにおいてはソース電極又はドレイン電極のいずれか一方を意味する。「第２の主電極」とは、ＩＧＢＴにおいては上記第１の主電極とはならないエミッタ電極又はコレクタ電極のいずれか一方、絶縁ゲート型トランジスタにおいては上記第１の主電極とはならないソース電極又はドレイン電極のいずれか一方を意味する。即ち、第１の主電極が、エミッタ電極であれば、第２の主電極はコレクタ電極であり、第１の主電極がソース電極であれば、第２の主電極はドレイン電極である。又、「制御電極」とはＩＧＢＴ及び絶縁ゲート型トランジスタのゲート電極を意味することは勿論である。
【００１８】
特に、比較器の第１の入力端子と低位電源端子間に第１のダイオードを、第２の入力端子と低位電源端子間に第２のダイオードを接続することにより、これらのダイオードの順方向降下電圧により、比較器の入力電圧をクランプすることが出来る。更に、比較器の高位電源端子と低位電源端子間にツェナーダイオード等の定電圧ダイオードを接続すれば、比較器を高電圧から保護出来る。又、直流電源と高位電源端子間に第３の半導体素子を接続することが好ましい。又、特に、第２の半導体素子の電流容量が第１及び第２の半導体素子の電流容量よりも小さくなるように、それぞれの半導体素子を構成するユニット素子数の比を決定すれば良い。このようなユニット素子数の選択を行って、パワーＩＣの平面パターンのレイアウトを設定することにより、第２の半導体素子の回路構成を小型化出来、更に半導体チップの面積を縮小出来るとともに、高電圧条件対応の半導体装置の製造コストを大幅に削減出来る。
【００１９】
【発明の実施の形態】
次に、図面を参照して、本発明の実施の形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。
【００２０】
本発明の実施の形態に係る高電圧用電流振動型遮断機能付き半導体装置は、図１に示すように、外部入力端子Ｔ_１に接続された第１の主電極ＤＡ、第１の外部出力端子Ｔ_３に接続された第２の主電極ＳＡ及び制御電極ＧＡとを有する第１の半導体素子ＱＡと、外部入力端子Ｔ_１に接続された第１の主電極ＤＢと、第２の外部出力端子Ｔ_３に接続した第２の主電極ＳＢ及び第１の半導体素子ＱＡの制御電極ＧＡに接続した制御電極ＧＢとを有する第２の半導体素子ＱＢと、第２の半導体素子ＱＢの第２の主電極ＳＢと第２の外部出力端子Ｔ_３を経由して接続された基準回路としての基準抵抗Ｒｒと、高位電源端子Ｎ_Ｈと低位電源端子Ｎ_Ｌとを具備し、第１の半導体素子ＱＡの第２の主電極に第１の入力端子を接続し、第２の半導体素子ＱＢの第２の主電極に第２の入力端子を接続した比較器ＣＭＰ１と、比較器ＣＭＰ１の出力に応じて、第１の半導体素子ＱＡ及び第２の半導体素子ＱＢの制御電極ＧＡ，ＧＢにそれぞれ制御電圧を供給する駆動回路１１１と、第１の入力端子と低位電源端子Ｎ_Ｌ間に接続された第１のダイオードＤ２１と、第２の入力端子と低位電源端子Ｎ_Ｌ間に抵抗Ｒ２８を介して接続された第２のダイオードＤ２２とから少なくとも構成されている。そして、第１の外部出力端子Ｔ_３に接続される負荷１０２に流れる電流が、基準回路（基準抵抗）Ｒｒで決まる所定の電流値を上回ったときには、第１の半導体素子ＱＡをオン／オフ制御して電流振動を生成し、この電流振動により、外部入力端子Ｔ_１と第１の外部出力端子Ｔ_３間の導通状態を遮断する。
【００２１】
なお、この例では、「基準回路」として基準抵抗Ｒｒを用いたが、基準抵抗Ｒｒの他に、定電流源（定電流回路）、或いは抵抗と定電流回路との並列回路等を使用することが可能である。基準回路として基準抵抗Ｒｒを用いる場合は、基準抵抗Ｒを電流容量比ｎ（この例ではｎ＝１０００）で割った値、即ちＲｒ／ｎ＝Ｒｒ／１０００と負荷抵抗の大小関係を比較して、負荷抵抗がＲｒ／ｎより小さくなったら、第１の半導体素子ＱＡをオン／オフ動作させる。一方、基準回路として定電流源Ｉ_ｒｅｆを用いる場合は、Ｉ_ｒｅｆを電流容量比倍した電流値、即ちｎ×Ｉ_ｒｅｆ＝１０００×Ｉ_ｒｅｆと負荷電流の大小関係を比較して、ｎ×Ｉ_ｒｅｆより負荷電流が大きくなったら、第１の半導体素子ＱＡをオン／オフ動作させる。基準回路として抵抗と定電流源との並列回路で構成した場合は、抵抗基準と電流基準の合成された特性となる。これらの基準回路は、負荷側の異常状態を何により判定するかで使い分けるのが好ましい。
【００２２】
図２に示すように、第１の半導体素子ＱＡのゲート電極ＧＡとソース電極_ＳＡとの間には、加熱遮断回路１２０を接続することが好ましい（なお、電流振動の振動の回数を計測する方式を採用すれば、加熱遮断回路１２０による感熱遮断機能は必須ではない。）。図２に示す加熱遮断回路１２０は、第１の半導体素子ＱＡのゲート電極ＧＡに接続された過熱遮断用ＭＯＳトランジスタＱＳと、この過熱遮断用ＭＯＳトランジスタＱＳのゲート電極に信号を入力するラッチ回路１２２と、ラッチ回路１２２の状態を制御する温度センサ１２１等から構成されている。つまり、半導体チップ１１０の表面温度が規定以上の温度まで上昇したことが温度センサ１２１によって検出された場合には、温度センサ１２１からの検出情報により、ラッチ回路１２２の状態が遷移し、この状態がラッチ回路１２２に保持される。この結果、過熱遮断用ＭＯＳトランジスタＱＳがオン動作となり、第１の半導体素子ＱＡのゲート電極ＧＡとソース電極ＳＡ間を短絡し、第１の半導体素子ＱＡを強制的にオフ制御する。
【００２３】
ここで、温度センサ１２１はポリシリコン等で構成した４個のダイオードが直列接続されてなり、温度センサ１２１は第１の半導体素子ＱＡの近傍に集積化されている。第１の半導体素子ＱＡの接合温度が上昇するにつれて、半導体チップの表面温度が上昇し、温度センサ１２１の４個のダイオードの順方向降下電圧が次第に低下する。そして、４個のダイオードの順方向降下電圧の総和が、ｎＭＯＳトランジスタＱ５１のゲート電位が“Ｌ”レベルとされる電位まで下がると、ｎＭＯＳトランジスタＱ５１がオン状態からターンオフする。これにより、ｎＭＯＳトランジスタＱ５４のゲート電位が、第１の半導体素子ＱＡのゲート制御端子Ｇの電位にプルアップされ、ｎＭＯＳトランジスタＱ５４がターンオンする。このため、ｎＭＯＳトランジスタＱ５３がターンオフし、ｎＭＯＳトランジスタＱ５２がオフ状態からターンオンして、ラッチ回路１２２に“１”がラッチされることとなる。このとき、ラッチ回路１２２の出力が“Ｈ”レベルとなって、過熱遮断用素子ＱＳがオフ状態からターンオンする。この結果、第１の半導体素子ＱＡの真のゲートＴＧと第２主電極（ソース電極）ＳＡ間が短絡されて、第１の半導体素子ＱＡがオン状態からターンオフして、過熱遮断されることとなる。
【００２４】
本発明の高電圧条件に用いる半導体装置は、図１に示すように、第１の半導体素子ＱＡとこの第１の半導体素子の制御回路とを同一基板上に集積化した半導体集積回路（パワーＩＣ）である。制御回路は、第１の半導体素子ＱＡに接続された負荷１０２中を流れる電流を検知して、異常電流発生時には第１の半導体素子ＱＡとをオン／オフ制御して電流振動を生成し、この電流振動により、第１の半導体素子ＱＡを遮断する機能を有する。パワーＩＣを構成する基板として、セラミック、ガラスエポキシ等の絶縁性基板や絶縁金属基板等を用い、ハイブリッドＩＣの形態でも良い。しかし、より好ましくは、同一半導体基板（同一チップ）上にモノリシックに集積化した「モノリシックパワーＩＣ」とすべきである。
【００２５】
第１の半導体素子ＱＡとしては、例えば、ＤＭＯＳ構造、ＶＭＯＳ構造、或いはＵＭＯＳ構造のパワーＭＯＳトランジスタやこれらと類似な構造のＭＯＳＳＩＴが使用可能である。又、ＥＳＴ、ＭＯＳ制御サイリスタ（ＭＣＴ）等のＭＯＳ複合型デバイスでも良い。更に、ＩＧＢＴ等の他の絶縁ゲート型パワーデバイスが使用可能である。更に、常にゲートを逆バイアスで使うのであれば、接合型ＭＯＳトランジスタ、接合型ＳＩＴや静電誘導サイリスタ（ＳＩサイリスタ）等も使用可能である。この高電圧用パワーＩＣに用いる第１の半導体素子ＱＡはｎチャネル型でもｐチャネル型でもかまわない。即ち、本発明の半導体装置は、ｎチャネル型及びｐチャネル型の両方が存在する。以下の説明においては、ｎチャネル型の半導体装置をハイサイド（High-Side)素子として用いた場合について説明する。
【００２６】
この第１の半導体素子ＱＡは、例えば、複数個のユニット素子（単位セル）が並列接続されたマルチ・チャネル構造のパワーデバイスを採用すれば良い。そして、この第１の半導体素子ＱＡに並列接続されるように、第２の半導体素子ＱＢが、第１の半導体素子ＱＡに隣接する位置に配置されている。この第２の半導体素子ＱＢには、加熱遮断回路１２０は必須ではない。第２の半導体素子ＱＢが、第１の半導体素子ＱＡと同一プロセスで、隣接位置に配置されているので、温度ドリフトやロット間の不均一性の影響による互いの電気的特性のバラツキを除去（削減）できる。第２の半導体素子ＱＢの電流容量が第１の半導体素子ＱＡの電流容量よりも小さくなるように、第２の半導体素子ＱＢを構成する並列接続のユニット素子数を調整している。例えば、第２の半導体素子ＱＢのユニット素子数１に対して、第１の半導体素子ＱＡのユニット素子数を１０００となるように構成することにより、第２の半導体素子ＱＢと第１の半導体素子ＱＡのチャネル幅Ｗの比を１：１０００としている。又、温度センサ１２１は、第２の半導体素子ＱＢ及び第１の半導体素子ＱＡの上部に形成された層間絶縁膜の上部に堆積されたポリシリコン薄膜等で構成した複数個のダイオードが直列接続により構成され、温度センサ１２１を第１の半導体素子ＱＡのチャネル領域の近傍の位置に集積化している。
【００２７】
図１に基づいて本発明の半導体装置の動作を説明する。半導体チップ１１０の外部にある作動スイッチＳＷ１をオンすると外部入力端子Ｔ２を経由してオン信号が駆動回路１１１に入力され、図示されていないチャージポンプ回路で昇圧された電圧ＶＰが抵抗Ｒ８，Ｒ７を経由して第１及び第２の半導体素子ＱＡ，ＱＢのゲートＴＧに加えられ、第１の半導体素子ＱＡ及び第２の半導体素子ＱＢはオンする。電圧ＶＰの値は、例えば電源電圧をＶＢとするとＶＢ＋１０Ｖである。
【００２８】
第１の半導体素子ＱＡ，第２の半導体素子ＱＢを構成するＭＯＳトランジスタユニット素子１個当たりのオン抵抗をＲ_ｆｅｔとし、第１の半導体素子ＱＡ，第２の半導体素子ＱＢのオン抵抗をそれぞれＲ_ｏｎＡ，Ｒ_ｏｎＢとすると第１の半導体素子ＱＡ及び第２の半導体素子ＱＢが完全にオンしている場合、即ちオーミック領域では、上述した（１）式から（３）式が成立する。Ｒ_ｏｎＡは通常３０[ｍΩ]位である。このときＲ_ｏｎＢ＝３０[Ω]となる。ここで、Ｒｒ＝８．４[ｋΩ]とする。第１の半導体素子ＱＡ及び第２の半導体素子ＱＢのドレイン電流をそれぞれＩ_ＤＡ及びＩ_ＤＢとし、電源電圧ＶＢ＝４２[Ｖ]とすると、

となる。第１の半導体素子ＱＡ及び第２の半導体素子ＱＢのドレイン〜ソース間電圧をそれぞれＶ_ＤＳＡ及びＶ_ＤＳＢとすると、前述した（５）式〜（７）式が成立する。
【００２９】
Ｉ_ＤＡ＝５［Ａ］のときＶ_ＤＳＢ＝Ｖ_ＤＳＡとなり、Ｉ_ＤＡ＜５［Ａ］ではＶ_ＤＳＡ＜Ｖ_ＤＳＢとなり、Ｉ_ＤＡ ＞ ５［Ａ］ではＶ_ＤＳＡ＞Ｖ_ＤＳＢとなる。
【００３０】
スイッチＳＷ１がオンするとｐｎｐトランジスタＱ１１がオンし、比較器ＣＭＰ１の高位電源端子Ｎ_Ｈに電源電圧が印加される。比較器ＣＭＰ１の低位電源端子Ｎ_Ｌは抵抗Ｒ２７を介して接地され、Ｎ_ＨとＮ_Ｌの間はツェナーダイオードＺＤ２が接続されているので、ＺＤ２のツェナー電圧を１２［Ｖ］とするとＣＭＰ１の高位電源端子と低位電源端子間の電圧は１２［Ｖ］となり、電源電圧ＶＢ＝４２［Ｖ］より小さい電圧に保持されることになる。ＣＭＰ１の低位電源端子Ｎ_Ｌの電位Ｖ_ＮＬは、

に保たれる。
【００３１】
第１の半導体素子ＱＡのドレイン電流Ｉ_ＤＡが５［Ａ］以下のとき、Ｖ_ＤＳＡ＜Ｖ_ＤＳＢとなるため比較器ＣＭＰ１の出力は“Ｈ”となり、ｐｎｐトランジスタＱ１２はオフして、駆動回路１１１は第１の半導体素子ＱＡ及び第２の半導体素子ＱＢをオンし続ける。一方、第１の半導体素子ＱＡのドレイン電流Ｉ_ＤＡが５［Ａ］を超えるとＶ_ＤＳＡ＞Ｖ_ＤＳＢとなるため比較器ＣＭＰ１の出力“Ｌ”となり、ｐｎｐトランジスタＱ１２がオンする。このため、駆動回路１１１のソーストランジスタＱ５がオフし、シンクトランジスタＱ６がオンして第１の半導体素子ＱＡ、第２の半導体素子ＱＢのゲートは抵抗Ｒ７、Ｒ８を介して接地される。このため、第１の半導体素子ＱＡ、第２の半導体素子ＱＢはオフ動作に入る。即ち、５［Ａ］が電源電圧ＶＢ＝４２［Ｖ］のときの過電流判定値となる。このときの負荷抵抗は４２［Ｖ］／５［Ａ］＝８．４［Ω］で、これはｎ×Ｒｒ＝１０００×８．４［ｍΩ］に等しい。即ち、８．４［Ω］が過負荷判定値となり、負荷抵抗が８．４［Ω］以下になると第１の半導体素子ＱＡ、第２の半導体素子ＱＢはオフ動作に入る。過負荷判定値８．４［Ω］は電源電圧ＶＢに関わらず一定である。これは基準回路として抵抗を用いているからであり、基準回路として定電流回路を用いれば、過電流判定値は電源電圧ＶＢに関わらず一定になる。
【００３２】
第１の半導体素子ＱＡ、第２の半導体素子ＱＢがオフ動作に入ると第１の半導体素子ＱＡ、第２の半導体素子ＱＢのドイン〜ソース間電圧Ｖ_ＤＳＡ、Ｖ_ＤＳＢは増大する。第１の半導体素子ＱＡ、第２の半導体素子ＱＢのソース電位をＶ_ＳＡ、Ｖ_ＳＢとするとＶ_ＳＡ、Ｖ_ＳＢは接地電位ＧＮＤに向かって低下して行く。駆動回路１１１のシンクトランジスタＱ６がオンするため第１の半導体素子ＱＡのソース→抵抗Ｒ８１→抵抗Ｒ２６→ダイオードＤ１→抵抗Ｒ８→シンクトランジスタＱ６→ＧＮＤの経路で電流が流れ、ＣＭＰ１の（＋）入力端子電位を低下させるヒステリシス効果が発生し、ＣＭＰ１の出力は安定して “Ｌ”を維持する。ＣＭＰ１の入力端子電位も Ｖ_ＳＡ、Ｖ_ＳＢの低下に伴って低下して行くが、ＣＭＰ１（＋）入力端子電位はＣＭＰ１低位電源端子の電位Ｖ_ＮＬとダイオードＤ２１によりクランプされ、Ｖ_ＮＬ−０．７［Ｖ］（Ｄ２１の順方向電圧降下）以下には下がらない。Ｖ_ＮＬ＝ＶＢ−１２．３［Ｖ］だから、ＣＭＰ１（＋）入力端子電位はＶＢ−１３［Ｖ］以下には下がらない。一方、ＣＭＰ１の（−）入力端子もダイオードＤ２２によりクランプされるが、抵抗Ｒ２８を介してクランプされるため、ＣＭＰ１の（−）入力端子電圧はＲ２８の電圧降下分だけ、（＋）入力端子電位より低い電位にクランプされる。即ち（−）入力端子のクランプ電位はＶＢ−１３［Ｖ］−（Ｒ２８電圧降下分）となる。このためＶ_ＳＡ、Ｖ_ＳＢの電位が低下してクランプ電圧がＣＭＰ１に入力されるようになるとＣＭＰ１の出力は負荷側の状態に関わらず、“Ｈ”となり、駆動回路１１１は再び第１の半導体素子ＱＡ、第２の半導体素子ＱＢをオンさせる。Ｖ_ＳＡ、Ｖ_ＳＢがクランプ電圧を下回ると制御回路及びＭＯＳトランジスタの遅れ時間後に第１の半導体素子ＱＡ、第２の半導体素子ＱＢはオンし、Ｖ_ＳＡ、Ｖ_ＳＢがクランプ電圧を上回ると制御回路及びＭＯＳトランジスタの遅れ時間後に第１の半導体素子ＱＡ、第２の半導体素子ＱＢはオフするため、オン／オフ動作を続けることになる。オン／オフ動作が一定時間継続すると第１の半導体素子ＱＡの過熱遮断により、又はタイマー処理により第１の半導体素子ＱＡ及び第２の半導体素子ＱＢを遮断する。
【００３３】
（他の実施の形態）
上記の実施の形態による開示の一部を成す論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。
【００３４】
例えば、図１はｎチャネルのハイサイドの回路を示したが、図３に示すようなｐチャネルのハイサイドの回路も、ｐチャネル・第１の半導体素子ＱＡ（ｐ）を用いれば、ほぼ同様な回路構成で実現可能である。
【００３５】
又、一定の場合は、図４に示すように図１に示したツェナーダイオードＺＤ２を省略した構成でも良い。
【００３６】
このように、本発明はここでは記載していない様々な実施の形態等を含むことは勿論である。従って、本発明の技術的範囲は上記の説明から妥当な特許請求の範囲に係る発明特定事項によってのみ定められるものである。
【００３７】
【発明の効果】
本発明の半導体装置によれば、電源電圧が従来の１２Ｖ系から、例えば４２Ｖ系のような高電圧電源系に移行した場合でも、第１及び第２の半導体素子の半導体素子の第２の主電極間の電位を比較する比較器として、従来の１２Ｖ系の素子を使用することが可能となる。これにより、比較器の高耐圧化が不要となり、高耐圧化に伴うコストアップを回避することが出来る。
【００３８】
更に、本発明の半導体装置によれば、比較器の高電圧環境下での使用を避けることによる信頼性の向上が可能になる。
【図面の簡単な説明】
【図１】本発明の実施の形態に係る高電圧用の半導体装置の回路構成図である（ｎチャネルの場合）。
【図２】本発明の実施の形態に係る半導体装置に集積化する加熱遮断回路の回路構成図である。
【図３】本発明の他の実施の形態に係る高電圧用の半導体装置の回路構成図である（ｐチャネルの場合）。
【図４】本発明の更に他の実施の形態に係る高電圧用の半導体装置の回路構成図である（ｐチャネルの場合）。
【図５】従来の電源供給制御装置の回路構成図である。
【符号の説明】
１０１ 低電圧電源
１０２ 負荷
１１０、１１８，１２１，１２２ 半導体チップ
１１１ 駆動回路
１２０ 加熱遮断回路
１９１ 高電圧電源
ＣＭＰ１ 比較器
Ｄ１，Ｄ２１，Ｄ２２ ダイオード
ＱＡ 第１の半導体素子
ＱＢ 第２の半導体素子
Ｑ７１，Ｑ７２，Ｑ１３１，Ｑ２２１，Ｑ３１１，Ｑ３１２ ＭＯＳトランジスタ
ＲＧ ゲート抵抗
Ｒ１，Ｒ２，Ｒ５，Ｒ７，Ｒ８，Ｒ１０，Ｒ２１，Ｒ２２，Ｒ８１，Ｒ８２ 抵抗
Ｒｒ 基準抵抗
Ｔ_１，Ｔ_２，Ｔ_３，Ｔ_４ 入出力端子
ＺＤ１，ＺＤ２ ツェナーダイオード[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for a high voltage power supply control device.
[0002]
[Prior art]
An example of a semiconductor device (power semiconductor device) used in a conventional power supply control device is shown in FIG. The power supply control device shown in FIG. 5 is a device that selectively supplies power from a battery to each load in an automobile and controls power supply to the load by the main semiconductor element QA. The main semiconductor element QA is a temperature sensor built-in transistor QA. The drain terminal D of the main semiconductor element QAQA is connected to the power supply 101 that supplies the output voltage VB, and the load 102 is connected to the source terminal SA of the main semiconductor element QA. Here, the load 102 corresponds to a load used in an automobile, such as an automobile headlight, taillight, wiper motor, and power window motor.
[0003]
The power supply device shown in FIG. 5 has an overcurrent detection / protection function. The main semiconductor element QA has a terminal T_SA load 102 is connected via Further, a reference semiconductor element (reference MOS transistor) QB is connected in parallel to the main semiconductor element QA, and the reference semiconductor element QB has a terminal T_RA resistor Rr is connected via In the circuit configuration shown in FIG. 5, the drain-source voltage of the main semiconductor element QA generated by the load current flowing through the main semiconductor element QA is compared with the drain-source voltage of the reference semiconductor element QB determined by the resistor Rr. It is always checked whether or not an overcurrent exceeding a preset overcurrent determination value has flowed by comparing with the device CMP1. When an overcurrent flows, the drive circuit 111 is controlled to turn on / off the main semiconductor element QA and the reference semiconductor element QB. When the on / off operation continues for a certain time, the main semiconductor element QA is cut off. As a result, the wiring and the semiconductor device are prevented from burning due to overcurrent.
[0004]
The power supply apparatus shown in FIG. 5 will be described in detail below. The main semiconductor element QA and the reference semiconductor element QB are configured by connecting in parallel a plurality of unit elements each having nMOS transistors having the same characteristics and structure. When the number of unit elements of the main semiconductor element QA and the reference semiconductor element QB is N1 and N2, respectively, N1 >> N2 is established. In this example, N1: N2 = 1000: 1. The drain electrode D of the main semiconductor element QA and the drain electrode DB of the reference semiconductor element QB are connected to each other, and the gate electrodes are also connected to each other. A terminal T is connected between the source SB of the reference semiconductor element QB and the ground potential GND._RA resistor Rr is connected via A constant current circuit or a circuit in which a constant current circuit and a resistor are connected in parallel may be connected instead of the resistor Rr. FIG. 5 illustrates an example in which the resistor Rr is connected.
[0005]
Circuits in a range surrounded by a dotted line in FIG. 5 are usually integrated on the same semiconductor chip 110 and monolithically integrated as a power IC. Outside the semiconductor chip 110, there is a switch SW1 having one end connected to the resistor R10 and the other end connected to the ground potential GND, and the other end of the resistor R10 is connected to the power source VB. The potential at the connection point of the resistor R10 and the switch SW1 is the terminal T_GIs applied to the drive circuit 111 inside the semiconductor chip 110, and when the switch SW1 is turned on, the drive circuit 111 has a voltage VP boosted by a charge pump circuit (not shown) at the gates of the main semiconductor element QA and the reference semiconductor element QB. Is applied to turn on the main semiconductor element QA and the reference semiconductor element QB. For example, when the power supply voltage is VB, VP = VB + 10V.
[0006]
The on-resistance per unit element of the MOS transistors constituting the main semiconductor element QA and the reference semiconductor element QB is R_fetAnd the on-resistances of the main semiconductor element QA and the reference semiconductor element QB are R_onA, R_onBThen, when the main semiconductor element QA and the reference semiconductor element QB are completely turned on, that is, in the ohmic region,
R_onA= R_fet/ N1 (1)
R_onB= R_fet/N2...(2)
R_onA= R_onB(N2 / N1) = R_onB/1000...(3)
It becomes. On-resistance R of main semiconductor element QA_onAIs usually about 30 [mΩ]. At this time, the on-resistance R of the reference semiconductor element QB_onB= 30 [Ω].
[0007]
The reference resistance Rr is 2.4 [kΩ]. The drain currents of the main semiconductor element QA and the reference semiconductor element QB are respectively I_DAAnd I_DBAssuming that the power supply voltage VB = 12 [V],

It becomes. The drain-source voltages of the main semiconductor element QA and the reference semiconductor element QB are V, respectively._DSAAnd V_DSBThen,
V_DSB= R_onB× I_DB
= 30 [Ω] x 5 [mA] = 0.15 [V] (5)
V_DSA= R_onA× I_DA= 30 [mΩ] x I_DA(6)
V_DSA-V_DSB= 30 [mΩ] (I_DA-5 [A]) (7)
It becomes. I_DAWhen V = 5 [A], V_DSB= V_DSAAnd I_DA<5 [A] for V_DSA<V_DSBAnd I_DA> 5 [A] for V_DSA> V_DSBIt becomes.
[0008]
Consider the (+) and (−) input terminal voltages of the comparator CMP1 with reference to the power supply voltage VB. The (−) input terminal of CMP1 has a drain-source voltage V of the reference semiconductor element QB._DSBIs added. On the other hand, a voltage obtained by dividing the drain-source voltage of the main semiconductor element QA by the resistors R1 and R2 is applied to the (+) input terminal of CMP1. That is, when the voltage drop of the resistor R1 is VR1,
V_R1= V_DSA× (R1 / (R1 + R2)) (8)
The voltage V determined by_R1Is added to the (+) input terminal of CMP1. V_R1= V_DSBV becomes_DSAV_DSAthThen,
V_DSB= V_DSAth× (R1 / (R1 + R2)) (9)
V_DSAth-V_DSB= (R2 / R1) × V_DSB(10)
It becomes. In this example, from equation (1), I_DA= 5 [A] when V_DSA= V_DSBFrom equation (8), V_DSA> V_R1Therefore, in this state, V_R1<V_DSBIt becomes.
[0009]
V_R1<V_DSBAt this time, the output of CMP1 becomes “H”, the source transistor Q5 in the drive circuit 111 is turned on, the sink transistor Q6 is turned off, and the charge pump voltage VP is applied to the gates of the main semiconductor element QA and the reference semiconductor element QB. The main semiconductor element QA and the reference semiconductor element QB are turned on.
[0010]
V_DSAIs V_DSBV becomes larger and is expressed by the equation (10)._DSAthV becomes larger_R1> V_DSBIt becomes. At this time, I_DAIs larger than 5 [A], and is in a so-called overcurrent state. The output of CMP1 is “L”, the source transistor Q5 in the drive circuit 111 is turned off, the sink transistor Q6 is turned on, and the gate circuits of the main semiconductor element QA and the reference semiconductor element QB are grounded. Then, the reference semiconductor element QB enters an off operation. When entering the off operation, V_DSAAnd V_DSBIncreases and I_DAAnd I_DBDecrease. Therefore V_DSAAnd V_DSBOn the other hand, as can be seen from equation (10), V_DSBAs becomes larger, V_DSAth-V_DSBIt gets bigger and bigger. Therefore, V_DSAAnd V_DSBAs becomes larger, V_R1<V_DSBIs established again, the output of CMP1 becomes "H", and the main semiconductor element QA and the reference semiconductor element QB are turned on. That is, in the overcurrent state, the main semiconductor element QA and the reference semiconductor element QB perform on / off operations. When the on / off operation continues, the main semiconductor element QA is cut off by the overheat cutoff function by the temperature sensor built in the element. Alternatively, the main semiconductor element QA is shut off by measuring the on / off duration with a timer. In this way, when the load current flowing through the main semiconductor element QA is equal to or less than a predetermined value, the power supply device shown in FIG. 5 continues to turn on and supplies power to the load, and an overcurrent exceeding the predetermined value flows. After a certain time, the main semiconductor element QA is cut off to prevent the wiring and the power supply device itself from being burned out due to overcurrent.
[0011]
[Problems to be solved by the invention]
However, in the conventional power supply apparatus, in order to detect current, the source potential of the main semiconductor element QA and the source potential of the reference semiconductor element QB are compared by the comparator CMP1. The source potentials of the main semiconductor element QA and the reference semiconductor element QB are input to the (+) and (−) input terminals of the comparator CMP1, but the source potentials of the main semiconductor element QA and the reference semiconductor element QB are the power supply voltage VB. It varies in the range. The source potential of the main semiconductor element QA may change beyond the power supply voltage range VB due to the inductance of the wiring through which the load current flows. Accordingly, the CMP1 and the (+) and (−) input terminals of the CMP1 must have a breakdown voltage equal to or higher than the power supply voltage VB. On the other hand, the power supply system of automobiles is mainly a 12V system at present, and in that case, the maximum value of the power supply voltage VB may be about 18V. However, recently, in order to reduce power loss due to load current, boosting of the power supply voltage has been studied, and a 42V power supply has been specifically studied. In this case, the main semiconductor element QA, the reference semiconductor element QB, and the driving circuit thereof must improve the breakdown voltage to the breakdown voltage required for the 42V power supply system.
[0012]
At this time, in the conventional method, the breakdown voltage of the comparator CMP1 needs to be increased as well. A control circuit such as the comparator CMP1 is manufactured by a CMOS process or a BiCMOS process. However, it is necessary to increase the breakdown voltage of the element structure and improve the process associated therewith. The method of increasing the breakdown voltage is to increase the number of elements having the same breakdown voltage, or to increase the breakdown voltage of the element itself by increasing the thickness of the gate insulating film, forming a guard ring or a field plate, etc. There is. However, the method of increasing the number of elements necessitates an increase in chip area, a complicated process step, and the like, resulting in an increase in component costs. If the thickness of the gate insulating film is increased to increase the breakdown voltage, the conversion conductance g of the element is increased._mSuch performance (electrical characteristics) is degraded. In addition, using the device in a high withstand voltage environment causes a decrease in the reliability of the device.
[0013]
Even if the power supply voltage is increased, if the control circuit can use a conventional withstand voltage element, it is possible to prevent an increase in the component cost and also from the viewpoint of ensuring the reliability of the element. .
[0014]
An object of the present invention is to solve the above-mentioned conventional problems and circumstances, and even when the power supply voltage is shifted from the conventional 12V system to a high voltage power supply system such as a 42V system, the first and the second. It is an object of the present invention to provide a semiconductor device capable of using a conventional 12V element as a comparator for comparing potentials between second main electrodes of a semiconductor element.
[0015]
Another object of the present invention is to provide a semiconductor device that does not require a high breakdown voltage of a comparator used in a control circuit and can avoid an increase in cost due to the high breakdown voltage.
[0016]
Still another object of the present invention is to provide a semiconductor device capable of improving reliability by avoiding use of a comparator used in a control circuit in a high voltage environment.
[0017]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a first semiconductor element having a first main electrode connected to a DC power source, a second main electrode connected to a load, and a control electrode; A second semiconductor element having a first main electrode connected to the main electrode, a second main electrode connected to the reference circuit, and a control electrode connected to the control electrode of the first semiconductor element; a high-level power supply terminal; A low-level power supply terminal, a first input terminal connected to the second main electrode of the first semiconductor element, and a second input terminal connected to the second main electrode of the second semiconductor element , A drive circuit for supplying a control voltage to the control electrodes of the first and second semiconductor elements according to the output of the comparator, and a first input terminal connected between the first input terminal and the lower power supply terminal, respectively. A diode and a second die connected via a resistor between the second input terminal and the lower power supply terminal It is that at least comprising a semiconductor device and a over de. When an overcurrent exceeding a predetermined current value determined by the reference circuit flows through the first semiconductor element, the first semiconductor element is controlled to be turned on / off to generate a current vibration. The conduction state of the semiconductor element is cut off. Here, the “reference circuit” includes various circuits such as a constant current source and a parallel circuit of a resistor and a constant current source in addition to the reference resistor. The high-level power supply terminal is held at the system power supply voltage, and the voltage between the high-level power supply terminal and the low-level power supply terminal is held at a voltage smaller than the system power supply voltage. The first and second semiconductor elements include MOS field effect transistors (FETs), MOS transistors such as MOS static induction transistors (SIT), and insulated gate power devices such as insulated gate bipolar transistors (IGBT). It can be used. Alternatively, various MOS composite devices such as an emitter-switched thyristor (EST) may be used. These semiconductor elements may be n-channel type or p-channel type. The “first main electrode” means either an emitter electrode or a collector electrode in the IGBT, and either a source electrode or a drain electrode in an insulated gate transistor such as a MOS transistor. The “second main electrode” means either an emitter electrode or a collector electrode that does not become the first main electrode in the IGBT, or a source electrode that does not become the first main electrode in the insulated gate transistor. It means either one of the drain electrodes. That is, if the first main electrode is an emitter electrode, the second main electrode is a collector electrode, and if the first main electrode is a source electrode, the second main electrode is a drain electrode. The “control electrode” naturally means the gate electrode of the IGBT and the insulated gate transistor.
[0018]
In particular, by connecting a first diode between the first input terminal and the lower power supply terminal of the comparator and a second diode between the second input terminal and the lower power supply terminal, the forward drop of these diodes is achieved. The input voltage of the comparator can be clamped by the voltage. Further, if a constant voltage diode such as a Zener diode is connected between the high level power supply terminal and the low level power supply terminal of the comparator, the comparator can be protected from a high voltage. Further, it is preferable to connect the third semiconductor element between the DC power supply and the high-level power supply terminal. In particular, the ratio of the number of unit elements constituting each semiconductor element may be determined so that the current capacity of the second semiconductor element is smaller than the current capacity of the first and second semiconductor elements. By selecting the number of unit elements and setting the layout of the planar pattern of the power IC, the circuit configuration of the second semiconductor element can be reduced, the area of the semiconductor chip can be further reduced, and the high voltage can be reduced. The manufacturing cost of the semiconductor device that meets the conditions can be greatly reduced.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.
[0020]
As shown in FIG. 1, the semiconductor device with a high-voltage current oscillation type cutoff function according to the embodiment of the present invention has an external input terminal T₁The first main electrode DA connected to the first external output terminal T₃A first semiconductor element QA having a second main electrode SA and a control electrode GA connected to each other, and an external input terminal T₁The first main electrode DB connected to the second external output terminal T₃The second semiconductor electrode QB having the second main electrode SB connected to the control electrode and the control electrode GB connected to the control electrode GA of the first semiconductor element QA, and the second main electrode SB of the second semiconductor element QB And a second external output terminal T₃And a reference resistor Rr as a reference circuit connected via a high-level power supply terminal N_HAnd low power supply terminal N_LA comparator having a first input terminal connected to the second main electrode of the first semiconductor element QA and a second input terminal connected to the second main electrode of the second semiconductor element QB The driving circuit 111 that supplies control voltages to the control electrodes GA and GB of the first semiconductor element QA and the second semiconductor element QB according to the output of the CMP1 and the comparator CMP1, respectively, and the first input terminal and the lower level Power terminal N_LA first diode D21 connected in between, a second input terminal and a low power supply terminal N_LIt comprises at least a second diode D22 connected between them through a resistor R28. The first external output terminal T₃When the current flowing through the load 102 connected to the current exceeds a predetermined current value determined by the reference circuit (reference resistance) Rr, the first semiconductor element QA is controlled to be turned on / off to generate a current vibration. External input terminal T due to vibration₁And a first external output terminal T₃The conduction state between is cut off.
[0021]
In this example, the reference resistor Rr is used as the “reference circuit”. However, in addition to the reference resistor Rr, a constant current source (constant current circuit) or a parallel circuit of a resistor and a constant current circuit is used. Is possible. When the reference resistor Rr is used as the reference circuit, a value obtained by dividing the reference resistor R by the current-capacitance ratio n (n = 1000 in this example), that is, Rr / n = Rr / 1000 is compared with the magnitude relation of the load resistance. When the load resistance becomes smaller than Rr / n, the first semiconductor element QA is turned on / off. On the other hand, a constant current source I as a reference circuit_refWhen using_refIs a current value obtained by multiplying the current capacity ratio, that is, n × I_ref= 1000 × I_refAnd the magnitude relationship between the load current and n × I_refWhen the load current becomes larger, the first semiconductor element QA is turned on / off. When the reference circuit is composed of a parallel circuit of a resistor and a constant current source, the combined characteristic of the resistance reference and the current reference is obtained. These reference circuits are preferably used depending on what determines the abnormal state on the load side.
[0022]
As shown in FIG. 2, the gate electrode GA and the source electrode of the first semiconductor element QA_SAIt is preferable to connect a heat shut-off circuit 120 between them (if the method of measuring the number of vibrations of current vibration is employed, the thermal shut-off function by the heat shut-off circuit 120 is not essential). The heating cutoff circuit 120 shown in FIG. 2 includes an overheat cutoff MOS transistor QS connected to the gate electrode GA of the first semiconductor element QA, and a latch circuit 122 that inputs a signal to the gate electrode of the overheat cutoff MOS transistor QS. And a temperature sensor 121 for controlling the state of the latch circuit 122. That is, when the temperature sensor 121 detects that the surface temperature of the semiconductor chip 110 has risen to a predetermined temperature or higher, the state of the latch circuit 122 changes based on detection information from the temperature sensor 121, and this state is It is held in the latch circuit 122. As a result, the overheat cutoff MOS transistor QS is turned on, the gate electrode GA and the source electrode SA of the first semiconductor element QA are short-circuited, and the first semiconductor element QA is forcibly controlled to be turned off.
[0023]
Here, the temperature sensor 121 is formed by connecting four diodes made of polysilicon or the like in series, and the temperature sensor 121 is integrated in the vicinity of the first semiconductor element QA. As the junction temperature of the first semiconductor element QA increases, the surface temperature of the semiconductor chip increases, and the forward voltage drop of the four diodes of the temperature sensor 121 gradually decreases. When the sum of the forward drop voltages of the four diodes falls to a potential at which the gate potential of the nMOS transistor Q51 is set to the “L” level, the nMOS transistor Q51 is turned off from the on state. As a result, the gate potential of the nMOS transistor Q54 is pulled up to the potential of the gate control terminal G of the first semiconductor element QA, and the nMOS transistor Q54 is turned on. For this reason, the nMOS transistor Q53 is turned off, the nMOS transistor Q52 is turned on from the off state, and “1” is latched in the latch circuit 122. At this time, the output of the latch circuit 122 becomes “H” level, and the overheat cutoff element QS is turned on from the off state. As a result, the true gate TG of the first semiconductor element QA and the second main electrode (source electrode) SA are short-circuited, and the first semiconductor element QA is turned off from the on-state to be shut off from overheating. Become.
[0024]
As shown in FIG. 1, the semiconductor device used for the high voltage condition of the present invention is a semiconductor integrated circuit (power IC) in which a first semiconductor element QA and a control circuit for the first semiconductor element are integrated on the same substrate. ). The control circuit detects a current flowing through the load 102 connected to the first semiconductor element QA, and when an abnormal current occurs, the control circuit controls on / off of the first semiconductor element QA to generate a current vibration. It has a function of cutting off the first semiconductor element QA by current oscillation. As a substrate constituting the power IC, an insulating substrate such as ceramic or glass epoxy, an insulating metal substrate or the like may be used, and a hybrid IC may be used. However, more preferably, it should be a “monolithic power IC” monolithically integrated on the same semiconductor substrate (same chip).
[0025]
As the first semiconductor element QA, for example, a power MOS transistor having a DMOS structure, a VMOS structure, or a UMOS structure or a MOSSIT having a similar structure can be used. Also, a MOS composite type device such as an EST or a MOS control thyristor (MCT) may be used. Furthermore, other insulated gate power devices such as IGBTs can be used. Furthermore, if the gate is always used with a reverse bias, a junction MOS transistor, a junction SIT, an electrostatic induction thyristor (SI thyristor), or the like can be used. The first semiconductor element QA used in the high voltage power IC may be an n-channel type or a p-channel type. That is, the n-channel type and the p-channel type exist in the semiconductor device of the present invention. In the following description, a case where an n-channel semiconductor device is used as a high-side element will be described.
[0026]
The first semiconductor element QA may be, for example, a power device having a multi-channel structure in which a plurality of unit elements (unit cells) are connected in parallel. The second semiconductor element QB is disposed at a position adjacent to the first semiconductor element QA so as to be connected in parallel to the first semiconductor element QA. The heat cutoff circuit 120 is not essential for the second semiconductor element QB. Since the second semiconductor element QB is disposed at an adjacent position in the same process as the first semiconductor element QA, variations in electrical characteristics due to temperature drift and non-uniformity between lots are removed ( Reduction). The number of unit elements connected in parallel constituting the second semiconductor element QB is adjusted so that the current capacity of the second semiconductor element QB is smaller than the current capacity of the first semiconductor element QA. For example, by configuring the number of unit elements of the first semiconductor element QA to be 1000 with respect to the number of unit elements of the second semiconductor element QB, the second semiconductor element QB and the first semiconductor element The ratio of the QA channel width W is set to 1: 1000. In addition, the temperature sensor 121 includes a plurality of diodes composed of a polysilicon thin film or the like deposited on top of an interlayer insulating film formed on the second semiconductor element QB and the first semiconductor element QA. The temperature sensor 121 is configured and integrated at a position in the vicinity of the channel region of the first semiconductor element QA.
[0027]
The operation of the semiconductor device of the present invention will be described with reference to FIG. When the operation switch SW1 outside the semiconductor chip 110 is turned on, an on signal is input to the drive circuit 111 via the external input terminal T2, and the voltage VP boosted by a charge pump circuit (not shown) is applied to the resistors R8 and R7. The first semiconductor element QA and the second semiconductor element QB are turned on by being added to the gates TG of the first and second semiconductor elements QA and QB. The value of the voltage VP is, for example, VB + 10V when the power supply voltage is VB.
[0028]
The on-resistance per MOS transistor unit element constituting the first semiconductor element QA and the second semiconductor element QB is R_fetAnd the on-resistances of the first semiconductor element QA and the second semiconductor element QB are R_onA, R_onBThen, when the first semiconductor element QA and the second semiconductor element QB are completely turned on, that is, in the ohmic region, the above-described expressions (1) to (3) are established. R_onAIs usually about 30 [mΩ]. At this time R_onB= 30 [Ω]. Here, Rr = 8.4 [kΩ]. The drain currents of the first semiconductor element QA and the second semiconductor element QB are respectively expressed as I_DAAnd I_DBAnd power supply voltage VB = 42 [V],

It becomes. The drain-source voltage of each of the first semiconductor element QA and the second semiconductor element QB is V_DSAAnd V_DSBThen, the above-described equations (5) to (7) are established.
[0029]
I_DAWhen V = 5 [A], V_DSB= V_DSAAnd I_DA<5 [A] for V_DSA<V_DSBAnd I_DA > 5 [A] is V_DSA> V_DSBIt becomes.
[0030]
When the switch SW1 is turned on, the pnp transistor Q11 is turned on, and the higher power supply terminal N of the comparator CMP1 is turned on._HA power supply voltage is applied to. Low power supply terminal N of comparator CMP1_LIs grounded through resistor R27 and N_HAnd N_LSince the Zener diode ZD2 is connected between the two terminals, if the Zener voltage of ZD2 is set to 12 [V], the voltage between the high power supply terminal and the low power supply terminal of CMP1 becomes 12 [V], and the power supply voltage VB = 42 [V ] Is held at a smaller voltage. Low power supply terminal N of CMP1_LPotential V_NLIs

To be kept.
[0031]
Drain current I of the first semiconductor element QA_DAIs less than 5 [A], V_DSA<V_DSBTherefore, the output of the comparator CMP1 becomes “H”, the pnp transistor Q12 is turned off, and the drive circuit 111 keeps turning on the first semiconductor element QA and the second semiconductor element QB. On the other hand, the drain current I of the first semiconductor element QA_DAWhen V exceeds 5 [A], V_DSA> V_DSBTherefore, the output of the comparator CMP1 becomes “L”, and the pnp transistor Q12 is turned on. Therefore, the source transistor Q5 of the drive circuit 111 is turned off, the sink transistor Q6 is turned on, and the gates of the first semiconductor element QA and the second semiconductor element QB are grounded via the resistors R7 and R8. For this reason, the first semiconductor element QA and the second semiconductor element QB enter an off operation. That is, 5 [A] is an overcurrent determination value when the power supply voltage VB = 42 [V]. The load resistance at this time is 42 [V] / 5 [A] = 8.4 [Ω], which is equal to n × Rr = 1000 × 8.4 [mΩ]. That is, 8.4 [Ω] is an overload determination value, and when the load resistance is 8.4 [Ω] or less, the first semiconductor element QA and the second semiconductor element QB enter an off operation. The overload determination value 8.4 [Ω] is constant regardless of the power supply voltage VB. This is because a resistor is used as the reference circuit. When a constant current circuit is used as the reference circuit, the overcurrent determination value becomes constant regardless of the power supply voltage VB.
[0032]
When the first semiconductor element QA and the second semiconductor element QB are turned off, the voltage V between the source and source of the first semiconductor element QA and the second semiconductor element QB V_DSA, V_DSBWill increase. The source potential of the first semiconductor element QA and the second semiconductor element QB is V_SA, V_SBV_SA, V_SBDecreases toward the ground potential GND. Since the sink transistor Q6 of the drive circuit 111 is turned on, a current flows through the path of the source of the first semiconductor element QA → resistor R81 → resistor R26 → diode D1 → resistor R8 → sink transistor Q6 → GND, and the (+) input of CMP1 A hysteresis effect that lowers the terminal potential occurs, and the output of CMP1 is stably maintained at "L". The input terminal potential of CMP1 is also V_SA, V_SBHowever, the CMP1 (+) input terminal potential is the potential V1 of the CMP1 low-order power supply terminal._NLAnd the diode D21_NLIt does not drop below -0.7 [V] (D21 forward voltage drop). V_NL= VB-12.3 [V], the CMP1 (+) input terminal potential does not drop below VB-13 [V]. On the other hand, the (−) input terminal of CMP1 is also clamped by the diode D22, but is clamped via the resistor R28, so the (−) input terminal voltage of CMP1 is equal to the (+) input terminal potential by the voltage drop of R28. Clamped to a lower potential. That is, the clamp potential of the (−) input terminal is VB-13 [V] − (R28 voltage drop). For this reason V_SA, V_SBThe output of CMP1 becomes “H” regardless of the state on the load side, and the drive circuit 111 again returns to the first semiconductor element QA and the second semiconductor. The element QB is turned on. V_SA, V_SBFalls below the clamp voltage, the first semiconductor element QA and the second semiconductor element QB are turned on after the delay time of the control circuit and the MOS transistor, and V_SA, V_SBWhen the voltage exceeds the clamp voltage, the first semiconductor element QA and the second semiconductor element QB are turned off after the delay time of the control circuit and the MOS transistor, so that the on / off operation is continued. When the on / off operation continues for a certain time, the first semiconductor element QA and the second semiconductor element QB are cut off by overheating of the first semiconductor element QA or by timer processing.
[0033]
(Other embodiments)
It should not be understood that the description and the drawings, which form part of the disclosure according to the above-described embodiments, limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.
[0034]
For example, FIG. 1 shows an n-channel high-side circuit, but a p-channel high-side circuit as shown in FIG. 3 is almost the same if a p-channel first semiconductor element QA (p) is used. It can be realized with a simple circuit configuration.
[0035]
In a fixed case, as shown in FIG. 4, the Zener diode ZD <b> 2 shown in FIG. 1 may be omitted.
[0036]
As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.
[0037]
【The invention's effect】
According to the semiconductor device of the present invention, even when the power supply voltage shifts from the conventional 12V system to a high voltage power supply system such as the 42V system, the second main elements of the semiconductor elements of the first and second semiconductor elements are used. A conventional 12V element can be used as a comparator for comparing the potential between the electrodes. Thereby, it is not necessary to increase the breakdown voltage of the comparator, and it is possible to avoid an increase in cost due to the increase in breakdown voltage.
[0038]
Furthermore, according to the semiconductor device of the present invention, the reliability can be improved by avoiding the use of the comparator in a high voltage environment.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a high-voltage semiconductor device according to an embodiment of the present invention (in the case of n-channel).
FIG. 2 is a circuit configuration diagram of a heat cutoff circuit integrated in a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a circuit configuration diagram of a high-voltage semiconductor device according to another embodiment of the present invention (in the case of p-channel).
FIG. 4 is a circuit configuration diagram of a high-voltage semiconductor device according to still another embodiment of the present invention (in the case of p-channel).
FIG. 5 is a circuit configuration diagram of a conventional power supply control device.
[Explanation of symbols]
101 Low voltage power supply
102 load
110, 118, 121, 122 Semiconductor chip
111 Drive circuit
120 Heat shutdown circuit
191 High voltage power supply
CMP1 comparator
D1, D21, D22 Diode
QA first semiconductor element
QB second semiconductor element
Q71, Q72, Q131, Q221, Q311, Q312 MOS transistors
RG gate resistance
R1, R2, R5, R7, R8, R10, R21, R22, R81, R82 resistors
Rr Reference resistance
T₁, T₂, T₃, T₄  I / O terminal
ZD1, ZD2 Zener diode

Claims (5)

A first semiconductor element having a first main electrode connected to a DC power source, a second main electrode connected to a load, and a control electrode;
A first main electrode connected to the first main electrode of the first semiconductor element; a second main electrode connected to a reference circuit; and a control electrode connected to the control electrode of the first semiconductor element. Two semiconductor elements;
A high-level power supply terminal and a low-level power supply terminal, wherein the high-level power supply terminal is held at a system power supply voltage, and a voltage between the high-level power supply terminal and the low-level power supply terminal is held at a voltage smaller than the system power supply voltage. A comparator in which a first input terminal is connected to the second main electrode of the first semiconductor element, and a second input terminal is connected to the second main electrode of the second semiconductor element;
A driving circuit for supplying control voltages to the control electrodes of the first and second semiconductor elements, respectively, in accordance with the output of the comparator;
A first diode connected between the first input terminal and the lower power supply terminal;
An overcurrent exceeding at least a predetermined current value determined by the reference circuit flows through the first semiconductor element, comprising at least a second diode connected via a resistor between the second input terminal and the lower power supply terminal. In some cases, the semiconductor device is characterized in that current oscillation is generated by controlling on / off of the first semiconductor element, and the conduction state of the first semiconductor element is interrupted by the current oscillation. 2. The first semiconductor element includes N1 unit elements, and the second semiconductor element includes N2 unit elements, and N1 >> N2. Semiconductor device. 3. The semiconductor device according to claim 1, wherein a constant voltage diode is connected between the high power supply terminal and the low power supply terminal. 4. The semiconductor device according to claim 1, wherein a third semiconductor element is connected between the DC power supply and the high-level power supply terminal. 5. 5. The device according to claim 1, wherein the first and second semiconductor elements, the comparator, the drive circuit, and the first and second diodes are integrated on the same semiconductor substrate. The semiconductor device according to 1.

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