JP3652578B2 - Clock generator using SRTS method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock generator using the SRTS (Synchronous Residual Time Stamp) method, and in particular, creates timing information (transmission RTS information) of a transmission user clock by the SRTS method in broadband ISDN (B-ISDN) using ATM. The transmission RTS information is transmitted in a cell together with user data, and the reception user clock is set to the same timing as the transmission user clock on the reception side based on the transmission RTS information (referred to as reception RTS information), and is synchronized with the reception user clock. The present invention relates to a clock generator of an interface device that outputs user data.
[0002]
[Prior art]
As a means for realizing broadband communication, there is a B-ISDN (Broadband-ISDN) switching technique based on an asynchronous transfer mode (ATM). Such B-ISDN includes a service for transmitting user data at a constant speed, that is, a CBR service (Constant Bit Rate Service). In the CBR service, the timing of the receiving side clock (receiving user clock) must match the timing of the transmitting side user clock. When the transmission user clock is synchronized with the network clock (network clock), the reception user clock is generated from the network clock on the reception side, whereby the timings of the clocks on the transmission side and the reception side can be matched. .
[0003]
However, the timing of the transmission user clock (voice 64kbps, DS1 1.544Mbps standardized in ITU-DS recommendation G700 series, DS3 44.736Mbps, etc.) is not synchronized with the network clock timing on the network side There is. In such a case, even if the nominal value of the frequency of the transmission user clock is known and the reception side divides the network clock (e.g. 155.56 MHz) to generate the reception user clock of the same nominal value, the reception user clock is generated. A timing error occurs between the user clock and the transmission user clock, and a faithful CBR service cannot be performed.
[0004]
From the above, the SRTS (synchronous Residual Time Stamp) method has been proposed as a method of synchronizing the reception user clock with the transmission user clock. This SRTS method includes the transmission user clock timing information in the ATM cell on the transmission side, extracts the transmission user clock timing information on the reception side, and synchronizes the reception user clock with the transmission user clock based on the timing information. It is. In order to transmit timing information of the transmission user clock, AAL-1 (ATM Adaptation Layer-1) standardized by ITU-DS recommendation I363 or the like is used as an ATM cell.
[0005]
FIG. 12 is a format explanatory diagram of an AAL type 1 (AAL-1) ATM cell, and FIG. 13 is a format explanatory diagram of a 1-byte SAR-PDU header. In AAL-1, a 48-byte information field is composed of a 47-byte SAR-PDU payload and a 1-byte SAR-PDU (PDU: Protocol Data Unit) header. The 47-byte SAR-PDU payload is used to transfer user data, and the 1-byte SAR-PDU header is a 4-bit SN (Sequence Number) field and a 4-bit SNP (Sequence Number Protection) feed. It is configured.
The SN field is a CSI (Convergence Sublayer)
The SNP field is also divided into two subfields CRC (Cyclic Redundancy Check) and EPB (Even Parity Bit). SC counts cells with 1 to 8 circulations (1,2, ..., 8,1,2, ..., 8,1, ...). Can be monitored. SN error detection and correction is performed by CRC and EPB. CRC is a polynomial for SN (G (X) = X ^Three + X + 1), and EPB is an even parity bit in the SAR-PDU header. The CSI bit is a function of AAL-1 CS (Convergence Sublayer) and is used for transmission and reproduction of user clock timing information as described below.
[0006]
In the SRTS method, the user clock timing information is RTS (Residual Time
4 bits of information (RTS4, RTS3, RTS2, RTS1) called “Stamp”. This RTS information is transferred by the CSI bit which is the CS function of AAL-1. FIG. 14 is an explanatory diagram of the structure of the RTS information format. The RTS information format has a multiframe structure for 8 ATM cells. Since user data is transferred in the SAR-PDU payload, the number of bits of user data in 8 ATM cells is
3008 bits (8 cells x 47 bytes x 8 bits).
The CSI bit is composed of 8 bits (CSI) corresponding to 0 to 7 of SC (Sequence Count) value. ₀ ~ CSI ₇ The CSI bit (CSI bit) of the ATM cell with SC value = 1, 3, 5, 7 ₁ , CSI _Three , CSI _Five , CSI ₇ ) Transmits 4-bit RTS information. That is, RTS4 is transferred by an ATM cell with SC = 1, RTS3 is transferred by an ATM cell with SC = 3, RTS2 is transferred by an ATM cell with SC = 5, and RTS1 is transferred by an ATM cell with SC = 7.
[0007]
FIG. 15 is an explanatory diagram of a generation cycle of RTS information. Sending user data D in CBR service _TU Is constant speed data, and the clock synchronized with the data is shown in FIG. _TU It is said. In an ATM cell, this transmission user data D _TU Information is transmitted in the SAR-PDU payload, and the transmission user clock C is transmitted. _TU RTS information, which is the timing information, is transmitted with the CSI bit. Therefore, the frequency of the transmission user clock is f _TU , The time for one bit of user data is T _TU = 1 / f _TU Then, RTS information generation cycle T _TS = T _TU × 3008. Transmit clock for generating RTS data RTS sampling timing clock C _TS RTS information is the clock C _TS This transmission RTS sampling timing clock C is generated at the rising edge of _TS Is the transmission user clock C _TU Is divided by 1/3008.
[0008]
In SRTS, the network clock frequency f synchronized with the line timing on the network side _N (Example: 155.56MHz) divided by network divided clock C _NX (Frequency f _NX = F _N / 2 ^N , 1/2 ^N = Frequency division ratio). Dividing ratio 1/2 ^N Is the network divided clock frequency f _NX And nominal value of user clock frequency (Nominal Value) f _NOM The ratio of 1 ≦ (f _NX / F _NOM ) <2 is determined.
Next, the network divided clock frequency f _NX Is divided by a 4-bit binary counter and f _NX / 2 ¹ , F _NX / 2 ² , F _NX / 2 ^Three , F _NX / 2 ^Four Frequency network timing information Q ₁ , Q ₂ , Q _Three , Q _Four Is generated. Network timing information Q ₁ , Q ₂ , Q _Three , Q _Four Transmit sampling clock C _TS The values sampled at the rise of RTS1, RTS2, RTS3, and RTS4 are RTS information.
The generation of RTS information and the format of its transmission are defined as described above in the international recommendation.
[0009]
FIG. 16 is a configuration diagram of an RTS generation and transmission unit when transmission RTS information is generated and transmitted in accordance with international recommendations.
The ATM cell disassembling unit 10 receives the network clock C included in the ATM cell RATM received from the ATM network. _N (Frequency f _N : 155.56MHz as an example) extracted by PLL (Phase Locked Loop) and output. The network clock divider 11 is a network clock C synchronized with the line timing on the network side. _N Is divided by the network divided clock C _NX Is output. In this case, the network clock dividing unit 11 uses the network divided clock f. _NX And nominal value f of user clock frequency _NOM The ratio of 1 ≦ (f _NX / F _NOM ) <1/2 to be in the range of <2 ^N (N is an integer). For example, in DS1 transmission, the nominal value f of the transmission user clock frequency _NOM Is 1.544MHz, so the network clock frequency f _N Is 155.56 MHz, N = 6, and the network divided clock frequency is f. _NX = 155.56MHz / 2 ⁶ = 2.43MHz. Similarly, in DS3 transmission, N = 1 and f _NX = 155.56MHz / 2 = 77.78MHz.
[0010]
Next, the 4-bit binary counter unit 12 is connected to the network divided clock C. _NX And the frequency is f from each of the four stages. _NX / 2 ¹ , F _NX / 2 ² , F _NX / 2 ^Three , F _NX / 2 ^Four Network timing information Q ₁ , Q ₂ , Q _Three , Q _Four Is output.
On the other hand, the transmission frequency division counter unit 13 transmits the transmission user data D _TU Transmit user clock C synchronized to _TU (Frequency f _TU ) Divided by 3008 and sent RTS sampling clock C _TS (Frequency f _TS = F _TU / 3008) is output.
[0011]
The transmission RTS generator 14 generates network timing information Q ₁ , Q ₂ , Q _Three , Q _Four RTS sampling clock C _TS And is output as transmission RTS information TRTS1, TRTS2, TRTS3, and TRTS4. Transmission user clock C _TU Frequency f _TU Varies, the transmission RTS sampling clock C _TS Since the rise time of fluctuates, the values of the transmission RTS information TRST1 to TRST4 also change. In other words, the transmission RTS information includes the transmission user clock C _TU Timing information is included.
[0012]
ATM cell assembling unit 15 transmits user data D _TU And the transmission user clock C synchronized with it _TU And the transmission RTS information input from the transmission RTS generator 14, 3008 × T _TU Eight ATM cells TATM are assembled every time and the ATM cell is connected to the network clock C. _N (F _N = 155.56MHz) and send to the ATM network.
[0013]
FIG. 17 is a configuration diagram of a reception unit that generates a reception user clock (reception clock) synchronized with a transmission user clock using RTS information. In the figure, 20 is a reception user clock generation unit, 21 is a local RTS information generation unit, and a reception user clock C _RU RTS information LRTS1 to LRTS4 which is the timing information of the received RTS information clock C synchronized with the local RTS information LRTS1 to LRTS4 _RCK Is generated. The local RTS information generation unit 21: (1) Network clock C _N Divide the clock and divide clock C _NX Network clock dividing unit 21a for outputting the frequency dividing clock C _NX 4-bit binary counter 21b that counts (3), receiving user clock C _RU Is divided by 1/3008 to generate a timing signal for generating local RTS information, and the received timing signal is received RTS information clock C _RCK Local RTS timing generation unit 21c that outputs as a local RTS timing circuit 21d that outputs the contents (4-bit data) of the 4-bit binary counter unit when the timing signal is generated as local RTS information LRTS1 to LRTS4. Yes.
[0014]
Reference numeral 22 denotes RTS information (referred to as reception RTS information) RRTS1 to RRTS4 included in the ATM cell sent from the transmission side as clock C. _RCK The received RTS information register 23 is stored in synchronism with the received RTS information, 23 is a comparator for outputting the difference between the received RTS information RRTS1 to RRTS4 and the local RTS information LRTS1 to LRTS4, and 24 is the received user clock C so that the difference becomes zero. _RU Is a digital PLL (DPLL) that adjusts the timing (phase) of the output and outputs a reference clock C as shown in FIG. _OSC The pulse adjustment unit 24a for controlling the phase by increasing / decreasing the number of pulses, and the adjusted clock C _a Divided by the received user clock C _RU Is provided. 31 is the network clock C from the ATM cell received from the ATM network. _N Is extracted and input to the local RTS information generation unit 21, and the received ATM cell is converted to user data D. _RU And an ATM cell disassembly unit that decomposes and outputs RTS information RRTS1 to RRTS4.
[0015]
The local RTS information generation unit 21 receives the received user clock C by the SRTS method. _RU RTS information LRTS1 to LRTS4 which is the timing information of the received RTS information clock C synchronized with the local RTS information LRTS1 to LRTS4 _RCK Is generated. The comparator 23 outputs the difference between the local RTS information LRTS1 to LRTS4 and the received RTS information RRTS1 to RRTS4 included in the received ATM cell, and the DPLL 24 receives the signal by increasing or decreasing the reference clock number so that the difference becomes zero. User clock C _RU Adjust the timing. As a result, the receiving user clock C _RU The timing (frequency, phase) of the transmission user clock C _TU The timing can be matched.
The ATM cell disassembly unit 31 receives the network clock C from the ATM cell received from the ATM network. _N The received user clock C that is extracted and output and input from the DPLL 24 _RU User data D in synchronization with _RU And the reception RTS information clock C _RCK The received RTS information RRTS1 to RRTS4 is output in synchronization with the data and input to the register 22.
[0016]
Incidentally, the method of reproducing the received user clock by the digital PLL has the following problems (1) to (3).
(1) Nominal value f of user clock frequency _NOM Where αHz is the output clock of the reference oscillator (reference clock) C _OSC Frequency f _OSC Is
f _OSC = ΒHz (β = α × N; N is the division ratio)
Thus, the jitter ΔT when correcting step by step is ΔT = 1 / β seconds. Also, the receiving user clock cycle T _RU Is T _RU Since ≒ 1 / α, the ratio of jitter to the received user clock period (jitter ratio) UI is
UI = ΔT / T _RU ≒ α / β = 1 / N
It is. Therefore, N needs to be increased in order to reduce the jitter ratio UI. However, if the jitter ratio is reduced, the reference clock C _OSC Frequency f _OSC Is
f _OSC = ΒHz (β = α × N) becomes large, and there is a problem that power consumption increases.
[0017]
(2) The nominal value α of the user clock frequency that can be supported by SRTS is the network clock frequency f. _N B-ISDN network clock frequency f _N = 155.52MHz nominal user clock frequency f _NOM = 77.76MHz must be supported. For example, user clock frequency f like DS3 interface _RU In the case of = 44.736 MHz, if N ≧ 16 in order to reduce the jitter ratio to 0.1 or less, β = 715.776 MHz. Therefore, the digital PLL system has a problem that a very high-speed element is required when the user clock becomes high.
[0018]
(3) Further, the correction amount for correcting by one step is ΔT = 1 / β second, and the correction cycle of the reception user clock is the period of the reception user clock T _RU Then,
T = 3008 × T _RU ≒ 3008 / α
It is. Therefore, the allowable range W of the reproducible deviation of the user clock is
W = ΔT / T≈ (1 / β) × (α / 3008) = 1 / (3008 × N)
It is. That is, if N is increased in order to reduce the jitter ratio, there is a problem that the allowable range of user clock deviation is reduced.
[0019]
In order to solve the above problem, an analog PLL circuit (APLL) 25 is provided as shown in FIG. 18, and the analog PLL circuit is connected to the DPLL 24 via a pulse frequency dividing counter 26. It has been known.
In the figure, 20 is a digital received user clock generator, and 31a is a cell buffer. The cell buffer 31a is provided in the ATM cell disassembling unit 31, and stores the ATM cell by the network clock (ATM clock) and receives the user clock C. _RU Is read in synchronization with In the reception user clock generation unit 20, the counter 21 corresponds to the local RTS information generation unit 21 in FIG. 17, and an RTS value generation clock (network division clock C _NX ) And receive user clock C _RU The count value is latched every 3008 cycles, and the count value is output as local RTS information LRTS1 to LRTS4.
[0020]
The DPLL 24 increases or decreases the reference clock number so that the difference between the local RTS information LRTS1 to LRTS4 and the received RTS information RRTS1 to RRTS4 becomes zero, and the counter 26 divides the DPLL output clock, for example, a phase comparison clock C of 8 KHz. _REF Is generated. The analog PLL circuit (APLL) 25 is a phase comparison clock C. _REF Received user clock C phase-synchronized with _RU Is output. In other words, the phase difference detection unit 25a outputs the phase comparison clock C _REF And the received user clock C, which is the output of APLL _RU The low-pass filter 25b smoothes the phase difference signal, and the VCO (Voltage controlled oscillator) 25c receives the received user clock C having a frequency corresponding to the phase difference. _RU The frequency divider 25d receives the received user clock C. _RU Is divided into 8 KHz clocks and fed back to the phase difference detector 25a. As described above, the analog PLL circuit (APLL) 25 receives the reception user clock C. _RU Is set to the phase instructed by the DPLL, and the ATM cell disassembly unit 31 _RU The user data is output from the cell buffer 31a in synchronization with the received RTS information at a predetermined timing.
[0021]
[Problems to be solved by the invention]
According to the clock generator in which the APLL is connected to the DPLL via the frequency divider, it is possible to theoretically reduce jitter and power consumption, and increase the tolerance for deviation. However, in practice, the feedback of the analog PLL and the feedback of the DPLL to the RTS interfere with each other, and there is a problem that the jitter characteristics are deteriorated by simply connecting them.
Further, in the conventional clock generator, the DPLL increases or decreases the clock fixedly by a number proportional to the difference. The relationship between the difference and the number of increase / decrease clocks may theoretically be linear, but if an analog PLL is present, the jitter characteristics may not be improved linearly. In such a case, there is a problem that the conventional clock generator cannot be adjusted so as to optimize the jitter characteristics.
[0022]
In the conventional clock generator using the SRTS method, the next reception user clock C is received using the current reception RTS information. _RU Control the phase of. For this reason, control for one cycle period is delayed. Here, one cycle is a multiframe period of 8 cells, which is 3008 periods of the received user clock. On the other hand, the transmission side creates and transmits the current RTS information based on the previous transmission user clock frequency. For this reason, the transmission RTS information is frequency information delayed by one cycle. As described above, in the conventional clock generator using the SRTS method, the frequency of the reception user clock is controlled based on the frequency information of the transmission user clock 16 cells before, and accurate synchronization control of the transmission user clock and the reception user clock is performed. There is a problem that can not be.
[0023]
As described above, the first object of the present invention is to eliminate the interference between the feedback of the APLL and the feedback of the DPLL and improve the jitter characteristics.
The second object of the present invention is to provide a degree of freedom so that various phase adjustments can be made and to optimize the jitter characteristics.
A third object of the present invention is to perform accurate synchronization control of a transmission user clock and a reception user clock.
[0024]
[Means for Solving the Problems]
According to the present invention, (1) the first reception user clock is generated, and the local timing information (local RTS information) generated based on the reception user clock and the network are received from the network. A digital PLL circuit that controls the phase of the received user clock so that the difference from the received timing information (received RTS information) becomes zero; and (2) the first received user clock output from the digital PLL circuit is divided. A frequency dividing circuit that generates a phase comparison clock; (3) an analog PLL circuit that receives the phase comparison clock and generates a second received user clock; and (4) user data is written using the first received user clock; This is achieved by a clock generator using the SRTS method, comprising buffer means for reading user data with the second received user clock. By providing the buffer means, interference between the feedback of the DPLL to the RTS and the feedback of the analog PLL can be prevented, and the initial jitter characteristic can be improved.
[0025]
The second object is that according to the present invention, (1) storage means for storing correction data corresponding to the difference between the local RTS information and the received RTS information, and (2) change the correction data stored in the storage means. This is achieved by a clock generator comprising: changing means for generating a phase control signal based on correction data. As described above, since the correction data can be freely changed from the outside, the correction data can be determined so that the jitter characteristic is optimum. The correction data includes a clock phase correction cycle, a phase correction timing, and the number of phase corrections.
[0026]
The third object is that according to the present invention, (1) local timing information (local RTS information) created using a reference clock that is phase-controlled based on RTS information and reception timing information received from the network A digital PLL circuit that controls the timing of the reference clock so that the difference from (received RTS information) becomes zero, and (2) a frequency division that divides the reference clock output from the digital PLL circuit to generate a phase comparison clock Circuit, (3) an analog PLL circuit that generates a received user clock synchronized with the phase comparison clock, (4) a buffer that stores cells received from the network in synchronization with the network clock, and (5) a multi-frame one cycle before The user data included in the constituting cell is included in the multi-frame received this time and is synchronized with the received user clock created using the received RTS information. Data read control unit for reading from the buffer is achieved by the clock generator using the SRTS method comprising a. In this way, the user data included in the cells constituting the multiframe one cycle before is read from the buffer in synchronization with the received user clock included in the current multiframe and created using the received RTS information. It is possible to accurately control the transmission user clock and the reception user clock without delay.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
(A) First embodiment
FIG. 1 is a block diagram of a clock generator using the SRTS method in the first embodiment of the present invention. The clock generator of FIG. 18 is (1) a FIFO buffer for data transfer between a DPLL circuit and an APLL circuit. (2) The difference is that a phase control unit is provided and phase control is performed so that jitter characteristics are optimized.
The reception user clock generation unit 51 receives the first reception user clock C. _RU1 Local timing information (local RTS information LRTS1 to LRTS4) is generated, the local RTS information LRTS1 to LRTS4 is compared with the reception timing information received from the network (received RTS information RRTS1 to RRTS4), and the difference So that the received user clock C is zero. _RU1 Controls the phase (increase / decrease in clock)
[0028]
The reference clock counter 52 receives the first reception user clock C. _RU1 8 KHz phase comparison clock C _REF Is generated. The analog PLL circuit (APLL) 53 outputs a phase comparison clock C output from the reference clock counter 52. _REF PLL control so as to match the phase of the second received user clock C _RU2 Is generated. The analog PLL circuit (APLL) 53 includes a phase difference detection unit 53a, a low-pass filter 53b, a voltage controlled oscillator (VCO) 53c, and a frequency dividing circuit 53d. The phase difference detector 53a is configured to output a phase comparison clock C _REF And the received user clock C, which is the output of APLL _RU2 The low-pass filter 53b smoothes the phase difference signal, and the VCO 53c has a second received user clock C having a frequency corresponding to the phase difference. _RU2 The frequency divider 53d outputs the received user clock C _RU2 Is divided into 8 KHz clocks and fed back to the phase difference detector 53a.
[0029]
The ATM cell decomposition unit 54 stores the ATM cell in the cell buffer 54 a in synchronization with the network clock (ATM clock), and outputs the first reception user clock C output from the reception user clock generation unit 51. _RU1 The user data is output from the cell buffer 54a in synchronization with the received RTS information RTS1 to RTS4 at a predetermined timing. The data transfer FIFO buffer 55 includes a first reception user clock C. _RU1 The user data read from the cell buffer 54a is stored in synchronization with the second received user clock C output from the analog PLL circuit 53. _RU2 Are read out in order from the oldest one.
[0030]
In the data reproduction system using the AAL1 format, the cell disassembly unit 54 separates the SAR-PDU header and the payload from the ATM cell. That is, the cell disassembly unit 54 stores the ATM cell received from the network in synchronization with the ATM clock in the cell buffer 54a, separates the SAR-PDU header and the payload portion, and sets the payload portion (user data) as the first receiving user. Clock C _RU1 Send in sync with. Further, the SAR-PDU header is analyzed to perform various controls, and the received RTS information RTS1 to RTS4 is extracted.
On the other hand, the RTS counter (4-bit binary counter) 51a is an RTS reference clock (network divided clock) C. _NX Count. Since the RTS information is meaningful with eight ATM cells, the RTS latch circuit 51b latches the received RTS information RRTS1 to RRTS4 at the timing when the eight ATM cells are gathered, and latches the contents of the RTS counter 51a. A latch signal is generated. The counter latch circuit 51c latches the contents (4-bit data) of the RTS counter 51a when the latch signal is generated as the local RTS information LRTS1 to LRTS4 and inputs it to the comparison unit 51d.
[0031]
The comparison unit 51d compares the latched count values (local RTS information LRTS1 to LRTS4) with the received RTS values RRTS1 to RRTS4 from the ATM cell, and the phase control unit 51e obtains correction data based on the comparison result, and the correction data And the DPLL 51e generates a first received user clock C based on the phase control signal. _RU1 Is controlled so as to match the phase of the transmission user clock. As will be described later, the correction data uses a preset value written in advance from the outside.
[0032]
A data read control unit (not shown) receives a first received user clock C from the cell buffer 54a. _RU1 The user data is read out in synchronization with and stored in the data transfer FIFO buffer 55. The reference clock counter 52 is connected to the first reception user clock C. _RU1 8KHz phase comparison clock C _REF The analog PLL circuit 53 controls the second reception user clock C by analog PLL control. _RU2 Is generated. The data transfer FIFO buffer 55 receives the second reception user clock C. _RU2 The user data is sent in the first in / first out manner from the oldest one in synchronization with.
As described above, according to the first embodiment, by providing the data transfer FIFO buffer, interference between the feedback of the analog PLL and the feedback of the DPLL to the RTS can be eliminated, and the jitter characteristic can be improved.
[0033]
(B) Second embodiment
FIG. 2 is a block diagram of a clock generator using the SRTS method according to the second embodiment of the present invention. Components identical with those of the first embodiment shown in FIG. The difference is
(1) The data transfer FIFO buffer 55 of the first embodiment is deleted.
(2) The reception user clock generation unit 51 is provided with an RTS latch timing control unit 51g for generating the RTS latch timing signal LTS.
(3) The RTS latch timing control unit 51g divides the clock output from the DPLL unit 51f to receive the user clock C _RU The point of generating the RTS latch timing signal LTS every 3008 periods
(3) The provision of an RTS FIFO buffer 51h for storing the received RTS information RRTS1 to RRTS4 extracted from the ATM cell,
(4) The RTS latch timing signal LTS latches the 4-bit received RTS information RRTS1 to RRTS4 stored in the RTS FIFO buffer 51h in the received RTS latch unit 51b, and the contents (4-bit data) of the RTS counter 51a are local. RTS information LRTS1 to LRTS4 is latched in the counter latch unit 51c,
(5) Received user clock C output from the analog PLL circuit 53 _RU The user data is read from the cell buffer 54a and output in synchronization with
It is.
[0034]
According to the second embodiment, since the DPLL only feeds back the RTS latch timing, there is no interference between the DPLL and the APLL, the data transfer FIFO buffer 55 of the first embodiment can be omitted, and the cell User data with good jitter characteristics can be read from the buffer 54a and output.
[0035]
(C) Third embodiment
FIG. 3 is a block diagram of a clock generator using the SRTS method of the third embodiment of the present invention. The same reference numerals are given to the same parts as those of the second embodiment of FIG. The difference is
(1) In the cell decomposition unit 54, a data write control unit 54b for writing cells in the cell buffer 54a in synchronization with the ATM clock, and receiving user data from the cell buffer 54a. _RU A data read control unit 54c that reads in synchronization with
(2) The cell buffer 54a stores at least the latest 16 cells (corresponding to two cycles),
(3) The data read control unit 54c receives the user data included in the 8 cells received in the previous multiframe and the received user clock C created using the received RTS information included in the currently received multiframe. _RU The point read from the cell buffer 54a in synchronization with
It is.
[0036]
In the second embodiment of FIG. 2, the next received user clock C is received using the current received RTS information. _RU Control the phase of. For this reason, one cycle control is delayed. Here, one cycle is a multiframe period of 8 cells, which is 3008 periods of the received user clock. On the other hand, the transmission side creates and transmits the current transmission RTS information based on the transmission user clock frequency one cycle before. For this reason, the transmission RTS information is frequency information delayed by one cycle.
According to the third embodiment, the latest 16-cell user data is stored in the cell buffer 54a, and the data read control unit 54c receives the received user clock C. _RU In synchronization with this, the user data of the old cell 16 cells before is sequentially read and output. Therefore, the phase / frequency of the receiving user clock is controlled based on the frequency information of the transmitting user clock 16 cells before, and user data 16 cells before can be read in synchronization with the receiving user clock, and there is no delay. Accurate control of the transmission user clock and the reception user clock can be performed.
[0037]
(D) Phase control unit
FIG. 4 is a block diagram of the phase controller 51e in the first to third embodiments. Since the RTS information is 4 bits, the difference (= received RTS information−local RTS information) output from the comparator 51d takes 16 values, for example, +7 to −8. For this reason, the phase control unit 51e stores the correction data (correction data +7 to correction data -8) corresponding to each difference. ₁ ~ 61 ₁₆ The AND gate unit 62 outputs correction data corresponding to the difference output from the comparison unit. ₁ ~ 62 ₁₆ OR gate unit 63 that outputs correction data output from the AND gate unit according to the difference, performs phase correction control based on the correction data, and outputs an advance / delay DPLL control trigger (phase control signal) to DPLL unit 51f A correction unit 64 that performs correction, and a change unit 65 that changes correction data. The correction data set in the register can be freely changed by the user by the changing unit 65 so that the jitter characteristic is optimized. Further, the DPLL unit 51f adds a pulse to advance the phase of the reference clock when the advance is instructed by the DPLL control trigger, and drops the pulse to delay the phase of the reference clock when the delay is instructed.
[0038]
(A) First example of correction data
FIG. 5 shows a first correction data example of the present invention, in which a correction cycle is set as correction data. In the figure, the difference D (= + 7 to -8) in one cycle (= 3008 clock cycle) and the correction cycle (= T ₇ ~ T _-8 ) And the correction position determined by the correction cycle are shown. The correction period corresponding to the difference D can be changed and can be freely changed so as to improve the jitter characteristics. If there is no need to perform correction at the difference D = 0, the correction cycle T ₀ Is set to a value larger than one cycle period. Also, if the difference D (= received RTS information-local RTS information) is positive, the phase of the received user clock is advanced from the transmitted user clock, so control is delayed at each correction point. Since the phase is delayed from the transmission user clock, control is advanced at the correction point.
[0039]
(B) Second example of correction data
FIG. 6 shows a second correction data example of the present invention, in which the number of corrections is set as the correction data. In the figure, the correspondence between the difference D (= + 7 to −8) and the number of corrections in one cycle (= 3008 clock cycle) is shown. The relationship between the number of corrections and the correction points in one cycle is set in advance, and the correction positions of the correction number 10 and the correction number 3 are shown.
The number of corrections corresponding to the difference D can be changed and can be freely changed to improve the jitter characteristics. If the difference D (= received RTS information−local RTS information) is positive, the phase of the received user clock is advanced from the transmitted user clock, so that the delay is controlled at the correction point. If the difference is negative, the received user clock is Since the phase is delayed from the transmission user clock, the control is advanced at the correction point.
[0040]
(C) Third example of correction data
FIG. 7 shows a third example of correction data according to the present invention, in which a correction timing (correction point) is set as correction data. In the figure, the correspondence between the difference D (= + 7 to −8) in one cycle (= 3008 clock cycle) and the correction timing is shown. The correction timing corresponding to the difference D can be changed and can be freely changed so as to improve the jitter characteristics. If the difference D (= received RTS information−local RTS information) is positive, the phase of the received user clock is advanced from the transmitted user clock, so that the delay is controlled at the correction timing. If the difference is negative, the received user clock is Since the phase lags behind the transmission user clock, the advance control is performed at the correction timing.
[0041]
(D) Configuration of correction unit
FIG. 8 is an explanatory diagram of DPLL control trigger generation control of the correction unit 64 (see FIG. 4) in the phase control unit 51e. (A) is an addition type, (b) is a subtraction type, and (c) is a leaky packet type principle. It is a structural example.
In the addition type of FIG. 8A, when the correction cycle p is input as correction data, the up counter 64a ₁ Is the receiving user clock C _RU Count up. Comparison unit 64a ₂ Checks whether the count value is equal to the correction period p, and when it is equal, generates a DPLL control trigger DCT and counter 64a ₁ Reset the count value.
In the subtraction type of FIG. 8B, when the correction cycle p is input as the correction data, the correction cycle p is reduced to the down counter 64b. ₁ Preset. Thereafter, the down counter 64b ₁ Is the receiving user clock C _RU Count down. Comparison unit 64b ₂ Checks whether the count value is equal to 0, and when it is equal to 0, it generates a DPLL control trigger DCT and counter 64b ₁ To reset.
[0042]
The leaky packet type shown in FIG. 8C is an effective configuration when set with a correction cycle (for example, 600.5) including a value after the decimal point. When a correction cycle p (including a value after the decimal point) is input as correction data, the up counter 64c is thereafter processed. ₁ Is the receiving user clock C _RU Count up. Adder 64c ₂ Is the counter value and the latch circuit 64c. _Three Output (initial value is zero). Comparison unit 64c _Four Checks whether the addition result B is equal to or longer than the correction cycle A (= p) (A ≦ B), and if so, generates a DPLL control trigger DCT and resets the counter. The subtractor 64c _Five Calculates B-A and latches the calculation result into latch 64c. _Three Latch on. Thereafter, the above operation is repeated by inputting the next correction period p.
[0043]
(E) Correction processing
(e-1) Addition type
FIG. 9 is an addition type phase lead / lag control processing flow.
When the difference D (= received RTS information−local RTS information) is input from the comparator 51d (FIG. 4) (step 101), a setting value (correction data) corresponding to the difference is obtained from the table (step 102), and i = 0 and n = 0 are set (step 103).
Next, every time a reception user clock is generated, i and n are incremented (step 104), and it is checked whether n> 3008 is satisfied (step 105). If n ≦ 3008, it is checked whether i = set value (step 106). If i is not a set value, the processes in and after step 104 are repeated. If i is a set value, the sign of the difference D is determined (step 107). If the sign of the difference D is positive, a DPLL control trigger DCT for instructing delayed phase control is output to perform delayed phase control (step 108). If the sign of the difference D is negative, the DPLL control trigger DCT for instructing the advance phase control is output to perform the advance phase control (step 109). If the difference D = 0, the current state is maintained without performing the advance / delay phase control (step 110). After executing the processing of steps 108 to 110, i = 0 is set (step 111), and thereafter, the processing after step 104 is repeated until n> 3008.
[0044]
(e-2) Subtraction type
FIG. 10 is a flowchart of the subtraction type phase advance / delay control process.
When the difference D (= received RTS information−local RTS information) is input from the comparator 51d (FIG. 4) (step 201), a setting value (correction data) corresponding to the difference is obtained from the table (step 202), i = Set value, n = 0 (step 203).
Next, every time the reception user clock is generated, i is decremented, n is incremented (step 204), and it is checked whether n> 3008 is satisfied (step 205). If n ≦ 3008, it is checked whether i = 0 (step 206). If i is not 0, the processing after step 204 is repeated. If i is 0, the sign of the difference D is determined (step 207). If the sign of the difference D is positive, the DPLL control trigger DCT that instructs the delayed phase control is output to perform the delayed phase control (step 208). If the sign of the difference D is negative, the DPLL control trigger DCT for instructing the advance phase control is output to perform the advance phase control (step 209). If the difference D = 0, the current state is maintained without performing the advance / delay phase control (step 210). After executing the processing in steps 208 to 210, i = set value (step 211), and thereafter, the processing from step 204 is repeated until n> 3008.
[0045]
(e-3) Leaky packet type
FIG. 11 is a flow chart of a leaky packet type phase advance / delay control process.
When the difference D (= received RTS information−local RTS information) is input from the comparator 51d (FIG. 4) (step 301), a setting value (correction data) corresponding to the difference is obtained from the table (step 302), i = 0 and n = 0 are set (step 303).
Next, every time the reception user clock is generated, i and n are incremented (step 304), and it is checked whether n> 3008 is satisfied (step 305). If n ≦ 3008, it is checked whether i ≧ set value (step 306). If i <set value, the processing from step 304 is repeated. If i ≧ set value, the sign of the difference D is determined (step 307). If the sign of the difference D is positive, a DPLL control trigger DCT for instructing delayed phase control is output to perform delayed phase control (step 308). If the sign of the difference D is negative, the DPLL control trigger DCT for instructing the advance phase control is output to perform the advance phase control (step 309). If the difference D = 0, the current state is maintained without performing the advance / delay phase control (step 310). After executing the processes in steps 308 to 310, i = (i−set value) is set (step 311), and thereafter, the processes in and after step 304 are repeated until n> 3008.
The present invention has been described with reference to the embodiments. However, the present invention can be variously modified in accordance with the gist of the present invention described in the claims, and the present invention does not exclude these.
[0046]
【The invention's effect】
As described above, according to the present invention, the user data read from the cell buffer is stored in the buffer means in synchronization with the first reception user clock generated in the DPLL, and the stored data is generated from the buffer means in the analog PLL in chronological order. Since it is configured to read in synchronization with the receiving user clock No. 2, the DPLL feedback and the analog PLL feedback can be prevented from interfering with each other, and the jitter characteristics can be improved.
[0047]
Further, according to the present invention, correction data (clock phase correction period, phase correction timing, phase correction frequency) corresponding to the difference between local RTS information and received RTS information is stored, and the correction amount can be freely set from the outside Since it can be changed, it is possible to generate the clock by determining the correction amount so that the jitter characteristic becomes optimum.
Also, according to the present invention, user data included in a cell constituting a multiframe received one cycle before is buffered in synchronization with a received user clock included in the currently received multiframe and created using the received RTS information. Therefore, accurate synchronization control of the transmission user clock and the reception user clock without delay can be performed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a clock generator according to a first embodiment.
FIG. 2 is a configuration diagram of a clock generator of a second embodiment.
FIG. 3 is a block diagram of a clock generator according to a third embodiment.
FIG. 4 is a configuration diagram of a phase control unit.
FIG. 5 is a first explanatory diagram of correction data;
FIG. 6 is a second explanatory diagram of correction data.
FIG. 7 is a third explanatory diagram of correction data.
FIG. 8 is an explanatory diagram of DPLL control trigger generation when a correction cycle is passed to a correction unit.
FIG. 9 is an addition type phase advance / delay control process flow;
FIG. 10 is a flowchart of a subtraction type phase advance / delay control process.
FIG. 11 is a flow chart of phase lead / lag control processing of the leaky packet method.
FIG. 12 is an explanatory diagram of the structure of AAL type 1;
FIG. 13 is an explanatory diagram of the structure of a SAR-PDU header.
FIG. 14 is an explanatory diagram of a structure of an RTS information format.
FIG. 15 is a generation cycle of RTS information.
FIG. 16 is a configuration diagram of a conventional RTS generation and transmission unit.
FIG. 17 is a configuration diagram of a reception unit that generates a reception user clock synchronized with a transmission user clock.
FIG. 18 is a configuration diagram of a conventional clock generator in which DPLL and APLL are combined.
[Explanation of symbols]
51d..Comparison part
51e ... Phase control unit
51f ・ ・ DPLL
52 .. Reference clock counter (frequency divider)
53 ・ ・ APLL
55 .. FIFO for data transfer

Claims (8)

In the clock generator using the SRTS method that generates a reception clock synchronized with the transmission clock on the cell transmission side on the cell reception side,
The first reception clock is generated, and the difference between the local timing information (local RTS information) created based on the reception clock and the reception timing information (reception RTS information) received from the network is zero. A digital PLL circuit for controlling the phase of the reception clock;
A frequency divider that divides a first reception clock output from the digital PLL circuit to generate a phase comparison clock;
An analog PLL circuit for generating a second reception clock phase-synchronized with the phase comparison clock;
Buffer means for writing user data at a first reception clock and reading user data at a second reception clock;
A clock generator using the SRTS method, comprising: Comparison means for comparing local RTS information with received RTS information,
A phase control unit that generates a phase control signal based on a difference between local RTS information and received RTS information;
The clock generator according to claim 1, wherein the digital PLL circuit controls the phase of the first reception clock based on the phase control signal. The phase control unit
Storage means for storing correction data according to the difference between the local RTS information and the received RTS information;
Means for generating a phase control signal based on the correction data;
The clock generator according to claim 2, further comprising: In the clock generator using the SRTS method that generates a reception clock synchronized with the transmission clock on the cell transmission side on the cell reception side,
The reference so that the difference between the local timing information (local RTS information) created using the reference clock that is phase-controlled based on the RTS information and the reception timing information (received RTS information) received from the network becomes zero. Digital PLL circuit that controls the phase of the clock,
A frequency divider that divides the reference clock output from the digital PLL circuit to generate a phase comparison clock,
An analog PLL circuit that generates a reception clock that is phase-synchronized with the phase comparison clock, a buffer that stores cells received from the network in synchronization with the network clock,
A data read control unit that reads user data included in a cell constituting a multiframe received one cycle before from the buffer in synchronization with a reception clock included in the currently received multiframe and created using reception RTS information ,
A clock generator using the SRTS method. Comparison means for comparing local RTS information with received RTS information,
A phase control unit that generates a phase control signal based on a difference between local RTS information and received RTS information;
5. The clock generator according to claim 4, wherein the digital PLL circuit controls the phase of a reference clock based on a phase control signal. The phase control unit
Storage means for storing correction data according to the difference between the local RTS information and the received RTS information;
Means for generating a phase control signal based on the correction data;
6. The clock generator according to claim 5, further comprising: In the clock generator using the SRTS method that generates a reception clock synchronized with the transmission clock on the cell transmission side on the cell reception side,
Comparison means for comparing local timing information (local RTS information) created using a reference clock that is phase-controlled based on RTS information and reception timing information (received RTS information) received from the network,
A phase controller that generates a phase control signal based on the difference between the local RTS information and the received RTS information;
A digital PLL circuit for controlling the phase of the reference clock based on a phase control signal;
A frequency divider that divides the reference clock output from the digital PLL circuit to generate a phase comparison clock,
An analog PLL circuit that generates a reception clock that is phase-synchronized with a phase comparison clock, and the phase control unit includes:
Storage means for storing correction data according to the difference between the local RTS information and the received RTS information;
Means for generating a phase control signal based on the correction data;
A clock generator characterized by comprising: 8. The clock control apparatus according to claim 3, wherein the correction data includes at least one of phase correction synchronization, phase correction timing, and the number of phase control operations.

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