JP3640421B2 - Drive circuit for brushless motor - Google Patents

Description

端子６２がハイ・レベルで端子６３がロウ・レベルの場合、あるいは端子６２がロウ・レベルで端子６３がハイ・レベルの場合には、抵抗３７、抵抗４０のどちらかにしかＶ_ir／Ｒ₂ の電流が流れないので、Ｕ相端子電位補正回路の出力端子で観測される電位は、式（３）の様になる。

【０１０６】
結局、抵抗降下分の電圧を加算したい場合（Ｖ→Ｕ、Ｗ→Ｕ通電時）には端子６２、端子６３をハイ・レベルに設定し、抵抗降下分の電圧を減算したい場合（Ｕ→Ｖ、Ｕ→Ｗ通電時）には端子６２、端子６３をロウ・レベルに設定すれば端子電位を補正することが可能である。
また、Ｕ相が無通電相で補正する必要がない時（Ｖ→Ｗ、Ｗ→Ｖ通電時）には、端子６２をハイ・レベル、端子６３をロウ・レベルに設定するか、あるいは端子６２をロウ・レベル、端子６３をハイ・レベルに設定すれば良い。同様にＶ相に対しては、抵抗降下分の電圧を加算したい場合（Ｕ→Ｖ、Ｗ→Ｖ通電時）には端子６４、端子６５をハイ・レベルに設定し、抵抗降下分の電圧を減算したい場合（Ｖ→Ｕ、Ｖ→Ｗ通電時）には端子６４、端子６５をロウ・レベルに設定し、補正する必要がない時（Ｕ→Ｗ、Ｗ→Ｕ通電時）には、端子６４をハイ・レベル、端子６５をロウ・レベルに設定するか、あるいは端子６４をロウ・レベル、端子６５をハイ・レベルに設定すれば良い。
更にＷ相に対しては、抵抗降下分の電圧を加算したい場合（Ｕ→Ｗ、Ｖ→Ｗ通電時）には端子６６、端子６７をハイ・レベルに設定し、抵抗降下分の電圧を減算したい場合（Ｗ→Ｕ、Ｗ→Ｖ通電時）には端子６６、端子６７をロウ・レベルに設定し、補正する必要がない時（Ｕ→Ｖ、Ｖ→Ｕ通電時）には、端子６６をハイ・レベル、端子６７をロウ・レベルに設定するか、あるいは端子６６をロウ・レベル、端子６７をハイ・レベルに設定すれば良い。上記、通電相と端子６２〜６７に入力する補正切り換え信号の関係をタイミングチャートにまとめたものを図６（ｂ）に示す。
【０１０７】
また図６（ａ）は、検出した巻線端子電位に、実駆動期間のみ抵抗・電流の積を補正するための具体的な補正切り換え信号生成回路１６の詳細回路図である。本実施例では、入力として回転子位置信号３ａ、３ｂ、３ｃを使用して、論理素子の組み合わせで端子電位補正回路１の各端子６２〜６７へ図６（ｂ）に示す切り換え信号を送っている。
また本実施例では図１に示すように、電流制御回路２１１とそのバッファアンプ２１２、抵抗２１３、駆動トランジスタ２１４とで電機子に流れる巻線電流の電流制御をしているので、補正回路１の端子６１に電流制御回路２１１の出力を用いている。
電流制御回路２１１は、論理パルス信号２０１から実際の回転速度と指令回転速度との誤差を検出し、検出した誤差が零になるように電機子巻線に通電する電流量を制御する。
尚、本実施例においては、３相ブラシレスモータに適用した例について記述したが、３相に限らず複数相のブラシレスモータ全般に適用可能であることは明白である。また、本実施例においてトランジスタ回路で構成した手段をＯＰアンプやディジタルＩＣで構成しても良い。
【０１０８】
実施例２．
本実施例では、各相電機子巻線電圧を検出し、そのままでは位相遅れが生じるので実負荷状態でのみ負荷抵抗と電流の積である補正電圧を各相の電圧差に印加して補正し、実負荷状態での正しい位相での端子電圧を得て、この巻線端子電圧を基に転流回路で各電機子巻線の駆動電圧を生成するようにした。
本実施例では、この考えによるブラシレスモータの駆動装置の構成と動作を説明する。図８は本発明によるブラシレスモータの駆動装置の第２の実施例の全体構成を示すブロック図である。図８において実施例１と同一の部材は同一番号で示した。端子間電圧を補正して補正端子間電圧信号１００ａ〜１００ｆを出力する端子間電圧補正回路１００、補正された端子間電圧を比較して論理信号１０１ａ、１０１ｂ、１０１ｃを得る比較回路１０１、波形整形回路３を含んで回転子位置信号生成回路１０２が構成されている。
【０１０９】
図９に端子間電圧補正回路１００の具体的な一構成例を示す。図９において、１１０〜１２７はｎｐｎトランジスタ、１２８はｐｎｐトランジスタ、１２９〜１５５は抵抗、１５６〜１６２は定電流源であり、ｎｐｎトランジスタ１１０、１１７のベースにはＵ相端子電位が、ｎｐｎトランジスタ１１６、１２３のベースにはＶ相端子電位が、ｎｐｎトランジスタ１１１、１２２のベースにはＷ相端子電位が入力され、ｐｎｐトランジスタ１２８のベースには電機子巻線抵抗降下に係る電圧が入力される端子１６３が接続されている。また、１６４〜１６９は端子間電圧の補正を切り換える補正切り換え信号が入力される端子である。補正された端子間電圧は、１００ａ〜１００ｆとして出力される。
【０１１０】
端子間電圧補正回路の具体的動作について図を参照しながら説明する。図９において、電源電圧をＶ_cc、抵抗１２９、１３１、１３８、１４０、１４７、１４９の抵抗値をＲ₃ 、抵抗１３０、１３９、１４８の抵抗値をＲ₄ 、抵抗１３４、１３５、１４３、１４４、１５２、１５３の抵抗値をＲ₅ 、定電流源１５６、１５７、１５９〜１６２から供給される電流値をｉ₂ 、ｎｐｎトランジスタのベース電流をｉ_b 、端子１６３に入力される電圧をＶ_irとする。
【０１１１】
まず、端子１６４がハイ・レベルの場合について考える。この時ｎｐｎトランジスタ１１３のエミッタ電位は０となり、抵抗１３４には電流が流れない。抵抗１３０には、ｎｐｎトランジスタ１１０のエミッタ端子からｎｐｎトランジスタ１１１のエミッタ端子の方向に、（Ｕ−Ｗ）／Ｒ₄ なる電流が流れる。したがって、抵抗１２９に流れる電流は、ｉ₂ ＋（Ｕ−Ｗ）／Ｒ₄ −ｉ_b となり、端子間電圧補正回路１００から出力される１００ａは、式（４）の様になる。

一方、端子１６４がロウ・レベルの場合、抵抗１３４にもＶ_ir／Ｒ₅ なる電流が流れ、端子間電圧補正回路１００から出力される１００ａは、式（５）の様になる。

他の端子間電圧についても同様の手順で考えると、端子１６４〜１６９のロジック・レベルと１００ａ〜１００ｆの関係は図１０の様になる。
【０１１２】
図１１に比較回路１０１の具体的な一構成例を示す。図１１において、１７０〜１７２はコンパレータである。コンパレータ１７０は１００ｂと１００ａを比較して論理信号１０１ａを出力し、コンパレータ１７１は１００ｄと１００ｃを比較して論理信号１０１ｂを出力し、コンパレータ１７２は１００ｆと１００ｅを比較して論理信号１０１ｃを出力する。
比較回路１０１の具体的動作について考える。端子１６４および端子１６５がハイ・レベルの場合、コンパレータ１７０からはＵ＞Ｗなる論理信号１０１ａが出力される。端子１６４がロウ・レベルで端子１６５がハイ・レベルの場合には、｛Ｕ＋（Ｒ₄ ・Ｖ_ir）／（２・Ｒ₅ ）｝＞Ｗなる論理信号１０１ａが出力される。逆に、端子１６４がハイ・レベルで端子１６５がロウ・レベルの場合には、｛Ｕ−（Ｒ₄ ・Ｖ_ir）／（２・Ｒ₅ ）｝＞Ｗなる論理信号１０１ａが出力される。
【０１１３】
図５に示したように、Ｕ相とＷ相の端子電位が一致したことにより回転子位置を検出するのは、Ｕ→ＶからＷ→Ｖへ通電を切り換える時と、Ｖ→ＵからＶ→Ｗへ通電を切り換える時であるが、どちらの場合も比較時点においてＵ相は通電相でＷ相は無通電相となるので、Ｕ相端子電位には抵抗降下分の電圧が重畳されている。したがって、比較時点においてＵ相端子電位から抵抗降下分の電圧を補正する必要がある。Ｕ→ＶからＷ→Ｖへ通電を切り換える時はＵ相端子電位から抵抗降下分の電圧を減算する必要があり、Ｖ→ＵからＶ→Ｗへ通電を切り換える時はＵ相端子電位に抵抗降下分の電圧を加算する必要がある。したがって、（Ｒ₄ ・Ｖ_ir）／（２・Ｒ₅ ）を電機子巻線抵抗降下に係る電圧になるようにＲ４、Ｒ５を設定し、Ｕ→Ｖ通電時には端子１６４をハイ・レベル、端子１６５をロウ・レベルに、Ｖ→Ｕ通電時には端子１６４をロウ・レベル、端子１６５をハイ・レベルにしておけば、抵抗降下分の電圧を補正したＵ相端子電位とＷ相端子電位を比較して論理信号１０１ａを得ることになるので、実施例１と同様の効果を得ることが可能である。
【０１１４】
他の端子間電圧についても同様の手順で考えることができ、Ｖ→Ｗ通電時には端子１６６をハイ・レベル、端子１６７をロウ・レベルに、Ｗ→Ｖ通電時には端子１６６をロウ・レベル、端子１６７をハイ・レベルに、Ｗ→Ｕ通電時には端子１６８をハイ・レベル、端子１６９をロウ・レベルに、Ｕ→Ｗ通電時には端子１６８をロウ・レベル、端子１６９をハイ・レベルに設定すれば、実施例１と同様の効果を得ることが可能である。上記、通電相と端子１６４〜１６９に入力する補正切り換え信号の関係を図１２に示す。
【０１１５】
実施例３．
本実施例では、実施例１で述べた各相電機子巻線電圧を検出し、実負荷状態でのみ負荷抵抗と電流の積である補正電圧を印加して補正した後の、実負荷状態での正しい位相での端子電圧を基に、転流回路で各電機子巻線の駆動信号を生成するが、この際の補正切り換え信号として上記駆動信号を用いるようにした。
本実施例では、この考えによるブラシレスモータの駆動装置の構成と動作を説明する。図１３は本発明によるブラシレスモータの駆動装置の第３の実施例の全体構成を示すブロック図である。図１３において実施例１と同一の部材は同一番号で示した。本実施例では、駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆが各々端子電位補正回路１の端子６３、端子６５、端子６７、端子６２、端子６４、端子６６に入力される。
【０１１６】
実施例１の図６に示した補正切り換え信号は転流に同期した信号である。したがって、駆動トランジスタＴＲ１〜ＴＲ６を順次スイッチングする駆動信号を補正切り換え信号にも使用することが可能である。図１のようにブリッジ回路１１が構成された場合の通電相と駆動信号９ａ〜９ｆの関係を図７に示す。図６の端子６２、端子６３、端子６４、端子６５、端子６６、端子６７に対する補正切り換え信号と駆動信号９ｄ、９ａ、９ｅ、９ｂ、９ｆ、９ｃは各々一致している。したがって、本発明におけるブラシレスモータの駆動装置の一実施例を図１３に示すように構成することが可能である。
【０１１７】
実施例４．
本実施例は、実施例２と実施例３を併せた例である。即ち、各相電機子巻線電圧を検出し、実負荷状態でのみ負荷抵抗と電流の積である補正電圧を各相の電圧差に印加して補正し、正しい位相での端子電圧を基に転流回路で各電機子巻線の駆動信号を生成するが、この際の補正切り換え信号を駆動信号から得るようにした。
図１４は本発明のブラシレスモータの駆動装置の第４の実施例の全体構成を示すブロック図である。図１４において実施例２と同一の部材は同一番号で示した。本実施例では、駆動信号９ａが端子間電圧補正回路１００の端子１６５、端子１６８に、駆動信号９ｂが端子間電圧補正回路１００の端子１６４、端子１６７に、駆動信号９ｃが端子間電圧補正回路１００の端子１６６、端子１６９に入力される。
【０１１８】
端子間電圧を補正する場合も、実施例３と同様に、駆動トランジスタＴＲ１〜ＴＲ６を順次スイッチングする駆動信号を補正切り換え信号に用いることが可能である。例えば、端子１６４に入力する補正切り換え信号は、Ｕ→Ｖ通電時にハイ・レベル、Ｖ→Ｕ通電時にロウ・レベルであれば良いので、駆動信号９ｂ、９ｅを使用することが可能である。同様に端子１６５に入力する補正切り換え信号には駆動信号９ａ、９ｄを、端子１６６に入力する補正切り換え信号には駆動信号９ｃ、９ｆを、端子１６７に入力する補正切り換え信号には駆動信号９ｂ、９ｅを、端子１６８に入力する補正切り換え信号には駆動信号９ａ、９ｄを、端子１６９に入力する補正切り換え信号には駆動信号９ｃ、９ｆを使用することが可能である。したがって、本発明におけるブラシレスモータの駆動装置の一実施例を図１４に示すように構成することが可能である。
【０１１９】
実施例５．
本実施例では、実負荷状態でのみ負荷抵抗と電流の積である補正電圧を印加する際の負荷電流値として、負荷電流検出用のセンス抵抗を設けてこの検出電圧で実負荷電流を得るようにした。
本実施例では、この考えによるブラシレスモータの駆動装置の構成と動作を説明する。図１５において、実施例１と同一の部材は同一番号で示した。本実施例では、ＴＲ４〜ＴＲ６の共通エミッタ端子と端子電位補正回路１の端子６１が接続されている。
【０１２０】
図１５において、抵抗１０は駆動トランジスタＴＲ４〜ＴＲ６の共通エミッタ端子に接続されているので、電機子巻線に流れる電流は抵抗１０にも流れる。したがって、抵抗１０における電圧降下として、電機子巻線に通電されている電流量を検出することが可能である。電機子巻線に流れている電流をＩ_L 、１相分の電機子巻線抵抗の抵抗値をｒ、抵抗１０の抵抗値をＲ_s とすると、電機子巻線での抵抗降下はＩ_L ・ｒ、端子６１に入力される電位はＩ_L ・Ｒ_s である。端子電位補正回路で補正される電圧は、
Ｒ₁ ・Ｉ_L ・Ｒ_s ／Ｒ₂
であるので、この値がＩ_L ・ｒに等しくなるようにＲ₁ 、Ｒ₂ 、Ｒ_s を設定すれば良い。
【０１２１】
実施例６．
実施例２に実施例５の考えを適用した例を説明する。
図１６は本発明のブラシレスモータの駆動装置の第６の実施例の全体構成を示すブロック図である。図１６において実施例２と同一の部材は同一番号で示した。本実施例では、ＴＲ４〜ＴＲ６の共通エミッタ端子と端子間電圧補正回路１００の端子１６３が接続されている。
【０１２２】
端子間電圧を補正する場合も、電機子巻線抵抗降下に係る量の電圧は、実施例５と同様に、ＴＲ４〜ＴＲ６の共通エミッタ端子から検出することが可能であり、本発明におけるブラシレスモータの駆動装置の一実施例を図１６に示すように構成することが可能である。
【０１２３】
実施例７．
上記実施例では、いずれも波形は乱れのない理想的な波形であるとして動作を説明してきた。しかし実際には波形にはノイズが乗り、動作はチャタリングが生じており、図１８以降に述べるスパイク状のノイズが混入している。こうした波形でも正常に動作するよう考慮した例を説明する。
本実施例ではこうした考慮が払われており、検出信号波形をいったん波形整形回路で正しい安定な形に戻してから上記実施例で述べた補正及び駆動をしようとする。
図１７に波形整形回路３の具体的な一構成例を示す。図１７において、１８０はラッチ回路、１８１〜１８６はＤフリップフロップ、１８７〜１８９はＥＯＲ回路、１９０はＯＲ回路、１９１は単安定マルチバイブレータである。図１８は定常回転状態における端子電位波形および波形整形回路の各部の信号波形を示したものであり、図１９は図１８の時刻Ｔ０〜Ｔ１の間を拡大した図である。
【０１２４】
図１８、図１９を参照しながら波形整形回路の具体的動作について説明する。波形整形回路への入力信号は、比較回路２あるいは比較回路１０１から出力される論理信号２ａ、２ｂ、２ｃあるいは１０１ａ、１０１ｂ、１０１ｃである。実施例１、実施例２では、駆動トランジスタのスイッチングに伴って端子電位波形に発生するスパイク状の電圧変動を無視して考えてきたが、実際には、端子電位波形にスパイク状の電圧変動が発生する。当然、電機子巻線抵抗降下を補正した端子電位波形にも、その電圧変動は残留する。したがって、端子電位同士を比較して得られる論理信号２ａ、２ｂ、２ｃは図１８に示したようなスパイク状のノイズを含んでいる。
【０１２５】
この論理信号は、まず、ラッチ回路１８０に入力される。ラッチ回路１８０は、イネーブル端子１８０ａの状態に応じてラッチ動作を行う回路で、イネーブル端子１８０ａがハイ・レベルの時は入力データをそのまま出力する。イネーブル端子１８０ａがロウ・レベルになると、入力データをラッチし、イネーブル端子１８０ａがロウ・レベルの間、ラッチしたデータを出力し続ける。初期状態においてラッチ回路１８０のイネーブル端子１８０ａはハイ・レベルであり、論理信号２ａ、２ｂ、２ｃはそのまま各々Ｄフリップフロップ１８１、１８３、１８５に入力される。Ｄフリップフロップ１８１〜１８６とＥＯＲ回路１８７〜１８９は両エッジ微分回路を構成しており、論理信号２ａ、２ｂ、２ｃの立ち上がり及び立ち下がりエッジのタイミングでＥＯＲ回路１８７〜１８９は微分パルスを出力する。時刻Ｔ２において、補正された端子電位１ａと１ｃの電位レベルが一致し２ａの極性が変化すると、両エッジ微分回路でエッジが検出され、微分パルス２０３が発生される。ＥＯＲ回路１８７〜１８９の出力信号はＯＲ回路１９０で合成されて論理パルス信号２０１になり、単安定マルチバイブレータ１９１に入力される。単安定マルチバイブレータ１９１は論理パルス信号２０１の立ち上がりエッジをトリガにして、一定時間Ｔ３の間、ロウ・レベルのパルス２０４を出力する。パルス２０４はラッチ回路のイネーブル端子１８０ａに入力される。イネーブル端子１８０ａがロウ・レベルとなったので、ラッチ回路１８０は論理信号２ａ、２ｂ、２ｃをラッチし、パルス２０４がロウ・レベルの間ラッチしたデータを出力し続ける。Ｄフリップフロップ１８２、１８４、１８６の出力信号１９５、１９６、１９７は波形整形された回転子位置信号３ａ、３ｂ、３ｃとなり、次段の転流回路９に入力され、転流動作が行われる。転流動作が行われると、駆動トランジスタがスイッチングするのでＵ相端子電位波形にスパイク状の電圧変動が発生し、その結果、所望でない位置においてスパイク状のノイズ２０５が２ｂに発生する。しかし、スパイク状ノイズ２０５が発生した時点においては、ラッチ回路へのデータ入力は単安定マルチバイブレータ１９１からのパルス２０４によりディセーブルされている。したがって、スパイク状ノイズ２０５はラッチ回路１８０でマスクされ、波形整形された回転子位置信号３ａ、３ｂ、３ｃにはスパイク状ノイズは発生しない。
【０１２６】
上記で説明した波形整形回路３において、ＯＲ回路１９０から出力される論理パルス信号２０１は、定常回転時において一定時間間隔で得られる信号である。したがって、この論理パルス信号２０１を回転速度を制御するための速度信号として使用することが可能である。
尚、本実施例では、３相ブラシレスモータの例を記述したが、３相に限らず複数相のブラシレスモータ全般に適用可能である。
【０１２７】
実施例８．
次にスタート時に負荷に影響されず、短時間に安定起動する装置の構成と動作について説明する。
即ち起動時には、各相毎の検出電圧からあり得る組み合わせの信号が得られるように駆動を始めるようにした。具体的には、ブラシレスモータの各相巻線電位から回転子の位置信号を検出し、この回転子位置信号の立ち上がり・立ち下がりエッジを検出・選択して必要エッジ信号を得るようにし、また必要エッジ信号をカウントして起動時の各相の電機子巻線の印加駆動信号とした。更に、この入力がある時間得られない場合は強制的に印加駆動信号を与えるようにした。
図２０に上記考えによる３相ブラシレスモータの駆動装置の一実施例の全体構成図を示す。９は駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する転流回路、１１はブラシレスモータの所定相を通電するブリッジ回路、４はブラシレスモータの各端子電位から位置信号３ａ、３ｂ、３ｃを生成する回転子位置信号生成回路、７は位置信号３ａ、３ｂ、３ｃの立ち上がり及び立ち下がりエッジを検出・選択して必要エッジ信号を得て、その必要エッジ信号をカウントするカウンタ回路、６は疑似パルス６ａを出力するパルス発生回路を表している。
【０１２８】
以下詳細に説明する。モータ回転信号５ａは外部から入力される信号で、イネーブルの時は回転を、ディセーブルの時は停止を表す。また、本実施例では、イネーブルはハイ、ディセーブルはロウとする。
【０１２９】
図２０において、モータ回転信号５ａは転流回路９とカウンタ回路７に接続されている。転流回路９から出力される駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆは各々トランジスタＴＲ１、ＴＲ２、ＴＲ３、ＴＲ４、ＴＲ５、ＴＲ６のベースに接続される。本実施例では、トランジスタＴＲ１、ＴＲ２、ＴＲ３はｐｎｐ型トランジスタで、トランジスタＴＲ４、ＴＲ５、ＴＲ６はｎｐｎ型トランジスタで構成している。また、トランジスタＴＲ１、ＴＲ２、ＴＲ３のエミッタは電源に、コレクタはトランジスタＴＲ４、ＴＲ５、ＴＲ６のコレクタに接続され、トランジスタＴＲ４、ＴＲ５、ＴＲ６のエミッタは抵抗１０を介して接地されている。これらのトランジスタ群によりブリッジ回路１１が構成されている。また、トランジスタＴＲ１、ＴＲ２、ＴＲ３、ＴＲ４、ＴＲ５、ＴＲ６のコレクタは３相ブラシレスモータのスター結線されたＵ相、Ｖ相、Ｗ相の各電機子巻線の端子に接続されている。従って各トランジスタをオンオフすることによって各電機子巻線が通電される。図２１に本実施例のおける駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆと通電相の関係表を示す。図２１は図７を表で表わしたものである。図２１中矢印の順に通電相を切換れば回転子は正転する。
【０１３０】
ブリッジ回路１１と接続されている各電機子巻線の端子は回転子位置信号生成回路４にも接続されている。回転子位置信号生成回路４では、Ｕ相、Ｖ相、Ｗ相の端子電圧Ｕ、Ｖ、Ｗから３ビットの位置信号３ａ、３ｂ、３ｃを生成する。図２２に本実施例における駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆと位置信号３ａ、３ｂ、３ｃの論理関係例を示す。回転子位置信号生成回路４から出力された位置信号３ａ、３ｂ、３ｃはカウンタ回路７に入力される。
【０１３１】
本実施例のカウンタ回路７の構成図を図２３に示す。位置信号３ａ、３ｂ、３ｃは、各々、立ち上がりエッジ検出回路２５０、２５２、２５４と立ち下がりエッジ検出回路２５１、２５３、２５５に入力され、立ち上がりエッジ検出回路２５０、２５２、２５４で立ち上がりエッジパルス２５０ａ、２５２ａ、２５４ａが、立ち下がりエッジ検出回路で立ち下がりエッジパルス２５１ａ、２５３ａ、２５５ａが出力される。検出されたエッジパルス２５０ａ、２５２ａ、２５４ａ、２５１ａ、２５３ａ、２５５ａはパルス選択回路２５６に入力される。また、図２０に示すパルス発生回路６から出力される疑似パルス６ａもパルス選択回路２５６に入力される。パルス選択回路２５６の出力であるパルス列７ｄはカウンタに入力される。本実施例では、パルス列７ｄをカウントするカウンタに６進カウンタ２５７を用いている。本実施例で用いた６進カウンタ２５７の入力されたパルス数と出力値の論理関係例を図２４に示す。図中入力パルス数が６以上の場合、カウンタ値７ａ、７ｂ、７ｃは再びロウ・ロウ・ロウからカウントする。また、パルス列７ｄは、図２０中のパルス発生回路６にも入力されるため、カウンタ回路７から出力される。６進カウンタ２５７から出力されるカウンタ値７ａ、７ｂ、７ｃはカウンタ回路７内のパルス選択回路２５６と、図２０中の転流回路９に入力される。パルス選択回路２５６は、現在のカウンタ値７ａ、７ｂ、７ｃを参照して、正転時に次に検出されるべき理論的な位置信号のエッジパルスもしくは疑似パルス６ａを出力する。本実施例におけるカウンタ値７ａ、７ｂ、７ｃと正転時に次に検出されるべき理論的なエッジパルス２５０ａ、２５２ａ、２５４ａ、２５１ａ、２５３ａ、２５５ａの論理関係例を図２５に示す。図２５より、例えば、カウンタ値７ａ、７ｂ、７ｃがロウ・ロウ・ロウの時は、エッジパルス２５３ａを出力し、他の例えばエッジパルス２５０ａが入力されても出力しない。但し、疑似パルス６ａは、入力されるとカウンタ値７ａ、７ｂ、７ｃに関わらず出力される。
【０１３２】
図２６に本実施例のパルス発生回路６の構成図を示す。本実施例ではパルス発生回路６をリトリガブルワンショット２６０と立ち上がりエッジ検出回路２６１で構成した。リトリガブルワンショット２６０には上記パルス選択回路２５６出力のパルス列７ｄが入力される。リトリガブルワンショット２６０の出力２６０ａは立ち上がりエッジ検出回路２６１に入力され、上記カウンタ回路７内に設けた立ち上がりエッジ検出回路２５０、２５２、２５４と同様に、リトリガブルワンショット２６０の出力２６０ａの立ち上がりエッジを検出し、疑似パルス６ａを出力する。このような構成において、リトリガブルワンショット２６０内で設定された時間以内にパルス列７ｄのパルスが入力された場合、リトリガブルワンショット２６０はクリアされ、出力２６０ａは変化せず、従って、疑似パルス６ａは出力されない。しかし、設定された時間内にパルス列７ｄが入力されない場合、リトリガブルワンショット２６０の出力２６０ａがロウからハイに変化する構成なので、その立ち上がりを検出し、疑似パルス６ａが出力される。
【０１３３】
また、本実施例ではリトリガブルワンショット２６０がクリアされた場合は出力２６０ａはロウで、所定時間内にパルス列７ｄが入力されない場合ハイに変化する様構成されているが、立ち下がりエッジ検出回路を用いて、リトリガブルワンショット２６０がクリアされた場合の出力２６０ａはハイで、所定時間内にパルス列７ｄが入力されない場合ロウに変化する構成にしても同様の疑似パルス６ａが得られる。
【０１３４】
転流回路９は、モータ回転信号５ａがロウの時は駆動信号９ａ、９ｂ、９ｃをハイに、駆動信号９ｄ、９ｅ、９ｆをロウに設定して、ブリッジ回路１１のトランジスタ群をオフしてブラシレスモータを無通電状態にする。次にモータ回転信号５ａがハイになった直後の起動モード時は、カウンタ値７ａ、７ｂ、７ｃの組合せによって回転子が正転する様に駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。本実施例で設定した駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆとカウンタ回路７出力値７ａ、７ｂ、７ｃの論理関係組合せ例を図２７に示す。図中矢印の方向に駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを切り換えれば回転子は正転する。
【０１３５】
次に本実施例におけるブラシレスモータの動作について説明する。モータ回転信号５ａがハイになった直後は、カウンタ値７ａ、７ｂ、７ｃはロウ・ロウ・ロウになるので、図２７より駆動信号９ｂがロウに、９ｆがハイになり、図２１よりＶ−Ｗ相が通電される。この時、ブラシレスモータの回転子が正転して位置信号が変化する場合、逆転して位置信号が変化する場合、もしくは通電安定点に停止して位置信号が変化しない場合がある。
【０１３６】
まず、回転子が正転した場合について説明する。図２８は回転子が正転した場合の各部信号波形例である。Ｖ−Ｗ相が通電されることで図２１と図２２より位置信号３ａ、３ｂ、３ｃがハイ・ハイ・ロウになる。この時カウンタ値７ａ、７ｂ、７ｃがロウ・ロウ・ロウであるから、図２５よりエッジパルス２５３ａもしくは疑似パルス６ａが検出されない限り６進カウンタ２５７はカウントしない。そして、イナーシャによって回転子が更に正転方向に回転すると、電機子巻線に発生する逆起電力により端子電圧Ｕ、Ｖ、Ｗが変化し、位置信号３ａ、３ｂ、３ｃがハイ・ロウ・ロウになり、図２８中の（Ａ）のようにエッジパルス２５３ａが検出される。従って、６進カウンタ２５７はカウントアップして、カウンタ値７ａ、７ｂ、７ｃがハイ・ロウ・ロウになり、転流回路９は図２１と図２７よりＵ−Ｗ相を通電するように駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆをロウ・ハイ・ハイ・ロウ・ロウ・ハイに設定する。そして、その後は定常回転するまでカウンタ値７ａ、７ｂ、７ｃの組合せを参照し図２７に示す関係に従って順次通電相を切換えてブラシレスモータは起動される。
【０１３７】
次に、回転子が逆転して位置信号が変化した場合について図２９を用いて説明する。図２９は回転子が逆転した場合の各部信号波形例である。回転子が逆転すると位置信号３ａが変化して、図２９中の（Ｂ）に示すエッジパルス２５１ａが検出されるが、上記に述べた様にエッジパルス２５３ａが検出されないため６進カウンタ２５７はカウントアップしない。そして、所定時間ｔ₁ 以内にエッジパルス２５３ａが検出できないため、図２９中の（Ｃ）に示すようにパルス発生回路６から疑似パルス６ａが出力される。６進カウンタ２５７はこの疑似パルス６ａによってカウントアップして、カウンタ値７ａ、７ｂ、７ｃがハイ・ロウ・ロウと変化する。そして、転流回路９で図２１と図２７よりＵ−Ｗ相が通電するように駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆをロウ・ハイ・ハイ・ロウ・ロウ・ハイに設定する。これによって、回転子は正転し、その後は上記正転時と同様に定常回転するまでカウンタ値７ａ、７ｂ、７ｃの組合せを参照し図２７に示す関係に従って順次通電相を切換えてブラシレスモータは起動される。
【０１３８】
更に回転子が動かず位置信号が変化しない場合も逆転する場合と同様に、所定時間ｔ₁ 以内にエッジパルス２５３ａを検出できないため、パルス発生回路６から疑似パルス６ａが出力される。そして、上記逆転時と同様に６進カウンタ２５７はその疑似パルス６ａをカウントし、図２１と図２７より通電相がＵ−Ｗ相に切換わり、その後定常回転するまでカウンタ値７ａ、７ｂ、７ｃの組合せを参照し図２７に示す関係に従って順次通電相を切換えてブラシレスモータは起動される。
【０１３９】
実施例９．
次に動作中に何らかの原因でモータが止まり再起動が必要な場合でも、短時間に安定に再起動する装置の構成と動作について説明する。
具体的には再起動時には、ブラシレスモータの各相巻線電位から回転子の位置信号を検出し、この回転子位置信号の立ち上がり・立ち下がりエッジを検出・選択して必要エッジ信号を得るようにし、更にこの信号と組み合わせてモータの回転を監視する定常回転検知回路を設けた。異常検知時にはエッジ信号をカウントして再起動時の各相の電機子巻線の強制印加駆動信号とした。
図３０に上記考えによる３相ブラシレスモータの駆動装置の実施例９の全体構成図を示す。ブリッジ回路１１、回転子位置信号生成回路４、カウンタ回路７、パルス発生回路６は実施例８と同様なので説明を省略する。２６５はカウンタ値７ａ、７ｂ、７ｃと位置信号３ａ、３ｂ、３ｃを比較する定常回転検知回路である。
【０１４０】
本実施例において、位置信号３ａ、３ｂ、３ｃは転流回路９にも入力される。転流回路９は、起動モード時は、実施例８と同様にカウンタ値７ａ、７ｂ、７ｃの組合せによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力し、定常回転中は、位置信号３ａ、３ｂ、３ｃの組合せによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力するよう構成されている。また、位置信号３ａ、３ｂ、３ｃとカウンタ値７ａ、７ｂ、７ｃは定常回転検知回路２６５にも入力される。定常回転検知回路２６５は、定常回転中、カウンタ値が変化した後、所定時間後に位置信号３ａ、３ｂ、３ｃとカウンタ値７ａ、７ｂ、７ｃを比較する。本実施例における位置信号３ａ、３ｂ、３ｃとカウンタ値７ａ、７ｂ、７ｃの理論的な論理関係組合せ例を図３１に示す。そして、その組合せが図３１に示す組合せでないときは、再起動パルス２６５ａを出力する。再起動パルス２６５ａは転流回路９に入力される。
【０１４１】
このような構成において、定常回転中、何らかの負荷により回転子が停止した時の例を図３２を用いて説明する。図３２において（Ｄ）以降回転子が停止したとする。この場合、パルス（ｏ１）からパルス発生回路６内で設定された時間ｔ₁ 経過後、パルス発生回路６から疑似パルス（ｐ２）が出力される。そして、疑似パルス（ｐ２）はパルス選択回路２５６からパルス列７ｄのパルス（ｏ２）として出力され、カウンタ値７ａ、７ｂ、７ｃはロウ・ハイ・ロウから図２４の論理関係例よりロウ・ロウ・ハイに変化する。定常回転中は前述したように、位置信号３ａ、３ｂ、３ｃの組合せによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力しているので、カウンタ値７ａ、７ｂ、７ｃが変化しても通電相は切換わらない。そして、カウンタ値７ａ、７ｂ、７ｃが変化してから所定時間ｔ₂ 後、定常回転検知回路２６５で位置信号３ａ、３ｂ、３ｃとカウンタ値７ａ、７ｂ、７ｃの比較を行なう。この場合、図３１より、理論的な組合せではないため、定常回転検知回路２６５から再起動パルス（ｑ３）が出力され、起動モードに移行する。起動モードでは前述したように、カウンタ値７ａ、７ｂ、７ｃの組合せによって起動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する構成なので、図２７より駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆがハイ・ハイ・ロウ・ロウ・ハイ・ロウになり通電が切換わり、正転する。その後は、実施例８で述べたようにして、定常回転するまで、図２７に示す関係に従ってカウンタ値７ａ、７ｂ、７ｃの組合せによって順次通電が切換わる。
【０１４２】
実施例１０．
次に起動時または再起動時から定常動作への切換装置を設けたモータ駆動回路を説明する。
本実施例では、この切り換えを時間設定とし、ある時間後に定常動作に切り換えるようにした。
図３３に本発明による３相ブラシレスモータの駆動装置の実施例１０の全体構成図を示す。ブリッジ回路１１、回転子位置信号生成回路４、カウンタ回路７、パルス発生回路６、定常回転検知回路２６５は上記第８及び第９の実施例と同様である。８は、転流回路９で駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する際に、カウンタ値７ａ、７ｂ、７ｃと位置信号３ａ、３ｂ、３ｃのどちらを参照するかを切換えるための切換信号８ａを出力する切換信号発生回路である。以下、切換信号発生回路８を説明する。
【０１４３】
本実施例において、モータ回転信号５ａと再起動パルス２６５ａは切換信号発生回路８に入力される。切換信号８ａは転流回路９に入力される。
図３４に本実施例の切換信号発生回路８の構成図を示す。本実施例では切換信号発生回路８をタイマ２７０で構成している。
【０１４４】
次に図３５を用いて本実施例の切換信号発生回路８の動作を説明する。本実施例ではタイマ２７０に入力されるモータ回転信号５ａがハイになると、タイマ２７０はオンされ、転流回路９は図２７に示す関係に従ってカウンタ値７ａ、７ｂ、７ｃの組合せによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。そして、所定時間ｔ₀ 経過後に切換信号８ａがロウからハイに変化し、転流回路９は、位置信号３ａ、３ｂ、３ｃの組合せを用いて図２２に示すように駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。
【０１４５】
また、転流回路９が位置信号３ａ、３ｂ、３ｃの組合せによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力している時、定常回転検知回路２６５出力の再起動パルス２６５ａが入力されるとタイマ２７０はリセットされて、切換信号８ａがハイからロウに変化する。これにより、転流回路９は、カウンタ値７ａ、７ｂ、７ｃを用いて駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。そして、再び所定時間ｔ₀ 後に切換信号８ａがロウからハイに変化して、転流回路９は位置信号３ａ、３ｂ、３ｃの組合せを用いて図２２に示すように駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。
【０１４６】
本実施例において、切換信号８ａは、カウンタ値７ａ、７ｂ、７ｃを参照する場合をロウ、位置信号３ａ、３ｂ、３ｃを参照する場合をハイに設定したが、逆に設定してもよい。
【０１４７】
実施例１１．
本実施例では、切換動作時にカウンタが一定値をカウントした後に定常動作に切り換えるようにした。こうすることで確実にモータ回転ができる。
図３６に本発明による３相ブラシレスモータの駆動装置の第１１の実施例の全体構成図を示す。８Ｃは、転流回路９で駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する際に、カウンタ値７ａ、７ｂ、７ｃと位置信号３ａ、３ｂ、３ｃのどちらを参照するかを切換えるための切換信号８ａを出力する切換信号発生回路である。以下、切換信号発生回路８Ｃを説明する。
【０１４８】
本実施例ではパルス列７ｄとモータ回転信号５ａと再起動パルス２６５ａが切換信号発生回路８Ｃに入力される。切換信号８ａは転流回路９に入力される。
図３７に本実施例の切換信号発生回路８Ｃの構成図を示す。本実施例では切換信号発生回路８Ｃをモード切換カウンタ２７１で構成している。
【０１４９】
次に図３８を用いて本実施例の切換信号発生回路８Ｃの動作を説明する。モード切換カウンタ２７１は、モータ回転信号５ａがハイになると、パルス列７ｄのカウントを開始し、転流回路９は図２７に示す関係に従ってカウンタ値７ａ、７ｂ、７ｃの組合せによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。そして、モード切換カウンタ２７１がパルス列７ｄを所定回数Ｘ回カウントしたら、切換信号８ａがロウからハイに変化し、転流回路９は図２２に示すように位置信号３ａ、３ｂ、３ｃの組合せによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。
【０１５０】
また、転流回路９が位置信号３ａ、３ｂ、３ｃの組合せによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力している時、定常回転検知回路２６５出力の再起動パルス２６５ａが入力されるとモード切換カウンタ２７１はリセットされ、切換信号８ａがハイからロウに変化する。これにより、転流回路９は図２７に示す関係に従って、カウンタ値７ａ、７ｂ、７ｃを用いて駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。そして、モード切換カウンタ２７１は、再びパルス列７ｄのカウントを開始し、所定回数Ｘ回カウントしたら、切換信号８ａがロウからハイに変化して、転流回路９は位置信号３ａ、３ｂ、３ｃの組合せを用いて図２２に示すように駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。
【０１５１】
実施例１２．
本実施例では、切り換えを時間と位置信号の検出の組み合せ、つまり両方の条件を満足した時に切り換わる方式とした。
図３９に本発明による３相ブラシレスモータの駆動装置の第１２の実施例の全体構成図を示す。８Ｄはカウンタ値７ａ、７ｂ、７ｃと位置信号３ａ、３ｂ、３ｃのどちらを参照するかを切換えるための切換信号８ａを出力する切換信号発生回路である。以下、切換信号発生回路８Ｄを説明する。
本実施例ではモータ回転信号５ａと再起動パルス２６５ａと位置信号３ａ、３ｂ、３ｃが切換信号発生回路８Ｄに入力される。切換信号８ａは転流回路９に入力される。
【０１５２】
図４０に本実施例の切換信号発生回路８Ｄの構成図を示す。本実施例では切換信号発生回路８Ｄを位置信号組合せ判別回路２７２とタイマ２７０によって構成されている。タイマ２７０は実施例１０の構成と同様である。位置信号組合せ判別回路２７２には、位置信号３ａ、３ｂ、３ｃが入力され、位置信号３ａ、３ｂ、３ｃが所定の組合せになった時、出力はハイになる構成である。本実施例では位置信号３ａ、３ｂ、３ｃがハイ・ロウ・ロウの組合せになった時、ハイに変化する。位置信号組合せ判別回路２７２とタイマ２７０の出力はＡＮＤ回路２７３に入力され、ＡＮＤ回路出力２７３ａとモータ回転信号５ａと再起動パルス２６５ａはラッチ回路２７４に入力される。ラッチ回路２７４はモータ回転信号５ａと再起動パルス２６５ａによってクリアされ、入力信号が一旦ハイになると、クリアされるまで出力をハイに保持する回路である。
【０１５３】
次に図４１を用いて本実施例の切換信号発生回路８Ｄの動作を説明する。モータ回転信号５ａがハイになると、タイマ２７０がオンされ、転流回路９は図２７に示す関係に従ってカウンタ値７ａ、７ｂ、７ｃの組み合わせによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。そして、所定時間ｔ₀ 経過後、タイマ出力２７０ａがハイに変化する。そして、タイマ出力２７０ａがハイで、位置信号３ａ、３ｂ、３ｃがハイ・ロウ・ロウの組合せになった時、ＡＮＤ回路出力２７３ａがハイに変化する。モータ回転信号５ａがハイに変化した後の最初のＡＮＤ回路出力２７３ａの立ち上がりエッジでラッチ回路２７４が動作し、切換信号８ａがハイに保持される。これにより、転流回路９は図２２に示すように位置信号３ａ、３ｂ、３ｃの組合せによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。
【０１５４】
また、転流回路９が位置信号３ａ、３ｂ、３ｃの組み合わせによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力している時、再起動パルス２６５ａが入力されると、タイマ２７０とラッチ回路２７４はリセットされて、切換信号８ａがハイからロウに変化する。これにより、転流回路９はカウンタ値７ａ、７ｂ、７ｃを用いて駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。そして、上記に述べたように、所定時間ｔ₀ 後、位置信号３ａ、３ｂ、３ｃがハイ・ロウ・ロウの組合せになった時、切換信号８ａがロウからハイに変化して、転流回路９は再び位置信号３ａ、３ｂ、３ｃの組合せを用いて駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。
【０１５５】
実施例１３．
本実施例は、切り換えをカウンタが一定値になったことと、位置信号が正常検出されたことの両方が得られることで切り換わる方式である。
図４２に本発明による３相ブラシレスモータの駆動装置の実施例１３の全体構成図を示す。以下、本実施例の切換信号発生回路８Ｅを説明する。
本実施例では位置信号３ａ、３ｂ、３ｃとパルス列７ｄとモータ回転信号５ａと再起動パルス２６５ａが切換信号発生回路８Ｅに入力される。切換信号８ａは転流回路９に入力される。
【０１５６】
図４３に本実施例の切換信号発生回路８Ｅの構成図を示す。本実施例の切換信号発生回路８Ｅは、先の実施例で述べた位置信号組合せ判別回路２７２とモード切換カウンタ２７１によって構成されている。
次に図４４を用いて本実施例の切換信号発生回路８Ｅの動作を説明する。モータ回転信号５ａがハイになると、モード切換カウンタ２７１はパルス列７ｄのカウントを開始し、転流回路９は図２７に示す関係に従ってカウンタ値７ａ、７ｂ、７ｃの組み合わせによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。そして、所定回数Ｘ回カウントすると、モード切換カウンタ２７１の出力２７１ａがハイになり、位置信号が所定のハイ・ロウ・ロウの組合せになり、ＡＮＤ回路２７３の出力２７３ａがハイになる。モータ回転信号５ａがハイに変化した後の最初のＡＮＤ回路出力２７３ａの立ち上がりエッジでラッチ回路２７４が動作し、切換信号８ａがロウからハイに変化してハイで保持される。こうして、転流回路９は位置信号３ａ、３ｂ、３ｃの組み合わせによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。
【０１５７】
また、転流回路９が位置信号３ａ、３ｂ、３ｃの組み合わせによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力している時、再起動パルス２６５ａが入力されると、モード切換カウンタ２７１とラッチ回路２７４はリセットされ、切換信号８ａがハイからロウに変化し、転流回路９はカウンタ値７ａ、７ｂ、７ｃの組み合わせを用いて駆動信号を出力する。
モード切換カウンタ２７１がパルス列７ｄを所定回数Ｘ回カウントし、位置信号が所定のハイ・ロウ・ロウの組合せになった時、切換信号８ａがロウからハイに変化し、再び、位置信号３ａ、３ｂ、３ｃの組み合わせを用いて駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。
【０１５８】
実施例１４．
本実施例は、切り換えを設定時間経過後と駆動信号が正常であることを同時に満足することで切り換えるようにした。
図４５に本発明による３相ブラシレスモータの駆動装置の実施例１４の全体構成図を示す。以下、本実施例の切換信号発生回路８Ｆを説明する。
本実施例では駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆとモータ回転信号５ａと再起動パルス２６５ａが切換信号発生回路８Ｆに入力される。
【０１５９】
図４６に本実施例の切換信号発生回路８Ｆの構成図を示す。本実施例の切換信号発生回路８Ｆは、駆動信号組合せ判別回路２７５と先に述べたタイマ２７０によって構成されている。駆動信号組合せ判別回路２７５には駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆが入力される。駆動信号組合せ判別回路２７５は、駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆが所定の組合せになった時出力２７５ａがハイになる構成である。本実施例では、駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆがロウ・ハイ・ハイ・ロウ・ハイ・ロウの組合せになった時出力２７５ａがハイになる。駆動信号組合せ判別回路２７５とタイマ２７０の出力はＡＮＤ回路２７３に入力され、また、ＡＮＤ回路出力２７３ａとモータ回転信号５ａと再起動パルス２６５ａは、先の実施例で述べたラッチ回路２７４に入力される。
【０１６０】
図４７は、本実施例の切換信号発生回路８Ｆの動作の説明図である。モータ回転信号５ａがハイになると、タイマ２７０がオンされ、転流回路９はカウンタ値の組み合わせを用いて駆動信号を出力する。そして、所定時間ｔ₀ 経過後、タイマ出力２７０ａがハイに変化し、駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆがロウ・ハイ・ハイ・ロウ・ハイ・ロウの組合せになった時、ＡＮＤ回路２７３の出力２７３ａがハイに変化する。以降、先の実施例で述べたと同様に変化していき、転流回路９は再び位置信号３ａ、３ｂ、３ｃの組み合わせを用いて駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。
また、再起動パルス２６５ａが入力された場合の動作も図４７に示すように、先の実施例で述べたと同様の動作をしていって、転流回路９はｔ₀ 後に再び位置信号３ａ、３ｂ、３ｃの組み合わせを用いて駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。
【０１６１】
実施例１５．
本実施例では、切り換えをカウンタが一定値をカウント後、駆動信号が正常になったことの両方を満足する条件で行うようにした。
図４８に本発明による３相ブラシレスモータの駆動装置実施例１５の全体構成図を示す。以下、本実施例の切換信号発生回路８Ｇを説明する。
本実施例では駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆとパルス列７ｄとモータ回転信号５ａと再起動パルス２６５ａが切換信号発生回路８Ｇに入力される。
【０１６２】
図４９に本実施例の切換信号発生回路８Ｇの構成図を示す。本実施例の切換信号発生回路８Ｇは、駆動信号組合せ判別回路２７５とモード切換カウンタ２７１によって構成されている。
図５０は、本実施例の切換信号発生回路８Ｇの動作を説明する図である。起動時、及び再起動時の動作は、今まで述べてきた実施例の動作説明と同様なので説明を省略する。
【０１６３】
実施例１６．
本実施例では、切り換えを速度検出で行う例を説明する。
図５１に本発明による３相ブラシレスモータの駆動装置の実施例１６の全体構成図を示す。以下、本実施例の切換信号発生回路８Ｈを説明する。
本実施例では回転子位置信号生成回路４内の波形整形回路３から出力される論理パルス２０１とモータ回転信号５ａと再起動パルス２６５ａが切換信号発生回路８Ｈに入力される。
【０１６４】
図５２に本実施例の切換信号発生回路８Ｈの構成図を示す。本実施例の切換信号発生回路８Ｈは、速度信号生成回路２７７と、基準速度発生回路２７６と、比較回路２７８によって構成されている。論理パルス２０１とＣＬＫは速度信号生成回路２７７に入力される。実施例１あるいは実施例７で記述したように、論理パルス２０１はある時間間隔で得られる信号であるので、論理パルス２０１からブラシレスモータの回転速度を検出することが可能である。
図５３に速度信号２７７ａの生成方法のタイミングチャートを示す。速度信号生成回路２７７は、モータ回転信号５ａがハイの時、ＣＬＫのエッジのタイミングでカウントアップし、波形整形回路３から入力される論理パルスの立ち上がりエッジのタイミングでクリアされ、図中矢印の値が速度信号２７７ａとして出力される。基準速度発生回路２７６は、起動モードから定常回転モードに切換える基準速度信号２７６ａを出力する。比較回路２７８は論理パルスの立ち上がりエッジのタイミングにおいて、速度信号２７７ａと基準速度信号２７６ａを例えば電圧レベルやビット数などで比較して、速度信号２７７ａが基準速度信号２７６ａに達したら切換信号８ａを出力する。
【０１６５】
次に図５４を用いて本実施例の切換信号発生回路８Ｈの動作について説明する。起動時にモータ回転信号５ａがハイになると、比較回路２７８で速度信号２７７ａと基準速度信号２７６ａの比較を開始する。そして、速度信号２７７ａが基準速度信号２７６ａに達したら、比較回路２７８出力の切換信号８ａがハイに変化する。
また、再起動パルス２６５ａが入力されると、比較回路２７８はリセットされ、切換信号８ａがハイからロウに変化する。
そして、速度信号２７７ａが基準速度信号２７６ａに達したら、切換信号８ａがロウから再びハイに変化する。
【０１６６】
実施例１７．
本実施例は、切り換えを時間設定とカウンタ値と位置信号の正常検出の３つを同時に満足する条件で行うようにしたものである。
図５５に本発明による３相ブラシレスモータの駆動装置の実施例１７の全体構成図を示す。以下、本実施例の切換信号発生回路８Ｉを説明する。
本実施例ではカウンタ値７ａ、７ｂ、７ｃと位置信号３ａ、３ｂ、３ｃとモータ回転信号５ａと再起動パルス２６５ａが切換信号発生回路８Ｉに入力される。
【０１６７】
図５６に本実施例の切換信号発生回路８Ｉの構成図を示す。本実施例の切換信号発生回路８Ｉは、位置信号カウンタ値判別回路２８０とタイマ２７０によって構成されている。
図５７は、本実施例の切換信号発生回路８Ｉの動作を説明する図である。本図に基づく動作は既に上記実施例で述べたと同様なので、説明を省略する。
【０１６８】
実施例１８．
本実施例は、切り換えを速度検出と位置信号の正常検出の両方を満足することで行った例である。
図５８に本発明による３相ブラシレスモータの駆動装置の実施例１８の全体構成図を示す。以下、本実施例の切換信号発生回路８Ｊを説明する。
【０１６９】
図５９に本実施例の切換信号発生回路８Ｊの構成図を示す。本実施例の切換信号発生回路８Ｊは、基準速度発生回路２７６と速度信号生成回路２７７と、比較回路２７８と、位置信号組合せ判別回路２７２から構成されている。
次に図６０は、本実施例の切換信号発生回路８Ｊの動作を説明する図である。本図に基づく動作は、既に上記実施例で述べたと同様なので、説明を省略する。
【０１７０】
実施例１９．
本実施例は、切り換えを速度検出と駆動信号の正常検出の論理積で行った例である。
図６１に本発明による３相ブラシレスモータの駆動装置の実施例１９の全体構成図を示す。以下、本実施例の切換信号発生回路８Ｋを説明する。
【０１７１】
図６２に本実施例の切換信号発生回路８Ｋの構成図を示す。本実施例の切換信号発生回路８Ｋは、基準速度発生回路２７６と、速度信号生成回路２７７と、比較回路２７８と、駆動信号組合せ判別回路２７５から構成されている。
図６３は、本実施例の切換信号発生回路８Ｋの動作を説明する図である。本図に基づく動作は、既に述べた上記実施例と同様なので、説明を省略する。
【０１７２】
実施例２０．
本実施例は、切り換えを速度検出と位置信号正常検出とカウンタ値の３つの論理積で行う例である。
図６４に本発明による３相ブラシレスモータの駆動装置の実施例２０の全体構成図を示す。以下、本実施例の切換信号発生回路８Ｌを説明する。
【０１７３】
図６５に本実施例の切換信号発生回路８Ｌの構成図を示す。本実施例の切換信号発生回路８Ｌは、基準速度発生回路２７６と、速度信号生成回路２７７と、比較回路２７８と、位置信号カウンタ値判別回路２８０から構成されている。
図６６は、本実施例の切換信号発生回路８Ｌの動作を説明する図である。本図に基づく動作は、既に述べた上記実施例と同様なので、説明を省略する。
【０１７４】
実施例２１．
本実施例は、再起動時の定常回転検知回路として、独立に設けることをやめ、再起動時にはパルス発生回路等からの擬似パルスで強制起動モードにする例を説明する。
図６７に本発明による３相ブラシレスモータの駆動装置の実施例２１の全体構成図を示す。
本実施例では、位置信号３ａ、３ｂ、３ｃとカウンタ値７ａ、７ｂ、７ｃとパルス発生回路６出力の疑似パルス６ａが転流回路９に入力される。転流回路９は、本疑似パルス６ａによってリセットされ、起動モードに移行するよう構成されている。
【０１７５】
以上のような構成において、定常回転中、何らかの負荷により回転子が停止すると、パルス発生回路６から疑似パルス６ａが出力され、擬似パルス６ａのは、転流回路９に入力される。転流回路９では、本疑似パルス６ａによってリセットされ、起動モードに移行する。従って、定常回転するまで、カウンタ値７ａ、７ｂ、７ｃの組合せによって駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する。
【０１７６】
実施例２２．
本実施例は、巻線電圧検出とは別の独立の１つの位置検出素子を用い、この信号と巻線電圧による位置検出とを組合せることで、確実に正しい方向の駆動信号を得るようにした。
図６８に本発明による３相ブラシレスモータの駆動装置の実施例２２の全体構成図を示す。３００は回転子の位置を検出し、パルス化された位置信号３００ａを出力する位置検出器、３０１は入力信号の立ち上がりエッジから出力を保持するホールド回路である。
図６８において、位置信号３００ａはホールド回路３０１に入力される。本実施例では、位置信号３００ａは、図６９に示すように位置信号３ｂと電気角π／６ずれている。また、ブラシレスモータの各通電安定点は図中破線の位置にあり、位置信号３００ａの立ち上がりエッジ及び立ち下がりエッジの位置と一致している。
【０１７７】
図６８中のホールド回路３０１は、モータ回転信号５ａがハイになった直後の位置信号３００ａの値をモータ回転信号５ａがロウになるまで保持する。例えば、モータ回転信号５ａがハイになった直後の位置信号３００ａがハイの場合は、モータ回転信号５ａがロウになるまで、ホールド回路出力３０１ａはハイに保持される。ホールド回路３０１の出力３０１ａは転流回路９と図７１に記載のカウンタ回路７内のパルス選択回路２５６に入力される。
転流回路９は、ホールド回路出力値３０１ａとカウンタ値７ａ、７ｂ、７ｃを参照して駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する構成になっている。図７０に本実施例におけるホールド回路出力３０１ａとカウンタ値７ａ、７ｂ、７ｃと駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆの論理関係例を示す。
【０１７８】
図７１に本実施例におけるカウンタ回路７の構成を示す。立ち上がりエッジ検出回路２５０、２５２、２５４、立ち下がりエッジ検出回路２５１、２５３、２５５及び６進カウンタ２５７は上記実施例と同様である。
パルス選択回路２５６には位置信号３ａ、３ｂ、３ｃの立ち上がりエッジパルス２５０ａ、２５２ａ、２５４ａと立ち下がりエッジパルス２５１ａ、２５３ａ、２５５ａと疑似パルス６ａとホールド回路出力３０１ａが入力される。パルス選択回路２５６は、現在のカウンタ値７ａ、７ｂ、７ｃとホールド回路出力３０１ａを参照して、正転時に次に検出されるべき理論的な位置信号のエッジパルスもしくは疑似パルス６ａを出力する構成である。本実施例におけるカウンタ値７ａ、７ｂ、７ｃとホールド回路出力３０１ａと正転時に次に検出されるべき理論的なエッジパルス２５０ａ、２５２ａ、２５４ａ、２５１ａ、２５３ａ、２５５ａの関係例を図７２に示す。図７２より、例えば、カウンタ値７ａ、７ｂ、７ｃがロウ・ロウ・ロウでホールド回路出力３０１ａがハイの時は、エッジパルス２５３ａもしくは疑似パルス６ａを出力し、他の例えばエッジパルス２５０ａが入力されても出力しない。
【０１７９】
次に本実施例におけるブラシレスモータの動作について説明する。まず、モータ回転信号５ａがハイになった直後、ホールド回路出力３０１ａがハイの場合について図７３を用いて説明する。ホールド回路出力３０１ａがハイなので、図７０より転流回路９は駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆをハイ・ロウ・ハイ・ロウ・ロウ・ハイに設定する。そして、ブラシレスモータの回転子が正転し、順次通電を切換えて起動する。
【０１８０】
また、モータ回転信号５ａがハイになった直後、ホールド回路出力３０１ａがロウの場合について図７４を用いて説明する。ホールド回路出力３０１ａがロウなので、図７０より転流回路９は駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆをハイ・ハイ・ロウ・ロウ・ハイ・ロウに設定する。そして、ブラシレスモータの回転子が正転し、順次通電を切換えて起動する。
【０１８１】
実施例２３．
本実施例は、起動時または再起動時の駆動を更に確実にした例である。
図７５に本発明による３相ブラシレスモータの駆動装置の第２３の実施例の全体構成図を示す。３０２は入力信号の立ち上がりエッジもしくは立ち下がりエッジを検出するエッジ検出回路である。
【０１８２】
転流回路９は、モータ回転信号５ａがハイになった直後の通電をホールド回路出力３０１ａに基づいて行なう。ホールド回路出力３０１ａがハイの時はＶ−Ｗ相を、ロウの時はＷ−Ｖ相を通電する。そして、第一回目の転流はエッジ検出回路３０２の出力パルス３０２ａとホールド回路出力３０１ａに基づいて転流を行なう。ホールド回路出力３０１ａがハイの時はＵ−Ｗ相を、ロウの時はＷ−Ｕ相を通電する。そして、それ以降の転流は位置信号３ａ、３ｂ、３ｃを参照して駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆを出力する構成になっている。位置信号３ａ、３ｂ、３ｃと駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆの論理関係例は図２２と同様である。
【０１８３】
次に本実施例におけるブラシレスモータの動作について説明する。まず、モータ回転信号５ａがハイになった直後、ホールド回路出力３０１ａがハイの場合について図７６を用いて説明する。ホールド回路出力３０１ａがハイなので、Ｖ−Ｗ相を通電するように図２１から駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆをハイ・ロウ・ハイ・ロウ・ロウ・ハイに設定する。そして、回転子が正転し、エッジ検出回路３０２の出力パルス３０２ａが検出されたときに第一回目の転流を行なう。ホールド回路出力３０１ａがハイであるから、Ｕ−Ｗ相を通電するように図２１から駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆをロウ・ハイ・ハイ・ロウ・ロウ・ハイに設定する。そして、それ以降の転流は位置信号３ａ、３ｂ、３ｃを参照して順次通電を切換えて回転子は正転する。
【０１８４】
また、モータ回転信号５ａがハイになった直後、ホールド回路出力３０１ａがロウの場合について図７７を用いて説明する。ホールド回路出力３０１ａがロウなので、Ｗ−Ｖ相を通電するように図２１から駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆをハイ・ハイ・ロウ・ロウ・ハイ・ロウに設定する。そして、回転子が正転し、エッジ検出回路３０２の出力パルス３０２ａが検出されたときに第一回目の転流を行なう。ホールド回路出力３０１ａがロウであるから、Ｗ−Ｕ相を通電するように図２１から駆動信号９ａ、９ｂ、９ｃ、９ｄ、９ｅ、９ｆをハイ・ハイ・ロウ・ハイ・ロウ・ロウに設定する。そして、それ以降の転流は位置信号３ａ、３ｂ、３ｃを参照して順次通電を切換えて回転子は正転する。
【０１８５】
尚、本明細書においては、請求項１〜１９について別々の実施例を示したが、これらを組み合わせて構成しても十分な効果が得られることは明白である。
【０１８６】
実施例２４．
図７８は、本実施例のブラシレスモータ用駆動回路の全体構成を示すブロック図である。
図７８において、図１と同一の構成部材については、同一番号で示した。
図７８において、４０６は起動回路であり、４０９は、実測した速度信号３ｄの周期をカウンタで計測し、指令値と計測値の差である周期誤差を速度誤差信号４０９ａとして出力する速度誤差検出回路である。４１０は、速度誤差信号４０９ａが０になるような電流指令値４１０ａを電流供給回路４１１に出力する速度誤差補償フィルタである。電流供給回路４１１は、図１に示した抵抗１０、ブリッジ回路１１、バッファアンプ２１２、抵抗２１３、駆動トランジスタ２１４から構成されており、駆動信号９ａ〜９ｆに基づいて電機子巻線１２、１３、１４に所定の駆動電流を供給する。
【０１８７】
本発明での重要な手段である回転子位置信号検出回路４を構成している端子電位補正回路１、比較回路２、波形整形回路３の構成および動作については、既に実施例１で述べられている。
図７９は、定常回転状態における端子電位補正回路１の各部の信号波形を示した図である。
この端子電位補正回路１の具体的動作も実施例１で述べており、式（１）〜（３）を用いて補正動作を説明している。
【０１８８】
通電状態から無通電状態に切り換わる時に発生するスパイク状の電圧変動は、回転子位置の誤検出や騒音の原因となるので、波形整形回路３が必要となる。この例は、実施例７で図１７に示している。
図８０に波形整形回路３の他の構成例を示す。
図において、１８０はラッチ回路、１８１〜１８６はＤフリップフロップ、１８７〜１８９はＥＯＲ回路、１９０はＯＲ回路である。また、４２１はマスク信号発生回路、４２２はタイマである。図８１は、定常回転状態における端子電位波形および波形整形回路の各部の信号波形を示したものであり、図８２は図８１の時刻Ｔ０〜Ｔ１の間を拡大した図である。
【０１８９】
本実施例の波形整形回路の具体的動作を上記各図を用いて説明する。
波形整形回路への入力信号は、比較回路２から出力される論理信号２ａ、２ｂ、２ｃである。論理信号２ａ、２ｂ、２ｃは補正された端子電位同士を比較して得られるものであるので、図８１に示すようにチャタリングを生じている。
論理信号２ａ、２ｂ、２ｃは、まず、ラッチ回路１８０に入力される。ラッチ回路１８０は、イネーブル端子１８０ａの状態に応じてラッチ動作を行う回路である。初期状態において、マスク信号発生回路４２１から出力されるマスク信号４２１ａはハイ・レベルであり、論理信号２ａ、２ｂ、２ｃはそのまま各々Ｄフリップフロップ１８１、１８３、１８５に入力される。Ｄフリップフロップ１８１〜１８６とＥＯＲ回路１８７〜１８９は両エッジ微分回路を構成しており、論理信号２ａ、２ｂ、２ｃの立ち上がり及び立ち下がりエッジのタイミングでＥＯＲ回路１８７〜１８９は微分パルス１９８、１９９、２００を出力する。
【０１９０】
時刻Ｔ２において、補正された端子電位１ａと１ｃの電位レベルが一致し２ａの極性が変化すると、両エッジ微分回路でエッジが検出され、微分パルス１９８ｂが発生される。ＥＯＲ回路１８７〜１８９の出力信号はＯＲ回路１９０で合成されて論理パルス信号３ｄになり、マスク信号発生回路４２１およびタイマ４２２に入力される。マスク信号発生回路４２１は論理パルス信号３ｄの立ち上がりエッジをトリガにして、マスク信号４２１ａをロウ・レベルにする。タイマ４２２は論理パルス信号３ｄの立ち上がりエッジで初期化され、タイマ値４２２ａは０となる。その後、タイマ４２２は、入力されるクロックに同期してカウントアップ動作を行う。イネーブル端子１８０ａがロウ・レベルとなったので、ラッチ回路１８０は論理信号２ａ、２ｂ、２ｃをラッチする。その後、マスク信号発生回路４２１はタイマ４２２のタイマ値４２２ａを監視し、タイマ値４２２ａが所定の値になったらマスク信号４２１ａをハイ・レベルにする。ラッチ回路１８０はイネーブル端子１８０ａがハイ・レベルとなったので、ラッチを解除する。
【０１９１】
Ｄフリップフロップ１８２、１８４、１８６の出力信号は波形整形された回転子位置信号３ａ、３ｂ、３ｃとなり、次段の転流回路９に入力され、転流動作が行われる。転流動作が行われると、駆動トランジスタがスイッチングするのでＵ相端子電位波形にスパイク状の電圧変動が発生し、その結果、所望でない位置においてスパイク状のノイズ２ｄが２ｂに発生する。しかし、スパイク状ノイズ２ｄが発生した時点においては、ラッチ回路へのデータ入力はマスク信号発生回路４２１から出力されるマスク信号４２１ａによりディセーブルされている。したがって、スパイク状ノイズ２ｄはラッチ回路１８０でマスクされ、波形整形された回転子位置信号３ａ、３ｂ、３ｃにはスパイク状ノイズは発生しない。このようにして、安定な回転子位置信号３ａ、３ｂ、３ｃが得られ、この回転子位置信号に基づいて電機子巻線が印加駆動され回転子が回転する。
【０１９２】
尚、本実施例では、３相ブラシレスモータに適用した例について記述したが、３相に限らず複数相のブラシレスモータ全般に適用可能であることは明白である。
【０１９３】
実施例２５．
本実施例では、実施例１で述べたマスク信号４２１ａがロウ・レベルを維持している時間Ｔ３を、モータに対する指令回転数が変わった場合に、指令回転数に比例して変化させるような構成にした。
本実施例のブラシレスモータ用駆動回路の全体構成は、実施例２４と同様である。但し、以下に述べるようにタイマへの指令回転数（ＣＬＫ）を変化させる構成とした。
【０１９４】
本実施例のマスク信号発生回路４２１およびタイマ４２２の動作を図８３、図８４、図８５を参照して説明する。実施例２４で説明したように、論理信号２ａ、２ｂ、２ｃの立ち上がりエッジあるいは立ち下がりエッジが検出され論理パルス信号３ｄが発生すると、マスク信号発生回路４２１は論理パルス信号３ｄの立ち上がりエッジをトリガにして、マスク信号４２１ａをロウ・レベルにする。タイマ４２２は論理パルス信号３ｄの立ち上がりエッジで初期化され、タイマ値４２２ａは０となる。その後、タイマ４２２は入力されるクロックの立ち上がりエッジに同期してカウント・アップ動作を行う。その後、マスク信号発生回路４２１はタイマ４２２のタイマ値４２２ａを監視し、タイマ値４２２ａがＮ（図８３ではＮ＝１０に設定）になったらマスク信号４２１ａをハイ・レベルにする。クロックの周期をＴ４とすると、マスク信号４２１ａはＴ４×１０の間ロウ・レベルを維持する。
【０１９５】
次に、図８３の状態から、指令回転数が２倍になった場合について説明する。図８４に示すようにＣＬＫ（ブラシレスモータ用駆動回路の外部から入力される）の周期をＴ４／２に設定する。これにより、マスク信号４２１ａがロウ・レベルを維持している時間はＴ４×５となる。あるいは、図８５に示すように、タイマに入力するクロックの周期はＴ４のままで、Ｎの値を５に変更する。これにより、マスク信号４２１ａがロウ・レベルを維持している時間は、クロック周期を変えた場合と同様にＴ４×５となる。このようにして、マスク信号がロウ・レベルを維持している時間を、指令回転数に基づいて変化させる。
【０１９６】
実施例２６．
本実施例では、スタート時に負荷に影響されず、短時間で起動し、さらに、動作中に何らかの原因で回転異常となって再起動が必要な場合でも、短時間で安定に再起動するブラシレスモータ用駆動回路の構成と動作について説明する。本趣旨は実施例８でも説明したが、本実施例では起動または再起動時の動作を主として説明する。
本実施例のブラシレスモータ用駆動回路の全体構成は、図７８と同様である。ここでは、本発明を実現する上で重要な手段となる起動回路の構成と動作について、以下に説明する。本実施例での新規構成要素は、擬似パルス発生回路４３１と再起動パルス発生回路４３２である。その他の構成要素は、実施例８の図２３等に示されたものと同等である。
【０１９７】
図７８に記載のモータ回転信号５ａは、ブラシレスモータ用駆動回路の外部から入力される信号で、イネーブルの時は回転を、ディセーブルの時は停止を表す。本実施例では、イネーブルをハイ・レベル、ディセーブルをロウ・レベルとする。
【０１９８】
図８６に起動回路４０６の具体的な一構成例を示す。回転子位置信号３ａ、３ｂ、３ｃは、各々、立ち上がりエッジ検出回路２５０、２５２、２５４と立ち下がりエッジ検出回路２５１、２５３、２５５と定常回転検知回路２６５に入力され、立ち上がりエッジ検出回路２５０、２５２、２５４と立ち下がりエッジ検出回路２５１、２５３、２５５がそれぞれ立ち上がり、立ち下がりエッジパルス２５０ａ〜２５５ａを出力する。これら検出されたエッジパルスは、パルス選択回路２５６に入力され、パルス選択回路２５６から出力される選択パルス２５６ａは、擬似パルス発生回路４３１に入力される。
擬似パルス発生回路４３１から出力されるパルス列４３１ａは６進カウンタ２５７に入力される。６進カウンタ２５７の入力されたパルス数と出力値の論理関係例は、図２４に示すものと同様である。図中、入力パルス数が６以上の場合、カウンタ値７ａ、７ｂ、７ｃは、再びロウ・ロウ・ロウからカウントする。６進カウンタ２５７から出力されるカウンタ値は、パルス選択回路２５６と定常回転検知回路２６５と図７８に示した転流回路９に入力される。定常回転検知回路２６５から出力される回転異常信号２６５ｂは、再起動パルス発生回路４３２に入力される。また、再起動パルス発生回路にはモータ回転信号５ａが入力される。再起動パルス発生回路４３２から出力される再起動パルス７ｅは、図７８に示した転流回路９に入力される。
【０１９９】
パルス選択回路２５６は、図７の論理で回転子が正転している場合に、入力されたエッジパルス２５０ａ〜２５５ａをそのままパルス列として出力する。即ち、入力されたエッジパルスの種類とカウンタ値７ａ、７ｂ、７ｃの関係が図２５の関係を満たす時は入力されたエッジパルスをそのまま出力し、それ以外の時は入力されたエッジパルスをマスクする。したがって、逆転時にはカウンタ値７ａ、７ｂ、７ｃとエッジパルスの関係が正転時とは異なるので、入力されたエッジパルスはマスクされる。
擬似パルス発生回路４３１は、所定時間内にパルス選択回路２５６から選択パルス列２５６ａが順次入力された場合にはパルス列をそのまま出力し、パルス列が所定時間入力されない場合に擬似パルスを発生する回路である。図８７に擬似パルス発生回路４３１の具体的な一構成例を、図８８に擬似パルス発生回路４３１の動作を示すタイミングチャートの一例を示す。
【０２００】
図８７において、４３３はカウンタ、４３４はゲート回路、４３５は立ち上がりエッジ検出回路、４３６はディレイ回路、４３７はＯＲ回路である。カウンタ４３３は、パルス列４３１ａで初期化され、入力クロックに同期してカウントアップする。ゲート回路４３４は、カウンタ値４３３ａをデコードし、デコードした値が設定値より小さい場合にロウ・レベルの信号を、設定値より大きい場合にハイ・レベルの信号を出力する。したがって、パルス選択回路２５６から選択パルス２５６ａが所定時間入力されないと、ゲート回路の出力信号４３４ａがハイ・レベルとなり、立ち上がりエッジ検出回路４３５で立ち上がりエッジが検出され、検出されたエッジパルスがディレイ回路４３６で遅延され、それが図８８の擬似パルス４３６ｂとして出力される。
【０２０１】
定常回転検知回路２６５は、実施例９で説明した回転子が正常に正転しているかを監視する回路である。
再起動パルス発生回路４３２は、起動後あるいは再起動後所定時間経過するまでは回転異常信号２５６ｂをマスクし、所定時間経過後は回転異常信号の立ち上がりエッジを検出し、それを再起動パルスとして出力する回路である。
図８９に再起動パルス発生回路４３２の一構成例を示す。
図において、４４０、４４４は立ち上がりエッジ検出回路、４４１、４４６はＯＲ回路、４４２はカウンタ、４４３はゲート回路、４４５はＡＮＤ回路である。カウンタ４４２は、モータ回転信号５ａの立ち上がりエッジ、あるいは再起動パルス７ｅで初期化され、ＯＲ回路４４６の出力に同期してカウントアップする。ゲート回路４４３は、カウンタ値４４２ａをデコードし、デコードした値が設定値より小さい場合にロウ・レベルの信号を設定値より大きい場合にハイ・レベルの信号を出力する。したがって、起動後あるいは再起動後所定時間経過するまでは回転異常信号２６５ｂはマスクされ、所定時間経過後は、回転異常信号の立ち上がりエッジが再起動パルスとして出力される。
【０２０２】
本実施例におけるブラシレスモータの起動動作について説明する。以下、ロウ・レベルをＬ、ハイ・レベルをＨと記述することがある。モータ回転信号５ａがハイ・レベルになった直後は、カウンタ値７ａ、７ｂ、７ｃはＬＬＬになるので、図２７より駆動信号９ｂがＬに、９ｆがＨになり、図７よりＶ−Ｗ相が通電される。この時、ブラシレスモータの回転子が正転して回転子位置信号が変化する場合、逆転して回転子位置信号が変化する場合、もしくは通電安定点に停止して位置信号が変化しない場合がある。
【０２０３】
まず、回転子が正転した場合について説明する。この場合、実施例８の図２８に示す各部信号波形例となる。実施例８の対応部分で説明のとおり、エッジパルス２５３ａが検出されるか、あるいは、擬似パルス発生回路で擬似パルス４３６ｂが発生した時のみ、６進カウンタ２５７はカウントする。回転子が正転方向に回転すると、電機子巻線に発生する逆起電圧により端子電位Ｕ、Ｖ、Ｗが変化し、回転子位置信号３ａ、３ｂ、３ｃはＨＬＬになり、図中（Ａ）のようにエッジパルス２５３ａが検出される。したがって、６進カウンタ２５７はカウントアップし、カウンタ値７ａ、７ｂ、７ｃはＨＬＬになり、転流回路９は図７、図２７よりＵ−Ｗ相を通電するように駆動信号９ａ〜９ｆをＬＨＨＬＬＨに設定する。そして、擬似パルス発生回路４３１は、その出力４３１ａとして図２８の７ｄに示す波形を出し続け、その後は定常回転するまでカウンタ値７ａ、７ｂ、７ｃの組合せに従って図２７に示す関係で順次通電相を切換えてブラシレスモータを起動する。
【０２０４】
次に、回転子が逆転した場合について説明する。この場合も実施例８の図２９に示す各部信号波形例となる。実施例８で説明の通り、回転子が逆転すると回転子位置信号３ａが変化して、図中（Ｂ）に示すエッジパルス２５１ａが検出される。しかし、カウンタ値の関係からパルス選択回路２５６でマスクされる。そして、擬似パルス発生回路４３１内のゲート回路４３４で設定される所定時間ｔ１以内にエッジパルス２５３ａが検出できないと、図中（Ｃ）に示すように擬似パルス発生回路４３１から擬似パルス６ａの相当の４３１ａが出力される。６進カウンタ２５７はこの擬似パルス４３１ａによってカウントアップし、カウンタ値７ａ、７ｂ、７ｃがＨＬＬと変化する。そして、転流回路９はカウンタ値７ａ、７ｂ、７ｃに応じて、Ｕ−Ｗ相を通電するように駆動信号９ａ〜９ｆをＬＨＨＬＬＨに設定する。これによって、回転子は正転し、その後は正転時と同様に定常回転するまでカウンタ値７ａ、７ｂ、７ｃの組合せに従って図２７に示す関係で順次通電相を切換えてブラシレスモータを起動する。
【０２０５】
次に、回転子が動かず回転子位置信号が変化しない場合について説明する。逆転する場合と同様に、所定時間ｔ１以内にエッジパルス２５３ａを検出できないため、擬似パルス発生回路４３１から擬似パルス（６ａ相当）が出力される。そして、逆転時と同様に６進カウンタ２５７はその擬似パルスをカウントし、転流回路は通電相をＵ−Ｗ相に切換え、その後定常回転するまでカウンタ値７ａ、７ｂ、７ｃの組合せに従って図２７に示す関係で順次通電相を切換えてブラシレスモータを起動する。
【０２０６】
このような構成において、定常回転中、何らかの負荷により回転子が停止した時の例を図９０を用いて説明する。図９０において（Ｄ）以降で回転子が停止したとする。この場合、パルス４３１ｃを検出してから擬似パルス発生回路４３１内のゲート回路４３４で設定された時間ｔ１経過後、擬似パルス４３６ｂが擬似パルス発生回路４３１内のディレイ回路４３６で出力される。そして、擬似パルス４３６ｂは擬似パルス発生回路４３１から出力されるパルス列４３１ａのパルスとして出力され、カウンタ値７ａ、７ｂ、７ｃはＬＨＬからＬＬＨに変化する。定常回転中は前述したように回転子位置信号３ａ、３ｂ、３ｃの組合せによって駆動信号９ａ〜９ｆを出力しているので、カウンタ値７ａ、７ｂ、７ｃが変化しても通電相は切り換えされない。したがって、カウンタ値７ａ、７ｂ、７ｃと回転子位置信号３ａ、３ｂ、３ｃの関係が図３１の関係を満たさなくなり、定常回転検知回路２６５から回転異常信号２６５ｂがハイ・レベルになる。
【０２０７】
この時、起動および再起動後所定時間経過していれば、回転異常信号の立ち上がりエッジが再起動パルス発生回路４３２で検出され、再起動パルス７ｅとして出力される。再起動パルスは転流回路９に入力され、転流回路は起動モードに移行する。
起動モード時の転流回路は、カウンタ値７ａ、７ｂ、７ｃの組合せに応じて駆動信号９ａ〜９ｆを出力する構成なので、図７、図２７より駆動信号９ａ〜９ｆはＨＨＬＬＨＬになりＷ−Ｖ相が通電される。Ｗ−Ｖ相が通電されることにより回転子が正転し、回転子位置信号３ａ、３ｂ、３ｃがＬＬＨに変化すると、カウンタ値７ａ、７ｂ、７ｃと回転子位置信号３ａ、３ｂ、３ｃの関係は図３１の関係を満たすので、回転異常信号２６５ｂはロウ・レベルとなる。その後は、図２８、図２９で説明したように、定常回転するまで、カウンタ値７ａ、７ｂ、７ｃの組合せに従って図２７に示す関係で順次通電相を切換えてブラシレスモータを起動する。
【０２０８】
実施例２７．
本実施例では、起動モードから定常回転モードに切り換える切り換え手段を設けたブラシレスモータ用駆動回路の構成と動作について説明する。
図９１に切り換え手段を設けた起動回路４０６Ｂの具体的な一構成例を示す。立ち上がりエッジ検出回路、立ち下がりエッジ検出回路、パルス選択回路、擬似パルス発生回路、６進カウンタ、定常回転検知回路、再起動パルス発生回路は、実施例２６と同一の回路である。新規な構成要素である４５０は、転流回路９で駆動信号９ａ〜９ｆを出力する際に、カウンタ値７ａ、７ｂ、７ｃと回転子位置信号３ａ、３ｂ、３ｃのどちらを参照するかを切り換えるための切り換え信号４５０ａを出力する切り換え信号発生回路である。
尚、本実施例の転流回路９は、切り換え信号４５０ａがロウ・レベルの場合にカウンタ値７ａ、７ｂ、７ｃを参照し、切り換え信号４５０ａがハイ・レベルの場合に回転子位置信号３ａ、３ｂ、３ｃを参照する。以下、切り換え信号発生回路４５０を説明する。
【０２０９】
本実施例において、モータ回転信号５ａと再起動パルス４３２ａが切り換え信号発生回路４５０に入力される。切り換え信号４５０ａは、転流回路９に入力される。
図９２に切り換え信号発生回路４５０の具体的な一構成例を示す。
図において、４５１は立ち上がりエッジ検出回路、４５２、４５５はＯＲ回路、４５３はカウンタ、４５４はゲート回路である。
図９３は切り換え信号発生回路４５０の動作を示す各部信号波形例である。カウンタ４５３は、モータ回転信号５ａの立ち上がりエッジ、あるいは再起動パルス４３２ａで初期化され、ＯＲ回路４５５の出力４５５ａに同期してカウントアップする。ゲート回路４５４は、カウンタ値４５３ａをデコードし、デコードした値が設定値より小さい場合にロウ・レベルの信号を出力し、設定値より大きい場合にハイ・レベルの信号を出力する。したがって、切り換え信号４５０ａは起動後あるいは再起動後所定時間経過するまではロウ・レベル、それ以降はハイ・レベルとなる。切り換え信号４５０ａは転流回路９に入力され、転流回路９は切り換え信号４５０ａに従って参照する手段を切り換える。
【０２１０】
実施例２８．
本実施例では、従来の速度誤差補償フィルタに比べ、低域利得特性が改善された速度誤差補償フィルタを有するブラシレスモータ用駆動回路の構成について説明する。本実施例のブラシレスモータ用駆動回路の全体構成は、図１または図７８と同様であるので、説明は省略する。本発明を実現する上で重要な手段となる速度誤差補償フィルタの構成について、以下に説明する。
【０２１１】
図９４は、アナログ・フィルタで速度誤差補償フィルタを構成した場合の伝達ブロック図である。
図において、４６０は比例・積分（ＰＩ）フィルタ、４６１は１次遅れフィルタ、４６２はゲイン要素または係数倍器、４６３は加算器、４６４は１次遅れフィルタである。
速度誤差補償フィルタの入力端子Ｘには、速度誤差検出回路４０９から出力される速度誤差信号４０９ａが入力される。出力端子Ｙから出力されるフィルタ出力は、電機子巻線への電流指令値４１０ａとして電流供給回路４１１に与えられる。従来技術で示した図１２３のフィルタ構成と異なる点は、入力である速度誤差信号４０９ａを、新たな１次遅れフィルタ４６１を経由してＰＩフィルタ４６０の出力に加算するように構成した点である。この時、速度誤差補償フィルタの伝達関数Ｇ_C （ｓ）は式（６）の様になる。

【０２１２】
図９５は、Ｋ_P ＝１、Ｔ_I ＝１／（２π×１０）、Ｋ_w ＝１、Ｔ_A ＝１／（２π×５）、Ｔ_L ＝１／（２π×６０）とした時の、速度誤差補償フィルタのオープンループ特性のシミュレーション結果である。また、従来のフィルタ構成で、Ｋ_P ＝１、Ｔ_I ＝１／（２π×１０）、Ｔ_L ＝１／（２π×６０）とした時のシミュレーション結果を図９５中に破線で示す。本発明で提案したフィルタ構成により、低域の利得特性が改善されている。
【０２１３】
図９４には、アナログ・フィルタで構成した場合の例を示したが、ディジタル・フィルタで構成することも、勿論、可能である。
図９６は、ディジタル・フィルタで速度誤差補償フィルタを構成した場合の伝達ブロック図である。
図において、４７０〜４７２は信号を１サンプリング時間遅延する遅延要素、４７３〜４７９はゲイン要素、４８０〜４８３は加算器である。遅延要素４７１、ゲイン要素４７６、４７７、加算器４８１、４８２でＰＩフィルタ４８４を構成し、遅延要素４７０、ゲイン要素４７３〜４７５、加算器４８０で１次遅れフィルタ４８５を構成し、遅延要素４７２、ゲイン要素４７８、４７９、加算器４８３で１次遅れフィルタ４８６を構成している。この時、速度誤差補償フィルタの伝達関数Ｇ_C （ｚ）は式（７）の様になる。

【０２１４】
実施例２９．
本実施例では、従来の速度誤差補償フィルタに比べ、低域利得特性が改善された速度誤差補償フィルタの別の実施例について説明する。
【０２１５】
図９７は、アナログ・フィルタで速度誤差補償フィルタを構成した場合の伝達ブロック図である。
図において、実施例２８と同一な部材は同一番号で示した。従来技術で示した速度誤差補償フィルタ構成と異なる点は、速度誤差信号４０９ａを入力とする新たな１次遅れフィルタ４６１の出力を、ＰＩフィルタと一次遅れフィルタの直列回路出力に、加算するように構成した点である。この時、速度誤差補償フィルタの伝達関数Ｇ_C （ｓ）は式（８）の様になる。

【０２１６】
図９８は、Ｋ_P ＝１、Ｔ_I ＝１／（２π×１０）、Ｋ_w ＝１、Ｔ_A ＝１／（２π×５）、Ｔ_L ＝１／（２π×６０）とした時の、速度誤差補償フィルタのオープンループ特性のシミュレーション結果である。また、従来のフィルタ構成で、Ｋ_P ＝１、Ｔ_I ＝１／（２π×１０）、Ｔ_L ＝１／（２π×６０）とした時のシミュレーション結果を図９８中に破線で示す。本発明で提案したフィルタ構成により、低域の利得特性が改善されている。
【０２１７】
図９７には、アナログ・フィルタで構成した場合の例を示したが、ディジタル・フィルタで構成することも、勿論、可能である。
図９９は、ディジタル・フィルタで速度誤差補償フィルタを構成した場合の伝達ブロック図である。
図９９において、実施例２８と同一な部材は同一番号で示した。４８７、４８８は加算器である。この時、速度誤差補償フィルタの伝達関数Ｇ_C （ｚ）は式（９）の様になる。

【０２１８】
実施例３０．
本実施例では、指令回転数が変わった場合に、速度誤差検出回路の目標回転速度と、速度誤差補償フィルタのゲイン要素の利得を切り換えるように構成されたブラシレスモータ用駆動回路について説明する。
図１００は、本発明のブラシレスモータ用駆動回路の実施例３０の全体構成を示すブロック図である。
図１００において、図７８と同一の構成部材については同一番号で示した。４９０は、モード切り換え信号４９０ａが入力される入力端子である。モード切り換え信号４９０ａは、ブラシレスモータ用駆動回路の外部から入力される信号で、モータの回転数を切り換えるための２値化信号である。
【０２１９】
先の実施例で説明した波形整形回路３において、ＯＲ回路から出力される論理パルス信号３ｄは、定常回転時において一定時間間隔で得られる信号である。したがって、この論理パルス信号３ｄを回転速度を制御するための速度信号として用いることが可能である。
図１０１に速度誤差検出回路４０９の具体的な一構成例を示す。
図において、４９１、４９２は初期値レジスタ、４９３はセレクタ、４９４はカウンタである。初期値レジスタ４９１、４９２は、目標回転速度が格納されているレジスタであり、本実施例では、２種類の指令回転数に対応するために２つの初期値レジスタを有している。セレクタ４９３は、モード切り換え信号４９０ａの論理レベルに応じて、２種類の初期値レジスタ４９１、４９２を切り換える。カウンタ４９４は、論理パルス信号３ｄの立ち上がりエッジのタイミングでセレクタ４９３で選択された初期値をロードし、クロックをカウントアップする。
【０２２０】
例えば、定常回転時において論理パルス信号３ｄの周期が１（ｍｓｅｃ）および０．５（ｍｓｅｃ）となる２種類の指令回転数（各々指令回転数Ａ、指令回転数Ｂと記述する）に対応する場合について説明する。
クロックの周波数は１（ＭＨｚ）とし、モード切り換え信号４９０ａがハイ・レベルの場合に指令回転数Ａに、モード切り換え信号４９０ａがロウ・レベルの場合に指令回転数Ｂに対応させる。初期値レジスタ４９１には−１０００を、初期値レジスタ４９２には−５００を設定する。このような構成において、モード切り換え信号４９０ａがハイ・レベルの場合、セレクタ４９３は初期値レジスタ４９１を選択し、カウンタ４９４は論理パルス信号３ｄの立ち上がりエッジのタイミングで初期値−１０００をロードする。その後、カウンタ４９４はクロックをカウントアップし、論理パルス信号３ｄの周期が１（ｍｓｅｃ）より短い場合に負値を、論理パルス信号３ｄの周期が１（ｍｓｅｃ）より長い場合に正値を速度誤差信号４０９ａとして出力する。
一方、モード切り換え信号４９０ａがロウ・レベルの場合には、セレクタ４９３は初期値レジスタ４９２を選択し、カウンタ４９４は論理パルス信号３ｄの立ち上がりエッジのタイミングで初期値−５００をロードする。その後、カウンタ４９４はクロックに同期してカウントアップし、論理パルス信号３ｄの周期が０．５（ｍｓｅｃ）より短い場合に負値を、論理パルス信号３ｄの周期が０．５（ｍｓｅｃ）より長い場合に正値を速度誤差信号４０９ａとして出力する。
【０２２１】
実施例３１．
上記実施例では、指令回転数を変える場合の速度誤差検出回路４０９の動作について説明してきた。しかし、目標回転速度を切り換えて対応したため、指令回転数の違いにより検出感度が変わってしまうという問題点がある。本実施例では、この問題に対処するために、速度誤差補償フィルタのゲイン要素も切り換えるように構成する。
【０２２２】
図１０２に速度誤差補償フィルタのゲイン要素を切り換える場合のＰＩフィルタ４８４Ａのブロック図を示す。
図１０２において、実施例２８で示した図９６と同一な構成要素は同一番号で示した。４９５、４９６は別な指令回転数に対応するために、新たに設けたゲイン要素である。４９７、４９８はセレクタであり、セレクタ４９７、４９８は、モード切り換え信号４９０ａの論理レベルに応じて、各々、ゲイン要素４７６、４９５およびゲイン要素４７７、４９６のどちらの出力を用いるかを選択する。同様に、一次遅れフィルタ４８５、４８６のゲイン要素もモード切り換え信号４９０ａで切り換えるように構成する。
勿論、利得を切り換える他の一般的な方法を用いてもよい。
【０２２３】
尚、本実施例では、指令回転数を１ビットの２値化信号で切り換える例について記述したが、さらに複数の指令回転数に対応する場合にはＮビットの２値化信号で切り換えるように構成することも可能である。
【０２２４】
実施例３２．
本実施例では、本発明のブラシレスモータ用駆動回路における、通電相を切り換えるタイミングと、電機子巻線に供給する電流量を増減するタイミングの関係について説明する。
本実施例のブラシレスモータ用駆動回路の全体構成は図７８と同様である。
図１０３は、本発明のブラシレスモータ用駆動回路の定常回転時の動作を示すタイミングチャートである。図１０３を参照しながら説明する。
図において、３ａ、３ｂ、３ｃは回転子位置信号、９ａ〜９ｆは駆動信号、３ｄは速度を表す論理パルス信号、４０９ａは速度誤差信号、４１０ａは電流指令値である。
定常回転時において、駆動信号９ａ〜９ｆは回転子位置信号３ａ、３ｂ、３ｃに基づいて生成される。したがって、定常回転時において、通電相の切り換えは図に示すタイミングで行われる。
【０２２５】
論理パルス信号３ｄは、回転子位置信号３ａ、３ｂ、３ｃの両エッジ微分パルスである。速度誤差検出回路４０９は、速度信号３ｄの周期を計測し、目標値と計測値との差である周期誤差を速度誤差信号４０９ａとして図１０３に示すタイミングで出力する。速度誤差信号４０９ａは、速度誤差補償フィルタ４１０に入力される。速度誤差補償フィルタ４１０は、速度誤差信号４０９ａが０になるようにフィルタ演算する。
フィルタ演算には、所定の演算時間を要するため、電流指令値４１０ａは、速度誤差信号４０９ａが変化してから演算時間分だけ経過してから変化する。電流供給回路４１１は、電流指令値４１０ａに基づいて電機子巻線に供給する電流量を調節する。
【０２２６】
以上、説明したように、本発明のブラシレスモータ用駆動回路では、通電相の切り換えタイミングと電機子巻線電流を増減するタイミングが同期してしており、電機子巻線電流の増減は転流後演算時間分だけ経過してから行われる。
【０２２７】
実施例３３．
本実施例では、起動および再起動の期間、電機子巻線に最大電流を供給するように構成されたブラシレスモータ用駆動回路について説明する。
図１０４は、本実施例のブラシレスモータ用駆動回路の全体構成を示すブロック図である。即ち、本構成は、実施例２７で説明した切り換え信号４５０ａが速度誤差補償フィルタ４１０に入力された構成となっている。
【０２２８】
図１０５に速度誤差補償フィルタの一構成例を示す。
図において、６００はマイクロコントローラ、６０１はＤ／Ａ変換器、６０２はマイクロコントローラ６００内のレジスタ０〜レジスタＮで構成されるレジスタ群である。
マイクロコントローラ６００は、速度誤差検出回路４０９から出力される速度誤差信号４０９ａを入力し、例えば実施例２８、実施例２９で示したようなフィルタ演算を行い、その演算結果をレジスタＮに格納する。さらに、マイクロコントローラ６００は、レジスタＮに格納されている値を所定のタイミングでＤ／Ａ変換器６０１に出力する。レジスタＮに格納されていたディジタル値はＤ／Ａ変換器６０１でアナログ値に変換され、電流指令値４１０ａとして電流供給回路４１１に入力される。
【０２２９】
起動モードと定常回転モードを切り換える切り換え信号４５０ａは、マイクロコントローラ６００に入力される。切り換え信号４５０ａは、実施例２７で説明したように、起動後あるいは再起動後所定時間経過するまではロウ・レベル、それ以降はハイ・レベルとなる信号であった。マイクロコントローラ６００は、切り換え信号４５０ａがロウ・レベルになるとレジスタＮを初期化し、レジスタＮの値を最大値に設定する。したがって、切り換え信号４５０ａがロウ・レベルの間、電流指令値４１０ａは最大設定値に設定され、起動および再起動の期間、電機子巻線には最大電流が供給される。
尚、本明細においては、請求項１〜２８について別々の実施例を示したが、これらを組み合わせて構成しても十分な効果が得られることは明白である。
【０２３０】
実施例３４．
図１０６は、本実施例のブラシレスモータ用駆動回路の全体構成を示すブロック図である。図１０６において、図７８と同一の構成部材は同一番号で示した。実施例２７で説明した転流回路９は、起動モード時はカウンタ値７ａ、７ｂ、７ｃを参照し、定常回転モード時は回転子位置信号３ａ、３ｂ、３ｃを参照して駆動信号９ａ〜９ｆを出力するように構成されていた。本実施例の転流回路６１０は、起動モード時および定常回転モード時共に、カウンタ値７ａ、７ｂ、７ｃを参照して駆動信号９ａ〜９ｆを出力する。カウンタ値７ａ、７ｂ、７ｃと駆動信号９ａ〜９ｆの論理関係は図２７と同様である。
【０２３１】
また、本実施例では、パルス選択回路の別な構成例について説明する。図１０７にパルス選択回路２５６と別な構成を有するパルス選択回路６０９の具体的な一構成例を示す。図において６１１〜６１３は反転回路、６１４〜６２５は３入力ＡＮＤ回路、６２６は６入力ＯＲ回路である。
【０２３２】
実施例８、２６で示したパルス選択回路２５６と本実施例で示すパルス選択回路６０９の動作を比較する。図１０８は、モータが定速逆回転した時の、回転子位置信号３ａ、３ｂ、３ｃ、立ち上がり・立ち下がりエッジパルス２５０ａ〜２５５ａ、カウンタ値７ａ、７ｂ、７ｃ、パルス選択回路２５６の出力信号２５６ａ、擬似パルス発生回路４３１の出力信号４３１ａのタイミングチャートを示したものである。
一方、図１０９は、モータが定速逆回転した時の、回転子位置信号３ａ、３ｂ、３ｃ、立ち上がり・立ち下がりエッジパルス２５０ａ〜２５５ａ、カウンタ値７ａ、７ｂ、７ｃ、パルス選択回路６０９の出力信号６０９ａ、擬似パルス発生回路４３１の出力信号４３１ａのタイミングチャートを示したものである。
【０２３３】
実施例８、２６で示したパルス選択回路２５６は、入力されたエッジパルス２５０ａ〜２５５ａの種類とカウンタ値７ａ、７ｂ、７ｃの関係が図２５の関係を満たすときは入力されたエッジパルスをそのまま出力し、それ以外の時は入力されたエッジパルスをマスクする回路であった。以下、図１０８、１０９を参照しながら説明する。カウンタ値の初期値をＬＬＬと仮定する。図１０８、図１０９中（Ｅ）、（Ｆ）、（Ｇ）においてエッジパルス２５５ａ、２５２ａ、２５１ａが順次検出される。カウンタ値がＬＬＬであるので、パルス選択回路２５６は２５３ａ以外のエッジパルスをマスクする。したがって、図中（Ｅ）、（Ｆ）、（Ｇ）で検出されたエッジパルス２５５ａ、２５２ａ、２５１ａはマスクされる。
【０２３４】
同様に、パルス選択回路６０９でもこれらのエッジパルスはマスクされる。擬似パルス発生回路４３１内で設定される所定時間ｔ１が経過しても擬似パルス発生回路４３１への入力がないので、擬似パルス発生回路４３１は図中（Ｈ）において擬似パルスを発生する。この擬似パルスにより６進カウンタ２５７はカウントアップし、カウンタ値はＨＬＬとなる。そして、図中（Ｉ）においてエッジパルス２５４ａが検出される。カウンタ値はＨＬＬであるので、図中（Ｉ）で検出されたエッジパルス２５４ａはパルス選択回路２５６でマスクされずそのまま出力される。このように、パルス選択回路２５６は逆回転時のエッジパルス２５０ａ〜２５５ａを完全にマスクすることができなかった。
一方、パルス選択回路６０９では、（Ｉ）において回転子位置信号３ａがＬであるので、図中（Ｉ）で検出されたエッジパルス２５４ａはマスクされる。このように、本実施例のパルス選択回路６０９は、カウンタ値と入力されたエッジパルスの種類の組み合わせに加え、更に、回転子位置信号３ａ、３ｂ、３ｃの論理を組み合わせてエッジパルスを選択するように構成されているので、図１０９に示すように、逆回転時のエッジパルス２５０ａ〜２５５ａを完全にマスクすることができる。
【０２３５】
実施例３５．
次に、回転子駆動信号を台形波にして騒音を減らす例を説明する。
図１１０は、本実施例のブラシレスモータ用駆動回路の全体構成を示すブロック図である。図において、図１０６と同一の構成部材については同一番号で示した。新規な要素として、６３０は台形波状の駆動信号を合成するために必要な複数の論理信号６３０ａ〜６３０ｇを出力する論理回路、６３１は論理回路からの出力信号６３０ｇに基づいてコンデンサに充放電を行う充放電回路、６３２は充放電回路の出力信号６３１ａと論理回路の出力信号６３０ａ〜６３０ｆから台形波状の駆動信号６３２ａ〜６３２ｆを合成する台形波合成回路である。
上記論理回路６３０、充放電回路６３１、台形波合成回路６３２を含んで台形駆動信号生成回路６３３が構成されている。
【０２３６】
図１１１に論理回路６３０の具体的な一構成例を示す。図において、６３５〜６４３はＡＮＤ回路、６４４は３入力ＯＲ回路である。論理回路６３０の出力信号６３０ａ〜６３０ｇの動作波形は、図１１３の様になる。
図１１２に充放電回路６３１の具体的な一構成例を示す。図において、６４５、６４６は定電流源、６４７はコンデンサである。ＳＷ１は論理回路６３０の出力信号６３０ｇがハイ・レベルの時にオンし、ロウ・レベルの時にオフする。
充放電回路６３１の動作について説明する。論理回路の出力信号６３０ｇがロウ・レベルの時、ＳＷ１がオフし、コンデンサ６４７は定電流Ｉ３で充電される。一方、論理回路６３０の出力信号６３０ｇがハイ・レベルの時、ＳＷ１がオンし、コンデンサ６４７は定電流Ｉ３で放電される。充放電回路６３１の出力信号６３１ａは図１１３に示したような台形波状の信号となる。
【０２３７】
充放電回路６３１の出力信号６３１ａ、論理回路６３０の出力信号６３０ａ〜６３０ｆは台形波合成回路６３２に入力される。
台形波合成回路６３２の具体的な一構成例を図１１４に示す。図において、６４８〜６５１は反転アンプ回路、６５２〜６５７はＮＡＮＤ回路である。充放電回路６３１の出力信号６３１ａと論理回路６３０の出力信号６３０ａ〜６３０ｆの動作電圧範囲は同じであるとし、Ｖｒｅｆは動作電圧範囲の中心電位であるとする。反転アンプ回路６４８の反転入力端子には充放電回路６３１の出力信号６３１ａが、非反転入力端子には基準電位Ｖｒｅｆが入力され、Ｖｒｅｆを基準に６３１ａを反転した台形波を得ている。同様に、反転アンプ回路６４９、６５０、６５１では、Ｖｒｅｆを基準に各々６３０ａ、６３０ｃ、６３０ｅを反転した信号を得ている。
【０２３８】
以下、台形波合成回路６３２の具体的動作について、図を参照しながら説明する。ここでは、台形駆動信号６３２ａを合成する部分に着目して説明する。
ＳＷ２、ＳＷ３、ＳＷ４は各々６３０ｄ、６３０ｆ、６５２ａがハイ・レベルの時にオンし、ロウ・レベルの時にオフする。６５２ａはＮＡＮＤ回路６５２の出力信号である。図１１３に示した期間Ｔａでは、６３０ｄはハイ・レベル、６３０ｆはロウ・レベル、６５２ａはロウ・レベルであるので、ＳＷ２のみがオンし、台形駆動信号６３２ａは充放電回路６３１の出力信号６３１ａとなる。期間Ｔｂでは、６３０ｄはロウ・レベル、６３０ｆはロウ・レベル、６５２ａはハイ・レベルであるので、ＳＷ４のみがオンし、台形駆動信号６３２ａはＶｒｅｆを基準に６３０ｅを反転した信号になる。期間Ｔｃでは、６３０ｄはロウ・レベル、６３０ｆはハイ・レベル、６５２ａはロウ・レベルであるので、ＳＷ３のみがオンし、台形駆動信号６３２ａはＶｒｅｆを基準に６３１ａを反転した台形波になる。期間Ｔｄでは、６３０ｄはロウ・レベル、６３０ｆはロウ・レベル、６５２ａはハイ・レベルであるので、ＳＷ４のみがオンし、台形駆動信号６３２ａはＶｒｅｆを基準に６３０ｅを反転した台形波になる。
以上のようにして、台形駆動信号６３２ａが合成される。台形駆動信号６３２ｂ〜６３２ｆも同様の手順で合成される。このようにして、台形駆動信号生成回路６３３は、駆動信号９ａ〜９ｆの立ち上がり・立ち下がりエッジ時点から立ち上がり傾斜部分および立ち下がり傾斜部分が始まる台形駆動信号６３２ａ〜６３２ｆを生成する。
【０２３９】
実施例３６．
本実施例では、外部から入力される指令回転数に対応して台形駆動信号６３２ａ〜６３２ｆの傾斜時間を変化させるように構成したブラシレスモータ用駆動回路について説明する。
図１１５は、本実施例のブラシレスモータ用駆動回路の全体構成を示すブロック図である。図において、図１１０と同一の構成部材については同一番号で示した。図１１５において、６６０はモード切り換え信号６６０ａが入力される端子、６６１は充放電回路６３１と別な構成を有する充放電回路である。モード切り換え信号６６０ａは、ブラシレスモータ駆動回路の外部から入力される信号で、指令回転数に対応して極性が変化する２値化信号である。
【０２４０】
図１１６に充放電回路６６１の具体的な一構成例を示す。図において、６６２は反転回路、６６３、６６４は定電流源である。ＳＷ５、ＳＷ７はモード切り換え信号６６０ａがハイ・レベルの時にオンし、ロウ・レベルの時にオフする。ＳＷ６、ＳＷ８はモード切り換え信号６６０ａがロウ・レベルの時にオンし、ハイ・レベルの時にオフする。
【０２４１】
モード切り換え信号６６０ａがハイ・レベルの場合の充放電回路６６１の動作について説明する。
論理回路の出力信号６３０ｇがロウ・レベルの時、ＳＷ１がオフし、コンデンサ６４７は定電流Ｉ３で充電される。一方、論理回路６３０の出力信号６３０ｇがハイ・レベルの時、ＳＷ１がオンし、コンデンサ６４７は定電流Ｉ３で放電される。論理回路６３０の出力信号６３０ｇと充放電回路６６１の出力信号６６１ａの関係は図１１７で６３２ａがＨで示したようになる。
【０２４２】
モード切り換え信号６６０ａがロウ・レベルの場合には、論理回路の出力信号６３０ｇがロウ・レベルの時にコンデンサ６４７は定電流Ｉ４で充電され、論理回路６３０の出力信号６３０ｇがハイ・レベルの時、コンデンサ６４７は定電流Ｉ４で放電される。
【０２４３】
Ｉ４＝０．５×Ｉ３となるように設定すると、充放電回路６６１の出力信号６６１ａは図１１７で６３２ａがＬで示すようになり、台形波の傾斜時間は、倍になる。充放電回路６６１の出力信号６６１ａは台形波合成回路６３２に入力され、実施例３５で説明した手順で台形駆動信号６３２ａ〜６３２ｆが生成される。
このように、指令回転数に対応してモード切り換え信号６６０ａを切り換えるようにすれば、外部から入力される指令回転数に対応して台形駆動信号６３２ａ〜６３２ｆの傾斜時間を変化させることが可能である。
【０２４４】
実施例３７．
台形駆動信号生成回路６３３で生成される台形駆動信号６３２ａ〜６３２ｆの立ち上がり傾斜部分および立ち下がり傾斜部分は、駆動信号９ａ〜９ｆの立ち上がり・立ち下がりエッジ時点から始まる。したがって、駆動電流の切り換わり点が理想的な転流タイミングから遅れることになりトルク発生効率が低下する。本実施例では、各相端子電位または各相間電圧差から検出する回転子位置信号の位相を台形駆動信号の傾斜時間に対応して進み位相になるように構成したブラシレスモータ用駆動回路の構成と動作について説明する。
【０２４５】
図１１８は、本実施例のブラシレスモータ用駆動回路の全体構成を示すブロック図である。図において、図１１０と同一の構成部材については同一番号で示した。図１１８において、新規な要素として６７０は比較回路２と別な構成を有する比較回路である。
また、図１１９に比較回路６７０の具体的な一構成例を示す。図において、６７１〜６８５は抵抗、６８６〜６８８は差動増幅回路である。
【０２４６】
以下、比較回路６７０の具体的な動作について説明する。
一例として、抵抗６７１〜６８５が図１１９に示す値に設定されている場合について考える。この時、差動増幅回路６８６の出力信号６８６ａは１ａ＋１ｂ−２×１ｃに、差動増幅回路６８７の出力信号６８７ａは１ｂ＋１ｃ−２×１ａに、差動増幅回路６８８の出力信号６８８ａは１ｃ＋１ａ−２×１ｂになる。
今、１ａ、１ｂ、１ｃが式（１０）に示すような２π／３ずつ位相がずれた３相信号であったとすると、差動増幅回路６８６、６８７、６８８の出力信号６８６ａ、６８７ａ、６８８ａは式（１１）、（１２）、（１３）のようになる。差動増幅回路６８６、６８７、６８８の出力信号６８６ａ、６８７ａ、６８８ａは各々コンパレータ８５、８６、８７でＶｒｅｆと比較され、論理信号６７０ａ、６７０ｂ、６７０ｃが得られる。

【０２４７】
ここで、比較回路２の具体的な動作について再度説明する。
抵抗７０〜８１が全て１０ＫΩに設定されている場合について考える。この時、差動増幅回路８２の出力信号は１ａ−１ｃ、差動増幅回路８３の出力信号は１ｂ−１ａ、差動増幅回路８４の出力信号は１ｃ−１ｂであり、各々式（１４）、（１５）、（１６）のようになる。差動増幅回路８２、８３、８４の出力信号を８２ａ、８３ａ、８４ａとする。差動増幅回路８２、８３、８４の出力信号８２ａ、８３ａ、８４ａは各々コンパレータ８５、８６、８７でＶｒｅｆと比較され、論理信号２ａ、２ｂ、２ｃが得られる。

【０２４８】
差動増幅回路６８６、６８７、６８８の出力信号６８６ａ、６８７ａ、６８８ａは、差動増幅回路８２、８３、８４の出力信号８２ａ、８３ａ、８４ａに対してπ／６位相が進んでいる。したがって、比較回路６７０では、比較回路２から出力される論理信号２ａ、２ｂ、２ｃよりπ／６位相が進んだ論理信号６７０ａ、６７０ｂ、６７０ｃを得ることができる。
本実施例では、抵抗６７１〜６８５の値を図１１９に示した値に設定して説明したが、抵抗６７１〜６８５を変化させれば別な位相進み量に設定することも可能である。このようにして回転子位置信号の位相を進め、駆動電流の切り換わり点が理想的な転流タイミングに一致するようにする。
尚、本実施例では充放電回路６３１を用いた構成例を示したが、充放電回路６６１を用いて構成することも勿論可能である。
【０２４９】
【発明の効果】
本発明は上記で説明のように構成されているので、以下に記載のような効果がる。
【０２５０】
中性点を用いず、また電機子巻線電流で決まる補正値を実駆動期間だけ補正して位置信号を得るようにしたので、引き出し線が少なくて、位相遅れのない正しい駆動タイミングを定められる効果がある。
【０２５１】
中性点を用いず、また電機子巻線電流で決まる補正値を実駆動期間だけ補正して各相間電圧差から位置信号を得るようにしたので、引き出し線が少なくて、位相遅れのない正しい駆動タイミングを定められる効果がある。
【０２５２】
更に、位置信号から速度相当信号を得るようにしたので、上記に加えて簡単な装置で速度制御ができる効果がある。
【０２５３】
更に、実駆動期間を駆動信号が駆動状態にある期間としたので、位相遅れの補正がより正しくできる効果がある。
【０２５４】
更に、各相間電圧差の補正の実駆動期間を駆動信号が駆動状態にある期間としたので、位相遅れの補正がより正しくできる効果がある。
【０２５５】
更に、補正電圧を電機子巻線に流れる電流の検出用抵抗からとったので、位相遅れの補正がより正しくできる効果がある。
【０２５６】
更に、補正電圧を電機子巻線に流れる電流の検出用抵抗からとったので、各相間電圧差の位相遅れの補正がより正しくできる効果がある。
【０２５７】
更に、位置信号をラッチして新しい位置信号としたので、更に検出信号にノイズがあっても正しい位置信号を検出できる効果がある。
【０２５８】
位置信号の立ち上がり・立ち下がりのエッジ信号を選択し、またカウントして組み合わせて駆動信号とし、更に無入力時には強制カウントするようにしたので、安定起動ができる効果がある。
【０２５９】
位置信号の立ち上がり・立ち下がりのエッジ信号を選択し、またカウントして組み合わせて駆動信号とし、無入力時には強制カウントするようにし、更に回転異常時には再起動するようにしたので、回転中の異常時にも再起動ができる効果がある。
【０２６０】
起動・再起動時と、定常時との切り換えを所定の時間で切り換えるようにしたので、確実に定常運転に移れる効果がある。
【０２６１】
起動・再起動時と、定常時との切り換えをカウンタのカウンタ値で切り換えるようにしたので、確実に定常運転に移れる効果がある。
【０２６２】
起動・再起動時と、定常時との切り換えを回転子がある速度になったことで切り換えるようにしたので、確実に定常運転に移れる効果がある。
【０２６３】
起動・再起動時と、定常時との切り換えを検出位置信号が所定の組み合わせになったことで切り換えるようにしたので、確実に定常運転に移れる効果がある。
【０２６４】
起動・再起動時と、定常時との切り換えを電機子巻線への駆動信号が所定の組み合わせになったことで切り換えるようにしたので、確実に定常運転に移れる効果がある。
【０２６５】
起動・再起動時と、定常時との切り換えを、所定の時間、カウントアップ値、所定速度への到達、検出位置信号か電機子巻線への駆動信号が所定の組み合わせになったことの複数の条件成立で切り換えるようにしたので、更に確実に定常運転に移れる効果がある。
【０２６６】
カウンタへの位置信号をモニタして、無入力時には強制カウントするようにし、回転異常時には再起動するようにしたので、回転中の異常時にも再起動ができる効果がある。
【０２６７】
ある電気角で設定された別の位置検出器による位置信号で起動・再起動時の駆動信号としたので、起動時にも確実に正しい起動が得られる効果がある。
【０２６８】
ある電気角で設定された別の位置検出器による位置信号で起動・再起動時の駆動信号としたので、起動時にも確実に正しい起動が得られる効果がある。
【０２６９】
端子電位を比較して得られる論理信号を微分しラッチし、所定時間後にラッチを解くようにしたので、検出信号にノイズがあっても正しい回転子位置信号が得られる効果がある。
【０２７０】
また、タイマ時間長を可変にしたので、適切な時間を過渡時間として、ノイズをマスクして安定な転流制御ができる効果がある。
【０２７１】
起動時、再起動時または回転異常時には、モータを正転させる強制通電相に所定時間だけ切り換えるようにしたので、負荷の条件に影響されず、短時間で確実に起動できる効果がある。
【０２７２】
起動モードから定常回転モードへの切り換えをタイマで設定して行っているので、確実に定常回転モードに移行できる効果がある。
【０２７３】
ＰＩフィルタと１次遅れフィルタを並列接続したものに、更に、１次遅れフィルタを直列接続した速度誤差補償フィルタ構成としたので、良好な低域外乱圧縮特性が得られるという効果がある。
【０２７４】
ＰＩフィルタに１次遅れフィルタを直列接続したものと、１次遅れフィルタとを並列接続した速度誤差補償フィルタ構成としたので、良好な低域外乱圧縮特性が得られるという効果あある。
【０２７５】
モータへの指令回転数に応じて速度誤差検出器の目標値または速度誤差補償フィルタの利得を切り換えるようにしたので、速度誤差検出器に入力する基準クロックの周期を変化させなくてもよいという効果がある。
【０２７６】
電機子巻線に供給する電流量の増減を、通電相を切り換えた後、所定時間以内に行うように順序づけて構成されているので、電流値をフィードバックして端子電位を補正する処理を容易に行える効果がある。
【０２７７】
起動および再起動の期間、電機子巻線に最大電流を供給するように構成されているので、短時間で確実に起動できる効果がある。
【０２７８】
回転子位置信号の立ち上がり・立ち下がりエッジ内の必要信号を選択し、この必要信号をカウントしたカウンタ値で電機子巻線を駆動するようにしたので、短時間で確実に起動でき、また確実に定常運転に移行できる効果がある。
【０２７９】
台形波状の駆動信号で電機子巻線を印加駆動するようにしたので、転流時の騒音を減少することができる効果がある。
【０２８０】
台形波状の駆動信号の勾配を外部からの制御信号で変化するようにしたので、モータの回転数が変化しても確実に転流時の騒音を減少することができる効果がある。
【０２８１】
台形波状の駆動信号の略勾配中心が最適な転流タイミングに一致するように、回転子位置信号の位相を進めるようにしたので、トルク発生効率を下げることなく騒音を減少することができる効果がある。
【図面の簡単な説明】
【図１】 本発明のブラシレスモータ駆動装置の実施例１の全体構成を示すブロック図である。
【図２】 端子電位補正回路の具体的な構成例を示す図である。
【図３】 実施例１の比較回路の具体的な構成例を示す図である。
【図４】 実施例１、２の動作を説明するための信号波形図である。
【図５】 実施例１、２の動作を説明するための信号波形図である。
【図６】 補正切り換え信号生成回路の構成図と端子電位回路の信号波形図である。
【図７】 通電相と駆動信号の関係を表す図である。
【図８】 本発明のブラシレスモータ駆動装置の実施例２の全体構成を示すブロック図である。
【図９】 端子間電圧補正回路の具体的な構成例を示す図である。
【図１０】 端子間電圧補正回路の動作を説明するためのテーブル図である。
【図１１】 実施例２の比較回路の具体的な構成例を示す図である。
【図１２】 端子間電圧補正回路の動作を説明するためのテーブル図である。
【図１３】 本発明のブラシレスモータ駆動装置の実施例３の全体構成を示すブロック図である。
【図１４】 本発明のブラシレスモータ駆動装置の実施例４の全体構成を示すブロック図である。
【図１５】 本発明のブラシレスモータ駆動装置の実施例５の全体構成を示すブロック図である。
【図１６】 本発明のブラシレスモータ駆動装置の実施例６の全体構成を示すブロック図である。
【図１７】 波形整形回路の具体的な構成例を示す図である。
【図１８】 波形整形回路の動作を説明するための信号波形図である。
【図１９】 波形整形回路の動作を説明するための信号波形図である。
【図２０】 本発明のブラシレスモータ駆動装置の実施例８の全体構成を示すブロック図である。
【図２１】 実施例８の駆動信号と通電相の関係を示すテーブル図である。
【図２２】 実施例８の駆動信号と回転子位置信号の関係を示すテーブル図である。
【図２３】 実施例８のカウンタ回路の具体的な構成例を示す図である。
【図２４】 実施例８のカウンタ回路の動作を説明するためのテーブル図である。
【図２５】 実施例８のカウンタ回路の動作を説明するためのテーブル図である。
【図２６】 実施例８のパルス発生回路の具体的な構成例を示す図である。
【図２７】 実施例８の駆動信号とカウンタ回路の出力値の関係を示すテーブル図である。
【図２８】 実施例８の動作を説明するためのタイミングチャート図である。
【図２９】 実施例８の動作を説明するためのタイミングチャート図である。
【図３０】 本発明のブラシレスモータ駆動装置の実施例９の全体構成を示すブロック図である。
【図３１】 回転子位置信号とカウンタ値の関係を示すテーブル図である。
【図３２】 実施例９の動作を説明するためのタイミングチャート図である。
【図３３】 本発明のブラシレスモータ駆動装置の実施例１０の全体構成を示すブロック図である。
【図３４】 実施例１０の切換信号発生回路の具体的な構成例を示す図である。
【図３５】 実施例１０の切換信号発生回路の動作を説明するためのタイミングチャート図である。
【図３６】 本発明のブラシレスモータ駆動装置の実施例１１の全体構成を示すブロック図である。
【図３７】 実施例１１の切換信号発生回路の具体的な構成例を示す図である。
【図３８】 実施例１１の切換信号発生回路の動作を説明するためのタイミングチャート図である。
【図３９】 本発明のブラシレスモータ駆動装置の実施例１２の全体構成を示すブロック図である。
【図４０】 実施例１２の切換信号発生回路の具体的な構成例を示す図である。
【図４１】 実施例１２の切換信号発生回路の動作を説明するためのタイミングチャート図である。
【図４２】 本発明のブラシレスモータ駆動装置の実施例１３の全体構成を示すブロック図である。
【図４３】 実施例１３の切換信号発生回路の具体的な構成例を示す図である。
【図４４】 実施例１３の切換信号発生回路の動作を説明するためのタイミングチャート図である。
【図４５】 本発明のブラシレスモータ駆動装置の実施例１４の全体構成を示すブロック図である。
【図４６】 実施例１４の切換信号発生回路の具体的な構成例を示す図である。
【図４７】 実施例１４の切換信号発生回路の動作を説明するためのタイミングチャート図である。
【図４８】 本発明のブラシレスモータ駆動装置の実施例１５の全体構成を示すブロック図である。
【図４９】 実施例１５の切換信号発生回路の具体的な構成例を示す図である。
【図５０】 実施例１５の切換信号発生回路の動作を説明するためのタイミングチャート図である。
【図５１】 本発明のブラシレスモータ駆動装置の実施例１６の全体構成を示すブロック図である。
【図５２】 実施例１６の切換信号発生回路の具体的な構成例を示す図である。
【図５３】 速度信号生成回路の動作を説明するためのタイミングチャート図である。
【図５４】 実施例１６の切換信号発生回路の動作を説明するためのタイミングチャート図である。
【図５５】 本発明のブラシレスモータ駆動装置の実施例１７の全体構成を示すブロック図である。
【図５６】 実施例１７の切換信号発生回路の具体的な構成例を示す図である。
【図５７】 実施例１７の切換信号発生回路の動作を説明するためのタイミングチャート図である。
【図５８】 本発明のブラシレスモータ駆動装置の実施例１８の全体構成を示すブロック図である。
【図５９】 実施例１８の切換信号発生回路の具体的な構成例を示す図である。
【図６０】 実施例１８の切換信号発生回路の動作を説明するためのタイミングチャート図である。
【図６１】 本発明のブラシレスモータ駆動装置の実施例１９の全体構成を示すブロック図である。
【図６２】 実施例１９の切換信号発生回路の具体的な構成例を示す図である。
【図６３】 実施例１９の切換信号発生回路の動作を説明するためのタイミングチャート図である。
【図６４】 本発明のブラシレスモータ駆動装置の実施例２０の全体構成を示すブロック図である。
【図６５】 実施例２０の切換信号発生回路の具体的な構成例を示す図である。
【図６６】 実施例２０の切換信号発生回路の動作を説明するためのタイミングチャート図である。
【図６７】 実施例２１の全体構成を示すブロック図である。
【図６８】 本発明のブラシレスモータ駆動装置の実施例２２の全体構成を示すブロック図である。
【図６９】 実施例２２の動作を説明するタイミングチャート図である。
【図７０】 実施例２２の動作を説明するテーブル図である。
【図７１】 実施例２２のカウンタ回路の具体的な構成例を示す図である。
【図７２】 実施例２２の動作を説明するテーブル図である。
【図７３】 実施例２２の動作を説明するタイミングチャート図である。
【図７４】 実施例２２の動作を説明するタイミングチャート図である。
【図７５】 本発明のブラシレスモータ駆動装置の実施例２３の全体構成を示すブロック図である。
【図７６】 実施例２３の動作を説明するタイミングチャート図である。
【図７７】 実施例２３の動作を説明するタイミングチャート図である。
【図７８】 本発明のブラシレスモータ駆動装置の実施例２４の全体構成を示すブロック図である。
【図７９】 本発明のブラシレスモータ駆動装置の定常回転状態における端子電位補正回路の各部の信号波形を示した図である。
【図８０】 図７８の波形整形回路の構成例を示す図である。
【図８１】 定常回転における端子電位波形と波形整形回路の各部波形を示す図である。
【図８２】 図８０の波形整形回路の動作を説明するための信号波形図である。
【図８３】 実施例２５のマスク信号発生回路とタイマの動作を説明するための信号波形図である。
【図８４】 実施例２５のマスク信号発生回路とタイマの動作を説明するための信号波形図である。
【図８５】 実施例２５のマスク信号発生回路とタイマの動作を説明するための信号波形図である。
【図８６】 実施例２６の起動回路の構成を示す図である。
【図８７】 実施例２６の擬似パルス発生回路の構成を示す図である。
【図８８】 実施例２６の擬似パルス発生回路の動作を説明する信号波形図である。
【図８９】 実施例２６の再起動パルス発生回路の一構成例を示す図である。
【図９０】 実施例２６の動作を説明するための信号波形図である。
【図９１】 実施例２７の起動回路の構成を示す図である。
【図９２】 実施例２７の切り換え信号発生回路の構成を示す図である。
【図９３】 切り換え信号発生回路の動作を示す信号波形図である。
【図９４】 実施例２８の速度誤差補償フィルタのブロック図である。
【図９５】 実施例２８の速度誤差補償フィルタの周波数特性を示す図である。
【図９６】 実施例２８のディジタル方式の速度誤差補償フィルタのブロック図である。
【図９７】 実施例２９の速度誤差補償フィルタのブロック図である。
【図９８】 実施例２９の速度誤差補償フィルタの周波数特性を示す図である。
【図９９】 実施例２９のディジタル方式の速度誤差補償フィルタのブロック図である。
【図１００】 本発明のブラシレスモータ用駆動回路の実施例３０の全体構成を示すブロック図である。
【図１０１】 実施例３０の速度誤差検出回路の構成を示す図である。
【図１０２】 実施例３１のＰＩフィルタのブロック図である。
【図１０３】 実施例３２のブラシレスモータ用駆動回路の動作を説明するための信号波形図である。
【図１０４】 本発明のブラシレスモータ用駆動回路の実施例３３の全体構成を示すブロック図である。
【図１０５】 実施例３３の速度誤差補償フィルタの構成を示す図である。
【図１０６】 本発明のブラシレスモータ用駆動回路の実施例３４の全体構成を示すブロック図である。
【図１０７】 実施例３４のパルス選択回路の構成を示す図である。
【図１０８】 実施例３４の駆動回路の動作を説明するタイミングチャート図である。
【図１０９】 実施例３４の駆動回路の動作を説明するタイミングチャート図である。
【図１１０】 本発明のブラシレスモータ用駆動回路の実施例３５の全体構成を示すブロック図である。
【図１１１】 台形駆動信号生成回路中の論理回路の構成を示す図である。
【図１１２】 実施例３５の充放電回路の構成を示す図である。
【図１１３】 実施例３５の駆動回路の動作を説明するタイミングチャート図である。
【図１１４】 台形駆動信号生成回路中の台形波合成回路の構成を示す図である。
【図１１５】 本発明のブラシレスモータ用駆動回路の実施例３６の全体構成を示すブロック図である。
【図１１６】 実施例３６の充放電回路の構成を示す図である。
【図１１７】 実施例３６の駆動回路の動作を説明する信号波形図である。
【図１１８】 本発明のブラシレスモータ用駆動回路の実施例３７の全体構成を示すブロック図である。
【図１１９】 実施例３７の比較回路の構成を示す図である。
【図１２０】 従来のブラシレスモータ用駆動装置の全体構成を示すブロック図である。
【図１２１】 従来のブラシレスモータ用駆動装置の他の全体構成と動作タイミングを示す図である。
【図１２２】 従来のブラシレスモータ用駆動回路の速度制御系の構成を示すブロック図である。
【図１２３】 従来のブラシレスモータ用駆動回路の速度誤差補償フィルタのブロック図である。
【符号の説明】
１ 端子電位補正回路、２ 比較回路、３ 波形整形回路、４ 回転子位置信号生成回路、５ 端子、６ パルス発生回路、７ カウンタ回路、８，８Ｃ，８Ｄ，８Ｅ，８Ｆ，８Ｇ，８Ｈ，８Ｉ，８Ｊ，８Ｋ，８Ｌ 切換信号発生回路、９転流回路、１０ 抵抗、１１ ブリッジ回路、１２，１３，１４ 電機子巻線、１６ 補正切換信号生成回路、２０〜３４ ｎｐｎトランジスタ、３５ ｐｎｐトランジスタ、３６〜５６ 抵抗、５７〜６０ 定電流源、６１〜６７ 端子、７０〜８１ 抵抗、８２〜８４ 差動増幅器、８５〜８７ コンパレータ、１００ 端子間電圧補正回路、１０１ 比較回路、１０２ 回転子位置信号生成回路、１１０〜１２７ ｎｐｎトランジスタ、１２８ ｐｎｐトランジスタ、１２９〜１５５ 抵抗、１５６〜１６２ 定電流源、１６３〜１６９ 端子、１７０〜１７２ コンパレータ、１８０ ラッチ回路、１８１〜１８６ Ｄフリップフロップ、１８７〜１８９ ＥＯＲ回路、１９０ ＯＲ回路、１９１ 単安定マルチバイブレータ、２１０ 転流制御回路、２１１ 電流制御回路、２１２ バッファ増幅器、２１３ 抵抗、２１４ トランジスタ、２５０，２５２，２５４ 立ち上がりエッジ検出回路、２５１，２５３，２５５ 立ち下がりエッジ検出回路、２５６ パルス選択回路、２５７ ６進カウンタ、２６０ リトリガラブル・ワンショット、２６１ 立ち上がりエッジ検出回路、２６５ 定常回転検知回路、２７０ タイマ、２７１ モード切換カウンタ、２７２ 位置信号組み合わせ判別回路、２７３ ＡＮＤ回路、２７４ ラッチ回路、２７５ 駆動信号組み合わせ判別回路、２７６ 基準速度発生回路、２７７ 速度信号生成回路、２７８ 比較回路、２８０ 位置信号カウンタ値判別回路、３００ 位置検出器、３０１ ホールド回路、３０２ エッジ検出回路、４０６，４０６Ｂ 起動回路、４０９ 速度誤差検出回路、４１０ 速度誤差補償フィルタ、４１１ 電流供給回路、４２１ マスク信号発生回路、４２２ タイマ、４３１ 擬似パルス発生回路、４３２ 再起動パルス発生回路、４３３ カウンタ、４３４ ゲート回路、４３５ 立ち上がりエッジ検出回路、４３６ ディレイ回路、４３７ ＯＲ回路、４４０ 立ち上がりエッジ検出回路、４４１ ＯＲ回路、４４２ カウンタ、４４３ ゲート回路、４４４ 立ち上がりエッジ検出回路、４４５ ＡＮＤ回路、４４６ ＯＲ回路、４５０ 切り換え信号発生回路、４５１ 立ち上がりエッジ検出回路、４５２ ＯＲ回路、４５３ カウンタ、４５４ ゲート回路、４５５ ＯＲ回路、４６０ ＰＩフィルタ、４６１ １次遅れフィルタ、４６２ ゲイン要素、４６３ 加算器、４６４ １次遅れフィルタ、４７０，４７１，４７２ 遅延要素、４７３，４７４，４７５，４７６，４７７，４７８，４７９ ゲイン要素、４８１，４８２，４８３ 加算器、４８４ ＰＩフィルタ、４８５，４８６ １次遅れフィルタ、４８７，４８８ 加算器、４９０ 端子、４９１，４９２ 初期値レジスタ、４９３ セレクタ、４９４ カウンタ、４９５，４９６ ゲイン要素、４９７，４９８ セレクタ、６００ マイクロコントローラ、６０１ Ｄ／Ａ変換器、６０２ レジスタ群、６０９ パルス選択回路、６１０ 転流回路、６１１〜６１３ 反転回路、６１４〜６２５ ３入力ＡＮＤ回路、６２６ ６入力ＯＲ回路、６３０ 論理回路、６３１ 充放電回路、６３２ 台形波合成回路、６３３ 台形駆動信号生成回路、６３５〜６４３ ＡＮＤ回路、６４４ ３入力ＯＲ回路、６４５、６４６ 定電電源、６４７ コンデンサ、６４８〜６５１反転アンプ回路、６５２〜６５７ ＮＡＮＤ回路、６６０ 端子、６６１ 充放電回路、６６２ 反転回路、６６３、６６４ 定電流源、６７０比較回路、６７１〜６８５ 抵抗、６８６〜６８８ 差動増幅回路。[0001]
[Industrial application fields]
The present invention relates to a drive circuit for a brushless motor.
[0002]
[Prior art]
The rotational drive control of the brushless motor can be roughly divided into two control functions. One is commutation control for controlling the timing of applying current to the armature windings of each phase, and the other is speed control for keeping the rotation speed constant. The commutation control requires a rotor position signal indicating the relative position of the armature winding and the rotor, while the speed control requires a speed signal indicating the rotation speed of the rotor.
[0003]
A rotor position detecting element such as a hall element is used for commutation switching control of a typical typical brushless motor. However, the rotor position detection element is not cheap and requires more wiring, so that there is a disadvantage that it is complicated and increases the cost.
In addition, by attaching the rotor position detection element, the reduction in size and thickness of the motor is limited. Further, since the output of the rotor position detecting element varies depending on the temperature and humidity, there is a problem in terms of reliability.
[0004]
In order to eliminate this drawback, several brushless motor drive systems have been proposed in which the rotor position is detected from a back electromotive voltage signal induced in the armature winding. A typical driving method for detecting a position from a back electromotive voltage signal is described in Japanese Patent Publication No. 58-25038. For this, both the one that performs position detection by comparing the magnitudes of the terminal potentials and the one that performs position detection by comparing the neutral point potential of the armature winding and the magnitudes of the terminal potentials are disclosed. Yes.
[0005]
Of these, FIG. 120 shows the overall configuration of a method for detecting the position by comparing the neutral point potential with the terminal potential. 120, reference numerals 12, 13, and 14 denote star-connected armature windings of the brushless motor, and reference numeral 11 denotes a bridge circuit that switches energization currents flowing through the armature windings 12, 13, and 14. The comparator 500 compares the terminal potentials U, V, W of each phase that are not neutral points of the armature winding with the neutral point potential M, and detects the rotor position. The commutation control means 501 controls the bridge circuit 11 according to the rotor position detected by the comparator 500, and rotates the rotor by energizing the armature winding of a predetermined phase.
Furthermore, as a method for correcting the phase delay that occurs during the comparison of the terminal potentials, Japanese Patent Laid-Open No. 51-100200 discloses a method for correcting the resistance drop of the armature winding with a voltage dividing resistor, assuming a constant value. ing.
[0006]
By the way, in the drive method in which the rotor position is detected using the back electromotive voltage induced in the armature winding, the rotation speed of the rotor reaches a predetermined value or more and a predetermined back electromotive force is applied to the terminal of the armature winding. If no voltage is generated, the position of the rotor cannot be detected. For this reason, since the rotor position cannot be obtained at the time of startup, a means for forcibly applying a rotating magnetic field from the outside is required. However, when a rotating magnetic field is forcibly applied from the outside, the relative position of the rotor and the armature winding does not always stop at a position where it can rotate in the forward rotation direction. There is a problem that torque may work in the rotation direction and normal startup cannot be performed.
[0007]
In order to solve this problem, improvement proposals have been proposed in, for example, Japanese Patent Application Laid-Open Nos. 57-173385 and 2-237490. Japanese Patent Application Laid-Open No. 57-173385 includes means for energizing a specific phase of an armature winding for a predetermined time at start-up and means for forcibly applying a rotating magnetic field to the armature winding from the outside. An activation method is disclosed in which the rotor is started to rotate after the child is fixed in place. The method disclosed in Japanese Patent Laid-Open No. 57-173385 will be described with reference to FIG. 121A, a power source 510 includes a fixed timer circuit 512 via a power switch 511, and armature windings 12 (U phase), 13 (V phase), and 14 (W phase) of a three-phase DC brushless motor. Is connected. The collectors of the transistors 515, 516, and 517 are connected to the armature windings 12, 13, and 14, respectively, and the emitters of the transistors are grounded, and the drive circuit 518 is configured.
Further, a switching timer circuit 513 and a rotating magnetic field generation circuit 514 are connected to the fixed timer circuit 512, and a switching circuit 519 is further connected to the switching timer circuit 513. The switching circuit 519 switches between a current for driving the driving circuit 518 output from the rotating magnetic field generation circuit 514 and a driving current based on the induced voltage detected by the armature windings 12, 13, and 14 to the driving circuit 518. To supply. The output terminals of the switching circuit 519 are connected to the bases of the transistors 515, 516, and 517 of each phase. An induced voltage detection circuit 520 is connected to the input terminal of the switching circuit 519. The armature windings 12, 13, and 14 are connected to the input terminal of the induced voltage detection circuit 520. Further, an output signal for each of the three phases is input from the rotating magnetic field generation circuit 514 to the input terminal of the switching circuit 519.
[0008]
With this configuration, when the power switch 511 is turned on, one of the armature windings 12, 13, 14 is connected to the power source, and at the same time, the fixed timer circuit 512 is operated, and the armature windings 12, 13 are operated. , 14, for example, the control signal 521 shown in FIG. 121 (b) for exciting the W phase is output to the rotating magnetic field generation circuit 514 for a certain period of time and simultaneously to the switching timer circuit 513. The fixed timer circuit 512 is turned off after a fixed time elapses after the control signal 521 is output from the fixed timer circuit 512. When this is off, the driving signal 523, 524, 525 shown in FIG. 121 (b) for exciting the armature windings 12, 13, 14 from the rotating magnetic field generating circuit 514 via the switching circuit 519 is the transistor 515. 516 and 517, respectively. The switching circuit 519 is switched to the solid line connection state shown in FIG. 121 (a) by the switching command signal 522 shown in FIG. 121 (b) output from the switching timer circuit 513. This connection state is maintained until the output switching command signal 522 becomes low.
[0009]
A drive signal output from the rotating magnetic field generation circuit 514 sequentially applies a drive signal to the bases of the transistors 515, 516, and 517 of the drive circuit 518, and current flows sequentially from the power source 510 to the armature windings 12, 13, and 14. A rotating magnetic field is generated in the armature windings 12, 13, and 14, and the rotor starts to rotate.
In this way, when the motor is started and a predetermined time elapses, the switching signal 522 output from the switching timer circuit 513 goes low, and the switching circuit 519 is switched. A drive signal that is an output of the induced voltage detection circuit 520 is output to the drive circuit 518, and the transistors 515, 516, and 517 are sequentially driven, and the three-phase brushless motor maintains its rotation.
[0010]
Next, JP-A-2-237490 will be described. The brushless motor is provided with a magnetoelectric conversion element for detecting the rotational position of the rotor. Then, based on the rotational position detected by the magnetoelectric conversion element at the time of startup, a predetermined energization switching pattern corresponding to the rotor stop position is selected from among a plurality of energization patterns set in advance for activation. The drive current to the stator armature winding is switched by the energization switching pattern thus generated to generate a rotating magnetic field and start the rotor. When the induced voltage generated in the stator armature winding reaches a value necessary to detect the rotational position of the rotor, the rotational position of the rotor is detected from the induced voltage, and the armature winding is detected by this detection output. The drive current to the line is switched to generate a rotating magnetic field to rotate the rotor.
[0011]
On the other hand, in speed control of a brushless motor, conventionally, a method of maintaining a constant rotation speed by controlling the amount of current flowing through the armature winding is generally used. FIG. 122 shows a block diagram of a speed control system of a conventional brushless motor drive circuit. 122, reference numeral 530 denotes a speed detection circuit that detects the actual rotational speed of the rotor and outputs a speed signal. Reference numeral 531 denotes a speed error signal having a pulse width corresponding to the speed error by counting the period of the speed signal with a reference clock. The speed error compensation filter 532 outputs to the current supply circuit 533 a current command value that makes the speed error zero based on the speed error signal. The current supply circuit 533 adjusts the amount of current supplied to the armature winding of the brushless motor 534 based on the current command value. In such a conventional brushless motor drive circuit, the speed error compensation filter is composed of an analog filter, and a PI filter 460 and a first-order lag filter 464 connected in series as shown in FIG. 123 are used. It was.
[0012]
Also, in the conventional brushless motor drive circuit, the reference to be input to the speed error detector when the command rotational speed to the motor changes by utilizing the fact that the cycle of the speed signal is counted by the reference clock. The rotation speed was switched by changing the clock frequency in proportion to the command rotation speed.
[0013]
In addition, as a method for detecting a speed signal for controlling the rotational speed of the brushless motor, a method commonly referred to as an FG method using a dedicated frequency generator for speed detection, or a method induced by an armature winding. There is a method of detecting the speed by utilizing the fact that the amplitude of the back electromotive voltage signal is proportional to the rotation speed.
[0014]
[Problems to be solved by the invention]
In the conventional driving method that detects the position by comparing the magnitudes of the terminal potentials, one of the two terminal potentials to be compared is the energized phase and the other is the non-energized phase. When it rises, the effect of the resistance drop in the armature winding of the energized phase becomes large, and a phase delay occurs in the rotor position signal.
Due to this phase delay, the commutation timing is delayed, the generated torque is reduced, and the rotational speed is reduced. When the rotational speed is reduced, a vicious cycle occurs in which the energization current increases to increase the rotational speed and the effect of resistance drop increases. In the worst case, there is a problem that torque that surpasses the load cannot be generated and the vehicle stops.
[0015]
On the other hand, the conventional drive method that detects the position by comparing the neutral point potential with the terminal potential solves the problem of phase lag in the position detection signal, but the neutral point is detected from the inside of the brushless motor. There is a problem that the lead processing becomes complicated because it needs to be pulled out.
[0016]
In addition, the rotor position signal obtained by comparing the neutral point potential with the terminal potential is out of phase by 30 degrees in electrical angle with respect to the actually required rotor position signal, so phase correction must be performed. I must. Normally, an integration filter is often used for phase correction. However, when the motor is operated at a variable speed, the constant of the integration filter must be changed. Furthermore, if the constant is fixed, the commutation operation becomes unstable in a transient state.
[0017]
Furthermore, in both the above drive systems, there is a problem that the rotor position signal becomes inaccurate due to the influence of spike-like noise generated in the terminal potential waveform as the drive transistor is switched.
[0018]
In addition, the method of detecting the speed with a dedicated frequency generator requires a frequency generator with high machining accuracy, and further uses a dedicated detector, which is disadvantageous in terms of space efficiency and cost. .
[0019]
In the method of detecting the speed based on the amplitude of the counter electromotive voltage, the voltage generated by the drive current flowing through the armature winding is superimposed on the counter electromotive voltage, so that only the amplitude of the counter electromotive voltage signal can be detected. There is a problem that it is difficult and the amplitude fluctuates due to changes in the surrounding environment.
[0020]
Further, the conventional brushless motor activation method is configured as described above, and there is a problem that it takes a long time to activate since it has to wait for a predetermined time in a predetermined phase after the activation switch is turned on.
[0021]
Further, since the motor is started in an open loop at the time of starting, there is a problem that it is impossible to detect whether or not the motor is actually started until the motor is normally rotated by a drive signal from the induced voltage detection circuit.
[0022]
Moreover, when starting fails, it is necessary to start again, and there is a problem that it takes more time to start.
[0023]
Also, since the conventional speed error compensation filter of the brushless motor drive circuit is configured as described above, the disturbance cannot be sufficiently compressed when the disturbance in the low frequency range is large, resulting in rotational accuracy. There was a problem that it was not possible to satisfy the specifications.
[0024]
Further, the conventional brushless motor drive circuit needs to have a function of changing the frequency of the reference clock input to the speed error detector in proportion to the command rotational speed when the command rotational speed to the motor changes. There was a problem.
[0025]
In addition, the conventional brushless motor drive circuit is not configured to synchronize the timing of commutation and the timing of increasing or decreasing the armature winding current, so that the resistance value of the armature winding and the winding are energized. This is not suitable for performing processing such as adding / subtracting the correction value determined by the current value to the winding potential to the actual driving period.
[0026]
In addition, the conventional brushless motor drive circuit switches the drive transistor using a rectangular wave drive signal, which causes a problem that noise is generated during commutation.
[0027]
The present invention has been made in order to solve the above-mentioned problems. The rotor position signal has no phase lag even when loaded, and can be driven stably regardless of the transient state, and the brush processing is not complicated. The object is to obtain a motor drive circuit.
[0028]
Another object of the present invention is to provide a brushless motor drive circuit that can accurately detect a rotor position signal even if spike voltage fluctuations occur in the terminal potential waveform due to switching of the drive transistor.
[0029]
Another object of the present invention is to provide a brushless motor drive circuit capable of obtaining a speed signal without providing a dedicated speed detector.
[0030]
Another object of the present invention is to provide a brushless motor drive system that can be reliably started in the shortest time without being affected by load conditions.
[0031]
Another object of the present invention is to provide a brushless motor drive circuit that sufficiently compresses the disturbance and provides high-precision rotation even when the low-frequency disturbance is large.
[0032]
Another object of the present invention is to provide a brushless motor drive circuit capable of stably changing the rotational speed of the motor by switching the target rotational speed of the speed error detector and the gain element of the speed error compensation filter. And
[0033]
It is another object of the present invention to obtain a brushless motor drive circuit configured such that the commutation timing and the armature winding current increase / decrease timing are synchronized.
[0034]
Another object of the present invention is to provide a brushless motor drive circuit that generates less noise during commutation.
[0035]
[Means for Solving the Problems]
  A drive circuit for a brushless motor according to the present invention includes:The rotor is driven by a plurality of windings of star-connected armatures,
  A drive voltage for driving the rotor is applied between the plurality of windings, a winding in a phase to which current is sent by the driving voltage is used as a sending-side energization winding, and a winding in a phase into which current flows is used. As the inflow side energization winding, the winding of the phase where the drive voltage is not applied as the non-energization winding,
  The correction value determined by the resistance of the armature winding and the winding current isThe actual driving period is subtracted from the detection terminal potential of the sending side energization winding, and the correction value is added to the detection terminal potential of the inflow side energization winding.Each phase terminal potential correction means;
  Comparing means for comparing the magnitudes of the respective phase terminal potentials after the respective phase terminal potential corrections are provided, and the application driving of the armature windings of each phase is performed by the rotor position signal detected by the comparing means.
[0036]
  Another brushless motor drive circuit of the present invention is:The rotor is driven by a plurality of windings of star-connected armatures,
  A drive voltage for driving the rotor is applied between the plurality of windings, a winding in a phase to which current is sent by the driving voltage is used as a sending-side energization winding, and a winding in a phase into which current flows is used. As the inflow side energization winding, the winding of the phase where the drive voltage is not applied as the non-energization winding,
  When the sending-side energization winding changes from the energized state to the non-energized state, the correction value determined by the resistance of the armature winding and the winding current is subtracted from the detection terminal potential in the energized state, When the inflow-side energization winding changes from the energized state to the non-energized state, the correction value is added to the detection terminal potential in the energized state for the actual driving period to correct the winding terminal voltage difference between the phases.Each phase voltage difference correction means,
  Comparing means for comparing the magnitudes of the inter-phase voltage differences after the correction is provided, and the application driving of the armature windings of each phase is performed by the rotor position signal detected by the comparing means.
[0037]
Further, a rising / falling signal detecting means for the rotor position signal is provided, and the speed feedback control is performed by regarding these signal detection results as detected speed signals.
[0038]
Furthermore, the period during which the drive signal to the bridge circuit for exciting and driving the armature winding of each phase is in the drive state is given to each phase terminal potential correcting means as the actual drive period signal.
[0039]
Furthermore, the period during which the drive signal to the bridge circuit for exciting and driving the armature winding of each phase is in the drive state is given to each inter-phase voltage difference correction means as an actual drive period signal.
[0040]
Furthermore, an actual current detection resistor connected in series to a bridge circuit for exciting and driving the armature winding is provided, and the current flowing through the detection resistor is supplied to each phase terminal potential correcting means as a winding current.
[0041]
Furthermore, an actual current detection resistor connected in series to a bridge circuit for exciting and driving the armature winding is provided, and the current flowing through the detection resistor is supplied to each phase voltage difference correction means as a winding current.
[0042]
Further, a differentiation circuit that detects rising and falling edges of a comparison signal having a magnitude of each phase terminal potential or a voltage difference between phases, and a latch circuit that latches the comparison signal at the timing when the edge is detected by the differentiation circuit And the application of each armature winding as a rotor position signal by combining the outputs of the latch circuits.
[0043]
Another brushless motor drive circuit of the present invention is a rotor position signal for detecting a rotor position signal from each phase terminal potential or each phase voltage difference of a brushless motor that drives a rotor with a plurality of armature windings. Generating means and detecting the rising and falling edges of the rotor position signal of the above output and selecting the necessary edge signal from each detected edge signal as one output, and counting the necessary edge signal A counter for applying driving signals to the armature windings of the phase, and pulse generation means for counting up the counter when the output of one of the counters is not obtained for a predetermined time. The armature winding is applied and driven by the output.
[0044]
Another brushless motor drive circuit of the present invention is a rotor position signal for detecting a rotor position signal from each phase terminal potential or each phase voltage difference of a brushless motor that drives a rotor with a plurality of armature windings. Generating means, detecting the rising and falling edges of the rotor position signal of the above output, selecting the necessary edge signal from each detected edge signal as one output, and counting the necessary edge signal to A counter as an applied drive signal for the armature winding of the phase, and pulse generating means for counting up the counter when one output of this counter is input and this input cannot be obtained for a predetermined time, and the rotor position signal In combination with the above counter output and monitoring the rotation of the motor. Was to perform application driving the armature windings by the counter output.
[0045]
Furthermore, switching means and a timer are provided for switching the armature winding of each phase based on the value of the counter at the time of starting or restarting, and by the rotor position signal at the subsequent steady state, and the starting or restarting period is set to the timer. Changed by setting with.
[0046]
Furthermore, switching means is provided for switching the armature winding of each phase based on the value of the counter at the time of starting or restarting, and by the rotor position signal in the subsequent steady state, so that the counter becomes a predetermined value. Changed to start or restart period is over.
[0047]
Further, switching means for switching to drive the armature winding of each phase by the rotor position signal based on the value of the counter at the time of startup or restart, and the rotor speed signal detection means at the subsequent steady state, When the detected speed signal becomes a predetermined speed, the start or restart period is over, and switching is performed.
[0048]
Further, switching means is provided for switching the armature winding of each phase based on the value of the counter at the time of starting or restarting and at the subsequent steady state by the rotor position signal so that the detected rotor position signal is Switching was made after the start-up or restart period was over by reaching a predetermined combination of values.
[0049]
Further, switching means is provided for switching to drive the armature winding of each phase based on the value of the counter at the time of starting or restarting, and by the rotor position signal at the subsequent steady state, The drive signal becomes a predetermined combination of values so that the start or restart period is over and the switching is performed.
[0050]
Further, switching means for switching to drive the armature winding of each phase based on the counter value at the time of starting or restarting, and the rotor position signal in the subsequent steady state, and the speed of the timer or rotor as necessary Provided with signal detection means, the timer set time elapses or the speed signal detection value reaches a predetermined speed, the counter reaches a predetermined value, the detected rotor position signal becomes a predetermined combination value, or the armature of each phase Switching is performed on the assumption that the start-up or restart period has ended due to the fact that a plurality of combinations of drive signals to the windings have been established.
[0051]
Further, when the rotor position signal input to the counter does not change for a predetermined time, the counter is a counter that outputs a restart pulse as a rotation abnormality to start up and counts itself up.
[0052]
Further, it is determined by a position detector that detects a position shifted by an electrical angle π / 6 with respect to the rotor position signal detected from each phase terminal potential or each phase voltage difference, and the output of this position detector and the start instruction signal. A hold circuit for outputting a selection signal is provided, and at the time of start-up or restart, the counter determines a combination of drive signals to the armatures of each phase by the selection signal.
[0053]
Further, it is determined by a position detector that detects a position shifted by an electrical angle π / 6 with respect to the rotor position signal detected from each phase terminal potential or each phase voltage difference, and the output of this position detector and the start instruction signal. A hold circuit that outputs a selection signal is provided, and the position detector output is used for the drive signal to the first armature at the time of start-up or restart, and the counter selects the above-mentioned drive at the time of start-up or restart A signal that determines a combination of driving signals to the armature of each phase is used.
[0054]
Another brushless motor driving circuit according to the present invention further includes a differentiating circuit for detecting rising / falling edges of a comparison signal having a magnitude of each phase terminal potential or a magnitude of a voltage difference between phases, in addition to the basic configuration. A timer that operates by edge detection and stops after a predetermined time, and a latch circuit that latches the comparison signal when the edge is detected by the differentiation circuit and releases the latch when the timer stops are combined, and the above latch circuit output is combined Thus, the application drive of the armature winding of each phase is performed as the rotor position signal.
[0055]
Furthermore, the timer time length from when the latch circuit latches the comparison signal to when the latch is released is changed based on the command rotational speed to the armature.
[0056]
Another brushless motor driving circuit according to the present invention includes a rotor position signal generating means for detecting a rotor position signal from each phase terminal potential of a plurality of phases or a voltage difference between phases, and a rise of the rotor position signal of this output. A pulse generating means for detecting a falling edge, selecting a necessary edge signal from each detected edge signal, giving an output pulse train, and giving a pseudo pulse train if the required edge signal cannot be obtained for a predetermined time; and this pulse generating means A counter for counting output, a steady rotation detecting means for outputting a rotation abnormality signal when the relationship between the rotor position signal and the counter value is not in a predetermined relationship, and the steady rotation detection within a set time after starting and restarting The system includes a restart pulse generating means for masking the rotation abnormality signal of the means and outputting a restart pulse based on the rotation abnormality signal after the set time has elapsed. , Within the set time at the time of re-activation by re-activation pulse was to perform the application operation of the armature winding at the counter output.
[0057]
Furthermore, switching means and a timer are provided for switching to drive the armature winding of each phase based on the counter value at the time of starting or restarting, and based on the rotor position signal at the subsequent steady state, and starting or restarting Changed the period by setting the timer.
[0058]
Another brushless motor drive circuit of the present invention outputs a speed error signal as a speed error signal, and a speed detection means for detecting the speed at which the rotor is rotating, and the difference between the detected actual rotational speed and the target rotational speed. The speed error detecting means for detecting the speed error signal and the detected speed error signal are input, and the configuration is a parallel circuit of a proportional / integral (PI) filter and a first-order lag filter, and an added value of each output of the parallel circuit is input. It is a series circuit with a first-order lag filter, and is provided with a speed error compensation filter that uses the added first-order lag output as a current command value to the armature winding.
[0059]
Further, speed detecting means for detecting the speed at which the rotor is rotating, speed error detecting means for outputting a difference between the detected actual rotational speed and the target rotational speed as a speed error signal, and the detected speed An error signal is input, and its configuration is a parallel circuit of a series circuit of a proportional / integral filter and a first-order lag filter, and a first-order lag filter provided separately from this series circuit. A speed error compensation filter using the added value as a current command value for the armature winding is provided.
[0060]
Further, speed detection means for detecting the speed at which the rotor is rotating, speed error detection means for outputting a difference between the detected actual rotation speed and the target rotation speed as a speed error signal, and this detection A speed error compensation filter that obtains a current command value to the armature winding from the speed error signal, and a target rotational speed of the speed error detection means and a speed error compensation filter according to the command rotational speed to the drive circuit for the brushless motor The gain was changed.
[0061]
Another brushless motor drive circuit according to the present invention includes a rotor position detecting means for detecting the relative position of the armature winding and the rotor, a commutation control means for switching the energized phase at the detected rotor position, Speed detection means for detecting the speed at which the child is rotating, speed error detection means for outputting the difference between the detected actual rotation speed and the target rotation speed as a speed error signal, and the detected speed error signal And a speed error compensation filter that obtains a current command value to the armature winding from each other, and by switching the energized phase by the commutation control means, the current command value to the armature winding is increased or decreased after a certain time.
[0062]
Furthermore, a maximum current is applied to the armature winding during the start-up and restart periods.
[0063]
Another brushless motor driving circuit according to the present invention includes a rotor position signal generating means for detecting a rotor position signal from each phase terminal potential of a plurality of phases or a voltage difference between phases, and a rise of the rotor position signal of this output. A pulse generating means for detecting a falling edge, selecting a necessary edge signal from each detected edge signal, giving an output pulse train, and providing a pseudo pulse train if the predetermined edge signal cannot be obtained, and this pulse generating means And a counter that counts the output, and the armature winding is applied and driven by the counter output.
[0064]
Another drive circuit for a brushless motor according to the present invention further includes a comparison means for comparing the magnitude of each phase terminal potential or each phase voltage difference correction means with each phase terminal potential or each phase voltage difference of the output in addition to the basic configuration. A commutation circuit that obtains an armature winding drive signal from the rotor position signal detected by the rotor position signal detection means, and a trapezoidal drive signal generation circuit that processes the output of the commutation circuit to form a trapezoidal drive signal. The trapezoidal drive signal is supplied to the armature winding.
[0065]
Furthermore, a charge / discharge circuit is provided in the trapezoid drive signal generation circuit, and the time constant of the charge / discharge circuit is changed by an external control signal to change the trapezoid gradient.
[0066]
Furthermore, a phase advance circuit for advancing the phase of the rotor position signal is provided, and the phase advance amount of this phase advance circuit is set to be approximately equivalent to 1/2 of the gradient time of the trapezoid drive signal for driving the armature winding. .
[0067]
[Action]
In the brushless motor drive circuit according to the present invention, the detected winding terminal potential of each phase is subjected to voltage correction for the winding current only during the actual driving period. The child is driven.
[0068]
In the brushless motor drive circuit according to the present invention, the detected winding terminal voltage difference between the phases is subjected to voltage correction for the winding current only during the actual drive period, and the signal combination of the comparison results of the voltage differences between the phases after correction is used. The armature is driven.
[0069]
Further, the rising / falling signal of the rotor position signal is regarded as a detection speed signal, and feedback control is performed.
[0070]
Further, the period during which the drive signal to the bridge circuit is in the drive state is set as the actual drive state, which is the winding terminal potential correction period.
[0071]
Furthermore, the period during which the drive signal to the bridge circuit is in the drive state is set as the actual drive state, which is a correction period for the winding terminal voltage difference between the phases.
[0072]
Furthermore, a current flowing through a resistor connected in series with the bridge circuit is detected as a winding current and used as a correction voltage to the winding terminal potential.
[0073]
Furthermore, a current flowing through a resistor connected in series to the bridge circuit is detected as a winding current and used as a correction voltage for a winding terminal voltage difference between the phases.
[0074]
Further, the magnitude comparison signal of each winding potential or the voltage difference between the phases is once differentiated, and the comparison signal is latched at the timing when this differential signal is obtained, and a new rotor position signal that is not affected by noise is generated. The armature winding is driven from the combination of these position signals.
[0075]
In the brushless motor driving circuit according to the present invention, a necessary signal is selected from the rising and falling edges of the rotor position signal, and the armature winding is driven using the selected necessary signal at the time of start-up.
[0076]
In the drive circuit for a brushless motor according to the present invention, a necessary signal is selected from the rising and falling edges of the rotor position signal, the rotation state of the motor is monitored, and when the rotation is abnormal, the selected necessary signal is used. The armature winding is driven.
[0077]
Further, the drive is switched from the startup time to the steady time, and the startup period is determined by a set time corresponding to a timer.
[0078]
Further, the drive is switched from the startup to the steady state, and the startup period is determined by the counter counting up to a predetermined value.
[0079]
Further, the drive is switched from the start time to the steady state, and the start period is determined by the rotor detection speed corresponding to the predetermined speed.
[0080]
Further, the drive is switched from the startup to the steady state, and the startup period is determined by the detected rotor position signal having a predetermined value.
[0081]
Furthermore, the drive is switched from the start time to the steady state, and the start period is determined by the drive signal to the armature having a predetermined value.
[0082]
Furthermore, the drive is switched from the startup to the steady state, the startup period has a set time, the set speed is reached, a predetermined number of counts, the rotor position signal is steady, and the drive signal to the armature is steady. It is determined by establishment.
[0083]
Further, the operation of the counter is monitored, and when there is no output, it is regarded as a rotation abnormality and a restart state is entered.
[0084]
Furthermore, a combination of drive signals to the armature at the time of starting or restarting is determined by a position signal that detects a position separated by another predetermined electrical angle.
[0085]
Furthermore, the position signal that detects a position separated by another predetermined electrical angle is the first drive signal at the time of start-up or restart, and this is the position signal, and the drive signal to the armature at the time of subsequent start-up or restart Is determined by this position signal and other conditions.
[0086]
Further, by latching the magnitude comparison signal of each winding potential or the voltage difference between phases at a predetermined timing for a predetermined time, a rotor position signal having a waveform shape without fluctuation is obtained, and an armature is obtained from the combination of the rotor position signals. The winding is driven.
[0087]
Furthermore, the timer time for releasing the latch changes based on the externally commanded rotational speed to the armature.
[0088]
The drive circuit for a brushless motor according to the present invention switches to a forced energization phase for normal rotation of the motor at the time of start-up and restart, and becomes abnormal after a predetermined time has elapsed after start-up or restart. Will be restarted.
[0089]
Further, the switching of driving from the start-up to the steady-state is set by the timer, and the transition is surely made.
[0090]
In the brushless motor drive circuit according to the present invention, the current command value from the speed error signal to the armature winding is passed through the first-order lag filter that compresses the low-frequency disturbance parallel to the proportional integral (PI) filter. Is converted to
[0091]
In the brushless motor drive circuit according to the present invention, the speed error signal is detected via a first-order lag filter that compresses low-frequency disturbances arranged in series in a series circuit of a proportional integral (PI) filter and a first-order lag filter. It is converted into a current command value for the armature winding.
[0092]
In the brushless motor drive circuit of the present invention, the target rotational speed and the gain of the speed error compensation filter change depending on the command rotational speed to the motor, and a current command value from the speed error signal to the armature winding is obtained. The reference clock to the speed error detector may be constant.
[0093]
In the brushless motor drive circuit according to the present invention, after the energized phase is switched, an increase / decrease in the amount of current to the armature winding is commanded after a certain time.
[0094]
In the brushless motor drive circuit according to the present invention, the maximum current is applied to the armature at the time of start-up and restart, and the start-up is performed reliably.
[0095]
In the brushless motor driving circuit according to the present invention, a necessary signal within the rising and falling edges of the rotor position signal is selected, and the armature winding is driven with a counter value obtained by counting the necessary signal.
[0096]
Further, means for processing a rectangular wave drive signal to generate a trapezoidal drive signal is provided, and the armature winding is driven by the trapezoidal drive signal.
[0097]
Furthermore, the slope of the trapezoidal drive signal changes with an external control signal.
[0098]
Further, the phase advance circuit makes the optimum commutation timing coincide with the approximate gradient center of the trapezoidal drive signal.
[0099]
【Example】
Example 1.
The present invention detects the armature winding voltage of each phase and corrects it by applying a correction voltage, which is the product of the load resistance and the current only in the actual load state, since the phase lag occurs as it is, and correct in the actual load state. A terminal voltage at a phase is obtained, and a driving voltage for each armature winding is generated by a commutation circuit based on the winding terminal voltage.
Further, an example will be described in which an equivalent motor speed is detected from each phase armature winding voltage, and the detected speed is fed back and used for rotor speed control.
In the present embodiment, the configuration and operation of a brushless motor driving device based on this idea will be described. FIG. 1 is a block diagram showing the overall configuration of a first embodiment of a brushless motor driving apparatus according to the present invention. In FIG. 1, 12, 13 and 14 are neutral-point ungrounded three-phase star-connected brushless motor armature windings, 11 is an energization control of drive transistor groups TR1 to TR6 and armature windings 12, 13 is a bridge circuit that supplies a predetermined drive current to 13 and 14. The armature windings 12, 13, and 14 will be referred to as U phase, V phase, and W phase for convenience. 1 is a terminal potential correction circuit that corrects the terminal potential and outputs corrected terminal potential signals 1a, 1b, and 1c. 2 is a circuit that compares the corrected terminal potentials of each phase to obtain logic signals 2a, 2b, and 2c. The comparison circuit 3 is a waveform shaping circuit that obtains the rotor position signals 3a, 3b, and 3c by shaping the logic signals 2a, 2b, and 2c, and generates the rotor position signal including the members 1, 2, and 3 above. A circuit 4 is configured. 5 is a terminal to which a motor rotation signal for enabling the rotation of the motor is input, 6 is a pulse generation circuit, 7 is a counter circuit, 8 is a switching signal generation circuit, and the commutation circuit 9 is a rotor position signal generation circuit 4. The driving signals 9a to 9f are output in accordance with the states of the signals input from the terminal 5, the counter circuit 7 and the switching signal generating circuit 8 to control the switching of the driving transistor groups TR1 to TR6.
[0100]
FIG. 2 shows a specific configuration example of the terminal potential correction circuit 1. In FIG. 2, 20 to 34 are npn transistors, 35 is a pnp transistor, 36 to 56 are resistors, and 57 to 60 are constant current sources. The base of the npn transistor 20 has a U-phase terminal potential and the base of the npn transistor 25. Is connected to the base of the npn transistor 30 and to the base of the pnp transistor 35. The base of the pnp transistor 35 is connected to a terminal 61 to which a voltage related to the armature winding resistance drop is input. . 62 to 67 are terminals to which a correction switching signal for switching correction of the terminal potential is input. The corrected terminal potential of each phase is output as 1a, 1b, and 1c.
[0101]
FIG. 3 shows a specific configuration example of the comparison circuit 2. In FIG. 3, reference numerals 70 to 81 denote resistors, 82 to 84 denote differential amplifier circuits, and 85 to 87 denote comparators. Resistors are connected to the non-inverting input terminal of the differential amplifier circuit 82 and the inverting input terminal of the differential amplifier circuit 83, respectively. The U-phase terminal potential 1a corrected through 70 and 75 is corrected through the resistors 74 and 79 to the non-inverting input terminal of the differential amplifier circuit 83 and the inverting input terminal of the differential amplifier circuit 84, respectively. The phase terminal potential 1b is input to the non-inverting input terminal of the differential amplifier circuit 84 and the inverting input terminal of the differential amplifier circuit 82. The corrected W phase terminal potential 1c is input via the resistors 78 and 71, respectively. The inverting input terminals of the differential amplifier circuits 82, 83, and 84 are also connected to the output terminals of the differential amplifier circuits 82, 83, and 84 via resistors 73, 77, and 81, and the output terminals of the comparators 85, 86, 87 is connected to the non-inverting input terminal. Further, the reference voltage Vref is input to the non-inverting input terminals of the differential amplifier circuits 82, 83 and 84 and the inverting input terminals of the comparators 85, 86 and 87. The differential amplifier circuit 82 outputs differential amplified signals 1a and 1c with Vref as the center voltage. The differential amplified signal and Vref are compared by a comparator 85 to obtain a logic signal 2a. The logic signals 2b and 2c are obtained in the same procedure.
[0102]
FIG. 4 shows the relationship between the terminal potential waveform of each phase when there is no load when the terminal potential is not corrected, the logic signals 2a, 2b and 2c output from the comparison circuit 2, and the energized phase. . In the actual terminal potential waveform, spike-like voltage fluctuations occur during commutation, but are omitted here for the sake of simplicity. When there is no load, the amount of energization current is small, so the resistance drop in the armature winding is almost negligible, and the terminal potential waveform is symmetrical as shown in FIG. 4 and has a predetermined phase relationship with the rotor. A certain logic signal can be obtained.
On the other hand, FIG. 5 shows the relationship between the terminal potential waveform of each phase under load, the logic signals 2a, 2b, and 2c output from the comparison circuit 2 and the energized phase when the terminal potential is not corrected. is there. At the time of load, since there is an energization current, the influence of the resistance drop in the armature winding cannot be ignored. One of the two terminal potentials to be compared is an energized phase, and the other is a non-energized phase. For example, when energization is switched from V → W to U → W, the terminal potentials of the V phase and the U phase are compared, but the V phase is an energized phase and the U phase is an unenergized phase. A voltage corresponding to the resistance drop is superimposed on the terminal potential waveform of the V phase that is the energized phase. On the other hand, since no current flows in the U phase, only the back electromotive force is generated at the terminal potential (the power supply voltage of the bridge circuit is V_ccSince the neutral point is ungrounded, the potential at the neutral point is lowered by the resistance drop, and the terminal potential waveform actually observed is that the terminal potential of the U phase, which is a non-conducting phase, is leveled down. Will be in the shape). Accordingly, a shift occurs at a position where the potential levels of the V-phase terminal potential and the U-phase terminal potential coincide with each other, and the phase of the obtained logic signal is delayed as compared with the case of no load as shown by 2b in FIG. End up.
[0103]
In order to solve the problem that the phase delay occurs, the voltage of the resistance drop is added or subtracted from the terminal potential of the energized phase, and then the magnitudes of the terminal potentials are compared to determine the logic signals 2a and 2b. 2c may be obtained. For example, for the U phase, the resistance drop voltage is subtracted when the U phase is energized from the V phase or the W phase, and the resistance drop voltage is added when the V phase or the W phase is energized to the U phase. What is necessary is just to set it as such.
[0104]
Hereinafter, a specific operation of the terminal potential correction circuit 1 will be described with reference to the drawings. Although FIG. 2 shows the terminal potential correction circuit for the U, V, and W phases, the following description focuses on the U-phase terminal potential correction circuit.
First, consider the case where the terminals 62 and 63 are at high level. At this time, since the collector potentials of the npn transistor 22 and the npn transistor 24 are 0, the emitter potentials of the npn transistor 21 and the npn transistor 23 are also 0, and no current flows through the resistors 37 and 40. Therefore, the resistor 36 (resistance value R₁) Is supplied from a constant current source 57.₁The potential observed at the output terminal of the U-phase terminal potential correction circuit is the base-emitter voltage (V) of the transistor 20 from the input value of the terminal potential correction circuit._be) And the resistance drop voltage at the resistor 36.
1a = U−V_be-R₁・ I₁              (1)
[0105]
Next, consider the case where the terminals 62 and 63 are at low level. Terminal 61 has V_irIs input. At this time, the collector potentials of the npn transistor 22 and the npn transistor 24 are V_ir+ V_be(V), the emitter potentials of the npn transistor 21 and the npn transistor 23 are V_irResistance 37 (resistance value R₂), Resistor 40 (resistance value R₂) For each V_ir/ R₂Current flows. Therefore, the current flowing through the resistor 36 is i supplied from the constant current source 57.₁And the current flowing through the resistor 37 and the resistor 40 are added, and the potential observed at the output terminal of the U-phase terminal potential correction circuit is expressed by Equation (2).

When the terminal 62 is at a high level and the terminal 63 is at a low level, or when the terminal 62 is at a low level and the terminal 63 is at a high level, only one of the resistor 37 and the resistor 40 has V_ir/ R₂Therefore, the potential observed at the output terminal of the U-phase terminal potential correction circuit is as shown in Equation (3).

[0106]
Eventually, when it is desired to add the voltage corresponding to the resistance drop (when V → U, W → U energized), the terminal 62 and the terminal 63 are set to the high level, and the voltage corresponding to the resistance drop is subtracted (U → V). The terminal potential can be corrected by setting the terminal 62 and the terminal 63 to the low level (when U → W is energized).
When the U phase is a non-energized phase and does not need to be corrected (V → W, W → V energized), the terminal 62 is set to high level and the terminal 63 is set to low level, or the terminal 62 is set. Is set to low level and the terminal 63 is set to high level. Similarly, for the V phase, when it is desired to add the voltage corresponding to the resistance drop (when U → V, W → V energization), the terminals 64 and 65 are set to the high level, and the voltage corresponding to the resistance drop is set. When subtraction is desired (when V → U, V → W energized), the terminals 64 and 65 are set to low level, and when correction is not required (U → W, W → U energized), the terminal 64 may be set to a high level and the terminal 65 may be set to a low level, or the terminal 64 may be set to a low level and the terminal 65 may be set to a high level.
Furthermore, for the W phase, if you want to add the voltage for the resistance drop (U → W, V → W energization), set the terminal 66 and terminal 67 to high level and subtract the voltage for the resistance drop. If it is desired (W → U, W → V energization), the terminal 66 and the terminal 67 are set to a low level, and if no correction is required (U → V, V → U energization), the terminal 66 Is set to high level and the terminal 67 is set to low level, or the terminal 66 is set to low level and the terminal 67 is set to high level. FIG. 6B is a timing chart showing the relationship between the energized phase and the correction switching signal input to the terminals 62 to 67.
[0107]
FIG. 6A is a detailed circuit diagram of a specific correction switching signal generation circuit 16 for correcting the product of resistance and current only in the actual driving period to the detected winding terminal potential. In this embodiment, the rotor position signals 3a, 3b, and 3c are used as inputs, and a switching signal shown in FIG. 6B is sent to each terminal 62 to 67 of the terminal potential correction circuit 1 by a combination of logic elements. Yes.
In this embodiment, as shown in FIG. 1, the current control circuit 211 and its buffer amplifier 212, resistor 213, and drive transistor 214 control the winding current flowing through the armature. The terminal 61 uses the output of the current control circuit 211.
The current control circuit 211 detects an error between the actual rotation speed and the command rotation speed from the logic pulse signal 201, and controls the amount of current supplied to the armature winding so that the detected error becomes zero.
In this embodiment, an example applied to a three-phase brushless motor has been described. However, it is apparent that the present invention is applicable not only to three phases but also to a plurality of brushless motors in general. In the present embodiment, the means constituted by the transistor circuit may be constituted by an OP amplifier or a digital IC.
[0108]
Example 2
In this embodiment, the armature winding voltage of each phase is detected, and a phase lag occurs if it is left as it is, so that a correction voltage, which is the product of the load resistance and current, is applied to the voltage difference of each phase and corrected only in the actual load state. The terminal voltage at the correct phase in the actual load state was obtained, and the drive voltage of each armature winding was generated by the commutation circuit based on this winding terminal voltage.
In the present embodiment, the configuration and operation of a brushless motor driving device based on this idea will be described. FIG. 8 is a block diagram showing the overall configuration of the second embodiment of the brushless motor driving apparatus according to the present invention. In FIG. 8, the same members as those in the first embodiment are indicated by the same numbers. The inter-terminal voltage correction circuit 100 that corrects the inter-terminal voltage and outputs the corrected inter-terminal voltage signals 100a to 100f, the comparison circuit 101 that compares the corrected inter-terminal voltages to obtain the logic signals 101a, 101b, and 101c, and waveform shaping A rotor position signal generation circuit 102 is configured including the circuit 3.
[0109]
FIG. 9 shows a specific configuration example of the inter-terminal voltage correction circuit 100. 9, 110 to 127 are npn transistors, 128 is a pnp transistor, 129 to 155 are resistors, and 156 to 162 are constant current sources. The bases of the npn transistors 110 and 117 have a U-phase terminal potential, and the npn transistor 116. , 123 is supplied with the V-phase terminal potential, the npn transistors 111 and 122 are supplied with the W-phase terminal potential, and the pnp transistor 128 is supplied with the voltage related to the armature winding resistance drop. 163 is connected. Reference numerals 164 to 169 denote terminals to which a correction switching signal for switching correction of the inter-terminal voltage is input. The corrected inter-terminal voltage is output as 100a to 100f.
[0110]
A specific operation of the inter-terminal voltage correction circuit will be described with reference to the drawings. In FIG. 9, the power supply voltage is V_cc, Resistance values of the resistors 129, 131, 138, 140, 147, 149 are R_Three, Resistance values of resistors 130, 139 and 148 are R_Four, Resistance values of resistors 134, 135, 143, 144, 152, 153 are R_Five, The current value supplied from the constant current sources 156, 157, 159 to 162 is i.₂, The base current of the npn transistor is i_b, The voltage input to the terminal 163 is V_irAnd
[0111]
First, consider the case where the terminal 164 is at a high level. At this time, the emitter potential of the npn transistor 113 becomes 0 and no current flows through the resistor 134. The resistor 130 has (U−W) / R in the direction from the emitter terminal of the npn transistor 110 to the emitter terminal of the npn transistor 111._FourA current flows. Therefore, the current flowing through the resistor 129 is i₂+ (U−W) / R_Four-I_bThus, 100a output from the inter-terminal voltage correction circuit 100 is expressed by Equation (4).

On the other hand, when the terminal 164 is at a low level, the resistor 134 also has V_ir/ R_Five100a output from the inter-terminal voltage correction circuit 100 is expressed by Equation (5).

Considering the other terminal voltages in the same procedure, the relationship between the logic levels of the terminals 164 to 169 and 100a to 100f is as shown in FIG.
[0112]
FIG. 11 shows a specific configuration example of the comparison circuit 101. In FIG. 11, reference numerals 170 to 172 denote comparators. Comparator 170 compares 100b and 100a and outputs logic signal 101a, comparator 171 compares 100d and 100c and outputs logic signal 101b, and comparator 172 compares 100f and 100e and outputs logic signal 101c. .
Consider a specific operation of the comparison circuit 101. When the terminals 164 and 165 are at a high level, the comparator 170 outputs a logic signal 101a of U> W. When terminal 164 is low and terminal 165 is high, {U + (R_Four・ V_ir) / (2.R_Five)}> W is output as a logic signal 101a. Conversely, if terminal 164 is high and terminal 165 is low, {U− (R_Four・ V_ir) / (2.R_Five)}> W is output as a logic signal 101a.
[0113]
As shown in FIG. 5, the rotor position is detected when the U-phase and W-phase terminal potentials coincide with each other when the energization is switched from U to V to W to V, and from V to U to V to V. Although it is a time to switch the energization to W, in both cases, the U phase is an energized phase and the W phase is a non-energized phase at the time of comparison. Therefore, a voltage corresponding to a resistance drop is superimposed on the U phase terminal potential. Therefore, it is necessary to correct the voltage corresponding to the resistance drop from the U-phase terminal potential at the time of comparison. When switching from U → V to W → V, it is necessary to subtract the voltage of the resistance drop from the U phase terminal potential. When switching from V → U to V → W, the resistance drop to the U phase terminal potential. It is necessary to add the voltage of the minute. Therefore, (R_Four・ V_ir) / (2.R_Five) Is set to a voltage related to the armature winding resistance drop, the terminal 164 is set to the high level when the U → V energization, the terminal 165 is set to the low level, and the terminal 164 is set to the V → U energization. If the low level and the terminal 165 are set to the high level, the logic signal 101a is obtained by comparing the U-phase terminal potential and the W-phase terminal potential corrected for the voltage corresponding to the resistance drop. Similar effects can be obtained.
[0114]
The voltage between the other terminals can be considered in the same procedure. The terminal 166 is set to the high level when the V → W energization, the terminal 167 is set to the low level, and the terminal 166 is set to the low level when the W → V energization. If the terminal 168 is set to the high level when the W → U is energized, the terminal 169 is set to the low level, the terminal 168 is set to the low level when the U → W is energized, and the terminal 169 is set to the high level. The same effect as in Example 1 can be obtained. The relationship between the energized phase and the correction switching signal input to the terminals 164 to 169 is shown in FIG.
[0115]
Example 3
In the present embodiment, each phase armature winding voltage described in the first embodiment is detected, and the correction voltage, which is the product of the load resistance and current, is applied and corrected only in the actual load state. Based on the terminal voltage at the correct phase, a drive signal for each armature winding is generated by the commutation circuit. The drive signal is used as a correction switching signal at this time.
In the present embodiment, the configuration and operation of a brushless motor driving device based on this idea will be described. FIG. 13 is a block diagram showing the overall configuration of a third embodiment of the brushless motor driving apparatus according to the present invention. In FIG. 13, the same members as those in the first embodiment are indicated by the same numbers. In the present embodiment, the drive signals 9a, 9b, 9c, 9d, 9e, and 9f are input to the terminal 63, the terminal 65, the terminal 67, the terminal 62, the terminal 64, and the terminal 66 of the terminal potential correction circuit 1, respectively.
[0116]
The correction switching signal shown in FIG. 6 of the first embodiment is a signal synchronized with commutation. Therefore, the drive signal for sequentially switching the drive transistors TR1 to TR6 can be used as the correction switching signal. FIG. 7 shows the relationship between the energized phase and the drive signals 9a to 9f when the bridge circuit 11 is configured as shown in FIG. The correction switching signal for the terminal 62, terminal 63, terminal 64, terminal 65, terminal 66, and terminal 67 in FIG. 6 and the drive signals 9d, 9a, 9e, 9b, 9f, and 9c are the same. Therefore, an embodiment of the brushless motor driving apparatus according to the present invention can be configured as shown in FIG.
[0117]
Example 4
This example is an example in which Example 2 and Example 3 are combined. That is, the armature winding voltage of each phase is detected, and the correction voltage, which is the product of the load resistance and current, is applied to the voltage difference of each phase and corrected only in the actual load state, and based on the terminal voltage at the correct phase. A drive signal for each armature winding is generated by the commutation circuit, and a correction switching signal at this time is obtained from the drive signal.
FIG. 14 is a block diagram showing the overall configuration of the fourth embodiment of the brushless motor driving apparatus of the present invention. In FIG. 14, the same members as those in the second embodiment are indicated by the same numbers. In this embodiment, the drive signal 9a is applied to the terminals 165 and 168 of the inter-terminal voltage correction circuit 100, the drive signal 9b is applied to the terminals 164 and 167 of the inter-terminal voltage correction circuit 100, and the drive signal 9c is applied to the inter-terminal voltage correction circuit. 100 terminal 166 and terminal 169.
[0118]
When correcting the inter-terminal voltage, as in the third embodiment, it is possible to use a drive signal for sequentially switching the drive transistors TR1 to TR6 as the correction switching signal. For example, the correction switching signal input to the terminal 164 may be high level when U → V energization and low level when V → U energization, so that the drive signals 9b and 9e can be used. Similarly, the driving signals 9a and 9d are input to the correction switching signal input to the terminal 165, the driving signals 9c and 9f are input to the correction switching signal input to the terminal 166, and the driving signal 9b is input to the correction switching signal input to the terminal 167. The drive signals 9a and 9d can be used for the correction switching signal input to the terminal 168, and the drive signals 9c and 9f can be used for the correction switching signal input to the terminal 169. Therefore, an embodiment of the brushless motor driving apparatus according to the present invention can be configured as shown in FIG.
[0119]
Embodiment 5 FIG.
In this embodiment, a sense resistor for detecting a load current is provided as a load current value when a correction voltage that is a product of the load resistance and current is applied only in an actual load state, and an actual load current is obtained with this detected voltage. I made it.
In the present embodiment, the configuration and operation of a brushless motor driving device based on this idea will be described. In FIG. 15, the same members as those in the first embodiment are indicated by the same numbers. In this embodiment, the common emitter terminals of TR4 to TR6 and the terminal 61 of the terminal potential correction circuit 1 are connected.
[0120]
In FIG. 15, since the resistor 10 is connected to the common emitter terminals of the drive transistors TR <b> 4 to TR <b> 6, the current flowing through the armature winding also flows through the resistor 10. Therefore, it is possible to detect the amount of current flowing through the armature winding as a voltage drop in the resistor 10. I is the current flowing through the armature winding._LThe resistance value of the armature winding resistance for one phase is r, and the resistance value of the resistor 10 is R_sThen, the resistance drop in the armature winding is I_LR, the potential input to the terminal 61 is I_L・ R_sIt is. The voltage corrected by the terminal potential correction circuit is
R₁・ I_L・ R_s/ R₂
Therefore, this value is I_LR to be equal to r₁, R₂, R_sShould be set.
[0121]
Example 6
An example in which the idea of the fifth embodiment is applied to the second embodiment will be described.
FIG. 16 is a block diagram showing the overall configuration of the sixth embodiment of the brushless motor driving apparatus of the present invention. In FIG. 16, the same members as those in the second embodiment are indicated by the same numbers. In this embodiment, the common emitter terminals of TR4 to TR6 and the terminal 163 of the inter-terminal voltage correction circuit 100 are connected.
[0122]
When correcting the voltage between the terminals, the voltage of the amount related to the armature winding resistance drop can be detected from the common emitter terminals of TR4 to TR6 as in the fifth embodiment, and the brushless motor according to the present invention. One embodiment of the driving apparatus can be configured as shown in FIG.
[0123]
Example 7
In the above embodiments, the operation has been described assuming that the waveform is an ideal waveform without any disturbance. However, in reality, noise is added to the waveform, chattering occurs in the operation, and spike-like noise described in FIG. An example in which such a waveform is considered to operate normally will be described.
In this embodiment, such consideration is taken, and the correction and driving described in the above embodiment are attempted after the detection signal waveform is once returned to a correct and stable form by the waveform shaping circuit.
FIG. 17 shows a specific configuration example of the waveform shaping circuit 3. In FIG. 17, 180 is a latch circuit, 181 to 186 are D flip-flops, 187 to 189 are EOR circuits, 190 is an OR circuit, and 191 is a monostable multivibrator. FIG. 18 shows the terminal potential waveform and the signal waveform of each part of the waveform shaping circuit in the steady rotation state, and FIG. 19 is an enlarged view of time T0 to T1 in FIG.
[0124]
A specific operation of the waveform shaping circuit will be described with reference to FIGS. Input signals to the waveform shaping circuit are logic signals 2a, 2b, 2c or 101a, 101b, 101c output from the comparison circuit 2 or the comparison circuit 101. In the first and second embodiments, the spike-like voltage fluctuation generated in the terminal potential waveform due to the switching of the driving transistor has been ignored, but actually, the spike-like voltage fluctuation occurs in the terminal potential waveform. Occur. Naturally, the voltage fluctuation remains in the terminal potential waveform in which the armature winding resistance drop is corrected. Therefore, the logic signals 2a, 2b and 2c obtained by comparing the terminal potentials contain spike-like noise as shown in FIG.
[0125]
This logic signal is first input to the latch circuit 180. The latch circuit 180 is a circuit that performs a latch operation according to the state of the enable terminal 180a, and outputs the input data as it is when the enable terminal 180a is at a high level. When the enable terminal 180a becomes low level, input data is latched, and while the enable terminal 180a is low level, the latched data is continuously output. In the initial state, the enable terminal 180a of the latch circuit 180 is at a high level, and the logic signals 2a, 2b, and 2c are input to the D flip-flops 181, 183, and 185 as they are. The D flip-flops 181 to 186 and the EOR circuits 187 to 189 constitute a double edge differentiating circuit, and the EOR circuits 187 to 189 output differential pulses at the timings of rising and falling edges of the logic signals 2a, 2b and 2c. . At time T2, when the corrected terminal potentials 1a and 1c coincide with each other and the polarity of 2a changes, an edge is detected by the two-edge differentiating circuit and a differential pulse 203 is generated. The output signals of the EOR circuits 187 to 189 are combined by the OR circuit 190 to become a logic pulse signal 201 and input to the monostable multivibrator 191. The monostable multivibrator 191 uses the rising edge of the logic pulse signal 201 as a trigger, and outputs a low-level pulse 204 for a fixed time T3. The pulse 204 is input to the enable terminal 180a of the latch circuit. Since the enable terminal 180a becomes the low level, the latch circuit 180 latches the logic signals 2a, 2b, and 2c, and continues to output the latched data while the pulse 204 is at the low level. Output signals 195, 196, and 197 of the D flip-flops 182, 184, and 186 become rotor-shaped rotor position signals 3a, 3b, and 3c, which are input to the next-stage commutation circuit 9 to perform a commutation operation. When the commutation operation is performed, since the driving transistor is switched, a spike-like voltage fluctuation occurs in the U-phase terminal potential waveform, and as a result, a spike-like noise 205 is generated in 2b at an undesired position. However, when spike noise 205 is generated, data input to the latch circuit is disabled by the pulse 204 from the monostable multivibrator 191. Accordingly, the spike noise 205 is masked by the latch circuit 180, and no spike noise is generated in the waveform-shaped rotor position signals 3a, 3b, and 3c.
[0126]
In the waveform shaping circuit 3 described above, the logic pulse signal 201 output from the OR circuit 190 is a signal obtained at regular time intervals during steady rotation. Therefore, this logic pulse signal 201 can be used as a speed signal for controlling the rotation speed.
In this embodiment, an example of a three-phase brushless motor has been described. However, the present invention is not limited to three phases and can be applied to general brushless motors having a plurality of phases.
[0127]
Example 8 FIG.
Next, the configuration and operation of a device that is stably activated in a short time without being affected by the load at the start will be described.
That is, at the time of start-up, driving is started so that a possible combination of signals can be obtained from the detection voltage for each phase. Specifically, the rotor position signal is detected from each phase winding potential of the brushless motor, and the required edge signal is obtained by detecting and selecting the rising and falling edges of this rotor position signal. The edge signal was counted and used as an applied drive signal for the armature winding of each phase at startup. Furthermore, when this input cannot be obtained for a certain time, an applied drive signal is forcibly given.
FIG. 20 shows an overall configuration diagram of an embodiment of a driving device for a three-phase brushless motor based on the above idea. 9 is a commutation circuit that outputs drive signals 9a, 9b, 9c, 9d, 9e, and 9f, 11 is a bridge circuit that energizes a predetermined phase of the brushless motor, and 4 is a position signal 3a, 3b, from each terminal potential of the brushless motor. A rotor position signal generating circuit 7 for generating 3c; a counter circuit 7 for detecting and selecting rising and falling edges of the position signals 3a, 3b and 3c to obtain a necessary edge signal and counting the necessary edge signal; 6 Represents a pulse generation circuit for outputting a pseudo pulse 6a.
[0128]
This will be described in detail below. The motor rotation signal 5a is a signal input from the outside, and indicates rotation when enabled, and stop when disabled. In this embodiment, enable is high and disable is low.
[0129]
In FIG. 20, the motor rotation signal 5 a is connected to the commutation circuit 9 and the counter circuit 7. Drive signals 9a, 9b, 9c, 9d, 9e, and 9f output from the commutation circuit 9 are connected to the bases of the transistors TR1, TR2, TR3, TR4, TR5, and TR6, respectively. In this embodiment, the transistors TR1, TR2, and TR3 are pnp transistors, and the transistors TR4, TR5, and TR6 are npn transistors. The emitters of the transistors TR1, TR2, and TR3 are connected to the power source, the collectors are connected to the collectors of the transistors TR4, TR5, and TR6, and the emitters of the transistors TR4, TR5, and TR6 are grounded through the resistor 10. These transistor groups constitute a bridge circuit 11. The collectors of the transistors TR1, TR2, TR3, TR4, TR5, TR6 are connected to the terminals of the U-phase, V-phase, and W-phase armature windings of the three-phase brushless motor that are star-connected. Therefore, each armature winding is energized by turning on and off each transistor. FIG. 21 shows a relationship table between the drive signals 9a, 9b, 9c, 9d, 9e, 9f and the energized phases in the present embodiment. FIG. 21 is a table of FIG. When the energized phases are switched in the order of the arrows in FIG. 21, the rotor rotates normally.
[0130]
The terminal of each armature winding connected to the bridge circuit 11 is also connected to the rotor position signal generation circuit 4. The rotor position signal generation circuit 4 generates 3-bit position signals 3a, 3b, and 3c from U-phase, V-phase, and W-phase terminal voltages U, V, and W. FIG. 22 shows an example of the logical relationship between the drive signals 9a, 9b, 9c, 9d, 9e, 9f and the position signals 3a, 3b, 3c in this embodiment. The position signals 3 a, 3 b, 3 c output from the rotor position signal generation circuit 4 are input to the counter circuit 7.
[0131]
FIG. 23 shows a configuration diagram of the counter circuit 7 of this embodiment. The position signals 3a, 3b, and 3c are respectively input to the rising edge detection circuits 250, 252, and 254 and the falling edge detection circuits 251, 253, and 255. The rising edge detection circuits 250, 252, and 254 cause the rising edge pulse 250a, The falling edge detection circuits 252a and 254a output the falling edge pulses 251a, 253a, and 255a. The detected edge pulses 250a, 252a, 254a, 251a, 253a, and 255a are input to the pulse selection circuit 256. A pseudo pulse 6 a output from the pulse generation circuit 6 shown in FIG. 20 is also input to the pulse selection circuit 256. The pulse train 7d, which is the output of the pulse selection circuit 256, is input to the counter. In this embodiment, a hex counter 257 is used as a counter for counting the pulse train 7d. An example of the logical relationship between the number of pulses input to the hex counter 257 used in this embodiment and the output value is shown in FIG. In the figure, when the number of input pulses is 6 or more, the counter values 7a, 7b, and 7c are counted again from low, low, and low. The pulse train 7d is also input to the pulse generation circuit 6 in FIG. Counter values 7a, 7b, and 7c output from the hexadecimal counter 257 are input to the pulse selection circuit 256 in the counter circuit 7 and the commutation circuit 9 in FIG. The pulse selection circuit 256 refers to the current counter values 7a, 7b and 7c, and outputs an edge pulse or pseudo pulse 6a of a theoretical position signal to be detected next during forward rotation. FIG. 25 shows an example of the logical relationship between the counter values 7a, 7b, and 7c in this embodiment and the theoretical edge pulses 250a, 252a, 254a, 251a, 253a, and 255a to be detected next during normal rotation. From FIG. 25, for example, when the counter values 7a, 7b, and 7c are low, low, and low, the edge pulse 253a is output, and even if another edge pulse 250a is input, it is not output. However, when the pseudo pulse 6a is input, it is output regardless of the counter values 7a, 7b and 7c.
[0132]
FIG. 26 shows a configuration diagram of the pulse generation circuit 6 of the present embodiment. In this embodiment, the pulse generation circuit 6 is composed of a retriggerable one-shot 260 and a rising edge detection circuit 261. The retriggerable one-shot 260 receives the pulse train 7d output from the pulse selection circuit 256. The output 260 a of the retriggerable one-shot 260 is input to the rising edge detection circuit 261, and the rising edge of the output 260 a of the retriggerable one-shot 260 is the same as the rising edge detection circuits 250, 252 and 254 provided in the counter circuit 7. Is detected and a pseudo pulse 6a is output. In such a configuration, when the pulse of the pulse train 7d is input within the time set in the retriggerable one-shot 260, the retriggerable one-shot 260 is cleared and the output 260a does not change, so the pseudo pulse 6a Is not output. However, if the pulse train 7d is not input within the set time, the output 260a of the retriggerable one-shot 260 changes from low to high, so that the rising edge is detected and the pseudo pulse 6a is output.
[0133]
In this embodiment, the output 260a is low when the retriggerable one-shot 260 is cleared, and changes to high when the pulse train 7d is not input within a predetermined time. When the retriggerable one-shot 260 is cleared, the output 260a is high, and when the pulse train 7d is not input within a predetermined time, the same pseudo pulse 6a can be obtained even if the pulse train 7d changes to low.
[0134]
When the motor rotation signal 5a is low, the commutation circuit 9 sets the drive signals 9a, 9b, and 9c to high and sets the drive signals 9d, 9e, and 9f to low and turns off the transistor group of the bridge circuit 11. Turn off the brushless motor. Next, in the start-up mode immediately after the motor rotation signal 5a becomes high, the drive signals 9a, 9b, 9c, 9d, 9e, and 9f are set so that the rotor rotates normally by the combination of the counter values 7a, 7b, and 7c. Output. FIG. 27 shows a logical relationship combination example of the drive signals 9a, 9b, 9c, 9d, 9e, 9f and the counter circuit 7 output values 7a, 7b, 7c set in this embodiment. If the drive signals 9a, 9b, 9c, 9d, 9e, 9f are switched in the direction of the arrow in the figure, the rotor rotates normally.
[0135]
Next, the operation of the brushless motor in this embodiment will be described. Immediately after the motor rotation signal 5a becomes high, the counter values 7a, 7b, 7c become low, low, low, so that the drive signal 9b becomes low and 9f becomes high as shown in FIG. W phase is energized. At this time, the position signal may change when the rotor of the brushless motor rotates forward, the position signal changes due to reverse rotation, or the position signal does not change after stopping at the energization stable point.
[0136]
First, a case where the rotor rotates normally will be described. FIG. 28 is an example of signal waveforms at various parts when the rotor rotates normally. When the V-W phase is energized, the position signals 3a, 3b and 3c become high, high and low as shown in FIGS. At this time, since the counter values 7a, 7b, and 7c are low, low, and low, the hexadecimal counter 257 does not count unless the edge pulse 253a or the pseudo pulse 6a is detected from FIG. When the rotor further rotates in the forward direction due to the inertia, the terminal voltages U, V, and W are changed by the back electromotive force generated in the armature winding, and the position signals 3a, 3b, and 3c are high, low, low. Then, the edge pulse 253a is detected as shown in FIG. Accordingly, the hex counter 257 counts up, and the counter values 7a, 7b, 7c become high, low, low, and the commutation circuit 9 drives the U-W phase from FIG. 21 and FIG. 9a, 9b, 9c, 9d, 9e, and 9f are set to low high high low low low high. Thereafter, the brushless motor is started by sequentially switching the energized phases according to the relationship shown in FIG. 27 with reference to the combination of the counter values 7a, 7b, and 7c until the rotation is steady.
[0137]
Next, the case where the position signal is changed by the reverse rotation of the rotor will be described with reference to FIG. FIG. 29 shows examples of signal waveforms at various parts when the rotor is reversed. When the rotor reverses, the position signal 3a changes, and the edge pulse 251a shown in FIG. 29B is detected. However, since the edge pulse 253a is not detected as described above, the hex counter 257 counts. Do not up. And the predetermined time t₁Since the edge pulse 253a cannot be detected within the period, a pseudo pulse 6a is output from the pulse generation circuit 6 as shown in (C) of FIG. The hex counter 257 counts up with the pseudo pulse 6a, and the counter values 7a, 7b, and 7c change to high, low, and low. Then, the drive signals 9a, 9b, 9c, 9d, 9e, and 9f are set to low high high low low low high so that the U-W phase is energized in the commutation circuit 9 from FIG. 21 and FIG. . As a result, the rotor rotates normally, and thereafter the energized phases are sequentially switched according to the relationship shown in FIG. 27 with reference to the combination of the counter values 7a, 7b, 7c until the rotor rotates normally as in the case of the normal rotation. It is activated.
[0138]
Further, when the rotor does not move and the position signal does not change, the predetermined time t₁Since the edge pulse 253a cannot be detected within the range, the pseudo pulse 6a is output from the pulse generation circuit 6. Then, as in the case of reverse rotation, the hex counter 257 counts the pseudo pulse 6a, the energized phase is switched to the U-W phase from FIGS. 21 and 27, and then the counter values 7a, 7b, 7c until it rotates normally. The brushless motor is started by sequentially switching energized phases according to the relationship shown in FIG.
[0139]
Example 9
Next, the configuration and operation of an apparatus that stably restarts in a short time even when the motor stops for some reason during operation and restart is necessary will be described.
Specifically, when restarting, the rotor position signal is detected from the phase winding potential of the brushless motor, and the required edge signal is obtained by detecting and selecting the rising and falling edges of this rotor position signal. Further, a stationary rotation detection circuit for monitoring the rotation of the motor in combination with this signal is provided. When an abnormality was detected, the edge signal was counted and used as a forced application drive signal for the armature winding of each phase at the time of restart.
FIG. 30 shows an overall configuration diagram of a ninth embodiment of the driving device for a three-phase brushless motor based on the above-described idea. Since the bridge circuit 11, the rotor position signal generation circuit 4, the counter circuit 7, and the pulse generation circuit 6 are the same as those in the eighth embodiment, description thereof is omitted. Reference numeral 265 denotes a steady rotation detection circuit that compares the counter values 7a, 7b, and 7c with the position signals 3a, 3b, and 3c.
[0140]
In this embodiment, the position signals 3a, 3b and 3c are also input to the commutation circuit 9. The commutation circuit 9 outputs drive signals 9a, 9b, 9c, 9d, 9e, and 9f in a combination of the counter values 7a, 7b, and 7c in the start-up mode in the same manner as in the eighth embodiment. Drive signals 9a, 9b, 9c, 9d, 9e, and 9f are output by a combination of the signals 3a, 3b, and 3c. The position signals 3a, 3b, 3c and the counter values 7a, 7b, 7c are also input to the steady rotation detection circuit 265. The steady rotation detection circuit 265 compares the position signals 3a, 3b, and 3c with the counter values 7a, 7b, and 7c after a predetermined time after the counter value is changed during steady rotation. FIG. 31 shows an example of a theoretical logical relationship combination of the position signals 3a, 3b and 3c and the counter values 7a, 7b and 7c in this embodiment. If the combination is not the combination shown in FIG. 31, a restart pulse 265a is output. The restart pulse 265a is input to the commutation circuit 9.
[0141]
In such a configuration, an example in which the rotor is stopped by some load during steady rotation will be described with reference to FIG. In FIG. 32, it is assumed that the rotor is stopped after (D). In this case, the time t set in the pulse generation circuit 6 from the pulse (o1).₁After the elapse, a pseudo pulse (p2) is output from the pulse generation circuit 6. The pseudo pulse (p2) is output from the pulse selection circuit 256 as the pulse (o2) of the pulse train 7d, and the counter values 7a, 7b, and 7c are changed from low to high to low to low to high from the logical relationship example of FIG. To change. As described above, during the steady rotation, the drive signals 9a, 9b, 9c, 9d, 9e, and 9f are output by the combination of the position signals 3a, 3b, and 3c, so that the counter values 7a, 7b, and 7c change. However, the energized phase is not switched. Then, a predetermined time t after the counter values 7a, 7b, 7c change₂Thereafter, the steady rotation detection circuit 265 compares the position signals 3a, 3b, and 3c with the counter values 7a, 7b, and 7c. In this case, since it is not a theoretical combination from FIG. 31, a restart pulse (q3) is output from the steady rotation detection circuit 265, and the operation mode is shifted to the start mode. In the start mode, as described above, the start signals 9a, 9b, 9c, 9d, 9e, and 9f are output by the combination of the counter values 7a, 7b, and 7c. 9e and 9f become high, high, low, low, high, low and energization is switched to perform normal rotation. Thereafter, as described in the eighth embodiment, the energization is sequentially switched according to the combination of the counter values 7a, 7b, and 7c according to the relationship shown in FIG.
[0142]
Example 10
Next, a motor drive circuit provided with a switching device for switching from startup or restart to steady operation will be described.
In this embodiment, this switching is set as a time setting, and after a certain time, switching to a steady operation is performed.
FIG. 33 shows an overall configuration diagram of Embodiment 10 of the three-phase brushless motor driving apparatus according to the present invention. The bridge circuit 11, the rotor position signal generation circuit 4, the counter circuit 7, the pulse generation circuit 6, and the steady rotation detection circuit 265 are the same as those in the eighth and ninth embodiments. 8 switches between referring to the counter values 7a, 7b, 7c and the position signals 3a, 3b, 3c when the commutation circuit 9 outputs the drive signals 9a, 9b, 9c, 9d, 9e, 9f. This is a switching signal generation circuit that outputs a switching signal 8a. Hereinafter, the switching signal generation circuit 8 will be described.
[0143]
In the present embodiment, the motor rotation signal 5 a and the restart pulse 265 a are input to the switching signal generation circuit 8. The switching signal 8a is input to the commutation circuit 9.
FIG. 34 shows a configuration diagram of the switching signal generation circuit 8 of the present embodiment. In this embodiment, the switching signal generating circuit 8 is constituted by a timer 270.
[0144]
Next, the operation of the switching signal generating circuit 8 of this embodiment will be described with reference to FIG. In this embodiment, when the motor rotation signal 5a input to the timer 270 becomes high, the timer 270 is turned on, and the commutation circuit 9 is driven by the combination of the counter values 7a, 7b, 7c according to the relationship shown in FIG. 9b, 9c, 9d, 9e, 9f are output. And the predetermined time t₀After the lapse of time, the switching signal 8a changes from low to high, and the commutation circuit 9 uses the combination of the position signals 3a, 3b and 3c to drive the signals 9a, 9b, 9c, 9d, 9e and 9f as shown in FIG. Is output.
[0145]
Further, when the commutation circuit 9 outputs the drive signals 9a, 9b, 9c, 9d, 9e, and 9f by the combination of the position signals 3a, 3b, and 3c, the restart pulse 265a output from the steady rotation detection circuit 265 is input. Then, the timer 270 is reset and the switching signal 8a changes from high to low. Thereby, the commutation circuit 9 outputs the drive signals 9a, 9b, 9c, 9d, 9e, and 9f using the counter values 7a, 7b, and 7c. And again for a predetermined time t₀Later, the switching signal 8a changes from low to high, and the commutation circuit 9 uses the combination of the position signals 3a, 3b, and 3c to generate drive signals 9a, 9b, 9c, 9d, 9e, and 9f as shown in FIG. Output.
[0146]
In this embodiment, the switching signal 8a is set to low when referring to the counter values 7a, 7b, and 7c, and set to high when referring to the position signals 3a, 3b, and 3c.
[0147]
Example 11
In this embodiment, the counter is switched to the steady operation after counting a certain value during the switching operation. By doing so, the motor can be rotated reliably.
FIG. 36 is an overall configuration diagram of an eleventh embodiment of the three-phase brushless motor driving apparatus according to the present invention. When the commutation circuit 9 outputs the drive signals 9a, 9b, 9c, 9d, 9e, and 9f, 8C switches between the reference values 7a, 7b, and 7c and the position signals 3a, 3b, and 3c. This is a switching signal generation circuit that outputs a switching signal 8a. Hereinafter, the switching signal generation circuit 8C will be described.
[0148]
In this embodiment, the pulse train 7d, the motor rotation signal 5a, and the restart pulse 265a are input to the switching signal generation circuit 8C. The switching signal 8a is input to the commutation circuit 9.
FIG. 37 shows a configuration diagram of the switching signal generation circuit 8C of the present embodiment. In this embodiment, the switching signal generating circuit 8C is constituted by a mode switching counter 271.
[0149]
Next, the operation of the switching signal generating circuit 8C of this embodiment will be described with reference to FIG. When the motor rotation signal 5a becomes high, the mode switching counter 271 starts counting the pulse train 7d, and the commutation circuit 9 is driven by the combination of the counter values 7a, 7b, 7c according to the relationship shown in FIG. 9c, 9d, 9e, 9f are output. When the mode switching counter 271 counts the pulse train 7d X a predetermined number of times, the switching signal 8a changes from low to high, and the commutation circuit 9 is driven by a combination of position signals 3a, 3b and 3c as shown in FIG. Signals 9a, 9b, 9c, 9d, 9e, and 9f are output.
[0150]
Further, when the commutation circuit 9 outputs the drive signals 9a, 9b, 9c, 9d, 9e, and 9f by the combination of the position signals 3a, 3b, and 3c, the restart pulse 265a output from the steady rotation detection circuit 265 is input. Then, the mode switching counter 271 is reset and the switching signal 8a changes from high to low. Thereby, commutation circuit 9 outputs drive signals 9a, 9b, 9c, 9d, 9e, and 9f using counter values 7a, 7b, and 7c in accordance with the relationship shown in FIG. The mode switching counter 271 starts counting the pulse train 7d again. When the mode switching counter 271 counts the predetermined number of times X, the switching signal 8a changes from low to high, and the commutation circuit 9 combines the position signals 3a, 3b, and 3c. As shown in FIG. 22, drive signals 9a, 9b, 9c, 9d, 9e, 9f are output.
[0151]
Example 12
In this embodiment, switching is performed by a combination of time and position signal detection, that is, a method of switching when both conditions are satisfied.
FIG. 39 shows the overall configuration of a twelfth embodiment of the three-phase brushless motor driving apparatus according to the present invention. 8D is a switching signal generating circuit for outputting a switching signal 8a for switching which of the counter values 7a, 7b, 7c and the position signals 3a, 3b, 3c is to be referred to. Hereinafter, the switching signal generation circuit 8D will be described.
In this embodiment, the motor rotation signal 5a, the restart pulse 265a, and the position signals 3a, 3b, and 3c are input to the switching signal generation circuit 8D. The switching signal 8a is input to the commutation circuit 9.
[0152]
FIG. 40 shows a configuration diagram of the switching signal generation circuit 8D of the present embodiment. In this embodiment, the switching signal generation circuit 8D is constituted by a position signal combination determination circuit 272 and a timer 270. The timer 270 has the same configuration as that of the tenth embodiment. The position signal combination determination circuit 272 receives position signals 3a, 3b, and 3c, and when the position signals 3a, 3b, and 3c are in a predetermined combination, the output is high. In this embodiment, when the position signals 3a, 3b and 3c are a combination of high, low and low, they change to high. The outputs of the position signal combination determination circuit 272 and the timer 270 are input to the AND circuit 273, and the AND circuit output 273a, the motor rotation signal 5a, and the restart pulse 265a are input to the latch circuit 274. The latch circuit 274 is cleared by the motor rotation signal 5a and the restart pulse 265a, and once the input signal goes high, the output is held high until the input signal is cleared.
[0153]
Next, the operation of the switching signal generation circuit 8D of this embodiment will be described with reference to FIG. When the motor rotation signal 5a becomes high, the timer 270 is turned on, and the commutation circuit 9 outputs the drive signals 9a, 9b, 9c, 9d, 9e, 9f according to the combination of the counter values 7a, 7b, 7c according to the relationship shown in FIG. Output. And the predetermined time t₀After the elapse, the timer output 270a changes to high. When the timer output 270a is high and the position signals 3a, 3b, 3c are a combination of high / low / low, the AND circuit output 273a changes to high. The latch circuit 274 operates at the rising edge of the first AND circuit output 273a after the motor rotation signal 5a changes to high, and the switching signal 8a is held high. Thereby, the commutation circuit 9 outputs drive signals 9a, 9b, 9c, 9d, 9e, and 9f by a combination of the position signals 3a, 3b, and 3c as shown in FIG.
[0154]
When the commutation circuit 9 outputs the drive signals 9a, 9b, 9c, 9d, 9e, and 9f by the combination of the position signals 3a, 3b, and 3c, when the restart pulse 265a is input, the timer 270 The latch circuit 274 is reset, and the switching signal 8a changes from high to low. Thereby, the commutation circuit 9 outputs drive signals 9a, 9b, 9c, 9d, 9e, and 9f using the counter values 7a, 7b, and 7c. Then, as described above, the predetermined time t₀Later, when the position signals 3a, 3b, and 3c become a combination of high, low, and low, the switching signal 8a changes from low to high, and the commutation circuit 9 again changes the combination of the position signals 3a, 3b, and 3c. Drive signals 9a, 9b, 9c, 9d, 9e, and 9f are used.
[0155]
Example 13
In this embodiment, the switching is performed by obtaining both that the counter has reached a constant value and that the position signal has been detected normally.
FIG. 42 shows an overall configuration diagram of Embodiment 13 of the three-phase brushless motor drive device according to the present invention. Hereinafter, the switching signal generating circuit 8E of the present embodiment will be described.
In this embodiment, the position signals 3a, 3b, 3c, the pulse train 7d, the motor rotation signal 5a, and the restart pulse 265a are input to the switching signal generating circuit 8E. The switching signal 8a is input to the commutation circuit 9.
[0156]
FIG. 43 shows a configuration diagram of the switching signal generation circuit 8E of the present embodiment. The switching signal generation circuit 8E of this embodiment is configured by the position signal combination determination circuit 272 and the mode switching counter 271 described in the previous embodiment.
Next, the operation of the switching signal generation circuit 8E of this embodiment will be described with reference to FIG. When the motor rotation signal 5a becomes high, the mode switching counter 271 starts counting the pulse train 7d, and the commutation circuit 9 uses the combination of the counter values 7a, 7b, 7c according to the relationship shown in FIG. 27 to drive signals 9a, 9b, 9c. , 9d, 9e, 9f are output. When the predetermined number of times is counted X times, the output 271a of the mode switching counter 271 becomes high, the position signal becomes a predetermined high / low / low combination, and the output 273a of the AND circuit 273 becomes high. The latch circuit 274 operates at the rising edge of the first AND circuit output 273a after the motor rotation signal 5a changes to high, and the switching signal 8a changes from low to high and is held high. Thus, the commutation circuit 9 outputs the drive signals 9a, 9b, 9c, 9d, 9e, and 9f by the combination of the position signals 3a, 3b, and 3c.
[0157]
When the commutation circuit 9 outputs the drive signals 9a, 9b, 9c, 9d, 9e, 9f by the combination of the position signals 3a, 3b, 3c, when the restart pulse 265a is input, the mode switching counter 271 and the latch circuit 274 are reset, the switching signal 8a changes from high to low, and the commutation circuit 9 outputs a drive signal using a combination of the counter values 7a, 7b, and 7c.
When the mode switching counter 271 counts the pulse train 7d a predetermined number of times X and the position signal becomes a predetermined high / low / low combination, the switching signal 8a changes from low to high, and again the position signals 3a, 3b The drive signals 9a, 9b, 9c, 9d, 9e, and 9f are output using the combination of 3c.
[0158]
Example 14
In this embodiment, the switching is performed by satisfying that the drive signal is normal after the set time has elapsed.
FIG. 45 shows an overall configuration diagram of a four-phase brushless motor driving apparatus according to a fourteenth embodiment of the present invention. Hereinafter, the switching signal generation circuit 8F of the present embodiment will be described.
In this embodiment, the drive signals 9a, 9b, 9c, 9d, 9e, 9f, the motor rotation signal 5a, and the restart pulse 265a are input to the switching signal generation circuit 8F.
[0159]
FIG. 46 shows a configuration diagram of the switching signal generation circuit 8F of the present embodiment. The switching signal generation circuit 8F of this embodiment is constituted by a drive signal combination determination circuit 275 and the timer 270 described above. Drive signals 9a, 9b, 9c, 9d, 9e, and 9f are input to the drive signal combination determination circuit 275. The drive signal combination determination circuit 275 has a configuration in which the output 275a becomes high when the drive signals 9a, 9b, 9c, 9d, 9e, and 9f have a predetermined combination. In this embodiment, the output 275a becomes high when the drive signals 9a, 9b, 9c, 9d, 9e, 9f are a combination of low, high, high, low, high, and low. The outputs of the drive signal combination determination circuit 275 and the timer 270 are input to the AND circuit 273, and the AND circuit output 273a, the motor rotation signal 5a, and the restart pulse 265a are input to the latch circuit 274 described in the previous embodiment. The
[0160]
FIG. 47 is an explanatory diagram of the operation of the switching signal generation circuit 8F of this embodiment. When the motor rotation signal 5a becomes high, the timer 270 is turned on, and the commutation circuit 9 outputs a drive signal using a combination of counter values. And the predetermined time t₀After the elapse of time, when the timer output 270a changes to high and the drive signals 9a, 9b, 9c, 9d, 9e, 9f become a combination of low high high low low high low, the output 273a of the AND circuit 273 Changes to high. After that, the commutation circuit 9 outputs drive signals 9a, 9b, 9c, 9d, 9e, 9f again using a combination of the position signals 3a, 3b, 3c. .
Also, as shown in FIG. 47, the operation when the restart pulse 265a is input is the same as described in the previous embodiment, and the commutation circuit 9 is t₀Later, drive signals 9a, 9b, 9c, 9d, 9e, and 9f are output again using a combination of position signals 3a, 3b, and 3c.
[0161]
Example 15.
In this embodiment, the switching is performed under a condition that satisfies both that the drive signal becomes normal after the counter has counted a certain value.
FIG. 48 shows an overall configuration diagram of a fifteenth embodiment of a three-phase brushless motor driving apparatus according to the present invention. Hereinafter, the switching signal generation circuit 8G of the present embodiment will be described.
In this embodiment, the drive signals 9a, 9b, 9c, 9d, 9e, 9f, the pulse train 7d, the motor rotation signal 5a, and the restart pulse 265a are input to the switching signal generation circuit 8G.
[0162]
FIG. 49 shows a configuration diagram of the switching signal generation circuit 8G of the present embodiment. The switching signal generation circuit 8G of this embodiment is configured by a drive signal combination determination circuit 275 and a mode switching counter 271.
FIG. 50 is a diagram for explaining the operation of the switching signal generation circuit 8G of the present embodiment. Since the operations at the time of starting and at the time of restarting are the same as those of the embodiments described so far, the description thereof is omitted.
[0163]
Example 16
In this embodiment, an example in which switching is performed by speed detection will be described.
FIG. 51 is an overall configuration diagram of Embodiment 16 of the three-phase brushless motor driving apparatus according to the present invention. Hereinafter, the switching signal generation circuit 8H of the present embodiment will be described.
In this embodiment, a logic pulse 201, a motor rotation signal 5a, and a restart pulse 265a output from the waveform shaping circuit 3 in the rotor position signal generation circuit 4 are input to the switching signal generation circuit 8H.
[0164]
FIG. 52 shows a configuration diagram of the switching signal generation circuit 8H of the present embodiment. The switching signal generation circuit 8H according to the present embodiment includes a speed signal generation circuit 277, a reference speed generation circuit 276, and a comparison circuit 278. The logic pulses 201 and CLK are input to the speed signal generation circuit 277. As described in the first embodiment or the seventh embodiment, since the logic pulse 201 is a signal obtained at a certain time interval, the rotation speed of the brushless motor can be detected from the logic pulse 201.
FIG. 53 shows a timing chart of the method for generating the speed signal 277a. The speed signal generation circuit 277 counts up at the edge timing of the CLK when the motor rotation signal 5a is high, and is cleared at the timing of the rising edge of the logic pulse input from the waveform shaping circuit 3, and the value indicated by the arrow in the figure. Is output as the speed signal 277a. The reference speed generation circuit 276 outputs a reference speed signal 276a for switching from the start mode to the steady rotation mode. The comparison circuit 278 compares the speed signal 277a and the reference speed signal 276a with, for example, the voltage level and the number of bits at the timing of the rising edge of the logic pulse, and outputs the switching signal 8a when the speed signal 277a reaches the reference speed signal 276a. To do.
[0165]
Next, the operation of the switching signal generation circuit 8H of this embodiment will be described with reference to FIG. When the motor rotation signal 5a becomes high at startup, the comparison circuit 278 starts comparing the speed signal 277a with the reference speed signal 276a. When the speed signal 277a reaches the reference speed signal 276a, the switching signal 8a output from the comparison circuit 278 changes to high.
When the restart pulse 265a is input, the comparison circuit 278 is reset and the switching signal 8a changes from high to low.
When the speed signal 277a reaches the reference speed signal 276a, the switching signal 8a changes from low to high again.
[0166]
Example 17.
In this embodiment, the switching is performed under the condition that satisfies the three conditions of time setting, counter value, and normal detection of the position signal at the same time.
FIG. 55 is an overall configuration diagram of Embodiment 17 of the three-phase brushless motor driving apparatus according to the present invention. Hereinafter, the switching signal generating circuit 8I of this embodiment will be described.
In this embodiment, the counter values 7a, 7b, 7c, the position signals 3a, 3b, 3c, the motor rotation signal 5a, and the restart pulse 265a are input to the switching signal generating circuit 8I.
[0167]
FIG. 56 shows a configuration diagram of the switching signal generation circuit 8I of this embodiment. The switching signal generation circuit 8I of this embodiment is configured by a position signal counter value determination circuit 280 and a timer 270.
FIG. 57 is a diagram for explaining the operation of the switching signal generation circuit 8I of the present embodiment. Since the operation based on this figure is the same as that already described in the above embodiment, the description is omitted.
[0168]
Example 18
In this embodiment, the switching is performed by satisfying both the speed detection and the normal detection of the position signal.
FIG. 58 shows an overall configuration diagram of Embodiment 18 of the three-phase brushless motor driving apparatus according to the present invention. Hereinafter, the switching signal generating circuit 8J of the present embodiment will be described.
[0169]
FIG. 59 shows a configuration diagram of the switching signal generation circuit 8J of the present embodiment. The switching signal generation circuit 8J of the present embodiment includes a reference speed generation circuit 276, a speed signal generation circuit 277, a comparison circuit 278, and a position signal combination determination circuit 272.
Next, FIG. 60 is a diagram for explaining the operation of the switching signal generating circuit 8J of the present embodiment. Since the operation based on this figure is the same as that already described in the above embodiment, the description thereof will be omitted.
[0170]
Example 19.
In this embodiment, switching is performed by the logical product of speed detection and normal detection of the drive signal.
FIG. 61 shows an overall configuration diagram of Embodiment 19 of the three-phase brushless motor driving apparatus according to the present invention. Hereinafter, the switching signal generation circuit 8K of the present embodiment will be described.
[0171]
FIG. 62 shows a configuration diagram of the switching signal generation circuit 8K of the present embodiment. The switching signal generation circuit 8K of the present embodiment includes a reference speed generation circuit 276, a speed signal generation circuit 277, a comparison circuit 278, and a drive signal combination determination circuit 275.
FIG. 63 is a diagram for explaining the operation of the switching signal generating circuit 8K of the present embodiment. Since the operation based on this figure is the same as that of the above-described embodiment, the description thereof will be omitted.
[0172]
Example 20.
In this embodiment, switching is performed by three logical products of speed detection, position signal normal detection, and counter value.
FIG. 64 shows an overall configuration diagram of a twentieth embodiment of a three-phase brushless motor drive apparatus according to the present invention. Hereinafter, the switching signal generation circuit 8L of the present embodiment will be described.
[0173]
FIG. 65 shows a configuration diagram of the switching signal generation circuit 8L of the present embodiment. The switching signal generation circuit 8L of the present embodiment includes a reference speed generation circuit 276, a speed signal generation circuit 277, a comparison circuit 278, and a position signal counter value determination circuit 280.
FIG. 66 is a diagram for explaining the operation of the switching signal generation circuit 8L of the present embodiment. Since the operation based on this figure is the same as that of the above-described embodiment, the description thereof will be omitted.
[0174]
Example 21.
In the present embodiment, an example will be described in which the steady rotation detection circuit at the time of restart is not provided independently, and the forced start mode is set by a pseudo pulse from a pulse generation circuit or the like at the time of restart.
FIG. 67 is an overall configuration diagram of a twenty-first embodiment of the three-phase brushless motor driving apparatus according to the present invention.
In this embodiment, the position signals 3a, 3b, 3c, the counter values 7a, 7b, 7c and the pseudo pulse 6a output from the pulse generation circuit 6 are input to the commutation circuit 9. The commutation circuit 9 is reset by the pseudo pulse 6a and is shifted to the start mode.
[0175]
In the configuration as described above, when the rotor is stopped by some load during steady rotation, the pseudo pulse 6 a is output from the pulse generation circuit 6, and the pseudo pulse 6 a is input to the commutation circuit 9. The commutation circuit 9 is reset by the pseudo pulse 6a and shifts to the start mode. Therefore, the drive signals 9a, 9b, 9c, 9d, 9e, and 9f are output by the combination of the counter values 7a, 7b, and 7c until the rotation is steady.
[0176]
Example 22.
In this embodiment, an independent position detection element different from the winding voltage detection is used, and by combining this signal and the position detection based on the winding voltage, a drive signal in the correct direction is surely obtained. did.
FIG. 68 shows an overall configuration diagram of a twenty-second embodiment of the three-phase brushless motor drive apparatus according to the present invention. Reference numeral 300 denotes a position detector that detects the position of the rotor and outputs a pulsed position signal 300a. Reference numeral 301 denotes a hold circuit that holds the output from the rising edge of the input signal.
In FIG. 68, the position signal 300 a is input to the hold circuit 301. In this embodiment, the position signal 300a is shifted from the position signal 3b by an electrical angle π / 6 as shown in FIG. Further, each energization stable point of the brushless motor is at the position of the broken line in the figure, and coincides with the position of the rising edge and the falling edge of the position signal 300a.
[0177]
The hold circuit 301 in FIG. 68 holds the value of the position signal 300a immediately after the motor rotation signal 5a becomes high until the motor rotation signal 5a becomes low. For example, when the position signal 300a immediately after the motor rotation signal 5a becomes high, the hold circuit output 301a is held high until the motor rotation signal 5a becomes low. The output 301a of the hold circuit 301 is input to the commutation circuit 9 and the pulse selection circuit 256 in the counter circuit 7 shown in FIG.
The commutation circuit 9 is configured to output drive signals 9a, 9b, 9c, 9d, 9e, and 9f with reference to the hold circuit output value 301a and the counter values 7a, 7b, and 7c. FIG. 70 shows a logical relationship example of the hold circuit output 301a, the counter values 7a, 7b, and 7c and the drive signals 9a, 9b, 9c, 9d, 9e, and 9f in the present embodiment.
[0178]
FIG. 71 shows the configuration of the counter circuit 7 in this embodiment. The rising edge detection circuits 250, 252, and 254, the falling edge detection circuits 251, 253, and 255 and the hex counter 257 are the same as those in the above embodiment.
The pulse selection circuit 256 receives the rising edge pulses 250a, 252a, and 254a of the position signals 3a, 3b, and 3c, the falling edge pulses 251a, 253a, and 255a, the pseudo pulse 6a, and the hold circuit output 301a. The pulse selection circuit 256 outputs a theoretical position signal edge pulse or pseudo pulse 6a to be detected next during forward rotation with reference to the current counter values 7a, 7b and 7c and the hold circuit output 301a. It is. FIG. 72 shows an example of the relationship between the counter values 7a, 7b and 7c, the hold circuit output 301a and the theoretical edge pulses 250a, 252a, 254a, 251a, 253a and 255a to be detected next during normal rotation in this embodiment. . From FIG. 72, for example, when the counter values 7a, 7b, 7c are low / low / low and the hold circuit output 301a is high, the edge pulse 253a or the pseudo pulse 6a is output, and another edge pulse 250a, for example, is input. Even if it does not output.
[0179]
Next, the operation of the brushless motor in this embodiment will be described. First, the case where the hold circuit output 301a is high immediately after the motor rotation signal 5a becomes high will be described with reference to FIG. Since the hold circuit output 301a is high, the commutation circuit 9 sets the drive signals 9a, 9b, 9c, 9d, 9e, and 9f to high / low / high / low / low / high from FIG. Then, the rotor of the brushless motor rotates in the forward direction, and sequentially starts energization.
[0180]
A case where the hold circuit output 301a is low immediately after the motor rotation signal 5a becomes high will be described with reference to FIG. Since the hold circuit output 301a is low, the commutation circuit 9 sets the drive signals 9a, 9b, 9c, 9d, 9e, and 9f to high, high, low, low, high and low from FIG. Then, the rotor of the brushless motor rotates in the forward direction, and sequentially starts energization.
[0181]
Example 23.
The present embodiment is an example in which driving at the time of starting or restarting is further ensured.
FIG. 75 shows an overall configuration diagram of a twenty-third embodiment of the three-phase brushless motor driving apparatus according to the present invention. Reference numeral 302 denotes an edge detection circuit that detects a rising edge or a falling edge of an input signal.
[0182]
The commutation circuit 9 performs energization immediately after the motor rotation signal 5a becomes high based on the hold circuit output 301a. When the hold circuit output 301a is high, the V-W phase is energized, and when the hold circuit output 301a is low, the W-V phase is energized. The first commutation is performed based on the output pulse 302a of the edge detection circuit 302 and the hold circuit output 301a. When the hold circuit output 301a is high, the U-W phase is energized, and when the hold circuit output 301a is low, the W-U phase is energized. The subsequent commutation is configured to output drive signals 9a, 9b, 9c, 9d, 9e, and 9f with reference to the position signals 3a, 3b, and 3c. An example of the logical relationship between the position signals 3a, 3b, and 3c and the drive signals 9a, 9b, 9c, 9d, 9e, and 9f is the same as that shown in FIG.
[0183]
Next, the operation of the brushless motor in this embodiment will be described. First, a case where the hold circuit output 301a is high immediately after the motor rotation signal 5a becomes high will be described with reference to FIG. Since the hold circuit output 301a is high, the drive signals 9a, 9b, 9c, 9d, 9e, and 9f are set to high, low, high, low, low, and high from FIG. 21 so that the V-W phase is energized. Then, when the rotor rotates forward and the output pulse 302a of the edge detection circuit 302 is detected, the first commutation is performed. Since the hold circuit output 301a is high, the drive signals 9a, 9b, 9c, 9d, 9e, and 9f are set to low high high low low low high from FIG. 21 so that the U-W phase is energized. . In the subsequent commutation, the energization is sequentially switched with reference to the position signals 3a, 3b, and 3c, so that the rotor rotates normally.
[0184]
A case where the hold circuit output 301a is low immediately after the motor rotation signal 5a becomes high will be described with reference to FIG. Since the hold circuit output 301a is low, the drive signals 9a, 9b, 9c, 9d, 9e, and 9f are set to high, high, low, low, high, and low from FIG. 21 so that the W-V phase is energized. Then, when the rotor rotates forward and the output pulse 302a of the edge detection circuit 302 is detected, the first commutation is performed. Since the hold circuit output 301a is low, the drive signals 9a, 9b, 9c, 9d, 9e, and 9f are set to high, high, low, high, low, and low from FIG. 21 so that the W-U phase is energized. . In the subsequent commutation, the energization is sequentially switched with reference to the position signals 3a, 3b, and 3c, so that the rotor rotates normally.
[0185]
In the present specification, separate embodiments have been shown for claims 1 to 19, but it is obvious that a sufficient effect can be obtained by combining these embodiments.
[0186]
Example 24.
FIG. 78 is a block diagram showing the overall configuration of the brushless motor drive circuit of this embodiment.
In FIG. 78, the same components as those in FIG.
In FIG. 78, reference numeral 406 denotes an activation circuit, and reference numeral 409 denotes a speed error detection circuit that measures a cycle of the actually measured speed signal 3d with a counter and outputs a cycle error that is a difference between the command value and the measured value as a speed error signal 409a. It is. A speed error compensation filter 410 outputs a current command value 410a to the current supply circuit 411 so that the speed error signal 409a becomes zero. The current supply circuit 411 includes the resistor 10, the bridge circuit 11, the buffer amplifier 212, the resistor 213, and the drive transistor 214 shown in FIG. 1, and the armature windings 12, 13, 14 is supplied with a predetermined drive current.
[0187]
The configurations and operations of the terminal potential correction circuit 1, the comparison circuit 2, and the waveform shaping circuit 3 constituting the rotor position signal detection circuit 4, which is an important means in the present invention, have already been described in the first embodiment. Yes.
FIG. 79 is a diagram showing signal waveforms at various parts of the terminal potential correction circuit 1 in the steady rotation state.
The specific operation of the terminal potential correction circuit 1 is also described in the first embodiment, and the correction operation is described using equations (1) to (3).
[0188]
The spike-shaped voltage fluctuation that occurs when switching from the energized state to the non-energized state causes false detection of the rotor position and noise, so the waveform shaping circuit 3 is necessary. This example is shown in FIG.
FIG. 80 shows another configuration example of the waveform shaping circuit 3.
In the figure, 180 is a latch circuit, 181 to 186 are D flip-flops, 187 to 189 are EOR circuits, and 190 is an OR circuit. Reference numeral 421 denotes a mask signal generation circuit, and reference numeral 422 denotes a timer. FIG. 81 shows the terminal potential waveform and the signal waveform of each part of the waveform shaping circuit in the steady rotation state, and FIG. 82 is an enlarged view of time T0 to T1 in FIG.
[0189]
The specific operation of the waveform shaping circuit of this embodiment will be described with reference to the above drawings.
Input signals to the waveform shaping circuit are logic signals 2 a, 2 b and 2 c output from the comparison circuit 2. Since the logic signals 2a, 2b and 2c are obtained by comparing the corrected terminal potentials, chattering occurs as shown in FIG.
The logic signals 2a, 2b, and 2c are first input to the latch circuit 180. The latch circuit 180 is a circuit that performs a latch operation according to the state of the enable terminal 180a. In the initial state, the mask signal 421a output from the mask signal generation circuit 421 is at a high level, and the logic signals 2a, 2b, and 2c are input to the D flip-flops 181, 183, and 185 as they are. The D flip-flops 181 to 186 and the EOR circuits 187 to 189 constitute a double-edge differentiating circuit. The EOR circuits 187 to 189 are differentiated pulses 198 and 199 at the rising and falling edges of the logic signals 2a, 2b and 2c. , 200 is output.
[0190]
At time T2, when the corrected terminal potentials 1a and 1c match and the polarity of 2a changes, an edge is detected by the two-edge differentiating circuit and a differential pulse 198b is generated. The output signals of the EOR circuits 187 to 189 are combined by the OR circuit 190 to become a logic pulse signal 3d and input to the mask signal generation circuit 421 and the timer 422. The mask signal generation circuit 421 makes the mask signal 421a low level using the rising edge of the logic pulse signal 3d as a trigger. The timer 422 is initialized at the rising edge of the logic pulse signal 3d, and the timer value 422a becomes zero. Thereafter, the timer 422 performs a count-up operation in synchronization with the input clock. Since the enable terminal 180a becomes low level, the latch circuit 180 latches the logic signals 2a, 2b, and 2c. Thereafter, the mask signal generation circuit 421 monitors the timer value 422a of the timer 422, and when the timer value 422a reaches a predetermined value, sets the mask signal 421a to high level. Since the enable terminal 180a becomes high level, the latch circuit 180 releases the latch.
[0191]
The output signals of the D flip-flops 182, 184, and 186 become the rotor-shaped signals 3a, 3b, and 3c whose waveforms are shaped, and are input to the next-stage commutation circuit 9 to perform the commutation operation. When the commutation operation is performed, since the driving transistor is switched, a spike-like voltage fluctuation occurs in the U-phase terminal potential waveform. As a result, spike-like noise 2d is generated in 2b at an undesired position. However, when the spike-like noise 2d is generated, data input to the latch circuit is disabled by the mask signal 421a output from the mask signal generation circuit 421. Accordingly, the spike noise 2d is masked by the latch circuit 180, and no spike noise is generated in the waveform-shaped rotor position signals 3a, 3b, and 3c. In this way, stable rotor position signals 3a, 3b, and 3c are obtained, and the armature winding is applied and driven based on the rotor position signals to rotate the rotor.
[0192]
In this embodiment, an example applied to a three-phase brushless motor has been described. However, it is apparent that the present invention is applicable not only to three phases but also to a plurality of brushless motors in general.
[0193]
Example 25.
In the present embodiment, the time T3 during which the mask signal 421a described in the first embodiment is maintained at the low level is changed in proportion to the command rotational speed when the command rotational speed for the motor is changed. I made it.
The overall configuration of the brushless motor drive circuit of this embodiment is the same as that of the twenty-fourth embodiment. However, as described below, the configuration is such that the command rotational speed (CLK) to the timer is changed.
[0194]
The operations of the mask signal generating circuit 421 and the timer 422 of this embodiment will be described with reference to FIGS. 83, 84, and 85. As described in the twenty-fourth embodiment, when the rising edge or falling edge of the logic signals 2a, 2b, and 2c is detected and the logic pulse signal 3d is generated, the mask signal generation circuit 421 uses the rising edge of the logic pulse signal 3d as a trigger. Thus, the mask signal 421a is set to low level. The timer 422 is initialized at the rising edge of the logic pulse signal 3d, and the timer value 422a becomes zero. Thereafter, the timer 422 performs a count-up operation in synchronization with the rising edge of the input clock. Thereafter, the mask signal generation circuit 421 monitors the timer value 422a of the timer 422. When the timer value 422a becomes N (set to N = 10 in FIG. 83), the mask signal 421a is set to high level. Assuming that the clock cycle is T4, the mask signal 421a maintains the low level for T4 × 10.
[0195]
Next, the case where the command rotational speed has doubled from the state of FIG. 83 will be described. As shown in FIG. 84, the cycle of CLK (input from the outside of the brushless motor drive circuit) is set to T4 / 2. As a result, the time during which the mask signal 421a is maintained at the low level is T4 × 5. Alternatively, as shown in FIG. 85, the period of the clock input to the timer remains T4, and the value of N is changed to 5. As a result, the time during which the mask signal 421a is maintained at the low level is T4 × 5 as in the case where the clock cycle is changed. In this way, the time during which the mask signal is maintained at the low level is changed based on the command rotational speed.
[0196]
Example 26.
In this embodiment, a brushless motor that is not affected by the load at the start, starts in a short time, and further stably restarts in a short time even if the rotation becomes abnormal for some reason during the operation and needs to be restarted. The configuration and operation of the driving circuit will be described. Although the gist of the present invention has been described in the eighth embodiment, the operation at the time of starting or restarting will be mainly described in the present embodiment.
The overall configuration of the brushless motor drive circuit of this embodiment is the same as that shown in FIG. Here, the configuration and operation of the activation circuit, which is an important means for realizing the present invention, will be described below. New components in this embodiment are a pseudo pulse generation circuit 431 and a restart pulse generation circuit 432. Other components are the same as those shown in FIG.
[0197]
A motor rotation signal 5a shown in FIG. 78 is a signal input from the outside of the brushless motor drive circuit, and represents rotation when enabled and stopped when disabled. In this embodiment, enable is set to high level and disable is set to low level.
[0198]
FIG. 86 shows a specific configuration example of the activation circuit 406. The rotor position signals 3a, 3b, and 3c are input to the rising edge detection circuits 250, 252, and 254, the falling edge detection circuits 251, 253, and 255 and the steady rotation detection circuit 265, respectively, and the rising edge detection circuits 250 and 252 are input. 254 and falling edge detection circuits 251, 253, and 255 rise and output falling edge pulses 250a to 255a, respectively. These detected edge pulses are input to the pulse selection circuit 256, and the selection pulse 256 a output from the pulse selection circuit 256 is input to the pseudo pulse generation circuit 431.
The pulse train 431 a output from the pseudo pulse generation circuit 431 is input to the hexadecimal counter 257. An example of the logical relationship between the number of pulses input to the hex counter 257 and the output value is the same as that shown in FIG. In the figure, when the number of input pulses is 6 or more, the counter values 7a, 7b, and 7c are counted again from low, low, and low. The counter value output from the hexadecimal counter 257 is input to the pulse selection circuit 256, the steady rotation detection circuit 265, and the commutation circuit 9 shown in FIG. The rotation abnormality signal 265 b output from the steady rotation detection circuit 265 is input to the restart pulse generation circuit 432. A motor rotation signal 5a is input to the restart pulse generation circuit. The restart pulse 7e output from the restart pulse generation circuit 432 is input to the commutation circuit 9 shown in FIG.
[0199]
The pulse selection circuit 256 outputs the input edge pulses 250a to 255a as they are as a pulse train when the rotor is rotating forward in the logic of FIG. That is, when the relationship between the type of the input edge pulse and the counter values 7a, 7b, and 7c satisfies the relationship in FIG. 25, the input edge pulse is output as it is, and otherwise, the input edge pulse is masked. To do. Accordingly, since the relationship between the counter values 7a, 7b, 7c and the edge pulse is different from that in the normal rotation at the time of reverse rotation, the input edge pulse is masked.
The pseudo pulse generation circuit 431 is a circuit that outputs a pulse train as it is when the selection pulse train 256a is sequentially input from the pulse selection circuit 256 within a predetermined time, and generates a pseudo pulse when the pulse train is not input for a predetermined time. FIG. 87 shows a specific configuration example of the pseudo pulse generation circuit 431, and FIG. 88 shows an example of a timing chart showing the operation of the pseudo pulse generation circuit 431.
[0200]
87, reference numeral 433 is a counter, 434 is a gate circuit, 435 is a rising edge detection circuit, 436 is a delay circuit, and 437 is an OR circuit. The counter 433 is initialized by the pulse train 431a and counts up in synchronization with the input clock. The gate circuit 434 decodes the counter value 433a, and outputs a low level signal when the decoded value is smaller than the set value, and outputs a high level signal when the decoded value is larger than the set value. Therefore, if the selection pulse 256a is not input from the pulse selection circuit 256 for a predetermined time, the output signal 434a of the gate circuit becomes high level, the rising edge detection circuit 435 detects the rising edge, and the detected edge pulse is transferred to the delay circuit 436. And is output as a pseudo pulse 436b in FIG.
[0201]
The steady rotation detection circuit 265 is a circuit that monitors whether the rotor described in the ninth embodiment is normally rotating normally.
The restart pulse generation circuit 432 masks the rotation abnormality signal 256b after starting or until a predetermined time elapses after restarting, detects the rising edge of the rotation abnormality signal after the predetermined time elapses, and outputs it as a restart pulse. Circuit.
FIG. 89 shows a configuration example of the restart pulse generation circuit 432.
In the figure, 440 and 444 are rising edge detection circuits, 441 and 446 are OR circuits, 442 is a counter, 443 is a gate circuit, and 445 is an AND circuit. The counter 442 is initialized by the rising edge of the motor rotation signal 5a or the restart pulse 7e, and counts up in synchronization with the output of the OR circuit 446. The gate circuit 443 decodes the counter value 442a, and outputs a low level signal when the decoded value is smaller than the set value and a high level signal when the decoded value is larger than the set value. Therefore, the rotation abnormality signal 265b is masked until a predetermined time elapses after the activation or after the restart, and the rising edge of the rotation abnormality signal is output as a reactivation pulse after the elapse of the predetermined time.
[0202]
The starting operation of the brushless motor in this embodiment will be described. Hereinafter, the low level may be described as L and the high level as H. Immediately after the motor rotation signal 5a becomes high level, the counter values 7a, 7b and 7c become LLL, so that the drive signal 9b becomes L and 9f becomes H from FIG. 27, and the VW phase from FIG. Is energized. At this time, the rotor position signal may change when the rotor of the brushless motor rotates forward, the rotor position signal may change due to reverse rotation, or the position signal may not change after stopping at the energization stable point. .
[0203]
First, a case where the rotor rotates normally will be described. In this case, the signal waveform of each part shown in FIG. As described in the corresponding part of the eighth embodiment, the hex counter 257 counts only when the edge pulse 253a is detected or the pseudo pulse 436b is generated by the pseudo pulse generation circuit. When the rotor rotates in the forward direction, the terminal potentials U, V, and W change due to the counter electromotive voltage generated in the armature winding, and the rotor position signals 3a, 3b, and 3c become HLL, as shown in FIG. ), The edge pulse 253a is detected. Therefore, the hex counter 257 counts up, the counter values 7a, 7b, and 7c become HLL, and the commutation circuit 9 applies the drive signals 9a to 9f to LHHLLH so that the U-W phase is energized from FIGS. Set to. Then, the pseudo pulse generation circuit 431 continues to output the waveform indicated by 7d in FIG. 28 as its output 431a, and thereafter sequentially applies energized phases according to the combination of the counter values 7a, 7b, and 7c in accordance with the combination shown in FIG. Switch to start the brushless motor.
[0204]
Next, a case where the rotor is reversed will be described. In this case, the signal waveform example of each part shown in FIG. As described in the eighth embodiment, when the rotor reverses, the rotor position signal 3a changes, and an edge pulse 251a shown in FIG. However, the pulse selection circuit 256 masks the counter value. If the edge pulse 253a cannot be detected within the predetermined time t1 set by the gate circuit 434 in the pseudo pulse generation circuit 431, the pseudo pulse generation circuit 431 corresponds to the pseudo pulse 6a as shown in FIG. 431a is output. The hexadecimal counter 257 counts up with this pseudo pulse 431a, and the counter values 7a, 7b, and 7c change to HLL. The commutation circuit 9 sets the drive signals 9a to 9f to LHHLLH so as to energize the U-W phase according to the counter values 7a, 7b, and 7c. As a result, the rotor rotates normally, and thereafter the brushless motor is started by sequentially switching the energized phase according to the combination shown in FIG.
[0205]
Next, the case where the rotor does not move and the rotor position signal does not change will be described. As in the case of reverse rotation, since the edge pulse 253a cannot be detected within the predetermined time t1, a pseudo pulse (corresponding to 6a) is output from the pseudo pulse generation circuit 431. Then, as in the case of reverse rotation, the hex counter 257 counts the pseudo pulse, and the commutation circuit switches the energized phase to the U-W phase, and then continues according to the combination of the counter values 7a, 7b, 7c until it rotates normally. The brushless motor is started by sequentially switching the energized phases according to the relationship shown in FIG.
[0206]
In such a configuration, an example when the rotor is stopped by some load during steady rotation will be described with reference to FIG. In FIG. 90, it is assumed that the rotor stops after (D). In this case, the pseudo pulse 436b is output from the delay circuit 436 in the pseudo pulse generation circuit 431 after the time t1 set by the gate circuit 434 in the pseudo pulse generation circuit 431 has elapsed since the pulse 431c was detected. The pseudo pulse 436b is output as a pulse of the pulse train 431a output from the pseudo pulse generation circuit 431, and the counter values 7a, 7b, and 7c change from LHL to LLH. Since the drive signals 9a to 9f are output by the combination of the rotor position signals 3a, 3b, and 3c as described above during the steady rotation, the energized phase is not switched even if the counter values 7a, 7b, and 7c change. Therefore, the relationship between the counter values 7a, 7b, and 7c and the rotor position signals 3a, 3b, and 3c does not satisfy the relationship shown in FIG.
[0207]
At this time, if a predetermined time has elapsed after startup and restart, the rising edge of the rotation abnormality signal is detected by the restart pulse generation circuit 432 and output as the restart pulse 7e. The restart pulse is input to the commutation circuit 9, and the commutation circuit shifts to the start mode.
Since the commutation circuit in the start mode outputs the drive signals 9a to 9f according to the combination of the counter values 7a, 7b, and 7c, the drive signals 9a to 9f become HHLLHL and become W-V from FIGS. The phase is energized. When the rotor rotates forward by energizing the W-V phase and the rotor position signals 3a, 3b, 3c change to LLH, the counter values 7a, 7b, 7c and the rotor position signals 3a, 3b, 3c Since the relationship satisfies the relationship shown in FIG. 31, the rotation abnormality signal 265b is at a low level. Thereafter, as described with reference to FIGS. 28 and 29, the brushless motor is started by sequentially switching energized phases according to the combination of the counter values 7a, 7b, and 7c in accordance with the combination shown in FIG.
[0208]
Example 27.
In this embodiment, the configuration and operation of a brushless motor drive circuit provided with switching means for switching from the start mode to the steady rotation mode will be described.
FIG. 91 shows a specific configuration example of the activation circuit 406B provided with switching means. The rising edge detection circuit, falling edge detection circuit, pulse selection circuit, pseudo pulse generation circuit, hex counter, steady rotation detection circuit, and restart pulse generation circuit are the same circuits as in the twenty-sixth embodiment. 450, which is a new component, switches between referring to the counter values 7a, 7b, 7c and the rotor position signals 3a, 3b, 3c when the commutation circuit 9 outputs the drive signals 9a-9f. This is a switching signal generation circuit that outputs a switching signal 450a for the purpose.
The commutation circuit 9 of this embodiment refers to the counter values 7a, 7b and 7c when the switching signal 450a is at low level, and the rotor position signals 3a and 3b when the switching signal 450a is at high level. 3c. Hereinafter, the switching signal generation circuit 450 will be described.
[0209]
In this embodiment, the motor rotation signal 5 a and the restart pulse 432 a are input to the switching signal generation circuit 450. The switching signal 450a is input to the commutation circuit 9.
FIG. 92 shows a specific configuration example of the switching signal generation circuit 450.
In the figure, 451 is a rising edge detection circuit, 452 and 455 are OR circuits, 453 is a counter, and 454 is a gate circuit.
FIG. 93 is a signal waveform example of each part showing the operation of the switching signal generation circuit 450. The counter 453 is initialized by the rising edge of the motor rotation signal 5a or the restart pulse 432a, and counts up in synchronization with the output 455a of the OR circuit 455. The gate circuit 454 decodes the counter value 453a, and outputs a low level signal when the decoded value is smaller than the set value, and outputs a high level signal when the decoded value is larger than the set value. Accordingly, the switching signal 450a is at a low level until a predetermined time elapses after starting or restarting, and is at a high level thereafter. The switching signal 450a is input to the commutation circuit 9, and the commutation circuit 9 switches means to be referred to according to the switching signal 450a.
[0210]
Example 28.
In the present embodiment, the configuration of a brushless motor drive circuit having a speed error compensation filter with improved low frequency gain characteristics compared to a conventional speed error compensation filter will be described. The overall configuration of the brushless motor drive circuit of this embodiment is the same as that shown in FIG. The configuration of the speed error compensation filter, which is an important means for realizing the present invention, will be described below.
[0211]
FIG. 94 is a transmission block diagram when a speed error compensation filter is configured by an analog filter.
In the figure, 460 is a proportional / integral (PI) filter, 461 is a first-order lag filter, 462 is a gain element or coefficient multiplier, 463 is an adder, and 464 is a first-order lag filter.
The speed error signal 409a output from the speed error detection circuit 409 is input to the input terminal X of the speed error compensation filter. The filter output outputted from the output terminal Y is given to the current supply circuit 411 as a current command value 410a to the armature winding. The difference from the filter configuration of FIG. 123 shown in the prior art is that the input speed error signal 409 a is added to the output of the PI filter 460 via the new first-order lag filter 461. . At this time, the transfer function G of the speed error compensation filter_C(S) is as shown in Equation (6).

[0212]
FIG. 95 shows K_P= 1, T_I= 1 / (2π × 10), K_w= 1, T_A= 1 / (2π × 5), T_LIt is a simulation result of the open loop characteristic of the speed error compensation filter when = 1 / (2π × 60). Also, with the conventional filter configuration, K_P= 1, T_I= 1 / (2π × 10), T_LA simulation result when = 1 / (2π × 60) is shown by a broken line in FIG. The low frequency gain characteristic is improved by the filter configuration proposed in the present invention.
[0213]
FIG. 94 shows an example in which an analog filter is used, but it is of course possible to use a digital filter.
FIG. 96 is a transmission block diagram when a speed error compensation filter is configured by a digital filter.
In the figure, 470 to 472 are delay elements for delaying the signal by one sampling time, 473 to 479 are gain elements, and 480 to 483 are adders. The delay element 471, the gain elements 476 and 477, and the adders 481 and 482 constitute the PI filter 484, and the delay element 470, the gain elements 473 to 475 and the adder 480 constitute the first-order delay filter 485, and the delay element 472, The gain elements 478 and 479 and the adder 483 constitute a first-order lag filter 486. At this time, the transfer function G of the speed error compensation filter_C(Z) is as shown in Equation (7).

[0214]
Example 29.
In the present embodiment, another embodiment of a speed error compensation filter having improved low-frequency gain characteristics as compared with a conventional speed error compensation filter will be described.
[0215]
FIG. 97 is a transmission block diagram when a speed error compensation filter is configured by an analog filter.
In the figure, the same members as those in Example 28 are indicated by the same numbers. The difference from the speed error compensation filter configuration shown in the prior art is that the output of the new first-order lag filter 461 that receives the speed error signal 409a is added to the series circuit output of the PI filter and the first-order lag filter. It is a point that has been configured. At this time, the transfer function G of the speed error compensation filter_C(S) is as shown in Equation (8).

[0216]
FIG. 98 shows K_P= 1, T_I= 1 / (2π × 10), K_w= 1, T_A= 1 / (2π × 5), T_LIt is a simulation result of the open loop characteristic of the speed error compensation filter when = 1 / (2π × 60). Also, with the conventional filter configuration, K_P= 1, T_I= 1 / (2π × 10), T_LThe simulation result when = 1 / (2π × 60) is shown by a broken line in FIG. The low frequency gain characteristic is improved by the filter configuration proposed in the present invention.
[0217]
FIG. 97 shows an example in which an analog filter is used, but it is of course possible to use a digital filter.
FIG. 99 is a transmission block diagram when a speed error compensation filter is configured by a digital filter.
In FIG. 99, the same members as those in Example 28 are denoted by the same numbers. Reference numerals 487 and 488 denote adders. At this time, the transfer function G of the speed error compensation filter_C(Z) is as shown in Equation (9).

[0218]
Example 30. FIG.
In the present embodiment, a brushless motor drive circuit configured to switch the target rotation speed of the speed error detection circuit and the gain of the speed error compensation filter when the command rotation speed is changed will be described.
FIG. 100 is a block diagram showing an overall configuration of a brushless motor drive circuit according to a thirtieth embodiment of the present invention.
In FIG. 100, the same components as those in FIG. 78 are denoted by the same reference numerals. Reference numeral 490 denotes an input terminal to which a mode switching signal 490a is input. The mode switching signal 490a is a signal input from the outside of the brushless motor drive circuit, and is a binarized signal for switching the rotation speed of the motor.
[0219]
In the waveform shaping circuit 3 described in the previous embodiment, the logic pulse signal 3d output from the OR circuit is a signal obtained at regular time intervals during steady rotation. Therefore, this logic pulse signal 3d can be used as a speed signal for controlling the rotation speed.
FIG. 101 shows a specific configuration example of the speed error detection circuit 409.
In the figure, 491 and 492 are initial value registers, 493 is a selector, and 494 is a counter. The initial value registers 491 and 492 are registers in which the target rotational speed is stored. In this embodiment, the initial value registers 491 and 492 have two initial value registers to correspond to two types of command rotational speeds. The selector 493 switches between the two types of initial value registers 491 and 492 in accordance with the logic level of the mode switching signal 490a. The counter 494 loads the initial value selected by the selector 493 at the rising edge timing of the logic pulse signal 3d, and counts up the clock.
[0220]
For example, it corresponds to two types of command rotational speeds (denoted as command rotational speed A and command rotational speed B, respectively) in which the period of the logic pulse signal 3d is 1 (msec) and 0.5 (msec) during steady rotation. The case will be described.
The frequency of the clock is set to 1 (MHz) and corresponds to the command rotational speed A when the mode switching signal 490a is at a high level and to the command rotational speed B when the mode switching signal 490a is at a low level. The initial value register 491 is set to -1000, and the initial value register 492 is set to -500. In such a configuration, when the mode switching signal 490a is at the high level, the selector 493 selects the initial value register 491, and the counter 494 loads the initial value −1000 at the rising edge timing of the logic pulse signal 3d. After that, the counter 494 counts up the clock, and when the period of the logic pulse signal 3d is shorter than 1 (msec), a negative value is obtained. When the period of the logic pulse signal 3d is longer than 1 (msec), a positive value is obtained. Output as signal 409a.
On the other hand, when the mode switching signal 490a is at the low level, the selector 493 selects the initial value register 492, and the counter 494 loads the initial value −500 at the timing of the rising edge of the logic pulse signal 3d. Thereafter, the counter 494 counts up in synchronization with the clock, and when the period of the logic pulse signal 3d is shorter than 0.5 (msec), the counter 494 is negative, and the period of the logic pulse signal 3d is longer than 0.5 (msec). In this case, a positive value is output as the speed error signal 409a.
[0221]
Example 31.
In the above embodiment, the operation of the speed error detection circuit 409 when changing the command rotational speed has been described. However, since the target rotational speed is switched to cope with it, there is a problem that the detection sensitivity changes due to the difference in the command rotational speed. In this embodiment, in order to cope with this problem, the gain element of the speed error compensation filter is also switched.
[0222]
FIG. 102 shows a block diagram of the PI filter 484A when the gain element of the speed error compensation filter is switched.
In FIG. 102, the same constituent elements as those shown in FIG. Reference numerals 495 and 496 are gain elements newly provided to cope with different command rotational speeds. Reference numerals 497 and 498 denote selectors, and the selectors 497 and 498 select which output of the gain elements 476 and 495 and the gain elements 477 and 496 is used, respectively, according to the logic level of the mode switching signal 490a. Similarly, the gain elements of the first-order lag filters 485 and 486 are also switched by the mode switching signal 490a.
Of course, other general methods for switching the gain may be used.
[0223]
In this embodiment, an example in which the command rotational speed is switched by a 1-bit binary signal has been described. However, when a plurality of command rotational speeds are supported, the command rotational speed is switched by an N-bit binary signal. It is also possible to do.
[0224]
Example 32.
In the present embodiment, the relationship between the timing of switching the energized phase and the timing of increasing or decreasing the amount of current supplied to the armature winding in the brushless motor drive circuit of the present invention will be described.
The overall configuration of the brushless motor drive circuit of this embodiment is the same as that shown in FIG.
FIG. 103 is a timing chart showing the operation during steady rotation of the brushless motor drive circuit of the present invention. This will be described with reference to FIG.
In the figure, 3a, 3b and 3c are rotor position signals, 9a to 9f are drive signals, 3d is a logic pulse signal representing speed, 409a is a speed error signal, and 410a is a current command value.
During steady rotation, the drive signals 9a to 9f are generated based on the rotor position signals 3a, 3b, and 3c. Therefore, during steady rotation, the energized phase is switched at the timing shown in the figure.
[0225]
The logic pulse signal 3d is a double-edge differential pulse of the rotor position signals 3a, 3b, and 3c. The speed error detection circuit 409 measures the period of the speed signal 3d, and outputs a period error that is the difference between the target value and the measurement value as a speed error signal 409a at the timing shown in FIG. The speed error signal 409a is input to the speed error compensation filter 410. The speed error compensation filter 410 performs a filter operation so that the speed error signal 409a becomes zero.
Since the filter calculation requires a predetermined calculation time, the current command value 410a changes after the calculation time has elapsed after the speed error signal 409a changes. The current supply circuit 411 adjusts the amount of current supplied to the armature winding based on the current command value 410a.
[0226]
As described above, in the brushless motor drive circuit of the present invention, the switching timing of the energized phase is synchronized with the timing of increasing or decreasing the armature winding current, and the increase or decrease of the armature winding current is commutated. This is performed after the post-calculation time has elapsed.
[0227]
Example 33.
In the present embodiment, a brushless motor drive circuit configured to supply a maximum current to the armature winding during the startup and restart periods will be described.
FIG. 104 is a block diagram showing the overall configuration of the brushless motor drive circuit of this embodiment. That is, in this configuration, the switching signal 450a described in the twenty-seventh embodiment is input to the speed error compensation filter 410.
[0228]
FIG. 105 shows a configuration example of the speed error compensation filter.
In the figure, 600 is a microcontroller, 601 is a D / A converter, and 602 is a register group including registers 0 to N in the microcontroller 600.
The microcontroller 600 receives the speed error signal 409a output from the speed error detection circuit 409, performs the filter operation as shown in the twenty-eighth embodiment and the twenty-ninth embodiment, for example, and stores the calculation result in the register N. Further, the microcontroller 600 outputs the value stored in the register N to the D / A converter 601 at a predetermined timing. The digital value stored in the register N is converted to an analog value by the D / A converter 601 and input to the current supply circuit 411 as the current command value 410a.
[0229]
A switching signal 450 a for switching between the start mode and the steady rotation mode is input to the microcontroller 600. As described in the twenty-seventh embodiment, the switching signal 450a is a signal that is at a low level until a predetermined time elapses after starting or restarting, and is at a high level thereafter. When the switching signal 450a becomes low level, the microcontroller 600 initializes the register N and sets the value of the register N to the maximum value. Therefore, while the switching signal 450a is at the low level, the current command value 410a is set to the maximum set value, and the maximum current is supplied to the armature winding during the startup and restart periods.
In the present specification, separate embodiments have been shown for claims 1 to 28, but it is obvious that a sufficient effect can be obtained by combining these embodiments.
[0230]
Example 34.
FIG. 106 is a block diagram showing the overall configuration of the brushless motor drive circuit of this embodiment. In FIG. 106, the same components as those in FIG. 78 are denoted by the same reference numerals. The commutation circuit 9 described in the twenty-seventh embodiment refers to the counter values 7a, 7b, and 7c in the startup mode, and refers to the rotor position signals 3a, 3b, and 3c in the steady rotation mode, and the drive signals 9a to 9f. Was configured to output. The commutation circuit 610 of this embodiment outputs drive signals 9a to 9f with reference to the counter values 7a, 7b, and 7c in both the start mode and the steady rotation mode. The logical relationship between the counter values 7a, 7b, and 7c and the drive signals 9a to 9f is the same as in FIG.
[0231]
In this embodiment, another configuration example of the pulse selection circuit will be described. FIG. 107 shows a specific configuration example of a pulse selection circuit 609 having a configuration different from that of the pulse selection circuit 256. In the figure, 611 to 613 are inverting circuits, 614 to 625 are 3-input AND circuits, and 626 is a 6-input OR circuit.
[0232]
The operations of the pulse selection circuit 256 shown in Embodiments 8 and 26 and the pulse selection circuit 609 shown in this embodiment will be compared. FIG. 108 shows rotor position signals 3a, 3b, 3c, rising / falling edge pulses 250a-255a, counter values 7a, 7b, 7c, and output signal 256a of pulse selection circuit 256 when the motor rotates reversely at a constant speed. 4 shows a timing chart of the output signal 431a of the pseudo pulse generation circuit 431.
On the other hand, FIG. 109 shows rotor position signals 3a, 3b, 3c, rising / falling edge pulses 250a-255a, counter values 7a, 7b, 7c, and output of the pulse selection circuit 609 when the motor rotates reversely at a constant speed. The timing chart of the signal 609a and the output signal 431a of the pseudo pulse generation circuit 431 is shown.
[0233]
In the pulse selection circuit 256 shown in the eighth and twenty-sixth embodiments, when the relationship between the types of the input edge pulses 250a to 255a and the counter values 7a, 7b, and 7c satisfies the relationship shown in FIG. In other cases, the circuit outputs and masks the input edge pulse. Hereinafter, a description will be given with reference to FIGS. Assume that the initial value of the counter value is LLL. In FIGS. 108 and 109, edge pulses 255a, 252a, and 251a are sequentially detected at (E), (F), and (G). Since the counter value is LLL, the pulse selection circuit 256 masks edge pulses other than 253a. Therefore, the edge pulses 255a, 252a, and 251a detected at (E), (F), and (G) in the figure are masked.
[0234]
Similarly, in the pulse selection circuit 609, these edge pulses are masked. Even if the predetermined time t1 set in the pseudo pulse generation circuit 431 elapses, there is no input to the pseudo pulse generation circuit 431. Therefore, the pseudo pulse generation circuit 431 generates a pseudo pulse in FIG. The hex counter 257 counts up by this pseudo pulse, and the counter value becomes HLL. Then, an edge pulse 254a is detected at (I) in the figure. Since the counter value is HLL, the edge pulse 254a detected in (I) in the figure is output without being masked by the pulse selection circuit 256. Thus, the pulse selection circuit 256 could not completely mask the edge pulses 250a to 255a during the reverse rotation.
On the other hand, in the pulse selection circuit 609, since the rotor position signal 3a is L in (I), the edge pulse 254a detected in (I) in the figure is masked. As described above, the pulse selection circuit 609 according to the present embodiment selects the edge pulse by combining the logic of the rotor position signals 3a, 3b, and 3c in addition to the combination of the counter value and the type of the input edge pulse. Thus, as shown in FIG. 109, the edge pulses 250a to 255a at the time of reverse rotation can be completely masked.
[0235]
Example 35.
Next, an example in which noise is reduced by making the rotor drive signal a trapezoidal wave will be described.
FIG. 110 is a block diagram showing the overall configuration of the brushless motor drive circuit of this embodiment. In the figure, the same components as those in FIG. 106 are denoted by the same numbers. As a new element, 630 is a logic circuit that outputs a plurality of logic signals 630a to 630g necessary to synthesize a trapezoidal drive signal, and 631 charges and discharges a capacitor based on an output signal 630g from the logic circuit. A charge / discharge circuit 632 is a trapezoidal wave synthesis circuit that synthesizes trapezoidal drive signals 632a to 632f from the output signal 631a of the charge / discharge circuit and the output signals 630a to 630f of the logic circuit.
A trapezoidal drive signal generation circuit 633 is configured including the logic circuit 630, the charge / discharge circuit 631, and the trapezoidal wave synthesis circuit 632.
[0236]
FIG. 111 illustrates a specific configuration example of the logic circuit 630. In the figure, 635 to 643 are AND circuits, and 644 is a three-input OR circuit. The operation waveforms of the output signals 630a to 630g of the logic circuit 630 are as shown in FIG.
FIG. 112 shows a specific configuration example of the charge / discharge circuit 631. In the figure, 645 and 646 are constant current sources, and 647 is a capacitor. SW1 is turned on when the output signal 630g of the logic circuit 630 is at a high level and turned off when the output signal 630g is at a low level.
The operation of the charge / discharge circuit 631 will be described. When the output signal 630g of the logic circuit is at a low level, SW1 is turned off and the capacitor 647 is charged with a constant current I3. On the other hand, when the output signal 630g of the logic circuit 630 is at a high level, SW1 is turned on and the capacitor 647 is discharged with a constant current I3. The output signal 631a of the charge / discharge circuit 631 is a trapezoidal signal as shown in FIG.
[0237]
The output signal 631 a of the charge / discharge circuit 631 and the output signals 630 a to 630 f of the logic circuit 630 are input to the trapezoidal wave synthesis circuit 632.
A specific configuration example of the trapezoidal wave synthesis circuit 632 is shown in FIG. In the figure, 648 to 651 are inverting amplifier circuits, and 652 to 657 are NAND circuits. It is assumed that the operating voltage range of the output signal 631a of the charge / discharge circuit 631 and the output signals 630a to 630f of the logic circuit 630 are the same, and Vref is the center potential of the operating voltage range. The output signal 631a of the charge / discharge circuit 631 is input to the inverting input terminal of the inverting amplifier circuit 648, the reference potential Vref is input to the non-inverting input terminal, and a trapezoidal wave obtained by inverting 631a with respect to Vref is obtained. Similarly, the inverting amplifier circuits 649, 650, and 651 obtain signals obtained by inverting 630a, 630c, and 630e, respectively, with respect to Vref.
[0238]
Hereinafter, a specific operation of the trapezoidal wave synthesis circuit 632 will be described with reference to the drawings. Here, a description will be given focusing on a portion where the trapezoidal drive signal 632a is synthesized.
SW2, SW3, and SW4 are turned on when 630d, 630f, and 652a are at a high level, and turned off when at a low level. 652a is an output signal of the NAND circuit 652. In the period Ta shown in FIG. 113, since 630d is at a high level, 630f is at a low level, and 652a is at a low level, only SW2 is turned on, and the trapezoidal drive signal 632a is an output signal 631a of the charge / discharge circuit 631. Become. In the period Tb, since 630d is at a low level, 630f is at a low level, and 652a is at a high level, only SW4 is turned on, and the trapezoid drive signal 632a is a signal obtained by inverting 630e with Vref as a reference. In the period Tc, since 630d is at the low level, 630f is at the high level, and 652a is at the low level, only SW3 is turned on, and the trapezoid drive signal 632a becomes a trapezoidal wave obtained by inverting 631a with reference to Vref. In the period Td, since 630d is at a low level, 630f is at a low level, and 652a is at a high level, only SW4 is turned on, and the trapezoidal drive signal 632a becomes a trapezoidal wave obtained by inverting 630e with reference to Vref.
As described above, the trapezoidal drive signal 632a is synthesized. Trapezoid drive signals 632b to 632f are also synthesized in the same procedure. In this manner, the trapezoidal drive signal generation circuit 633 generates trapezoidal drive signals 632a to 632f where the rising slope portion and the falling slope portion start from the rising and falling edge times of the drive signals 9a to 9f.
[0239]
Example 36.
In the present embodiment, a brushless motor drive circuit configured to change the inclination time of the trapezoidal drive signals 632a to 632f in accordance with an externally input command rotational speed will be described.
FIG. 115 is a block diagram showing the overall configuration of the brushless motor drive circuit of this embodiment. In the figure, the same components as those in FIG. 110 are denoted by the same reference numerals. In FIG. 115, reference numeral 660 denotes a terminal to which a mode switching signal 660a is input, and reference numeral 661 denotes a charge / discharge circuit having a configuration different from that of the charge / discharge circuit 631. The mode switching signal 660a is a signal input from the outside of the brushless motor driving circuit, and is a binary signal whose polarity changes in accordance with the command rotational speed.
[0240]
FIG. 116 shows a specific configuration example of the charge / discharge circuit 661. In the figure, 662 is an inverting circuit, and 663 and 664 are constant current sources. SW5 and SW7 are turned on when the mode switching signal 660a is at a high level and turned off when the mode switching signal 660a is at a low level. SW6 and SW8 are turned on when the mode switching signal 660a is at the low level, and turned off when the mode switching signal 660a is at the high level.
[0241]
The operation of the charge / discharge circuit 661 when the mode switching signal 660a is at a high level will be described.
When the output signal 630g of the logic circuit is at a low level, SW1 is turned off and the capacitor 647 is charged with a constant current I3. On the other hand, when the output signal 630g of the logic circuit 630 is at a high level, SW1 is turned on and the capacitor 647 is discharged with a constant current I3. The relationship between the output signal 630g of the logic circuit 630 and the output signal 661a of the charge / discharge circuit 661 is as indicated by H in 632a in FIG.
[0242]
When the mode switching signal 660a is low level, the capacitor 647 is charged with a constant current I4 when the output signal 630g of the logic circuit is low level, and when the output signal 630g of the logic circuit 630 is high level, the capacitor 647 is discharged with a constant current I4.
[0243]
When setting so that I4 = 0.5 × I3, the output signal 661a of the charge / discharge circuit 661 becomes as indicated by L in 632a in FIG. 117, and the slope time of the trapezoidal wave is doubled. The output signal 661a of the charge / discharge circuit 661 is input to the trapezoidal wave synthesis circuit 632, and trapezoid drive signals 632a to 632f are generated by the procedure described in the thirty-fifth embodiment.
As described above, if the mode switching signal 660a is switched corresponding to the command rotational speed, it is possible to change the inclination time of the trapezoidal drive signals 632a to 632f corresponding to the command rotational speed input from the outside. is there.
[0244]
Example 37.
The rising and falling slopes of the trapezoidal drive signals 632a to 632f generated by the trapezoidal drive signal generation circuit 633 start from the rising and falling edges of the drive signals 9a to 9f. Therefore, the switching point of the drive current is delayed from the ideal commutation timing, and the torque generation efficiency is lowered. In the present embodiment, the configuration of the brushless motor drive circuit configured so that the phase of the rotor position signal detected from the terminal potential of each phase or the voltage difference between the phases becomes a leading phase corresponding to the slope time of the trapezoidal drive signal, The operation will be described.
[0245]
FIG. 118 is a block diagram showing the overall configuration of the brushless motor drive circuit of this embodiment. In the figure, the same components as those in FIG. 110 are denoted by the same reference numerals. In FIG. 118, a new element 670 is a comparison circuit having a configuration different from that of the comparison circuit 2.
FIG. 119 shows a specific configuration example of the comparison circuit 670. In the figure, 671 to 685 are resistors, and 686 to 688 are differential amplifier circuits.
[0246]
Hereinafter, a specific operation of the comparison circuit 670 will be described.
As an example, consider a case where the resistors 671 to 685 are set to the values shown in FIG. At this time, the output signal 686a of the differential amplifier circuit 686 is 1a + 1b-2 × 1c, the output signal 687a of the differential amplifier circuit 687 is 1b + 1c-2 × 1a, and the output signal 688a of the differential amplifier circuit 688 is 1c + 1a-2. × 1b.
Assuming that 1a, 1b, and 1c are three-phase signals that are out of phase by 2π / 3 as shown in Equation (10), the output signals 686a, 687a, and 688a of the differential amplifier circuits 686, 687, and 688 are Equations (11), (12), and (13) are obtained. The output signals 686a, 687a and 688a of the differential amplifier circuits 686, 687 and 688 are respectively compared with Vref by the comparators 85, 86 and 87 to obtain logic signals 670a, 670b and 670c.

[0247]
Here, the specific operation of the comparison circuit 2 will be described again.
Consider a case where the resistors 70 to 81 are all set to 10 KΩ. At this time, the output signal of the differential amplifier circuit 82 is 1a-1c, the output signal of the differential amplifier circuit 83 is 1b-1a, and the output signal of the differential amplifier circuit 84 is 1c-1b, respectively, (15) and (16). The output signals of the differential amplifier circuits 82, 83, and 84 are 82a, 83a, and 84a. The output signals 82a, 83a, 84a of the differential amplifier circuits 82, 83, 84 are compared with Vref by the comparators 85, 86, 87, respectively, and logic signals 2a, 2b, 2c are obtained.

[0248]
The output signals 686a, 687a, 688a of the differential amplifier circuits 686, 687, 688 have a π / 6 phase advance with respect to the output signals 82a, 83a, 84a of the differential amplifier circuits 82, 83, 84. Therefore, the comparison circuit 670 can obtain the logic signals 670a, 670b, and 670c whose phase is advanced by π / 6 from the logic signals 2a, 2b, and 2c output from the comparison circuit 2.
In this embodiment, the values of the resistors 671 to 685 are set to the values shown in FIG. 119. However, if the resistors 671 to 685 are changed, another phase advance amount can be set. In this way, the phase of the rotor position signal is advanced so that the switching point of the drive current matches the ideal commutation timing.
In this embodiment, the configuration example using the charging / discharging circuit 631 is shown, but it is of course possible to configure using the charging / discharging circuit 661.
[0249]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
[0250]
Since the position signal is obtained by correcting the correction value determined by the armature winding current for the actual driving period without using the neutral point, there are few lead lines and the correct driving timing without phase delay can be determined. effective.
[0251]
Since the position signal is obtained from the voltage difference between the phases by correcting the correction value determined by the armature winding current only during the actual driving period without using the neutral point, there are few lead lines and there is no phase delay. There is an effect that the drive timing can be determined.
[0252]
Further, since the speed equivalent signal is obtained from the position signal, the speed can be controlled with a simple device in addition to the above.
[0253]
Further, since the actual driving period is the period in which the driving signal is in the driving state, there is an effect that the phase delay can be corrected more correctly.
[0254]
Further, since the actual driving period for correcting the voltage difference between the phases is the period in which the drive signal is in the driving state, there is an effect that the phase delay can be corrected more correctly.
[0255]
Further, since the correction voltage is taken from the resistance for detecting the current flowing through the armature winding, there is an effect that the phase delay can be corrected more correctly.
[0256]
Further, since the correction voltage is taken from the resistance for detecting the current flowing through the armature winding, there is an effect that the phase delay of the voltage difference between the phases can be corrected more correctly.
[0257]
Further, since the position signal is latched to obtain a new position signal, there is an effect that a correct position signal can be detected even if there is noise in the detection signal.
[0258]
The rising and falling edge signals of the position signal are selected, counted and combined to form a drive signal, and forcibly counting when there is no input.
[0259]
Select edge signal of rising / falling position signal, count and combine to make driving signal, force counting when no input, and restart when rotation is abnormal, so when abnormal during rotation Also has the effect of being able to restart.
[0260]
Since the switching between the start / restart and the steady state is switched at a predetermined time, there is an effect that the steady operation can be surely performed.
[0261]
Since the switching between the start / restart and the steady state is switched by the counter value of the counter, there is an effect that the steady operation can be surely performed.
[0262]
Since the switching between the start / restart and the steady state is performed when the rotor reaches a certain speed, there is an effect that the steady operation can be surely performed.
[0263]
Since the switching between the start / restart and the steady state is performed when the detection position signal has a predetermined combination, there is an effect that the steady operation can be surely performed.
[0264]
Since the switching between the start / restart and the steady state is performed when the drive signals to the armature windings are in a predetermined combination, there is an effect that the steady operation can be surely performed.
[0265]
Switching between starting / restarting and steady state is a combination of a predetermined time, count-up value, reaching a predetermined speed, a combination of detection position signal or drive signal to armature winding Since switching is performed when the above condition is satisfied, there is an effect that the operation can be shifted to steady operation more reliably.
[0266]
The position signal to the counter is monitored, the count is forcibly performed when there is no input, and the restart is performed when the rotation is abnormal, so that it is possible to restart even when the rotation is abnormal.
[0267]
Since the drive signal at the time of start-up / restart-up is based on the position signal from another position detector set at a certain electrical angle, there is an effect that correct start-up can be surely obtained even at the time of start-up.
[0268]
Since the drive signal at the time of start-up / restart-up is based on the position signal from another position detector set at a certain electrical angle, there is an effect that correct start-up can be surely obtained even at the time of start-up.
[0269]
Since the logic signal obtained by comparing the terminal potentials is differentiated and latched, and the latch is released after a predetermined time, there is an effect that a correct rotor position signal can be obtained even if there is noise in the detection signal.
[0270]
Further, since the timer time length is made variable, there is an effect that stable commutation control can be performed by masking noise with an appropriate time as a transition time.
[0271]
When starting, restarting, or rotating abnormally, the forced energization phase for normal rotation of the motor is switched for a predetermined time, so that there is an effect that the start can be reliably performed in a short time without being influenced by the load conditions.
[0272]
Since the switching from the start mode to the steady rotation mode is set by the timer, there is an effect that the mode can be surely shifted to the steady rotation mode.
[0273]
Since a speed error compensation filter configuration in which a PI filter and a first-order lag filter are connected in parallel to each other and a first-order lag filter are connected in series is used, there is an effect that a good low-frequency disturbance compression characteristic can be obtained.
[0274]
Since the PI filter has a speed error compensation filter configuration in which a first-order lag filter is connected in series to a PI filter and a first-order lag filter is connected in parallel, there is an effect that a good low-frequency disturbance compression characteristic can be obtained.
[0275]
Since the target value of the speed error detector or the gain of the speed error compensation filter is switched according to the command rotational speed to the motor, there is no need to change the period of the reference clock input to the speed error detector. There is.
[0276]
Since the increase and decrease of the amount of current supplied to the armature winding is configured to be performed within a predetermined time after switching the energized phase, the process of correcting the terminal potential by feeding back the current value is easy There is an effect that can be done.
[0277]
Since the maximum current is supplied to the armature winding during the start-up and restart periods, there is an effect that the start-up can be reliably performed in a short time.
[0278]
Since the required signal within the rising and falling edges of the rotor position signal is selected and the armature winding is driven by the counter value that counts this required signal, it can be started up in a short time and reliably. There is an effect of shifting to steady operation.
[0279]
Since the armature winding is applied and driven with a trapezoidal drive signal, noise during commutation can be reduced.
[0280]
Since the slope of the trapezoidal drive signal is changed by the control signal from the outside, there is an effect that the noise at the time of commutation can be surely reduced even if the rotational speed of the motor is changed.
[0281]
Since the phase of the rotor position signal is advanced so that the approximate gradient center of the trapezoidal drive signal coincides with the optimal commutation timing, the noise can be reduced without reducing the torque generation efficiency. is there.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the overall configuration of a first embodiment of a brushless motor driving apparatus according to the present invention.
FIG. 2 is a diagram illustrating a specific configuration example of a terminal potential correction circuit.
FIG. 3 is a diagram illustrating a specific configuration example of a comparison circuit according to the first embodiment.
FIG. 4 is a signal waveform diagram for explaining the operation of the first and second embodiments.
FIG. 5 is a signal waveform diagram for explaining the operation of the first and second embodiments.
FIG. 6 is a configuration diagram of a correction switching signal generation circuit and a signal waveform diagram of a terminal potential circuit.
FIG. 7 is a diagram illustrating a relationship between an energized phase and a drive signal.
FIG. 8 is a block diagram showing an overall configuration of a second embodiment of the brushless motor driving apparatus of the present invention.
FIG. 9 is a diagram illustrating a specific configuration example of an inter-terminal voltage correction circuit.
FIG. 10 is a table for explaining the operation of the inter-terminal voltage correction circuit.
FIG. 11 is a diagram illustrating a specific configuration example of a comparison circuit according to the second embodiment.
FIG. 12 is a table for explaining the operation of the inter-terminal voltage correction circuit.
FIG. 13 is a block diagram showing an overall configuration of Embodiment 3 of the brushless motor driving apparatus of the present invention.
FIG. 14 is a block diagram showing an overall configuration of Embodiment 4 of the brushless motor driving apparatus of the present invention.
FIG. 15 is a block diagram showing an overall configuration of a fifth embodiment of the brushless motor driving apparatus of the present invention.
FIG. 16 is a block diagram showing an overall configuration of Embodiment 6 of the brushless motor driving apparatus of the present invention.
FIG. 17 is a diagram illustrating a specific configuration example of a waveform shaping circuit.
FIG. 18 is a signal waveform diagram for explaining the operation of the waveform shaping circuit.
FIG. 19 is a signal waveform diagram for explaining the operation of the waveform shaping circuit.
FIG. 20 is a block diagram showing an overall configuration of an eighth embodiment of the brushless motor driving apparatus of the present invention.
FIG. 21 is a table showing the relationship between drive signals and energized phases in Example 8.
22 is a table showing a relationship between a drive signal and a rotor position signal in Example 8. FIG.
FIG. 23 is a diagram illustrating a specific configuration example of a counter circuit according to an eighth embodiment.
FIG. 24 is a table for explaining the operation of the counter circuit according to the eighth embodiment.
FIG. 25 is a table for explaining the operation of the counter circuit according to the eighth embodiment.
FIG. 26 is a diagram illustrating a specific configuration example of a pulse generation circuit according to an eighth embodiment.
27 is a table showing the relationship between the drive signal and the output value of the counter circuit in Example 8. FIG.
FIG. 28 is a timing chart for explaining the operation of the eighth embodiment.
FIG. 29 is a timing chart for explaining the operation of the eighth embodiment.
FIG. 30 is a block diagram showing an overall configuration of a ninth embodiment of the brushless motor driving apparatus of the present invention.
FIG. 31 is a table showing a relationship between a rotor position signal and a counter value.
FIG. 32 is a timing chart for explaining the operation of the ninth embodiment.
FIG. 33 is a block diagram showing an overall configuration of a tenth embodiment of the brushless motor driving apparatus according to the present invention.
FIG. 34 is a diagram illustrating a specific configuration example of a switching signal generation circuit according to the tenth embodiment.
FIG. 35 is a timing chart for explaining the operation of the switching signal generating circuit according to the tenth embodiment;
FIG. 36 is a block diagram showing an overall configuration of an eleventh embodiment of the brushless motor driving apparatus according to the present invention.
FIG. 37 is a diagram illustrating a specific configuration example of a switching signal generation circuit according to an eleventh embodiment.
FIG. 38 is a timing chart for explaining the operation of the switching signal generating circuit according to the eleventh embodiment;
FIG. 39 is a block diagram showing an overall configuration of a twelfth embodiment of the brushless motor driving apparatus of the present invention.
FIG. 40 is a diagram illustrating a specific configuration example of a switching signal generation circuit according to a twelfth embodiment.
FIG. 41 is a timing chart for explaining the operation of the switching signal generation circuit according to the twelfth embodiment;
FIG. 42 is a block diagram showing an overall configuration of a thirteenth embodiment of the brushless motor driving apparatus according to the present invention.
FIG. 43 is a diagram illustrating a specific configuration example of a switching signal generation circuit according to the thirteenth embodiment.
FIG. 44 is a timing chart for explaining the operation of the switching signal generating circuit according to the thirteenth embodiment;
FIG. 45 is a block diagram showing an overall configuration of a fourteenth embodiment of the brushless motor driving apparatus according to the present invention.
FIG. 46 is a diagram illustrating a specific configuration example of a switching signal generation circuit according to the fourteenth embodiment.
FIG. 47 is a timing chart for explaining the operation of the switching signal generation circuit according to the fourteenth embodiment;
FIG. 48 is a block diagram showing an overall configuration of a fifteenth embodiment of the brushless motor driving apparatus according to the present invention.
FIG. 49 is a diagram illustrating a specific configuration example of a switching signal generation circuit according to the fifteenth embodiment.
FIG. 50 is a timing chart for explaining the operation of the switching signal generation circuit according to the fifteenth embodiment;
FIG. 51 is a block diagram showing an overall configuration of Embodiment 16 of a brushless motor driving apparatus of the present invention.
52 is a diagram illustrating a specific configuration example of a switching signal generation circuit according to the sixteenth embodiment. FIG.
FIG. 53 is a timing chart for explaining the operation of the speed signal generation circuit;
FIG. 54 is a timing chart for explaining the operation of the switching signal generating circuit of the sixteenth embodiment.
FIG. 55 is a block diagram showing an overall configuration of a seventeenth embodiment of the brushless motor driving apparatus according to the present invention.
FIG. 56 is a diagram illustrating a specific configuration example of a switching signal generation circuit according to the seventeenth embodiment;
FIG. 57 is a timing chart for explaining the operation of the switching signal generation circuit according to the seventeenth embodiment;
FIG. 58 is a block diagram showing an overall configuration of Embodiment 18 of the brushless motor driving apparatus of the present invention.
FIG. 59 is a diagram illustrating a specific configuration example of a switching signal generation circuit according to an eighteenth embodiment.
FIG. 60 is a timing chart for explaining the operation of the switching signal generating circuit of the eighteenth embodiment.
FIG. 61 is a block diagram showing an overall configuration of a nineteenth embodiment of the brushless motor driving apparatus according to the present invention.
FIG. 62 is a diagram illustrating a specific configuration example of a switching signal generation circuit according to the nineteenth embodiment.
FIG. 63 is a timing chart for explaining the operation of the switching signal generating circuit according to the nineteenth embodiment.
FIG. 64 is a block diagram showing an overall configuration of a twentieth embodiment of a brushless motor driving apparatus of the present invention.
FIG. 65 is a diagram illustrating a specific configuration example of a switching signal generation circuit according to the twentieth embodiment;
66 is a timing chart for explaining the operation of the switching signal generating circuit according to the twentieth embodiment; FIG.
67 is a block diagram showing the overall configuration of Example 21. FIG.
68 is a block diagram showing an overall configuration of a brushless motor drive apparatus according to Embodiment 22 of the present invention. FIG.
FIG. 69 is a timing chart for explaining the operation of Example 22;
FIG. 70 is a table for explaining operation of Example 22;
FIG. 71 is a diagram illustrating a specific configuration example of a counter circuit according to the twenty-second embodiment;
FIG. 72 is a table for explaining operation of Example 22;
FIG. 73 is a timing chart for explaining the operation of Example 22;
74 is a timing chart for explaining the operation of Example 22. FIG.
75 is a block diagram showing an overall configuration of a twenty-third embodiment of the brushless motor driving apparatus of the present invention. FIG.
FIG. 76 is a timing chart for explaining the operation of Example 23;
77 is a timing chart illustrating the operation of Example 23. FIG.
78 is a block diagram showing an overall configuration of a brushless motor driving apparatus according to Embodiment 24 of the present invention. FIG.
FIG. 79 is a diagram showing signal waveforms of respective parts of the terminal potential correction circuit in a steady rotation state of the brushless motor driving device of the present invention.
80 is a diagram illustrating a configuration example of a waveform shaping circuit in FIG. 78. FIG.
FIG. 81 is a diagram showing a terminal potential waveform and a waveform of each part of the waveform shaping circuit in steady rotation.
82 is a signal waveform diagram for explaining the operation of the waveform shaping circuit of FIG. 80. FIG.
FIG. 83 is a signal waveform diagram for explaining operations of a mask signal generating circuit and a timer according to Example 25;
84 is a signal waveform diagram for explaining operations of a mask signal generating circuit and a timer according to Example 25. FIG.
FIG. 85 is a signal waveform diagram for explaining operations of a mask signal generating circuit and a timer according to Example 25;
FIG. 86 is a diagram showing a configuration of a startup circuit of Example 26.
87 is a diagram showing a configuration of a pseudo pulse generating circuit in Example 26. FIG.
88 is a signal waveform diagram for explaining the operation of the pseudo pulse generating circuit of the twenty-sixth embodiment. FIG.
89 is a diagram illustrating a configuration example of a restart pulse generation circuit according to a twenty-sixth embodiment. FIG.
90 is a signal waveform chart for explaining the operation of Example 26. FIG.
FIG. 91 is a diagram illustrating a configuration of a startup circuit according to a twenty-seventh embodiment.
FIG. 92 is a diagram showing a configuration of a switching signal generating circuit in Example 27;
FIG. 93 is a signal waveform diagram representing an operation of the switching signal generating circuit.
94 is a block diagram of a speed error compensation filter according to Embodiment 28. FIG.
FIG. 95 is a diagram illustrating frequency characteristics of the speed error compensation filter according to the twenty-eighth embodiment.
96 is a block diagram of a digital speed error compensation filter according to Embodiment 28. FIG.
97 is a block diagram of a speed error compensation filter according to Embodiment 29. FIG.
FIG. 98 is a diagram illustrating frequency characteristics of the speed error compensation filter according to the twenty-ninth embodiment.
FIG. 99 is a block diagram of a digital speed error compensation filter according to a twenty-ninth embodiment.
FIG. 100 is a block diagram illustrating an overall configuration of a brushless motor drive circuit according to a thirtieth embodiment of the present invention.
FIG. 101 is a diagram illustrating a configuration of a speed error detection circuit according to a thirtieth embodiment.
102 is a block diagram of a PI filter of Example 31. FIG.
103 is a signal waveform chart for explaining the operation of the brushless motor drive circuit of Example 32. FIG.
FIG. 104 is a block diagram showing an overall configuration of a brushless motor drive circuit according to a thirty-third embodiment of the present invention.
105 is a diagram showing a configuration of a speed error compensation filter according to Embodiment 33. FIG.
FIG. 106 is a block diagram showing an overall configuration of a 34th embodiment of the brushless motor drive circuit of the present invention.
FIG. 107 is a diagram illustrating a configuration of a pulse selection circuit according to a thirty-fourth embodiment.
FIG. 108 is a timing chart illustrating the operation of the drive circuit according to the thirty-fourth embodiment.
FIG. 109 is a timing chart illustrating the operation of the drive circuit according to the thirty-fourth embodiment.
FIG. 110 is a block diagram showing an overall configuration of a brushless motor drive circuit according to a thirty-fifth embodiment of the present invention.
FIG. 111 is a diagram illustrating a configuration of a logic circuit in a trapezoidal drive signal generation circuit.
112 is a diagram showing the structure of a charge / discharge circuit of Example 35. FIG.
FIG. 113 is a timing chart illustrating the operation of the drive circuit according to the thirty-fifth embodiment.
FIG. 114 is a diagram showing a configuration of a trapezoidal wave synthesis circuit in the trapezoidal drive signal generation circuit.
FIG. 115 is a block diagram showing an overall configuration of a 36th embodiment of the brushless motor drive circuit of the present invention.
116 is a diagram showing the structure of the charge / discharge circuit of Example 36. FIG.
117 is a signal waveform diagram for explaining operation of the drive circuit in Example 36; FIG.
FIG. 118 is a block diagram showing an overall configuration of Embodiment 37 of a brushless motor drive circuit of the present invention.
119 is a diagram showing a configuration of a comparison circuit of Example 37. FIG.
FIG. 120 is a block diagram showing an overall configuration of a conventional brushless motor drive device.
FIG. 121 is a diagram showing another overall configuration and operation timing of a conventional brushless motor drive device.
FIG. 122 is a block diagram showing a configuration of a speed control system of a conventional brushless motor drive circuit.
FIG. 123 is a block diagram of a speed error compensation filter of a conventional brushless motor drive circuit.
[Explanation of symbols]
1 terminal potential correction circuit, 2 comparison circuit, 3 waveform shaping circuit, 4 rotor position signal generation circuit, 5 terminal, 6 pulse generation circuit, 7 counter circuit, 8, 8C, 8D, 8E, 8F, 8G, 8H, 8I , 8J, 8K, 8L switching signal generation circuit, 9 commutation circuit, 10 resistor, 11 bridge circuit, 12, 13, 14 armature winding, 16 correction switching signal generation circuit, 20-34 npn transistor, 35 pnp transistor, 36-56 resistance, 57-60 constant current source, 61-67 terminals, 70-81 resistance, 82-84 differential amplifier, 85-87 comparator, 100 terminal voltage correction circuit, 101 comparison circuit, 102 rotor position signal Generator circuit, 110-127 npn transistor, 128 pnp transistor, 129-155 resistance, 156-162 constant current 163 to 169 terminals, 170 to 172 comparators, 180 latch circuits, 181 to 186 D flip-flops, 187 to 189 EOR circuits, 190 OR circuits, 191 monostable multivibrators, 210 commutation control circuits, 211 current control circuits, 212 Buffer amplifier, 213 Resistor, 214 Transistor, 250, 252, 254 Rising edge detection circuit, 251, 253, 255 Falling edge detection circuit, 256 Pulse selection circuit, 257 Hexadecimal counter, 260 Retriggerable one-shot, 261 Rising edge detection Circuit, 265 steady rotation detection circuit, 270 timer, 271 mode switching counter, 272 position signal combination determination circuit, 273 AND circuit, 274 latch circuit, 275 drive signal combination Control circuit, 276 reference speed generation circuit, 277 speed signal generation circuit, 278 comparison circuit, 280 position signal counter value determination circuit, 300 position detector, 301 hold circuit, 302 edge detection circuit, 406, 406B start circuit, 409 speed Error detection circuit, 410 speed error compensation filter, 411 current supply circuit, 421 mask signal generation circuit, 422 timer, 431 pseudo pulse generation circuit, 432 restart pulse generation circuit, 433 counter, 434 gate circuit, 435 rising edge detection circuit, 436 delay circuit, 437 OR circuit, 440 rising edge detection circuit, 441 OR circuit, 442 counter, 443 gate circuit, 444 rising edge detection circuit, 445 AND circuit, 446 OR circuit, 450 switching signal Generator circuit, 451 rising edge detection circuit, 452 OR circuit, 453 counter, 454 gate circuit, 455 OR circuit, 460 PI filter, 461 primary delay filter, 462 gain element, 463 adder, 464 primary delay filter, 470, 471, 472 Delay element, 473, 474, 475, 476, 477, 478, 479 Gain element, 481, 482, 483 Adder, 484 PI filter, 485, 486 First-order lag filter, 487, 488 Adder, 490 terminals 491, 492 Initial value register, 493 selector, 494 counter, 495, 496 gain element, 497, 498 selector, 600 microcontroller, 601 D / A converter, 602 register group, 609 pulse selection circuit, 610 conversion Current circuit, 611 to 613 inversion circuit, 614 to 625, 3-input AND circuit, 626, 6-input OR circuit, 630 logic circuit, 631, charge / discharge circuit, 632 trapezoidal wave synthesis circuit, 633 trapezoidal drive signal generation circuit, 635-643 AND circuit 644 3-input OR circuit, 645, 646 constant power supply, 647 capacitor, 648 to 651 inverting amplifier circuit, 652 to 657 NAND circuit, 660 terminal, 661 charge / discharge circuit, 662 inverting circuit, 663, 664 constant current source, 670 Comparison circuit, 671-685 resistance, 686-688 differential amplifier circuit.

Claims (32)

The rotor is driven by a plurality of windings of star-connected armatures,
A driving voltage for driving the rotor is applied between the plurality of windings, and a winding in a phase to which a current is sent by the driving voltage is used as a sending-side conduction winding, and a winding in a phase into which a current flows is provided. As the inflow side energization winding, the winding of the phase where the drive voltage is not applied as the non-energization winding,
The correction value determined by the resistance of the armature winding and the winding current is subtracted from the detection terminal potential of the sending-side energization winding , and the correction value is applied to the detection terminal potential of the inflow-side energization winding. Each phase terminal potential correction means for adding the driving period ;
Comparing means for comparing the magnitude of each phase terminal potential after correcting each phase terminal potential, and driving for a brushless motor that applies and drives the armature winding of each phase with the rotor position signal detected by the comparing means circuit. The rotor is driven by a plurality of windings of star-connected armatures,
A driving voltage for driving the rotor is applied between the plurality of windings, and a winding in a phase to which a current is sent by the driving voltage is used as a sending-side conduction winding, and a winding in a phase into which a current flows is provided. As the inflow side energization winding, the winding of the phase where the drive voltage is not applied as the non-energization winding,
When the sending-side energization winding changes from the energized state to the non-energized state, the correction value determined by the resistance of the armature winding and the winding current is subtracted from the detection terminal potential in the energized state, When the inflow energization winding changes from the energized state to the non-energized state, the correction value is added to the detection terminal potential in the energized state for the actual driving period to correct the winding terminal voltage difference between the phases. Phase voltage difference correction means;
A brushless motor drive circuit, comprising: a comparing means for comparing the magnitudes of the voltage differences between the phases after the correction, and for applying and driving the armature windings of the respective phases with a rotor position signal detected by the comparing means.   3. The brushless motor drive circuit according to claim 1, further comprising means for detecting a rising / falling signal of the rotor position signal, and performing speed feedback control by regarding the detection result as a detected speed signal.   2. The brushless motor according to claim 1, wherein a period in which a drive signal to a bridge circuit for exciting and driving an armature winding of each phase is in a drive state is given to each phase terminal potential correcting means as an actual drive period signal. Drive circuit.   3. A brushless motor according to claim 2, wherein a period during which a drive signal to a bridge circuit for exciting and driving an armature winding of each phase is in a drive state is given to each inter-phase voltage difference correcting means as an actual drive period signal. Drive circuit.   An actual current detection resistor connected in series to a bridge circuit for exciting and driving the armature winding is provided, and a current flowing through the detection resistor is supplied to each phase terminal potential correcting means as a winding current. The drive circuit for brushless motors as described.   3. An actual current detection resistor connected in series to a bridge circuit for exciting and driving the armature winding, and a current flowing through the detection resistor is applied to each phase voltage difference correction means as a winding current. The drive circuit for brushless motors as described.   A differentiating circuit for detecting a rising / falling edge of a comparison signal having a magnitude of each phase terminal potential or a magnitude of a voltage difference between phases; and a latch circuit for latching the comparison signal at a timing when the edge is detected by the differentiating circuit. 3. The drive circuit for a brushless motor according to claim 1, wherein the drive circuit is applied to drive the armature winding of each phase as a rotor position signal by combining the outputs of the latch circuits. Rotor position signal generating means for detecting a position signal of the rotor from each phase terminal potential or each phase potential difference of a brushless motor that drives the rotor with a multi-phase armature winding;
The rising / falling edge of the rotor position signal of the above output is detected, the required edge signal is selected from each detected edge signal as one of the outputs, and the necessary edge signal is counted to start each phase of the electric machine A counter as an applied drive signal for the slave winding;
As input one of the output of the counter, if the input is not obtained a predetermined time, comprising a pulse generating means for counting up the counter, to make the impression drive of the armature winding at the counter output at starting 3. The brushless motor drive circuit according to claim 1 , wherein the drive circuit is a brushless motor drive circuit. The motor rotation is monitored by a combination of the rotor position signal and the counter output, and is provided with a steady rotation detecting means for outputting a restart pulse when the rotation is abnormal, and the armature is detected by the counter output when the rotation is abnormal. The drive circuit for a brushless motor according to claim 9, wherein the winding is applied and driven.   Switching means and a timer are provided for switching to drive the armature winding of each phase based on the counter value at the time of starting or restarting, and based on the rotor position signal at the subsequent steady state, and the starting or restarting period is set as described above. 11. The brushless motor driving circuit according to claim 9, wherein the switching is performed by a timer.   Switching means is provided for switching to drive the armature winding of each phase based on the value of the counter at the time of starting or restarting, and based on the rotor position signal at the subsequent steady state, and the counter becomes a predetermined value 11. The drive circuit for a brushless motor according to claim 9, wherein switching is performed when the start or restart period ends.   Switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of startup or restart, and based on the rotor position signal at the time of subsequent steadying, and a speed signal detection means for the rotor are provided, 11. The brushless motor drive circuit according to claim 9, wherein the detected speed signal is switched when the start-up or restart period ends when the speed signal reaches a predetermined value.   Switching means is provided for switching to drive the armature winding of each phase based on the counter value at the time of starting or restarting and based on the rotor position signal at the subsequent steady state, and the detected rotor position signal is predetermined. 11. The drive circuit for a brushless motor according to claim 9, wherein switching is performed when the start-up or restart period ends when the combination value is reached.   Switching means for switching to drive the armature winding of each phase based on the value of the counter at the time of starting or restarting and based on the rotor position signal at the subsequent steady state is provided. 11. The drive circuit for a brushless motor according to claim 9, wherein the drive signal is switched when the start-up or restart period ends when a predetermined combination of values is reached.   Switching means for switching to drive the armature winding of each phase based on the counter value at start-up or restart, and based on the rotor position signal at the subsequent steady state, and the speed of the timer or rotor as required A signal detecting means is provided, the timer set time elapses or the speed signal detection value becomes a predetermined value, the counter becomes a predetermined value, or the detected rotor position signal becomes a predetermined combination value or each phase The brushless according to claim 9 or 10, wherein the switching is performed as the start-up or restart period ends when a plurality of things that the drive signals to the armature winding become a predetermined combination are established. Motor drive circuit.   When the rotor position signal input to the counter does not change for a predetermined time, the counter is a counter that outputs a restart pulse as a rotation abnormality to start, and forcibly counts up. The brushless motor drive circuit according to claim 9.   A position detector that detects a position shifted by an electrical angle of π / 6 with respect to the rotor position signal detected from each phase terminal potential or each phase voltage difference, and a selection signal determined by the output of the position detector and the start instruction signal 10. A drive circuit for a brushless motor according to claim 9, wherein a hold circuit is provided, and at the time of start-up or restart, the counter determines a combination of drive signals to the armatures of each phase by the selection signal. .   A position detector that detects a position shifted by an electrical angle of π / 6 with respect to the rotor position signal detected from each phase terminal potential or each phase voltage difference, and a selection signal determined by the output of the position detector and the start instruction signal The position detector output is used for the drive signal to the first armature at the time of start-up or restart, and the counter uses the selection signal for drive at the time of subsequent start-up or restart. The drive circuit for a brushless motor according to claim 9, wherein a signal that determines a combination of drive signals to the armature of each phase is used.   A differential circuit that detects the rising and falling edges of the comparison signal of each phase terminal potential or each phase voltage difference, a timer that operates by detecting the edge of the differential circuit and stops after a predetermined time, and the differential circuit A latch circuit is provided that latches the comparison signal when the edge is detected and releases the latch when the timer stops, and combines the output of the latch circuit as a rotor position signal for each phase armature winding. 3. The brushless motor driving circuit according to claim 1, wherein application driving is performed.   21. The drive circuit for a brushless motor according to claim 20, wherein the length of a timer time from when the latch circuit latches the comparison signal to when the latch is released is changed based on a command rotational speed to the armature. A rotor position signal generating means for detecting a rotor position signal from each phase terminal potential or each phase voltage difference of a plurality of phases;
The rising / falling edge of the output rotor position signal is detected, a necessary edge signal is selected from each detected edge signal, an output pulse train is provided, and if the necessary edge signal cannot be obtained for a predetermined time, a pseudo pulse train Pulse generating means for providing
A counter for counting the pulse generating means output;
Steady rotation detection means for outputting a rotation abnormality signal when the relationship between the rotor position signal and the value of the counter is not a predetermined relationship;
Masking the abnormal rotation signal of the steady rotation detection means within a set time after starting and restarting, and providing a restart pulse generating means for outputting a restart pulse based on the abnormal rotation signal after the set time has elapsed. 3. The brushless motor drive circuit according to claim 1 , wherein the armature winding is applied and driven by the counter output within a set time at the time of restart by the restart pulse.   Switching means and a timer are provided for switching to drive the armature winding of each phase based on the counter value at the time of starting or restarting, and based on the rotor position signal at the subsequent steady state, and the starting or restarting period is set as described above. The brushless motor driving circuit according to claim 22, wherein the switching is performed by setting with a timer. Speed detecting means for detecting the speed at which the rotor is rotating;
A speed error detecting means for outputting a difference between the detected actual rotational speed of the rotor and the target rotational speed as a speed error signal;
The detected speed error signal is used as an input, and the configuration thereof includes a parallel circuit of a proportional / integral (PI) filter and a first-order lag filter, and a first-order lag filter having an input value of each output of the parallel circuit as an input. 3. The brushless motor drive circuit according to claim 1, further comprising a speed error compensation filter which is a series circuit and uses the added first-order lag output as a current command value to the armature winding. Speed detecting means for detecting the speed at which the rotor is rotating;
A speed error detecting means for outputting a difference between the detected actual rotational speed of the rotor and the target rotational speed as a speed error signal;
The detected speed error signal is input, and the configuration is a parallel circuit of a series circuit of a proportional / integral (PI) filter and a first-order lag filter, and a first-order lag filter provided separately from the series circuit, 3. The brushless motor drive circuit according to claim 1, further comprising a speed error compensation filter that uses an added value of each output of the parallel circuit as a current command value to the armature winding. Speed detecting means for detecting the speed at which the rotor is rotating;
A speed error detecting means for outputting a difference between the detected actual rotational speed of the rotor and the target rotational speed as a speed error signal;
A speed error compensation filter that obtains a current command value to the armature winding from the detected speed error signal, and a target rotational speed of the speed error detecting means according to a command rotational speed to the brushless motor drive circuit; 3. The brushless motor drive circuit according to claim 1 , wherein the gain of the speed error compensation filter is changed. A rotor position detecting means for detecting a relative position between the armature winding and the rotor;
Commutation control means for switching the energized phase at the detected rotor position;
Speed detecting means for detecting the speed at which the rotor is rotating;
A speed error detecting means for outputting a difference between the detected actual rotational speed of the rotor and the target rotational speed as a speed error signal;
A speed error compensation filter for obtaining a current command value to the armature winding from the detected speed error signal, and switching the energized phase by the commutation control means, and a current command value to the armature winding after a predetermined time. The brushless motor drive circuit according to claim 1 , wherein the increase / decrease is performed.   The brushless motor drive circuit according to any one of claims 1 to 27, wherein a maximum current is applied to the armature winding during the start-up and restart periods. A rotor position signal generating means for detecting a rotor position signal from each phase terminal potential or each phase voltage difference of a plurality of phases;
The rising / falling edge of the output rotor position signal is detected, a necessary edge signal is selected from each detected edge signal, an output pulse train is provided, and if the necessary edge signal cannot be obtained for a predetermined time, a pseudo pulse train 3. A brushless motor for a brushless motor according to claim 1 , further comprising: a pulse generating means for providing an output, and a counter for counting the output of the pulse generating means, and applying and driving the armature winding by the counter output. Driving circuit. Armature winding from the rotor position signal detected by the rotor position signal detection means including the comparison means for comparing the magnitude of each phase terminal potential or each phase voltage difference correction means and each phase terminal potential or each phase voltage difference of the output. A commutation circuit for obtaining a line drive signal;
The trapezoidal drive signal generation circuit which processes the commutation circuit output into a trapezoidal drive signal is further provided, and the trapezoidal drive signal is supplied to the armature winding. 2. A drive circuit for a brushless motor according to 2.   31. The trapezoidal drive signal generation circuit is provided with a charge / discharge circuit, and the slope of the trapezoidal drive signal is changed by changing the time constant of the charge / discharge circuit with an external control signal. Drive circuit for brushless motor.   A phase advance circuit for advancing the phase of the rotor position signal is provided, and the phase advance amount of the phase advance circuit is set to be approximately equivalent to a half of the gradient time of the trapezoid drive signal for driving the armature winding. The drive circuit for a brushless motor according to claim 30.

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