JP3622390B2 - Semiconductor memory device having ferroelectric capacitor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device having a plurality of ferroelectric capacitors capable of storing different storage data in one memory cell, and in particular, a three-dimensional arrangement structure of a plurality of ferroelectric capacitors and the capacitor. The present invention relates to a circuit configuration for selectively switching.
[0002]
[Prior art]
Conventionally, the ferroelectric memory element has a cell type in which one bit is composed of two selection transistors and two ferroelectric capacitors (2Tr-2Cap system), one selection transistor and one There were two types, one that constitutes one bit with one ferroelectric capacitor (1Tr-1Cap system).
The 2Tr-2Cap method has an advantage that a reference at the time of data reading can be set inside the cell, the data reading operation is hardly affected by variations in process and film characteristics, and low voltage operation is possible.
On the other hand, in the 1Tr-1Cap system, in order to make it suitable for high integration, the memory cell itself is simplified by sharing a cell serving as a reference for data reading for each pair of bit lines.
[0003]
[Problems to be solved by the invention]
As with other memory devices, these ferroelectric memory devices are also demanded to have a large capacity, and when increasing the overall storage capacity, how to minimize the increase in chip area is an important issue. Yes. For this reason, various studies such as the development of a ferroelectric thin film having a high dielectric constant and an increase in the electrode surface area have been promoted for the purpose of improving the capacitance value per unit area, and some results have been achieved.
However, even if it is attempted to increase the capacitance value per unit area of the ferroelectric memory element with the conventional cell format, the development of the ferroelectric thin film itself is difficult and the handling of the ferroelectric thin film is difficult. It is not easy to greatly increase the storage capacity value.
[0004]
The present invention has been made in view of such circumstances, and has proposed a new cell structure capable of greatly improving the memory capacity per unit area without increasing the cell area, and has a large capacity using the cell structure. An object is to provide a high-performance ferroelectric memory device.
[0005]
[Means for Solving the Problems]
In order to solve the above-described problems of the prior art and achieve the above object, in the ferroelectric memory device of the present invention, a plurality of ferroelectric capacitors having a common selection transistor are provided in a memory cell, A circuit for controlling which data is stored and which stored data is read is provided.
That is, in the ferroelectric memory device of the present invention, a selection transistor in which one of a source and a drain is connected to one of a pair of bit lines, and a storage node electrode on the other side of the source or drain of the selection transistor Are connected in parallel, and a plurality of ferroelectric capacitors each capable of storing different storage data constitute a memory cell, connected to the plate electrodes of the plurality of ferroelectric capacitors, and a word line is excited. And a plate line selection circuit for selectively connecting any plate electrode of the plurality of ferroelectric capacitors to the plate voltage supply line in accordance with an input plate line selection signal.
[0006]
It is preferable that the plurality of ferroelectric capacitors be disposed at a distance from each other in the direction perpendicular to the semiconductor substrate surface with the selection transistor interposed therebetween, because the memory capacity value per unit area can be at least twice that of the conventional one.
[0007]
When the selection transistor and the plurality of ferroelectric capacitors are arranged in a thick insulating layer on the semiconductor substrate, the selection transistor has an SOI (Silicon On Insulator) type element isolation structure, and the selection transistor High speed and low power consumption can be achieved, and electrical interference between the plate lines of the capacitor can be reduced, which is preferable.
[0008]
In the ferroelectric memory device having such a configuration, information of a plurality of bits can be stored in one memory cell, and a storage capacity several times that of the conventional one can be achieved. Further, by arranging the ferroelectric capacitors in three dimensions, it is possible to make the occupied area equal or suppress the increase in area as much as possible. In addition, it is possible to improve the performance of the selection transistor, and as a result, it is easy to realize a ferroelectric memory device capable of high-speed operation with a large capacity.
[0009]
On the other hand, when two ferroelectric capacitors are provided in the memory cell, a specific configuration of the plate line selection circuit for selectively connecting the ferroelectric capacitor to the plate line is a connection path between each plate electrode and the plate voltage supply line. Control gates can be provided in the middle, and the two control gates can be inverted by a plate line selection signal.
That is, the plate line selection circuit in this case includes an AND gate in which the word line is connected to the first input terminal, the plate line selection signal is connected to the second input terminal, and the two ferroelectric capacitors. Between the first plate gate and the plate voltage supply line, the gate of which is connected to the output of the AND gate, and the other plate electrode and the plate voltage supply line. And an output of the AND gate is connected to the gate via an inverter, and a second control gate that performs an inverting operation with respect to the first control gate is provided.
[0010]
In addition, it is preferable that these control gates have a transmission gate configuration that operates according to a plate line selection signal and its inverted signal because it is possible to reduce the impedance when conducting and to increase the impedance when not conducting.
That is, in the plate line selection circuit in this case, the AND gate is composed of a first AND gate and a second AND gate each having the first input terminal and the second input terminal, respectively. The AND line of 1 is supplied with the plate line selection signal at its second input terminal, and its output is connected to the gate of the transistor that constitutes the first control gate. An inverted signal of the plate line selection signal is input to a second input terminal, and an output thereof is connected to a gate of a transistor constituting the second control gate via the inverter, thereby constituting the first control gate. The first transistor is connected to the first transistor together with the reverse conductivity type transistor in which the output of the first AND gate is connected to the gate through the inverter. The transistor constituting the transmission gate and the second control gate constitutes the second transmission gate together with the reverse conductivity type transistor in which the output of the second AND gate is connected to the gate. It is characterized by that.
[0011]
Such a plate line selection circuit has a simple circuit configuration, and the 1Tr-2Cap type ferroelectric memory device newly proposed in the present invention for the purpose of increasing the memory capacity per unit area is included in the memory cell. It is suitable as a capacitor switching circuit.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a ferroelectric memory device (ferroelectric memory) according to the present invention will be described in detail with reference to the drawings.
As described above, the ferroelectric memory according to the present invention has a plurality of ferroelectric capacitors capable of storing different data in each memory cell, and a circuit for controlling the selection is provided. It is in. Therefore, there is no limitation on the number of ferroelectric capacitors in the memory cell, and the arrangement thereof is not particularly limited. However, in order to suppress an increase in cell area, it is desirable to arrange the capacitors three-dimensionally in a direction perpendicular to the substrate surface.
[0013]
Here, the present invention will be described by taking as an example a case where two ferroelectric capacitors are provided vertically symmetrically across a common selection transistor, and the memory capacity can be doubled without changing the cell area.
FIG. 1A is an equivalent circuit diagram showing a memory cell configuration example of the ferroelectric memory device of the present invention, and FIG. 1B is a circuit diagram showing a configuration example of a plate line selection circuit.
In the figure, reference numeral 1 denotes a memory cell of a ferroelectric memory, and 2 denotes a selection transistor. C ₀ and C ₁ represent two ferroelectric capacitors, an electrode serving as a storage node thereof (referred to as a storage node electrode in the present invention) is indicated by reference numeral 3, and a plate electrode thereof is indicated by reference numeral 4. BL is a bit line, WL is a word line, and PL ₀ and PL ₁ are plate lines connected to the plate electrodes of the ferroelectric capacitors C ₀ and C ₁ , respectively.
[0014]
In the present invention, two ferroelectric capacitors C ₀ and C ₁ are connected in parallel from the storage node electrode 3 side to one impurity diffusion region (for example, drain) of the common selection transistor 2 as described above. A memory cell is configured. Then, memory cells having the same configuration are regularly arranged at each intersection of the bit line BL and the word line, and the entire memory array is configured.
[0015]
On the other hand, in the ferroelectric memory of the present invention, as shown in FIG. 1A, for example, a plate line selection circuit 5 is provided around the memory array. The plate line selection circuit 5 is connected to the word line WL, the two plate lines PL ₀ and PL ₁ , and the plate voltage supply line PL. In addition, a selection signal line (not shown) and the like are also connected. The function and specific configuration of the plate line selection circuit 5 will be described later.
[0016]
FIG. 2 is a schematic cross-sectional view of the memory cell 1 and the plate line selection circuit 5 of FIG. 1 and other memory cells adjacent to the memory cell 1 and sharing the bit line BL. In FIG. 2, the plate line extraction structure of other memory cells is omitted for the sake of simplicity. FIG. 2 schematically shows the connection between the plate line selection circuit 5 and the plate line, and does not correspond to an actual circuit (for example, FIG. 1B).
[0017]
In FIG. 2, reference numerals 10b and 10c denote MOS transistor active regions left by etching back a silicon substrate (not shown), 11 is a first interlayer insulating layer, 16 is a second interlayer insulating layer, 17 is a connection plug, Reference numeral 18 denotes a third interlayer insulating layer, 19 denotes a semiconductor substrate, and 20 denotes an adhesive layer.
In the ferroelectric memory device of this embodiment, two ferroelectric capacitors C ₀ and C ₁ are arranged in a direction perpendicular to the surface of the semiconductor substrate 19 with the selection transistor 2 interposed therebetween. Therefore, the size of the memory cell 1 is almost determined by the area occupied by the selection transistor 2, and the memory cell 1 has two ferroelectric capacitors C ₀ and C ₁ and can store 2-bit data. Therefore, compared with the case where the selection transistor 2 and the ferroelectric capacitor are arranged on a plane, the capacitance value per unit area is improved by about 4 times, and the structure suitable for a very large capacity ferroelectric memory is provided. Yes.
[0018]
Next, a method for manufacturing the ferroelectric memory configured as described above will be described with reference to FIGS.
In FIG. 3A, first, a silicon substrate 10 is prepared, and a groove 10a having a predetermined depth is formed on the surface of the silicon substrate 10 by a normal photolithography technique and anisotropic etching such as RIE. As will be described below, element isolation is achieved for the selection transistor 2 of the memory cell 1 or the transistor constituting the plate line selection circuit 5 by filling the space between the grooves 10a with an insulating film. Of these groove interval portions, the left end (reference numeral 10 b) in the figure becomes the active region of the select transistor 2 of the memory cell 1, and the other groove interval portion 10 c becomes the active region of the transistors constituting the plate line selection circuit 5.
[0019]
3B, after forming a thin silicon oxide film (not shown) on the silicon substrate 10 in which the groove 10a is formed, the first interlayer insulating layer 11 and the etching stopper film 12 are formed by, for example, CVD (Chemical). The film is formed by the Vapor Deposition method. A relatively thick sacrificial layer 13 is formed on the etching stopper film 12 by using, for example, a CVD method or a SOG (Spin on Glass) method.
For example, a silicon oxide film can be used as the first interlayer insulating layer 11, and the sacrificial layer 13 is formed of a silicon oxide film. The etching stopper film 12 is made of a material having a high etching selectivity with respect to the sacrificial layer 13 on the upper layer side, such as a silicon nitride film. The first interlayer insulating layer 11 is desirably flattened by, for example, chemical mechanical polishing (CMP) after the film formation.
Then, the contact hole 14 reaching the groove interval portion 10b serving as the active region on the memory cell side is formed by anisotropic etching such as RIE.
[0020]
In FIG. 4C, first, a storage node electrode material is formed in a form embedded in the contact hole 14 and etched back to form a plug-shaped storage node electrode 3.
Thereafter, the sacrificial layer 13 is removed with a hydrofluoric acid-based etching solution, and the etching stopper film 12 is removed with a phosphoric acid-based etching solution.
[0021]
In FIG. 4D, first, the ferroelectric film 15 and the film to be the plate electrode 4 are continuously formed by, for example, the CVD method. Then, this laminated film is processed into a predetermined shape by a normal photolithography technique and anisotropic etching such as RIE. As a result, the ferroelectric capacitor _C0 is formed in a form standing from the active region 10b of the selection transistor.
[0022]
In FIG. 5E, first, the second interlayer insulating layer 16 is formed on the entire surface. The second interlayer insulating layer 16 is made of, for example, a silicon oxide film.
Contact holes are formed in the second interlayer insulating layer 16 and the first interlayer insulating layer 11. This contact hole is opened on the plate electrode of the ferroelectric capacitor C ₀ and on the active region 10 c of a predetermined transistor constituting the plate line selection circuit 5.
Then, a film made of polysilicon or the like is formed so as to fill these contact holes, and this is etched back to form the connection plug 17.
In addition, a laminated film of tungsten (W) or W and aluminum (Al) is formed, and the plate line PL ₀ is formed by a normal photolithography technique and anisotropic etching such as RIE.
[0023]
In FIG. 6F, first, a silicon oxide-based third interlayer insulating layer 18 is formed relatively thick on the entire surface by a CVD method or the like. An adhesive layer 20 made of, for example, polysilicon is formed as an adhesive material with the semiconductor substrate 19 such as a silicon wafer on the formed third interlayer insulating layer 18, and the upper surface of the adhesive layer 20 is flattened by CMP or the like. . Then, the semiconductor substrate 19 is bonded from the adhesive layer 20 side, and is adhered by heat treatment.
[0024]
In FIG. 7G, the bonded semiconductor substrate 19 is turned up, and polishing is performed from the upper surface by mechanical polishing, CMP, etc., and the polishing is completed when the first interlayer insulating layer 11 is exposed on the surface. Let As a result, the active regions 10b and 10c of the transistor are left buried in the surface of the first interlayer insulating layer 11.
[0025]
In FIG. 8H, first, impurities are divided into the active regions 10b and 10c according to the channel conductivity type, and then the word line ML serving as the gate electrode of the selection transistor 2 is formed in the active region 10b on the memory cell 1 side. Then, the gate electrode 21 of the transistor on the plate line selection circuit 5 side is formed by a normal photolithography technique and anisotropic etching such as RIE. These electrode materials are polysilicon films. Next, using these electrodes ML and 21 as a mask, the source region 22 and the drain region 23 are formed in each of the active regions 10b and 10c by ion-implanting the impurities over the entire surface according to the channel conductivity type.
Further, after an insulating film such as silicon oxide is formed on the entire surface, the bit line BL made of polysilicon is connected to the source region 22 of the select transistor 2 of the memory cell 1 using the same processing technique. Form.
Then, the first interlayer insulating layer 11 made of silicon oxide or the like is formed again on the entire surface, and the upper surface thereof is flattened.
[0026]
Then, by a process similar to the method of FIG. 4 described above, to form a second ferroelectric capacitor C ₁ (FIG. 9 (i)), a second for connecting this with the plate line selection circuit 5 forming a plate line PL ₁ (FIG. 2).
Thereafter, the ferroelectric memory can be completed through formation of a protective film and opening of a pad window.
[0027]
Finally, a specific configuration and operation of the plate line selection circuit 5 illustrated in FIG. 1B will be described. Note that the data write and data read operations to the memory cell are basically the same as in the normal case, and therefore the description of the operation here will be made on selective switching of the plate lines.
[0028]
Reference numerals TG ₀ and TG _{1 in the} figure indicate transfer gates. Transfer gate TG ₀ is connected between the plate voltage supply line PL and the plate line PL _0. Further, the transfer gate TG ₁ is connected between the plate voltage supply line PL and the plate line PL ₁ . Each transfer gate TG ₀ , TG ₁ is composed of a P-channel MOSFET (PMOS 30) in which sources and drains are interconnected and an N-channel MOSFET (NMOS 31).
[0029]
On the other hand, the symbols AND ₀ and AND ₁ indicate AND gates. A word line WL is connected to one input of AND ₀ and AND ₁ . The other input of the AND _0, the plate line selection signal APO are input. On the other hand, an inverted signal / APO of the plate line selection signal APO is input to the other input of AND ₁ .
The output of the AND ₀ is connected to the gate of NMOS31 constituting the transfer gates TG _0, via the inverter INV _0, is connected to the gate of the PMOS30 which constitute a transfer gate TG _0.
Similarly, the output of the AND ₁ includes a gate of NMOS31 of the transfer gate TG _1, is connected to the gate of the PMOS30 of the transfer gate TG ₁ via an inverter INV _1.
[0030]
Figure 1 ferroelectric capacitor C ₀ of the (a) is selected and the word line WL is energized, the plate line selection signal APO to the plate line selection circuit 5 having such a configuration is input.
If the plate line selection circuit 5 is made high active, the output of AND ₀ becomes “high (H)”, and the NMOS 31 and the PMOS 30 constituting the transfer gate TG ₀ are both turned on to supply the plate line PL ₀ with the plate voltage. Connect to line PL.
On the other hand, the output of AND ₁ remains “low (L)”, and no plate voltage is supplied to the plate line PL ₁ of the non-selected ferroelectric capacitor C ₁ .
[0031]
Conversely, the ferroelectric capacitor C ₁ is selected and the word line WL is energized, the plate line selection signal APO is not input, the inverted signal / APO are input. Therefore, the output of AND ₀ is “L”, the output of AND ₁ is “H”, the transfer gate TG ₀ is cut off, and the transfer gate TG ₁ is turned on. Therefore, the plate line connected to the plate voltage supply line PL is switched from PL ₀ to PL ₁ .
[0032]
【The invention's effect】
As described above, according to the semiconductor memory device having a ferroelectric capacitor according to the present invention, one memory cell is formed by one selection transistor and a plurality of ferroelectric capacitors, and a plurality of bits are stored in one memory cell. Data can be stored. At this time, an increase in the area occupied by the memory cell can be suppressed as much as possible by arranging a plurality of ferroelectric capacitors three-dimensionally.
In addition, by adopting an SOI type element isolation structure, it is possible to increase the speed and power consumption of the selection transistor, and to electrically connect the two plate lines connected to the plate electrodes of the two ferroelectric capacitors. The interference is small and stable operation of the ferroelectric capacitor is ensured.
[0033]
Therefore, according to the present invention, a new cell structure capable of greatly improving the memory capacity per unit area without increasing the cell area is proposed, and a large capacity and high performance ferroelectric memory using the same is proposed. An element can be provided.
[Brief description of the drawings]
FIG. 1A is an equivalent circuit diagram showing a memory cell configuration example of a ferroelectric memory device according to an embodiment of the present invention. FIG. 1B is a circuit diagram showing a configuration example of the plate line selection circuit.
FIG. 2 is a schematic cross-sectional view of the memory cell and plate line selection circuit of FIG. 1 and another memory cell adjacent to the memory cell and sharing a bit line.
FIG. 3 is a schematic cross-sectional view showing each manufacturing process of the ferroelectric memory shown in FIGS. 1 and 2 and shows a process up to a process of opening a contact hole for forming a storage node electrode;
FIG. 4 is a schematic cross-sectional view subsequent to FIG. 3, showing a process up to the first ferroelectric capacitor formation process;
FIG. 5 is a schematic cross-sectional view subsequent to FIG. 4 and shows a process up to forming a plate line.
FIG. 6 is a schematic cross-sectional view subsequent to FIG. 5, showing a process up to a bonding process of semiconductor substrates.
FIG. 7 is a schematic cross-sectional view subsequent to FIG. 6 and shows a process up to forming a transistor active region by polishing a silicon substrate.
FIG. 8 is a schematic cross-sectional view subsequent to FIG. 7, showing a process up to forming transistors, bit lines, and word lines.
FIG. 9 is a schematic cross-sectional view subsequent to FIG. 8, showing a process up to forming a second ferroelectric capacitor;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory cell, 2 ... Selection transistor, 3 ... Storage node electrode, 4 ... Plate electrode, 5 ... Plate line selection circuit, 10 ... Silicon substrate, 10a ... Groove for element isolation, 10b, 10c ... Active region of transistor, DESCRIPTION OF SYMBOLS 11 ... 1st interlayer insulation layer, 12 ... Etching stopper film, 13 ... Sacrificial layer, 14 ... Contact hole, 15 ... Ferroelectric film, 16 ... 2nd interlayer insulation layer, 17 ... Connection plug, 18 ... 3rd an interlayer insulating layer, 19 ... semiconductor substrate, 20 ... adhesive layer, 21 ... gate electrode, 22 ... source region, 23 ... drain region, PMOS constituting 30 ... transfer gate, 31 ... NMOS constituting the transfer gate, _{C 0} , C ₁ ... two ferroelectric capacitors, BL ... bit line, WL ... word line, PL ... plate voltage supply line, PL ₀ , PL ₁ ... plate line, TG ₀ , TG ₁ ... transfer gate, AND ₀ , AND ₁ ... AND gate, INV ₀ , INV ₁ ... inverter, APO ... plate line selection signal, / APO ... plate line selection signal inverted signal.

Claims (5)

A selection transistor having either a source or a drain connected to one of a pair of bit lines;
A memory cell is composed of a plurality of ferroelectric capacitors, each having a storage node electrode connected in parallel to the other side of the source or drain of the selection transistor and capable of storing different storage data.
The plate electrodes of any of the plurality of ferroelectric capacitors are connected to the plate electrodes of the plurality of ferroelectric capacitors and the word line is excited, depending on the input plate line selection signal. A semiconductor memory device having a ferroelectric capacitor having a plate line selection circuit selectively connected to a voltage supply line. 2. The semiconductor memory device having a ferroelectric capacitor according to claim 1, wherein the plurality of ferroelectric capacitors are spaced apart from each other in a direction perpendicular to the semiconductor substrate surface with the selection transistor interposed therebetween. 3. The semiconductor memory device having a ferroelectric capacitor according to claim 2, wherein the selection transistor and the plurality of ferroelectric capacitors are arranged in a form embedded in a thick insulating layer on a semiconductor substrate. A pair of the ferroelectric capacitors are provided in the memory cell,
The plate line selection circuit is
An AND gate having the word line connected to a first input terminal and the plate line selection signal connected to a second input terminal;
A first control gate connected between one plate electrode of the two ferroelectric capacitors and the plate voltage supply line, the gate of which is connected to the output of the AND gate;
A second control gate connected between the other plate electrode and the plate voltage supply line, the output of the AND gate being connected to the gate via an inverter, and an inverting operation with respect to the first control gate; A semiconductor memory device having a ferroelectric capacitor according to claim 1. The AND gate comprises a first AND gate and a second AND gate each having the first input terminal and the second input terminal,
The plate line selection signal is input to the second input terminal of the first AND gate, and the output is connected to the gate of the transistor constituting the first control gate.
The second AND gate receives an inverted signal of the plate line selection signal at its second input terminal, and its output is connected to the gate of the transistor constituting the second control gate via the inverter. ,
The transistor constituting the first control gate constitutes a first transmission gate together with a reverse conductivity type transistor in which the output of the first AND gate is connected to the gate via an inverter,
5. The strong transistor according to claim 4, wherein the transistor constituting the second control gate constitutes a second transmission gate together with a reverse conductivity type transistor in which an output of the second AND gate is connected to the gate. A semiconductor memory device having a dielectric capacitor.

Images