JP3621501B2 - Nonvolatile semiconductor memory device - Google Patents

Description

【００７３】
ループカウンタ１２ａの出力信号Ｎｉとヒューズデコーダの出力信号ＴＲＭｉの組み合わせ（入力信号対ＩＮＰＵＴ ｉ各々に相当）により、書き込み電圧選択回路は書き込み電圧制御回路に選択信号Ｖ１ ，Ｖ２ …，Ｖ１０Ｆを出力する。すなわち、この書き込み電圧選択回路２１は、トリミングヒューズ回路１９にプログラムされたトリミング情報と、ループカウンタ１２ａの示す書き込み回数に基づき、図９に示すような書き込み電圧ＶＰＰを生成するように動作する。
【００７４】
図１２は、図５の書き込み電圧制御回路の構成を示す回路図である。ＲＥＦは、チップ内部の他の回路で発生される一定電圧である。入力される選択信号Ｖ１ 〜Ｖ１０Ｆのうちのいずれかか“Ｈ”レベルになると、ノードＶＩＮと一定電圧ＲＥＦとが等しくなるように、ノード１３０ の電圧が決定される。これにより、書き込み電圧ＶＰＰは、ｐｎ接合ダイオードＱ１ 〜Ｑ４ の各ブレイクダウン電圧とノード１３０ の電圧の和に等しくなるように制御され、図５の書き込み電圧出力回路に供給される。
【００７５】
上記構成の第２の実施形態における不揮発性半導体メモリ装置において、例えば、図８におけるＴＲＭ４ が“Ｈ”レベルになるように、ダイソート工程において図７のヒューズ６７を切断すれば、１回目のデータ書き込みでは、書き込み電圧ＶＰＰは、信号Ｖ４ に対応する電圧になり、２回目のデータ書き込みでは、書き込み電圧ＶＰＰは、信号Ｖ７ に対応する電圧になり、３回目のデータ書き込みでは、書き込み電圧ＶＰＰは、信号Ｖ１０に対応する上限の電圧ＶＰＰｍａｘ になるように制御される。
【００７６】
また、４回目以降のデータ書き込みにおいては、常に、書き込み電圧ＶＰＰは、ＶＰＰｍａｘ になるように制御される。また、書き込み時間は、１回目から３回目までのデータ書き込みにおいては、一定値とし、４回目以降のデータ書き込みにおいては、毎回、前回の書き込み時間の４倍になるように制御する。これにより、チップ毎の書き込み特性を考慮して、チップ毎に最適な書き込み電圧の与え方を個々に設定できる。
【００７７】
以上、説明したように、本発明の不揮発性半導体メモリ装置によれば、次のような効果がある。書き込み回数が増えるにつれて次第に書き込み電圧を上昇させ、かつ、書き込み電圧が上限値になった後には、書き込み電圧を最大値に維持し、書き込み回数が増えるにつれて次第に書き込み時間を長くすることにより、全てのメモリセルに高速にデータを書き込むことができ、かつ、メモリセルのしきい電圧の分布の幅も狭くすることができる。さらに書き込み回数が増えるにつれて次第に書き込み電圧を上昇させる書き込み方式であることにより、メモリセルトランジスタのゲート酸化膜にかかるストレスを低減でき、メモリセルの信頼性向上を図ることができる。
【００７８】
また、チップ間において書き込み特性のばらつきがある場合にも、チップ毎に最適な書き込み電圧及び書き込み時間を設定する手段を備えることにより、全てのチップについて高速な書き込みが可能となり、狭いしきい電圧の分布が得られる。
【００７９】
なお、この発明が適用されるするスタックゲート型の半導体不揮発性メモリセルは、ＮＡＮＤ型、ＡＮＤ型、ＮＯＲ型、ＤＩＮＯＲ型等いずれの構成でメモリセルアレイを構成してもよい。
【００８０】
【発明の効果】
以上、説明したようにこの発明の不揮発性半導体記憶装置によれば、全てのメモリセルにおいて、しきい電圧の分布が広がらずに高速なデータ書き込みを実現することができ、かつ、メモリセルの閾値分布の幅も狭くすることができる。
【００８１】
また、チップ間において書き込み特性のばらつきがある場合にも、チップ毎に最適な書き込み電圧及び書き込み時間を設定する手段を備えることにより、メモリセルのしきい電圧の分布を広げない高速なデータ書き込みを、チップ毎のメモリセルの書き込み特性に応じつつ実現する。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る不揮発性メモリ装置の要部の構成を示す回路ブロック図。
【図２】図１の回路の動作を示す波形図。
【図３】図１の回路に関する書き込み動作の制御を示すフローチャート。
【図４】セルのしきい電圧を上昇させる、書き込み電圧の上昇分及びこの上昇分に等価な書き込み時間の関係を示す特性図。
【図５】本発明の第２の実施形態に係る不揮発性メモリ装置の要部の構成を示すブロック図。
【図６】図５の回路の動作を示すタイミング図。
【図７】図５のトリミングヒューズ回路の構成を示す回路図。
【図８】図５中のヒューズデコーダの回路構成を示す回路図。
【図９】ヒューズデコーダの出力信号と書き込み電圧の供給パターンとの関係を示す図。
【図１０】図５の書き込み電圧選択回路の構成を示す一部の回路図。
【図１１】図５の書き込み電圧選択回路の構成を示す一部の回路図。
【図１２】図５の書き込み電圧制御回路の構成を示す回路図。
【符号の説明】
１１…書き込み制御回路
１２，１２ａ，１２ｂ…ループカウンタ
１３…タイマ
１４…書き込み電圧制御回路
１５…昇圧回路
１６…書き込み電圧出力回路
１７…ロウデコーダ
１８…メモリセルアレイ
１９…トリミングヒューズ回路
２０…ヒューズデコーダ
２１…書き込み電圧選択回路
６２〜６５，７２，９９ｃ，１０３ ，１０５ 〜１０７ …インバータ
６６，９１ａ〜９９ａ，９１ｂ〜９９ｂ…ＭＯＳトランジスタ
６７…ヒューズ
７１，１０４ …ＮＡＮＤ回路
１０１ ，１０２ …ＮＯＲ回路
１０３ ，１０５ 〜１０７ …インバータ
Ｒ１ 〜Ｒ１２…抵抗
Ｑ１ 〜Ｑ４ …ｐｎ接合ダイオード[0001]
[Industrial application fields]
The present invention relates to a nonvolatile semiconductor memory device. In particular, the present invention relates to a write system control circuit for speeding up and optimizing data writing in a nonvolatile semiconductor memory device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, for example, a bit-by-bit verify method has been adopted in a stack gate type nonvolatile semiconductor memory device that can be electrically written and erased. In the bit-by-bit verification method, after data is written to the memory cell, it is verified whether or not the writing has been completed for each bit. Rewrite operation is performed only on complete bits (consent with memory cell). By repeating the writing and verification until data writing is completed for all bits, optimal writing can be realized according to the difference in writing speed for each bit.
[0003]
Such a bit-by-bit verify method is known as a means for narrowing the threshold voltage distribution width of each memory cell to which the same data is written after all data is written to a predetermined memory cell. It is what. The bit-by-bit verification method is described in detail, for example, in 1990 Symposium on VLSI Circuit (pages 105 to 106).
[0004]
In addition, there has been considered a method in which the write voltage is increased step by step in accordance with the increase in the number of writes during verification. This method is used together with the bit-by-bit verify method, and is a technique for completing data writing in all bits in as short a time as possible while reducing the voltage stress applied to the memory cell. (See, for example, Japanese Patent Application No. 6-147918 (claiming priority based on Japanese Patent Application No. 5-158386)).
[0005]
However, it is not possible to increase the write voltage that is increased stepwise during verification in an unlimited manner. This is because the upper limit value of the write voltage is determined by the breakdown voltage of the gate oxide film or the junction breakdown voltage of the transistor constituting the memory cell or the peripheral circuit. Therefore, there may be a memory cell in which data writing is not completely achieved even in the writing operation at the time when the writing voltage reaches the maximum (upper limit value). For such memory cells, the rewrite operation is repeated an appropriate number of times until data writing is completed.
[0006]
However, the rewrite operation is repeatedly performed with the same upper write voltage and the same write time, so that the number of rewrite operations repeated until the data writing to the hard-to-write memory cell is completed increases. . If the number of rewrite operations is increased, the verify time and the boost time for writing increase accordingly. Such a phenomenon increases the writing time of the entire memory system and increases the power consumption.
[0007]
As another problem, it is considered that process variations affect the write characteristics of the entire memory cell and the write characteristics are deflected for each chip. For example, the variation in process here may be a case where the thickness of a gate insulating film constituting a memory cell having a floating gate is slightly deviated in one wafer. Alternatively, the channel length and width of the memory cell transistor may vary from chip to chip. In order to transmit the write voltage into the memory cell, there is a coupling phenomenon of capacitors formed in both the gate insulating film between the control gate and the floating gate and the gate insulating film between the floating gate and the substrate. Therefore, if the channel length and width of the memory cell transistor and the thickness of the gate insulating film vary among the chips, memory chips having slightly different write characteristics are manufactured.
[0008]
However, conventionally, such a process variation is not taken into consideration, and even if the chip has any bias in the write characteristics of the entire memory cell, a predetermined write voltage is uniformly applied in the write operation. It was a method.
[0009]
[Problems to be solved by the invention]
In the method in which the write voltage is increased stepwise as the number of times of writing increases, the write voltage cannot be increased without limit. That is, the upper limit of the write voltage in this method is determined by the breakdown voltage or the junction breakdown voltage of the gate oxide film of the transistor constituting the memory cell or the peripheral circuit.
[0010]
Also, when there is a memory cell in which data writing has not been completely completed even when the write voltage reaches the maximum, the memory cell is then rewritten at the upper limit write voltage and the same. When repeated at the write time, the number of repetitions of the write operation until the data is completely written increases, and accordingly, the verify time corresponding to the increase and the boost time for writing increase. Such a phenomenon lengthens the entire writing time and increases power consumption.
[0011]
Conventionally, the variation in the process is not taken into consideration, and the write operation is a method in which a predetermined write voltage is uniformly applied regardless of the deviation of the write characteristics of the entire memory cell. It was not possible to cope with variations in writing characteristics between chips.
[0012]
The present invention has been made to solve the above problems, and a first object thereof is to provide a nonvolatile semiconductor memory device that realizes high-speed data writing without spreading the threshold voltage distribution of memory cells. It is in.
[0013]
A second object of the present invention is to provide a semiconductor memory device that realizes high-speed data writing in accordance with the write characteristics of the memory cell for each chip without widening the threshold voltage distribution of the memory cells.
[0014]
[Means for Solving the Problems]
In order to achieve the first object, the present invention provides a memory cell array,By applying a write voltage to the control gate,Means for writing data to the memory cells of the memory cell array; means for reading data from the memory cells of the memory cell array; determining whether correct data is written; Means for executing rewriting when no data has been written, and the write voltage as the number of rewrites increases.ΔVPP step by stepAfter the voltage is increased and the write voltage reaches the maximum value, the write voltage is maintained at the maximum value, and as the number of rewrite writes increases,The writing time T (n) is
ΔVPP = A · log ΔT
ΔT = T (n) / T (n−1)
(However, A is a constant, n is the number of writes, and T (n) is the write time of the nth write)
To meetAnd a means for setting the writing time gradually longer.
[0015]
In order to achieve the second object, the present invention further comprises program means for dividing the step-up level until the write voltage reaches the maximum value in a stepwise manner according to the number of write operations.
[0016]
According to the present invention, when the write voltage reaches the upper limit, the write time is extended to increase the write efficiency. Further, the step of raising the write voltage level is made variable by the program means in order to meet the write characteristics for each chip.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit block diagram showing a main part of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the circuit of FIG. FIG. 3 is a flowchart showing the control of the write operation relating to the circuit of FIG. In the present invention, it is assumed that the write and verify operations as shown in FIG. 3 can be automatically performed under the control of a control circuit inside the chip or a controller outside the chip.
[0018]
For example, when a command signal from the outside of the chip is received and the chip writing mode is entered, the control circuit inside the chip starts operating, the writing voltage is boosted (ST1), and data writing to the memory cell designated by the address is performed. The operation is performed (ST2). At this time, the number of write operations is counted as CNT (ST3). Thereafter, a verify operation is performed (ST4).
[0019]
The verify operation in the present invention assumes a bit-by-bit bit verify method. That is, the data of the written memory cell is read to the sense amplifier, and it is determined inside the chip whether or not the writing is completed for each bit. If it is not determined that all bits have been written, the write operation is performed again. However, writing is prohibited for bits that have already been written. If it is determined that all bits have been written, the entire writing operation is finished (ST5). However, the write operation count CNT does not exceed the prescribed write operation count M. When the number of write operations CNT has reached M times and writing has not been completed, a signal is detected outside the circuit system that performs this flow as abnormal termination. Hereinafter, the read operation for verification included in the verify operation is referred to as verify read.
[0020]
The system of the circuit block shown in FIG. 1 controls a series of data write operations from ST1 to ST3 shown in FIG. After ST4, the control shifts to a verify circuit (not shown), and when the verify circuit needs to rewrite, control is returned to the write circuit of FIG.
[0021]
In FIG. 1, a memory cell 181 in the memory cell array is a MOS type non-volatile memory transistor and has a floating gate for accumulating charges. A control gate CG disposed on the floating gate corresponds to a word line in the memory cell array. D is a drain on the substrate, and SL is a source on the substrate. The write voltage VPP according to the present invention is applied to the control gate CG. In the nonvolatile memory cell transistor, the threshold voltage fluctuates greatly as the absolute value increases according to the absolute value of the difference in potential applied to the substrate and the control gate CG at the time of writing, and corresponds to the threshold voltage. Store the data.
[0022]
When a command signal from the outside of the chip is received and the chip write mode is entered, the write control circuit 11 outputs control signals P and C. When data writing is started, the voltage of the write control signal P changes from “L” level to “H” level. The voltage of the control signal P is kept at the “H” level during the period of data writing operation (including the boosting time). The control signal C is also input to the timer 13. The control signal C is a signal for giving a write voltage to the memory cell after boosting is completed. When the control signal C changes to “H” level, the timer 13 starts a time measuring operation.
[0023]
The timer 13 outputs a pulse signal S when a predetermined time corresponding to the number of data writes has elapsed. When the pulse signal S is input to the write control circuit 11, the write control circuit 11 changes the voltages of the control signals P and C from the “H” level to the “L” level. Thereby, one-time data writing is completed. On the other hand, the counter 12 receives the signal S from the timer 13 and counts the number of data writes. The counter 12 outputs signals N1, N2,... Representing the number of times of writing (CNT). The output signals N1, N2,... Of the counter 12 are input to the timer 13 and the write voltage control circuit 14.
[0024]
When the “H” level control signal P is input, the booster circuit 15 starts the boost operation of the write voltage. When a certain period elapses after the booster circuit 15 starts operating, the output voltage VPP of the booster circuit 15 becomes the first write voltage VPP1. The output voltage (write voltage) VPP of the booster circuit 15 is determined by the output signal of the write voltage control circuit 14. That is, the write voltage control circuit 14 determines the level of the output voltage VPP of the booster circuit 15 in accordance with the number of data writes.
[0025]
As described above, in the first data write, the write voltage control circuit 14 controls the booster circuit 15 so that the booster circuit 15 outputs the first write voltage VPP1 as the output voltage. Thereafter, the voltage of the control signal C changes from “L” level to “H” level. The write voltage output circuit 16 supplies the output voltage (write voltage) of the booster circuit 15 to the row decoder 17 while the control signal C is at the “H” level, and the control gate CG of the memory cell selected by the row decoder 17. The write voltage is applied to (word line).
[0026]
Thereafter, the verify operation is performed outside this circuit system. After verify and read, it is checked whether or not the predetermined data is correctly written in the memory cell. If the data is correctly written in all the memory cells, the data writing is completed. The entire writing operation is terminated. In addition, when writing to at least one memory cell is insufficient, the second data writing (rewriting) is executed.
[0027]
Similar to the above, the second data write is performed by the write voltage VPP2. If the data is not correctly written to all the memory cells even after the second data write, the third and subsequent data write (until the data is correctly written to all the memory cells ( Execute (Rewrite).
[0028]
By the way, the counter 12 receives the signal S of the timer 13 and stores the number of times of writing when the signal S is received. Until the output of the counter 12 reaches a preset number K, the timer 13 outputs a signal S based on the output Ni of the counter 12 so that the write time T (n) at each write count becomes a fixed time t. Output.
[0029]
The write voltage control circuit 14 that receives a signal from the counter 12 controls the write voltage VPP so that the write voltage increases by ΔVPP until the output of the counter 12 reaches a preset number of times K. When the output of the counter 12 becomes larger than the preset number of times K, that is, in writing after the (K + 1) th time, the timer 13 has a writing time T (n) at each writing number based on the output Ni of the counter 12 as follows. The signal S is output so that A × T (n−1). The write voltage control circuit 14 receives the signal from the counter 12 and is controlled so as to maintain the upper limit write voltage VPPmax in the data write after the write count K.
[0030]
That is, the number of times K is the number of times that the write voltage reaches the upper limit VPPmax, A is a value depending on the increase ΔVPP of the write voltage, n is the number of times of write, and T (n) is the nth time. This is the writing time for writing data. That is, in the example of FIG. 2, the number of times K = 3 and A = 4, the first data writing time T (1) = t, the second data writing time T (2) = t, and the third data writing time. The writing time is T (3) = t.
[0031]
That is, the writing time is a fixed time t until the output voltage (writing voltage) VPP of the booster circuit 15 reaches the upper limit VPPmax. When the output voltage (write voltage) of the booster circuit 15 is increased by ΔVPP (for example, 1.5 V) for each write, and the output voltage VPP of the booster circuit 15 reaches the upper limit VPPmax (n = K = 3), For subsequent data writing, the output voltage of the booster circuit 15 is changed so that the writing time becomes T (n) = 4 × T (n−1) while maintaining the constant value VPPmax.
[0032]
That is, in the example of FIG. 2, the fourth data write time T (4) = 4 × T (4-1) = 4 × T (3) = 4t, the fifth data write time T (5) = 4 × T (5-1) = 4 × T (4) = 16t, and although not shown, the sixth data write time is T (6) = 4 × T (6-1) = 4 × T ( 5) = 64t.
[0033]
In the above example, the reason why A = 4 will be described. In the present invention, when the output voltage (write voltage) VPP of the booster circuit 15 reaches the upper limit VPPmax, the subsequent write of data is performed by the memory cell by the increase ΔVPP (1.5 V) of the write voltage. The write time is increased by an amount equivalent to the threshold voltage fluctuation. That is, since the write voltage VPP is limited, further expansion of the threshold voltage fluctuation of the memory cell in the next write operation is achieved by changing the write time.
[0034]
The present invention applies the following relationship between the write voltage increase ΔVPP and the write time T (n).
ΔVPP = 2.6 · log ΔT (1)
ΔT = T (n) / T (n−1) (2)
(However, the coefficient 2.6 depends on the manufacturing process.)
Accordingly, for example, when the increase ΔVPP of the write voltage is about 1.5 V, the change ΔT in the write time equivalent to the change in the threshold voltage of the memory cell due to the increase ΔVPP in the write voltage is about 4. Become.
[0035]
FIG. 4 is a characteristic diagram showing the relationship between the write voltage increase ΔVPP, which increases the cell threshold voltage by ΔVth, and the write time equivalent to ΔVPP. For the sake of explanation, it is assumed that the memory cells MC1, MC2 and MC3 all have the same threshold voltage level immediately before the end of writing. The memory cell MC1 is written fast, and the memory cell MC3 is written slowly. The memory cell MC2 has characteristics intermediate between MC1 and MC3.
[0036]
Loops 1, 2, 3,... 5 are the number of loops of the write-verify operation in FIG. Until the third writing (loop 3), the writing voltage increases by ΔVPP (= 1.5 V) and thereafter remains the same voltage VPPmax. The change ΔT in the writing time after the fourth writing (loop 4) is 4 times the previous time. Such conditions are the same as those in FIG.
[0037]
In FIG. 4, the memory cell MC1 is completely written in two loops. Since the write voltage is increased by ΔVPP each time up to loop 3, the threshold voltage of the cell increases in proportion to the write time.
[0038]
Writing to the memory cell MC2 is completed in four loops. From loop 4, the write voltage no longer rises because it has already reached the upper limit (VPPmax) and maintains VPPmax. Therefore, in the loop 4 and thereafter, the write time is changed by the amount of change in the threshold voltage of the cell equivalent to the amount of change in the threshold voltage of the cell when the write voltage is further increased by ΔVPP (dotted line 41). Get by. As for the transition of the threshold voltage of the cell, if the write voltage is constant, the time required for writing increases exponentially. Accordingly, in consideration of the fact that the threshold voltage of the cell changes in the loop 4 as shown by the curve 42, the writing time (4t) longer than the writing time (t) of the loop 3 is necessary.
[0039]
Writing to the memory cell MC3 is completed in five loops. The curve 43 in the loop 4 is the same as the curve 42. In the loop 5, in order to actually obtain the fluctuation amount of the cell threshold voltage equivalent to the fluctuation amount of the threshold voltage of the cell when the write voltage is further increased by ΔVPP as compared with the writing effect of the loop 4. Further, change the writing time. In loop 5, considering that the threshold voltage of the cell changes like curve 44, a write time (16t) longer than the write time (4t) of loop 4 is required.
[0040]
According to the above configuration, after the write voltage reaches the upper limit (VPPmax), the write time is increased each time by an amount corresponding to the increase in write voltage (ΔVPP). For this reason, the writing efficiency can be gradually increased every time the number of times of writing is repeated over all the writing operations. Thus, after sufficient writing is performed every time, verify reading can be performed, and high-speed data writing can be realized.
[0041]
For example, it is assumed that the first write time t to the memory cell is t, which is the sum of the boost times for verify read and write, and is equal to the write time t. If the first embodiment described above is applied and five loops are required until the writing of all memory cells is completed, the total writing time is
(T + t) + (t + t) + (t + t) + (4t + t) + (16t + t) = 28t (3)
It becomes.
[0042]
Assuming that the write time is not increased even when the write voltage reaches the upper limit (VPPmax) as in the conventional case, what is the boost for verify read and write without increasing the threshold voltage of the cell? Will do it again. That is, in the present invention, five loops are sufficient. In this case, 4t corresponds to four times, and 16t corresponds to 16 loops, so that a total of 23 loops are obtained. Therefore, the entire writing time is as follows:
(T + t) × 23 = 46t (4)
Thus, such an inefficient loop increases the writing time of the entire system.
[0043]
From the above, compared with the equation (4), the equation (3) shortens the writing time of the entire memory by 65%. In this way, unnecessary boosting time for verify reading and writing can be omitted in the present application, and the entire writing time can be shortened.
[0044]
In the first embodiment described above, the write voltage (control gate voltage) is gradually increased until the third data write, and the write voltage (control gate voltage) is kept constant for the fourth and subsequent data write. To increase the writing time.
[0045]
However, in the first embodiment, the specification is such that rewriting is uniformly performed on the memory cells in all the chips manufactured in a single wafer under the same conditions. If it does, it may not be optimal. The reason is shown below as Example 1 and Example 2.
[0046]
(Example 1): If a chip having a memory cell in which data writing is relatively fast compared to the design is manufactured due to process fluctuations, etc., this chip finishes writing with a smaller number of times of writing than a normal chip. Will do. In this case, the threshold voltage distribution of the memory cell after writing becomes higher than usual, and there is a possibility that there is a memory cell in an overwritten state in the worst case. The overwriting state means that the threshold voltage of the cell is distributed in a region where normal reading is impossible in the reading operation. For such a chip, it is necessary to set the write voltage lower than usual so as to suppress the threshold voltage distribution of the cell after writing to a low position.
[0047]
(Example 2): If a chip having a memory cell in which data writing is relatively slow compared to the design is manufactured due to process variation or the like, this chip can perform sufficient data writing with a write operation within the expected number of times. Since this is not possible, it is necessary to suppress the increase in the number of times of writing for this chip from the first time by raising the write voltage to some extent.
[0048]
In order to eliminate such fears, the present invention provides a second embodiment.
FIG. 5 is a circuit block diagram showing a main part of a nonvolatile semiconductor memory device according to the second embodiment of the present invention. FIG. 6 is a timing chart showing the operation of the circuit of FIG. This second embodiment is provided with a circuit for programming a method for applying a write voltage after chip fabrication so that an optimum method for applying a write voltage can be selected for each chip.
[0049]
The circuit block system shown in FIG. 5 controls a series of data write operations from ST1 to ST3 shown in FIG. After ST4, control is transferred to a verify circuit (not shown). If the verify circuit determines that rewriting is necessary, control is returned to the write circuit block of FIG.
[0050]
In FIG. 5, the write control circuit 11 controls the write operation of the entire chip when it recognizes the write mode upon receiving a command input from the outside of the chip. The write control circuit 11 outputs control signals P and C for each write. The control signal P activates the write voltage control circuit 14, the booster circuit 15, and the fuse decoder 20, respectively. The booster circuit 15 generates a write voltage VPP based on the power supply voltage VCC.
[0051]
The write voltage control circuit 14 supplies a write voltage VPP corresponding to the selection signals V 1 to V 10 of the write voltage selection circuit 21 to the write voltage output circuit 16. The write voltage output circuit 16 controlled by the control signal C applies the supplied write voltage VPP to the control gate CG (word line) of the memory cell 181 constituting the memory cell array 18 via the row decoder 17.
[0052]
Further, the control signal C starts the timer 13. The timer 13 outputs a signal S after a predetermined write time has elapsed. The signal S is a pulse signal and is input to the write control circuit 11 and the loop counters 12a and 12b. As a result, the control signals P and C are set to the “L” level, and the writing is completed.
[0053]
The loop counter 12 a is incremented by the signal S, counts the total number of writes, and outputs a signal Ni indicating the number of writes to the write voltage selection circuit 21. The timer 13 outputs write pulses (signal S) at regular intervals until the write voltage selection circuit 21 selects the signal V10 that designates the upper limit write voltage.
[0054]
Further, when the signal V10 corresponding to the upper limit write voltage is selected in the write voltage selection circuit 21, the signal F ("H" level in FIG. 6) after the pulse signal of the control signal C becomes "L" level. Is output. The loop counter 12b receives the output signal S of the timer 13, counts the number of writes after the write voltage VPP reaches the upper limit, and outputs a signal Mj. By receiving the output signal Mj of the loop counter 12b, the timer 13 outputs a signal S that increases the write time in proportion to the number of writes after the write voltage VPP reaches the upper limit. That is, after the write voltage VPP reaches the upper limit, the timer 13 controls the signal S so as to widen the pulse width of the control signal C at a constant magnification.
[0055]
FIG. 7 shows an example of the circuit configuration of the trimming fuse circuit 19 in FIG. FIG. 8 shows an example of the circuit configuration of the fuse decoder 20 in FIG. Both of them actually require a plurality of circuits having the above configuration. Here, the trimming fuse circuit 19 has a combined configuration of three circuits in FIG. 7 (i = 1 to 3). The fuse decoder has a combined configuration of eight circuits in FIG. 8 (i = 1 to 8).
[0056]
The trimming fuse circuit includes five inverters 61 to 65, a MOS transistor 66, and a fuse 67 connected in series. The control signal P is input to the inverter 61 and the gate of the MOS transistor 66. The fuse 67 is formed of a polysilicon layer, and fusing is performed by laser irradiation. The fuse 67 is connected between the output node of the inverter 62 and the drain of the MOS transistor 66. The source of the MOS transistor 66 is connected to the ground point.
[0057]
Program signal FSi (i = 1 to 3) is output from inverter 64, and program signal FSiB (i = 1 to 3) is output from inverter 65. The fuse decoder includes a NAND circuit 71 to which a control signal P and FSi or FSiB are input, and an inverter 72 that inverts an output signal of the NAND circuit 71 and outputs a signal TRMi (i = 1 to 8).
[0058]
In the trimming fuse circuit 19 and the fuse decoder 20, one of the signals TRMi (i = 1 to 8) becomes “H” level depending on whether or not the fuse 67 is cut. This makes it possible to select eight supply patterns of the write voltage VPP. Such selection of the VPP supply pattern is hereinafter referred to as trimming of the write voltage VPP. In this embodiment, the trimming of the write voltage is performed in a die sort process after chip manufacture.
[0059]
FIG. 9 shows the write voltage VPP selected by the output signal TRMi (i = 1 to 8) from the fuse decoder 20. The horizontal axis indicates the output signal TRMi of the fuse decoder, and the vertical axis indicates the write voltage VPP selected by the signal TRMi. Note that one scale on the vertical axis is, for example, 0.5 V, and the step width for each write count is, for example, 1.5 V.
[0060]
In FIG. 9, the upper limit write voltage VPPmax is a voltage corresponding to V10. This upper limit write voltage is usually set lower by a certain voltage than the gate oxide breakdown voltage or junction breakdown voltage of the transistors constituting the memory cell or peripheral circuit in order to ensure the reliability of the chip operation. When one of the signals V1 to V10 from the write voltage selection circuit 21 is selected, a corresponding write voltage is generated.
[0061]
Note that V10 and V10F in FIG. 6 are common waveforms when the write voltage reaches the upper limit regardless of trimming (signal TRMi). In addition, since the difference between the first write voltage and the next write voltage is 1.5V for each of TRM1-7, Vi and Vi + 3 are representatively shown because they are waveforms common to TRM1-7 during trimming. It was.
[0062]
FIG. 9 will be described using an example. For the chip having the above characteristics (example 1), for example, the supply pattern of the voltage VPP of TRM1 is selected. That is, based on the trimming information programmed in the trimming fuse circuit 19, the output signal TRM1 of the fuse decoder 20 is set to the “H” level. As a result, in this chip, one of the selection signals V1, V4, V7, and V10 corresponding to the write voltage VPP is supplied to the write voltage control circuit 14 every number of times of writing.
[0063]
That is, writing to the memory cell with the write voltage VPP corresponding to the signal V1 is executed in the loop 1 (which is the first loop of the ST1 to ST6 in the write-verify operation in FIG. 3) which is the first write operation. . If there is a memory cell that is insufficiently written by this write operation, writing to the memory cell is performed with the write voltage VPP corresponding to the signal V4 in the next loop 2. In this write operation, if there is a memory cell that is insufficiently written, writing to the memory cell with the write voltage VPP corresponding to the signal V7 in the next loop 3 is executed for each memory cell. Further, writing to the memory cells is performed on the memory cells with insufficient writing in the next loop 4 by the writing voltage VPP (upper limit writing voltage VPPmax) corresponding to the signal V10.
[0064]
After writing in the loop 4, writing to the memory cells is performed on the memory cells that are further insufficiently written with the write voltage VPP (upper limit write voltage VPPmax) corresponding to the signal V 10 in the loop 5 (not shown). The At this time, the write time becomes longer, and the write time corresponding to the variation of the threshold voltage of the memory cell when the write voltage is further increased by ΔVPP (for example, 1.5 V) is set. Thereafter, a write time equivalent to ΔVPP is set every time the number of writes increases. When the loop counter 12a has counted a predetermined number of times of writing, the writing operation is terminated. At this time, if there is a memory cell that is still insufficiently written, it is detected as an abnormal end outside the circuit system that performs the flow of FIG.
[0065]
For the chip having the above characteristics (example 2), for example, the supply pattern of the voltage VPP of TRM6 is selected. That is, programmed by the trimming fuse circuit 19, the output signal TRM6 of the fuse decoder 20 becomes "H" level. As a result, the chip is supplied with one of the voltages corresponding to the selection signals V6, V9, and V10 as the write voltage VPP for each write count.
[0066]
That is, writing to the memory cell is performed by the write voltage VPP corresponding to the signal V6 in the first loop 1 (referred to as the first loop of ST1 to ST6 of the write-verify operation in FIG. 3). . If there is a memory cell that is insufficiently written by this write operation, writing to the memory cell is performed with the write voltage VPP corresponding to the signal V9 in the next loop 2. In this write operation, if there is a memory cell that is insufficiently written, the memory cell is supplied to the memory cell by the write voltage VPP (upper limit write voltage VPPmax) corresponding to the signal V10 in the next loop 3, respectively. Writing is executed.
[0067]
After writing in the loop 3, writing to the memory cells is performed on the memory cells that are further insufficiently written with the write voltage VPP (upper limit write voltage VPPmax) corresponding to the signal V 10 in the loop 4 (not shown). The At this time, the write time becomes longer, and the write time corresponding to the variation of the threshold voltage of the memory cell when the write voltage is further increased by ΔVPP (for example, 1.5 V) is set. Thereafter, a write time equivalent to ΔVPP is set every time the number of writes increases. When the loop counter 12a has counted a predetermined number of times of writing, the writing operation is terminated. At this time, if there is a memory cell that is still insufficiently written, it is detected as an abnormal end outside the circuit system that performs the flow of FIG.
[0068]
10 and 11 are circuit diagrams partially showing the configuration of the write voltage selection circuit 21 in FIG. The write voltage selection circuit 21 includes 10 circuit configurations in FIG. 10 and 1 circuit in FIG. In FIG. 10, MOS transistors 9ia and 9ib (i = 1 to 8) are connected in series between a node 100 and a ground point, and an input signal pair INPUT i (i = 1 to 8) is input to each gate. Is done. For example, the MOS transistors 91a and 91b are connected in series between the node 100 and the ground point, and the input signal pair INPUT 1 is input to each gate. These drive MOS transistors 9ia and 9ib (i = 1 to 8) are N-channel enhancement type MOS transistors. The load MOS transistors 99a and 99b are N-channel depletion type MOS transistors, and are connected in series between the node 100 and the power supply terminal. The gates of MOS transistors 99a and 99b are both connected to node 100. The potential of the node 100 is inverted by the inverter 99c and becomes the write voltage selection signal Vi (i = 1 to 10).
[0069]
In FIG. 11, the write selection signal V 10 is input to the NOR gate 101 and the inverter 103. Further, the reset signal R and the output signal of the NOR gate 101 are input to the NOR gate 102. The output signal of the NOR gate 102 is input to the NOR gate 101, the NAND gate 104, and the inverter 106. The output signal of the inverter 103 is input to the NAND gate 104. The output signal of the NAND gate 104 passes through the inverter 105 and becomes a signal F. The output signal of the NOR gate 102 passes through the inverters 106 and 107 and becomes the signal V10F.
[0070]
That is, in FIG. 11, the NOR gates 101 and 102 constitute a flip-flop, and the signal V10 specifying the upper limit VPPmax of the write voltage is latched until the write is completed (reset).
[0071]
The signal F notifies the timer 13 and the loop counter 12b in FIG. 5 that the upper limit VPPmax of the write voltage has been reached. Upon receiving the signal F, the timer 13 supplies a signal S (pulse) to the write control circuit 11 so as to increase the write time by a predetermined time for each write, and causes the loop counters 12a and 12b to count pulses.
Table 1 shows an input / output table of the write voltage selection circuit of FIGS.
[0072]
[Table 1]

[0073]
The write voltage selection circuit outputs selection signals V1, V2,..., V10F to the write voltage control circuit according to the combination of the output signal Ni of the loop counter 12a and the output signal TRMi of the fuse decoder (corresponding to each of the input signal pair INPUT i). That is, the write voltage selection circuit 21 operates to generate a write voltage VPP as shown in FIG. 9 based on the trimming information programmed in the trimming fuse circuit 19 and the number of times of writing indicated by the loop counter 12a.
[0074]
FIG. 12 is a circuit diagram showing a configuration of the write voltage control circuit of FIG. REF is a constant voltage generated by other circuits inside the chip. When any one of the input selection signals V1 to V10F becomes “H” level, the voltage of the node 130 is determined so that the node VIN is equal to the constant voltage REF. Thus, the write voltage VPP is controlled to be equal to the sum of the breakdown voltages of the pn junction diodes Q1 to Q4 and the voltage of the node 130, and is supplied to the write voltage output circuit of FIG.
[0075]
In the nonvolatile semiconductor memory device according to the second embodiment having the above-described configuration, for example, if the fuse 67 in FIG. 7 is cut in the die sort process so that TRM4 in FIG. Then, the write voltage VPP becomes a voltage corresponding to the signal V4, and in the second data write, the write voltage VPP becomes a voltage corresponding to the signal V7, and in the third data write, the write voltage VPP is The upper limit voltage VPPmax corresponding to V10 is controlled.
[0076]
In the fourth and subsequent data writing, the write voltage VPP is always controlled to be VPPmax. Further, the writing time is controlled to be a constant value in the first to third data writing, and is controlled to be four times the previous writing time in the fourth and subsequent data writing. Thereby, it is possible to individually set the optimum writing voltage for each chip in consideration of the writing characteristics for each chip.
[0077]
As described above, the nonvolatile semiconductor memory device of the present invention has the following effects. By gradually increasing the write voltage as the number of writes increases, and maintaining the write voltage at the maximum value after the write voltage reaches the upper limit, and gradually increasing the write time as the number of writes increases, Data can be written to the memory cell at high speed, and the threshold voltage distribution width of the memory cell can be narrowed. Further, the writing method in which the writing voltage is gradually increased as the number of writings increases, so that stress applied to the gate oxide film of the memory cell transistor can be reduced, and the reliability of the memory cell can be improved.
[0078]
In addition, even when there is a variation in writing characteristics between chips, by providing means for setting an optimum writing voltage and writing time for each chip, high-speed writing can be performed for all chips, and a narrow threshold voltage can be set. Distribution is obtained.
[0079]
The stacked gate type semiconductor nonvolatile memory cell to which the present invention is applied may constitute a memory cell array in any configuration such as NAND type, AND type, NOR type, DINOR type, and the like.
[0080]
【The invention's effect】
As described above, according to the nonvolatile semiconductor memory device of the present invention, high-speed data writing can be realized in all memory cells without widening the threshold voltage distribution, and the threshold of the memory cell can be realized. The width of the distribution can also be narrowed.
[0081]
In addition, even when there is a variation in writing characteristics between chips, by providing means for setting an optimum writing voltage and writing time for each chip, high-speed data writing that does not broaden the threshold voltage distribution of the memory cells is possible. This is realized according to the write characteristics of the memory cell for each chip.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing a configuration of a main part of a nonvolatile memory device according to a first embodiment of the present invention.
FIG. 2 is a waveform diagram showing the operation of the circuit of FIG.
FIG. 3 is a flowchart showing control of a write operation related to the circuit of FIG. 1;
FIG. 4 is a characteristic diagram showing a relationship between an increase in write voltage and a write time equivalent to this increase in increasing the threshold voltage of the cell.
FIG. 5 is a block diagram showing a configuration of a main part of a nonvolatile memory device according to a second embodiment of the present invention.
6 is a timing chart showing the operation of the circuit of FIG.
7 is a circuit diagram showing a configuration of a trimming fuse circuit of FIG. 5;
8 is a circuit diagram showing a circuit configuration of a fuse decoder in FIG. 5. FIG.
FIG. 9 is a diagram showing a relationship between an output signal of a fuse decoder and a supply pattern of a write voltage.
10 is a partial circuit diagram illustrating a configuration of a write voltage selection circuit in FIG. 5;
11 is a partial circuit diagram showing the configuration of the write voltage selection circuit of FIG. 5;
12 is a circuit diagram showing a configuration of a write voltage control circuit in FIG. 5;
[Explanation of symbols]
11: Write control circuit
12, 12a, 12b ... loop counter
13 ... Timer
14: Write voltage control circuit
15 ... Booster circuit
16: Write voltage output circuit
17 ... Row decoder
18 ... Memory cell array
19 ... Trimming fuse circuit
20 ... Fuse decoder
21: Write voltage selection circuit
62-65, 72, 99c, 103, 105-107 ... inverter
66, 91a-99a, 91b-99b ... MOS transistors
67 ... Fuse
71, 104 ... NAND circuit
101, 102 ... NOR circuit
103, 105 to 107 ... inverter
R1 to R12 ... resistance
Q1 to Q4 ... pn junction diode

Claims (15)

A memory cell array including a plurality of nonvolatile memory cells;
A booster circuit for boosting a write voltage to be supplied to the memory cell;
A counter that counts the number of writes;
The supply time of the write voltage to the memory cell is constant until the arbitrary number of times of writing specified by the counter is reached, and after the arbitrary number of times of writing, the supply time of the write voltage to the memory cell is stepwise. A timer to increase to
The boost level by the booster circuit until the write voltage reaches a predetermined upper limit is divided in stages according to the arbitrary number of writes, and when the write voltage reaches a predetermined upper limit, the write voltage A non-volatile semiconductor memory device comprising a write voltage control circuit for maintaining The nonvolatile semiconductor memory device according to claim 1 ,
The supply time of the write voltage to be increased stepwise is the memory cell corresponding to the increment of one of the write voltages divided stepwise before the write voltage reaches a predetermined upper limit. The threshold voltage rise is set so as to be obtained. The nonvolatile semiconductor memory device according to claim 1 ,
It further comprises program means for dividing the step-up level by the step-up circuit until the write voltage reaches a predetermined upper limit in a stepwise manner according to the arbitrary number of writes. A memory cell array including a plurality of nonvolatile memory cells;
A booster circuit for boosting a write voltage to be supplied to the memory cell;
A first counter that counts a predetermined number of write operations;
A second counter that counts after an arbitrary number of writes of the predetermined number of times;
The supply time of the write voltage to the memory cell is constant until the number of times of writing specified by the second counter is reached, and the time of supply of the write voltage to the memory cell is set after the number of times of writing. A timer that gradually increases
The boost level by the booster circuit until the write voltage reaches a predetermined upper limit is divided in stages according to the arbitrary number of writes, and when the write voltage reaches a predetermined upper limit, the write voltage A write voltage control circuit for maintaining
A non-volatile semiconductor memory device, comprising: a program system that divides a step-up level by the step-up circuit until the write voltage reaches a predetermined upper limit in a stepwise manner according to the arbitrary number of write operations. The nonvolatile semiconductor memory device according to claim 4 .
The program system includes a write voltage selection circuit that outputs a selection signal for setting the boost level to the write voltage control circuit, a decoder that specifies the selection signal of the write voltage selection circuit, and a program signal that is supplied to the decoder. And a fuse circuit to be provided. The nonvolatile semiconductor memory device according to claim 4 .
The program system makes the first boost level of the arbitrary number of writes variable, and changes the arbitrary number of writes that can stepwise divide the boost level until the write voltage reaches a predetermined upper limit. It is characterized by being able to. The nonvolatile semiconductor memory device according to claim 4 .
The supply time of the write voltage to be increased stepwise is the memory cell corresponding to the increment of one of the write voltages divided stepwise before the write voltage reaches a predetermined upper limit. The threshold voltage rise is set so as to be obtained. A memory cell array including a plurality of nonvolatile memory cells;
A decoder for selecting the memory cells;
A booster circuit for boosting a write voltage to be supplied to the memory cell;
A counter that counts the number of writes;
The supply time of the write voltage to the memory cell is constant until the arbitrary number of times of writing specified by the counter is reached, and after the arbitrary number of times of writing, the supply time of the write voltage to the memory cell is stepwise. A timer to increase to
The boost level by the booster circuit until the write voltage reaches a predetermined upper limit is divided in stages according to the arbitrary number of writes, and when the write voltage reaches a predetermined upper limit, the write voltage And a write voltage control circuit for maintaining
Each time the counter counts, a verify operation is performed to determine whether correct data is written in the selected memory cell of the memory cell array, and for the selected memory cell until the correct data is written, the timer A nonvolatile semiconductor memory device that performs a write operation according to control. The nonvolatile semiconductor memory device according to claim 8 ,
The supply time of the write voltage to be increased stepwise is the memory cell corresponding to the increment of one of the write voltages divided stepwise before the write voltage reaches a predetermined upper limit. The threshold voltage rise is set so as to be obtained. The nonvolatile semiconductor memory device according to claim 8 ,
There is further provided program means for dividing the boost level by the booster circuit until the write voltage reaches a predetermined upper limit in a stepwise manner according to the arbitrary number of writes. The nonvolatile semiconductor memory device according to claim 10 ,
The program means includes a write voltage selection circuit that outputs a selection signal for setting the boost level to the write voltage control circuit, a decoder that specifies the selection signal of the write voltage selection circuit, and a program signal to the decoder. The number of times of writing in which the boosted level can be divided in stages until the write voltage reaches a predetermined upper limit is changed by the program means. A memory cell array including a plurality of nonvolatile memory cells;
A booster circuit for boosting a write voltage to be supplied to the memory cell;
A counter that counts the number of writes;
In order to control the supply time of the write voltage to the memory cell, among the predetermined number of counts by the counter, the first to arbitrary times are counted at regular time intervals, and the number of times after the arbitrary number is stepwise. A timer that outputs a signal for counting at increasing time intervals;
The boost level by the booster circuit until the write voltage reaches a predetermined upper limit is divided in stages according to the arbitrary number of times, and the write voltage is maintained when the write voltage reaches a predetermined upper limit A non-volatile semiconductor memory device comprising: a write voltage control circuit that performs The nonvolatile semiconductor memory device according to claim 12 ,
The time interval that increases stepwise in the signal output from the timer corresponds to the increment of one of the stepwise divisions of the write voltage before the write voltage reaches a predetermined upper limit. The memory cell is set so as to obtain a threshold voltage increase. A memory cell array including a plurality of nonvolatile memory cells;
A booster circuit for boosting a write voltage to be supplied to the memory cell;
A first counter that counts a predetermined number of write operations;
A second counter that counts after an arbitrary number of the predetermined number of times;
In order to control the supply time of the write voltage to the memory cell, out of a predetermined number of counts by the first counter, the first to the arbitrary number are counted at regular time intervals, and the number of times after the arbitrary number Is a timer that outputs a signal to be counted at time intervals that increase stepwise,
The boost level by the booster circuit until the write voltage reaches a predetermined upper limit is divided in stages according to the arbitrary number of times, and the write voltage is maintained when the write voltage reaches a predetermined upper limit A write voltage control circuit,
A program system that divides the boost level by the booster circuit until the write voltage reaches a predetermined upper limit in a stepwise manner according to the arbitrary number of times in order to make the arbitrary number of initial boost levels variable. A non-volatile semiconductor memory device comprising: 15. The nonvolatile semiconductor memory device according to claim 14 ,
The program system includes a write voltage selection circuit that outputs a selection signal for setting the boost level to the write voltage control circuit, a decoder that specifies the selection signal of the write voltage selection circuit, and a program signal that is supplied to the decoder. And a fuse circuit to be provided.

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